HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r261:489b6615789a

DAC CAL input data via Registre_data Driver C

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r261:489b6615789a martin

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r261:489b6615789a

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lib/lpp/lpp_memory/Bridge.vhd created 644 +53 0

@@ -0,0 +1,53
	1	-- Bridge.vhd
	2	library IEEE;
	3	use IEEE.std_logic_1164.all;
	4	use IEEE.numeric_std.all;
	5
	6	entity Bridge is
	7	port(
	8	clk : in std_logic;
	9	raz : in std_logic;
	10	EmptyUp : in std_logic;
	11	FullDwn : in std_logic;
	12	WriteDwn : out std_logic;
	13	ReadUp : out std_logic
	14	);
	15	end entity;
	16
	17
	18	architecture ar_Bridge of Bridge is
	19
	20	type etat is (e0,e1);
	21	signal ect : etat;
	22
	23	begin
	24
	25	process(clk,raz)
	26	begin
	27	if(raz='0')then
	28	WriteDwn <= '1';
	29	ReadUp <= '1';
	30	ect <= e0;
	31
	32	elsif(clk'event and clk='1')then
	33
	34	case ect is
	35
	36	when e0 =>
	37	WriteDwn <= '1';
	38	if(EmptyUp='0' and FullDwn='0')then
	39	ReadUp <= '0';
	40	ect <= e1;
	41	end if;
	42
	43	when e1 =>
	44	ReadUp <= '1';
	45	WriteDwn <= '0';
	46	ect <= e0;
	47
	48	end case;
	49
	50	end if;
	51	end process;
	52
	53	end architecture; No newline at end of file

lib/lpp/lpp_cna/APB_DAC.vhd +17 -20

                 rst     : in  std_logic;           --! Reset general du composant
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
-                DataIN : in std_logic_vector(15 downto 0);
                 Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
-                Readn   : out std_logic;
                 SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
                 SCLK    : out std_logic;           --! Horloge systeme du convertisseur
                 DATA    : out std_logic            --! Donn�e num�rique s�rialis�
 => apb_iobar(paddr, pmask));
             signal enable   : std_logic;
-            --signal flag_sd : std_logic;
+            signal Ready : std_logic;
             type DAC_ctrlr_Reg is record
-                 DAC_Enable  : std_logic_vector(0 downto 0);
+                 DAC_Cfg  : std_logic_vector(1 downto 0);
-            --     DAC_Data : std_logic_vector(15 downto 0);
+                 DAC_Data : std_logic_vector(15 downto 0);
             end record;
             signal Rec : DAC_ctrlr_Reg;
             begin
-            enable <= Rec.DAC_Enable(0);
+            enable <= Rec.DAC_Cfg(0);
-            --Rec.DAC_Cfg(1) <= flag_sd;
+            Rec.DAC_Cfg(1) <= Ready;
                 CONV0 : DacDriver
-                    generic map(cpt_serial)
+                    generic map (cpt_serial)
-                    port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Data);
+                    port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
                 process(rst,clk)
                 begin
                     if(rst='0')then
-                        --Rec.DAC_Data <=  (others => '0');
+                        Rec.DAC_Data <=  (others => '0');
-                        Rec.DAC_Enable(0) <= '0';
                     elsif(clk'event and clk='1')then
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    Rec.DAC_Enable(0) <= apbi.pwdata(0);
+                                    Rec.DAC_Cfg(0) <= apbi.pwdata(0);
-            --                    when "000001" =>
+                                when "000001" =>
-            --                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
+                                    Rec.DAC_Data <= apbi.pwdata(15 downto 0);
                                 when others =>
                                     null;
                             end case;
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    Rdata(31 downto 1) <= (others => '0');--X"ABCDEF5" & "00";
+                                    Rdata(31 downto 2) <= X"ABCDEF5" & "00";
-                                    Rdata(0 downto 0) <= Rec.DAC_Enable;
+                                    Rdata(1 downto 0) <= Rec.DAC_Cfg;
-             --                   when "000001" =>
+                                when "000001" =>
-             --                       Rdata(31 downto 16) <= X"FD18";
+                                    Rdata(31 downto 16) <= X"FD18";
-             --                       Rdata(15 downto 0) <= Rec.DAC_Data;
+                                    Rdata(15 downto 0) <= Rec.DAC_Data;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
-            Cal_EN <= Rec.DAC_Enable(0);
+            Cal_EN <= enable;
             end architecture;

lib/lpp/lpp_cna/DacDriver.vhd +6 -9

             --! Programme du Convertisseur Num�rique/Analogique
             entity DacDriver is
-              generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
+            generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
               port(
                 clk         : in std_logic;                        --! Horloge du composant
                 rst         : in std_logic;                        --! Reset general du composant
                 enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
-                Data_reg    : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
+                Data_C      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
                 SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
                 SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
-                Readn       : out std_logic;
+                Ready     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
                 Data        : out std_logic                        --! Donn�e num�rique s�rialis�
                 );
             end entity;
             architecture ar_DacDriver of DacDriver is
             signal s_SCLK      : std_logic;
-            signal s_SYNC    : std_logic;
+            signal Sended    : std_logic;
             begin
             Signal_sync : Gene_SYNC
-                port map (s_SCLK,rst,enable,s_SYNC);
+                port map (s_SCLK,rst,enable,Sended,SYNC);
             Serial : serialize
-                port map (clk,rst,s_SCLK,Data_reg,s_SYNC,Data);
+                port map (clk,rst,s_SCLK,Data_C,Sended,Ready,Data);
-            RenGEN : ReadFifo_GEN
-                port map (clk,rst,s_SYNC,Readn);
             SCLK        <= s_SCLK;
-            SYNC        <= s_SYNC;
             end architecture;

lib/lpp/lpp_cna/Gene_SYNC.vhd +7 -8

               port(
                 SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
                 enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-            --    OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
+                Sended : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
                 SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
                 );
             end Gene_SYNC;
                     if(raz='0')then
                         SYNC <= '0';
                         count <= 14;
-            --            OKAI_send <= '0';
+                        Sended <= '0';
                     elsif(SCLK' event and SCLK='1')then
                         if(enable='1')then
                             if(count=15)then
                                 SYNC <= '1';
-            --                    count <= count+1;
+                                count <= count+1;
-            --                elsif(count=16)then
+                            elsif(count=16)then
                                 count <= 0;
-            --                    SYNC <= '0';
+                                SYNC <= '0';
-            --                    OKAI_send <= '1';
+                                Sended <= '1';
                             else
                                 count <= count+1;
-                                SYNC <= '0';
+                                Sended <= '0';
-            --                    OKAI_send <= '0';
                             end if;
                         end if;

lib/lpp/lpp_cna/Serialize.vhd +9 -18

                 sclk    : in std_logic;                      --! Horloge Systeme
                 vectin  : in std_logic_vector(15 downto 0);  --! Vecteur d'entr�e
                 send    : in std_logic;                      --! Flag, Une nouvelle donn�e est pr�sente
-            --    sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
+                sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
                 Data    : out std_logic                      --! Donn�e num�rique s�rialis�
                 );
             end Serialize;
             architecture ar_Serialize of Serialize is
-            type etat is (attente,serialize,reg);
+            type etat is (attente,serialize);
             signal ect      : etat;
             signal vector_int   : std_logic_vector(16 downto 0);
             signal load         : std_logic;
             signal N            : integer range 0 to 16;
             signal CPT_ended    : std_logic:='0';
-            signal i            : std_logic;
             begin
                 process(clk,raz)
                         ect         <= attente;
                         vectin_reg  <= (others=> '0');
                         load        <= '0';
-                        i <= '1';
+                        sended      <= '1';
-            --            sended      <= '1';
                     elsif(clk'event and clk='1')then
                         vectin_reg <= vectin;
                         case ect is
                             when attente =>
                                 if (send='1') then
-            --                        sended  <= '0';
+                                    sended  <= '0';
-                                    if(i='1')then
+                                    load    <= '1';
-                                        i <= '0';
+                                    ect     <= serialize;
-                                        ect <= reg;
+                                else
-                                    else
+                                    ect <= attente;
-                                        load    <= '1';
-                                        ect     <= serialize;
-                                    end if;
                                 end if;
-                            when reg =>
-                                load    <= '1';
-                                ect <= serialize;
                             when serialize =>
                                 load <= '0';
                                 if(CPT_ended='1')then
                                     ect     <= attente;
-            --                        sended  <= '1';
+                                    sended  <= '1';
                                 end if;
                         end case;

lib/lpp/lpp_cna/lpp_cna.vhd +96 -108

@@ -1,108 +1,96
1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4	--	4	--
5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
8	-- (at your option) any later version.	8	-- (at your option) any later version.
9	--	9	--
10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
14	--	14	--
15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18	------------------------------------------------------------------------------	18	------------------------------------------------------------------------------
19	-- Author : Martin Morlot	19	-- Author : Martin Morlot
20	-- Mail : martin.morlot@lpp.polytechnique.fr	20	-- Mail : martin.morlot@lpp.polytechnique.fr
21	------------------------------------------------------------------------------	21	------------------------------------------------------------------------------
22	library ieee;	22	library ieee;
23	use ieee.std_logic_1164.all;	23	use ieee.std_logic_1164.all;
24	library grlib;	24	library grlib;
25	use grlib.amba.all;	25	use grlib.amba.all;
26	use std.textio.all;	26	use std.textio.all;
27	library lpp;	27	library lpp;
28	use lpp.lpp_amba.all;	28	use lpp.lpp_amba.all;
29		29
30	--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on	30	--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31		31
32	package lpp_cna is	32	package lpp_cna is
33		33
34	component APB_DAC is	34	component APB_DAC is
35	generic (	35	generic (
36	pindex : integer := 0;	36	pindex : integer := 0;
37	paddr : integer := 0;	37	paddr : integer := 0;
38	pmask : integer := 16#fff#;	38	pmask : integer := 16#fff#;
39	pirq : integer := 0;	39	pirq : integer := 0;
40	abits : integer := 8;	40	abits : integer := 8);
41	cpt_serial : integer := 6);	41	port (
42	port (	42	clk : in std_logic;
43	~~clk~~ : in std_logic;	43	rst : in std_logic;
44	rst : in std_logic;	44	apbi : in apb_slv_in_type;
45	apbi : in ~~apb_slv_in~~_type;	45	apbo : out apb_slv_out_type;
46	apbo : out apb_slv_out_type;	46	Cal_EN : out std_logic;
47	DataIN : in std_logic_vector(15 downto 0);	47	SYNC : out std_logic;
48	~~Cal_EN~~ : out std_logic;	48	SCLK : out std_logic;
49	~~Readn~~ : out std_logic;	49	DATA : out std_logic
50	SYNC : out std_logic;	50	);
51	SCLK : out std_logic;	51	end component;
52	DATA : out std_logic	52
53	);	53
54	end component;	54	component DacDriver is
55		55	generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
56		56	port(
57	component DacDriver is	57	clk : in std_logic;
58	generic(cpt_serial : integer := 6);	58	rst : in std_logic;
59	port(	59	enable : in std_logic;
60	~~clk~~ : in std_logic;	60	Data_C : in std_logic_vector(15 downto 0);
61	~~rst~~ : in std_logic;	61	SYNC : out std_logic;
62	~~enable~~ : in std_logic;	62	SCLK : out std_logic;
63	Data_reg : in std_logic_vector(15 downto 0);	63	Ready : out std_logic;
64	~~SYNC~~ : out std_logic;	64	Data : out std_logic
65	SCLK : out std_logic;	65	);
66	Readn : out std_logic;	66	end component;
67	Data : out std_logic	67
68	);	68
69	end component;	69	component Systeme_Clock is
70		70	generic(N :integer := 695);
71		71	port(
72	component Systeme_Clock is	72	clk, raz : in std_logic ;
73	generic(N :integer := 695);	73	sclk : out std_logic);
74	port(	74	end component;
75	clk, raz : in std_logic ;	75
76	clock : out std_logic);	76
77	end component;	77	component Gene_SYNC is
78		78	port(
79		79	SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
80	component Gene_SYNC is	80	enable : in std_logic; --! Autorise ou non l'utilisation du composant
81	port(	81	Sended : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
82	SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant	82	SYNC : out std_logic); --! Signal de synchronisation du convertisseur g�n�r�
83	enable : in std_logic; --! Autorise ou non l'utilisation du composant	83	end component;
84	-- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e	84
85	SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�	85
86	);	86	component Serialize is
87	end component;	87	port(
88		88	clk,raz : in std_logic;
89		89	sclk : in std_logic;
90	component Serialize is	90	vectin : in std_logic_vector(15 downto 0);
91	port(	91	send : in std_logic;
92	~~clk~~,~~raz~~ : in std_logic;	92	sended : out std_logic;
93	~~sclk~~ : in std_logic;	93	Data : out std_logic);
94	vectin : in std_logic_vector(15 downto 0);	94	end component;
95	send : in std_logic;	95
96	-- sended : out std_logic;	96	end; No newline at end of file
97	Data : out std_logic);
98	end component;
99
100	component ReadFifo_GEN is
101	port(
102	clk,raz : in std_logic;
103	SYNC : in std_logic;
104	Readn : out std_logic
105	);
106	end component;
107
108	end;

lib/lpp/lpp_memory/lpp_memory.vhd +11 0

@@ -135,6 +135,17 port(
135	);	135	);
136	end component;	136	end component;
137		137
		138	component Bridge is
		139	port(
		140	clk : in std_logic;
		141	raz : in std_logic;
		142	EmptyUp : in std_logic;
		143	FullDwn : in std_logic;
		144	WriteDwn : out std_logic;
		145	ReadUp : out std_logic
		146	);
		147	end component;
		148
138	component ssram_plugin is	149	component ssram_plugin is
139	generic (tech : integer := 0);	150	generic (tech : integer := 0);
140	port	151	port

lib/lpp/lpp_memory/vhdlsyn.txt +2 0

             lpp_memory.vhd
             lpp_FIFO.vhd
             FillFifo.vhd
+            Bridge.vhd
             APB_FIFO.vhd
             Bridge.vhd
             SSRAM_plugin.vhd
             lppFIFOx5.vhd
             lppFIFOxN.vhd

lib/lpp/lpp_cna/ReadFifo_GEN.vhd removed 0 -67

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