HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r270:4545cae6efef

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Jeandet Alexis -

r270:4545cae6efef alexis

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r270:4545cae6efef

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lib/lpp/lpp_cna/ReadFifo_GEN.vhd created 644 +67 0

@@ -0,0 +1,67
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	------------------------------------------------------------------------------
	22	library IEEE;
	23	use IEEE.numeric_std.all;
	24	use IEEE.std_logic_1164.all;
	25
	26	entity ReadFifo_GEN is
	27	port(
	28	clk,raz : in std_logic; --! Horloge et Reset du composant
	29	SYNC : in std_logic;
	30	Readn : out std_logic
	31	);
	32	end entity;
	33
	34
	35	architecture ar_ReadFifo_GEN of ReadFifo_GEN is
	36
	37	type etat is (eX,e0);
	38	signal ect : etat;
	39
	40	signal SYNC_reg : std_logic;
	41
	42	begin
	43	process(clk,raz)
	44	begin
	45	if(raz='0')then
	46	ect <= eX;
	47	Readn <= '1';
	48
	49	elsif(clk'event and clk='1')then
	50	SYNC_reg <= SYNC;
	51
	52	case ect is
	53	when eX =>
	54	if (SYNC_reg='0' and SYNC='1') then
	55	Readn <= '0';
	56	ect <= e0;
	57	end if;
	58
	59	when e0 =>
	60	Readn <= '1';
	61	ect <= eX;
	62
	63	end case;
	64	end if;
	65	end process;
	66
	67	end architecture; No newline at end of file

lib/lpp/lpp_memory/Bridge.vhd created 644 +53 0

@@ -0,0 +1,53
	1	-- Bridge.vhd
	2	library IEEE;
	3	use IEEE.std_logic_1164.all;
	4	use IEEE.numeric_std.all;
	5
	6	entity Bridge is
	7	port(
	8	clk : in std_logic;
	9	raz : in std_logic;
	10	EmptyUp : in std_logic;
	11	FullDwn : in std_logic;
	12	WriteDwn : out std_logic;
	13	ReadUp : out std_logic
	14	);
	15	end entity;
	16
	17
	18	architecture ar_Bridge of Bridge is
	19
	20	type etat is (e0,e1);
	21	signal ect : etat;
	22
	23	begin
	24
	25	process(clk,raz)
	26	begin
	27	if(raz='0')then
	28	WriteDwn <= '1';
	29	ReadUp <= '1';
	30	ect <= e0;
	31
	32	elsif(clk'event and clk='1')then
	33
	34	case ect is
	35
	36	when e0 =>
	37	WriteDwn <= '1';
	38	if(EmptyUp='0' and FullDwn='0')then
	39	ReadUp <= '0';
	40	ect <= e1;
	41	end if;
	42
	43	when e1 =>
	44	ReadUp <= '1';
	45	WriteDwn <= '0';
	46	ect <= e0;
	47
	48	end case;
	49
	50	end if;
	51	end process;
	52
	53	end architecture; No newline at end of file

LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c +1 -1

                 int i=0;
                 //int poub;
                 //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]);
-                while(i<count)
+                while(i<=count)
                 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE  full a 0  ALORS
                 {
                     //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);

lib/lpp/lpp_cna/APB_DAC.vhd +17 -12

                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
-                abits    : integer := 8);
+                abits    : integer := 8;
+                cpt_serial : integer := 6);
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
+                DataIN : in std_logic_vector(15 downto 0);
                 Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
+                Readn   : out std_logic;
                 SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
                 SCLK    : out std_logic;           --! Horloge systeme du convertisseur
                 DATA    : out std_logic            --! Donn�e num�rique s�rialis�
 => apb_iobar(paddr, pmask));
             signal enable   : std_logic;
-            signal flag_sd : std_logic;
+            signal Ready : std_logic;
             type DAC_ctrlr_Reg is record
                  DAC_Cfg  : std_logic_vector(1 downto 0);
-                 DAC_Data : std_logic_vector(15 downto 0);
+            --     DAC_Data : std_logic_vector(15 downto 0);
             end record;
             signal Rec : DAC_ctrlr_Reg;
             begin
             enable <= Rec.DAC_Cfg(0);
-            Rec.DAC_Cfg(1) <= flag_sd;
+            Rec.DAC_Cfg(1) <= Ready;
                 CONV0 : DacDriver
-                    port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
+                    generic map (cpt_serial)
+                    port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Ready,Data);
+            --        port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
                 process(rst,clk)
                 begin
                     if(rst='0')then
-                        Rec.DAC_Data <=  (others => '0');
+            --            Rec.DAC_Data <=  (others => '0');
                     elsif(clk'event and clk='1')then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                     Rec.DAC_Cfg(0) <= apbi.pwdata(0);
-                                when "000001" =>
+            --                    when "000001" =>
-                                    Rec.DAC_Data <= apbi.pwdata(15 downto 0);
+            --                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
                                 when others =>
                                     null;
                             end case;
                                 when "000000" =>
                                     Rdata(31 downto 2) <= X"ABCDEF5" & "00";
                                     Rdata(1 downto 0) <= Rec.DAC_Cfg;
-                                when "000001" =>
+            --                    when "000001" =>
-                                    Rdata(31 downto 16) <= X"FD18";
+            --                        Rdata(31 downto 16) <= X"FD18";
-                                    Rdata(15 downto 0) <= Rec.DAC_Data;
+            --                        Rdata(15 downto 0) <= Rec.DAC_Data;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
             Cal_EN <= enable;
-            end architecture;
+            end architecture;
  No newline at end of file

lib/lpp/lpp_cna/DacDriver.vhd +10 -7

             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
-            use work.Convertisseur_config.all;
             use lpp.lpp_cna.all;
             --! Programme du Convertisseur Num�rique/Analogique
             entity DacDriver is
+            generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
               port(
                 clk         : in std_logic;                        --! Horloge du composant
                 rst         : in std_logic;                        --! Reset general du composant
                 enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
-                Data_C      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
+                Data_IN      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
                 SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
                 SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
-                flag_sd     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
+                Readn       : out std_logic;
+                Ready     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
                 Data        : out std_logic                        --! Donn�e num�rique s�rialis�
                 );
             end entity;
             architecture ar_DacDriver of DacDriver is
             signal s_SCLK      : std_logic;
-            signal OKAI_send    : std_logic;
+            signal Send    : std_logic;
             begin
             SystemCLK : Systeme_Clock
-                generic map (nb_serial)
+                generic map (cpt_serial)
                 port map (clk,rst,s_SCLK);
             Signal_sync : Gene_SYNC
-                port map (s_SCLK,rst,enable,OKAI_send,SYNC);
+                port map (s_SCLK,rst,enable,Send,SYNC);
             Serial : serialize
-                port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
+                port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
+            RenGEN : ReadFifo_GEN
+                port map (clk,rst,Send,Readn);
             SCLK        <= s_SCLK;

lib/lpp/lpp_cna/Gene_SYNC.vhd +4 -4

               port(
                 SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
                 enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-                OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
+                Send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
                 SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
                 );
             end Gene_SYNC;
                     if(raz='0')then
                         SYNC <= '0';
                         count <= 14;
-                        OKAI_send <= '0';
+                        Send <= '0';
                     elsif(SCLK' event and SCLK='1')then
                         if(enable='1')then
                             elsif(count=16)then
                                 count <= 0;
                                 SYNC <= '0';
-                                OKAI_send <= '1';
+                                Send <= '1';
                             else
                                 count <= count+1;
-                                OKAI_send <= '0';
+                                Send <= '0';
                             end if;
                         end if;

lib/lpp/lpp_cna/lpp_cna.vhd +27 -15

                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
-                abits    : integer := 8);
+                abits    : integer := 8;
+                cpt_serial : integer := 6);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
-                Cal_EN  : out std_logic;
+                DataIN : in std_logic_vector(15 downto 0);
-                SYNC    : out std_logic;
+                Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
-                SCLK    : out std_logic;
+                Readn   : out std_logic;
+                SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
+                SCLK    : out std_logic;           --! Horloge systeme du convertisseur
                 DATA    : out std_logic
                 );
             end component;
             component DacDriver is
+            generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
                 port(
                     clk       : in std_logic;
                     rst         : in std_logic;
                     enable      : in std_logic;
-                    Data_C      : in std_logic_vector(15 downto 0);
+                    Data_IN      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
-                    SYNC        : out std_logic;
+                    SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
-                    SCLK        : out std_logic;
+                    SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
-                    flag_sd     : out std_logic;
+                    Readn       : out std_logic;
+                    Ready     : out std_logic;
                     Data        : out std_logic
                     );
             end component;
                 generic(N :integer := 695);
                 port(
                     clk, raz   : in std_logic ;
-                    clock      : out std_logic);
+                    sclk      : out std_logic);
             end component;
             component Gene_SYNC is
                 port(
-                    clk,raz     : in std_logic;
+                SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
-                    send     : in std_logic;
+                enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-                    Sysclk      : in std_logic;
+                Send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
-                    OKAI_send   : out std_logic;
+                SYNC : out std_logic);         --! Signal de synchronisation du convertisseur g�n�r�
-                    SYNC        : out std_logic);
             end component;
                 Data    : out std_logic);
             end component;
-            end;
+            component ReadFifo_GEN is
+              port(
+                clk,raz : in std_logic;                      --! Horloge et Reset du composant
+                SYNC : in std_logic;
+                Readn : out std_logic
+                );
+            end component;
+            end;
  No newline at end of file

lib/lpp/lpp_memory/lpp_memory.vhd +11 0

@@ -158,6 +158,17 port(
158	);	158	);
159	end component;	159	end component;
160		160
		161	component Bridge is
		162	port(
		163	clk : in std_logic;
		164	raz : in std_logic;
		165	EmptyUp : in std_logic;
		166	FullDwn : in std_logic;
		167	WriteDwn : out std_logic;
		168	ReadUp : out std_logic
		169	);
		170	end component;
		171
161	component ssram_plugin is	172	component ssram_plugin is
162	generic (tech : integer := 0);	173	generic (tech : integer := 0);
163	port	174	port

lib/lpp/lpp_cna/Convertisseur_config.vhd removed 0 -34

NO CONTENT: file was removed

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