@@ -0,0 +1,288 | |||
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1 | # | |
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2 | # Automatically generated make config: don't edit | |
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3 | # | |
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4 | ||
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5 | # | |
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6 | # Synthesis | |
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7 | # | |
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8 | # CONFIG_SYN_INFERRED is not set | |
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9 | # CONFIG_SYN_STRATIX is not set | |
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10 | # CONFIG_SYN_STRATIXII is not set | |
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11 | # CONFIG_SYN_STRATIXIII is not set | |
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12 | # CONFIG_SYN_CYCLONEIII is not set | |
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13 | # CONFIG_SYN_ALTERA is not set | |
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14 | # CONFIG_SYN_AXCEL is not set | |
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15 | # CONFIG_SYN_PROASIC is not set | |
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16 | # CONFIG_SYN_PROASICPLUS is not set | |
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17 | CONFIG_SYN_PROASIC3=y | |
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18 | # CONFIG_SYN_UT025CRH is not set | |
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19 | # CONFIG_SYN_ATC18 is not set | |
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20 | # CONFIG_SYN_ATC18RHA is not set | |
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21 | # CONFIG_SYN_CUSTOM1 is not set | |
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22 | # CONFIG_SYN_EASIC90 is not set | |
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23 | # CONFIG_SYN_IHP25 is not set | |
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24 | # CONFIG_SYN_IHP25RH is not set | |
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25 | # CONFIG_SYN_LATTICE is not set | |
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26 | # CONFIG_SYN_ECLIPSE is not set | |
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27 | # CONFIG_SYN_PEREGRINE is not set | |
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28 | # CONFIG_SYN_RH_LIB18T is not set | |
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29 | # CONFIG_SYN_RHUMC is not set | |
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30 | # CONFIG_SYN_SMIC13 is not set | |
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31 | # CONFIG_SYN_SPARTAN2 is not set | |
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32 | # CONFIG_SYN_SPARTAN3 is not set | |
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33 | # CONFIG_SYN_SPARTAN3E is not set | |
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34 | # CONFIG_SYN_VIRTEX is not set | |
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35 | # CONFIG_SYN_VIRTEXE is not set | |
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36 | # CONFIG_SYN_VIRTEX2 is not set | |
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37 | # CONFIG_SYN_VIRTEX4 is not set | |
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38 | # CONFIG_SYN_VIRTEX5 is not set | |
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39 | # CONFIG_SYN_UMC is not set | |
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40 | # CONFIG_SYN_TSMC90 is not set | |
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41 | # CONFIG_SYN_INFER_RAM is not set | |
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42 | # CONFIG_SYN_INFER_PADS is not set | |
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43 | # CONFIG_SYN_NO_ASYNC is not set | |
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44 | # CONFIG_SYN_SCAN is not set | |
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45 | ||
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46 | # | |
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47 | # Clock generation | |
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48 | # | |
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49 | # CONFIG_CLK_INFERRED is not set | |
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50 | # CONFIG_CLK_HCLKBUF is not set | |
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51 | # CONFIG_CLK_ALTDLL is not set | |
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52 | # CONFIG_CLK_LATDLL is not set | |
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53 | CONFIG_CLK_PRO3PLL=y | |
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54 | # CONFIG_CLK_LIB18T is not set | |
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55 | # CONFIG_CLK_RHUMC is not set | |
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56 | # CONFIG_CLK_CLKDLL is not set | |
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57 | # CONFIG_CLK_DCM is not set | |
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58 | CONFIG_CLK_MUL=2 | |
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59 | CONFIG_CLK_DIV=8 | |
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60 | CONFIG_OCLK_DIV=2 | |
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61 | # CONFIG_PCI_SYSCLK is not set | |
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62 | CONFIG_LEON3=y | |
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63 | CONFIG_PROC_NUM=1 | |
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64 | ||
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65 | # | |
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66 | # Processor | |
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67 | # | |
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68 | ||
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69 | # | |
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70 | # Integer unit | |
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71 | # | |
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72 | CONFIG_IU_NWINDOWS=8 | |
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73 | # CONFIG_IU_V8MULDIV is not set | |
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74 | # CONFIG_IU_SVT is not set | |
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75 | CONFIG_IU_LDELAY=1 | |
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76 | CONFIG_IU_WATCHPOINTS=0 | |
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77 | # CONFIG_PWD is not set | |
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78 | CONFIG_IU_RSTADDR=00000 | |
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79 | ||
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80 | # | |
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81 | # Floating-point unit | |
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82 | # | |
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83 | # CONFIG_FPU_ENABLE is not set | |
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84 | ||
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85 | # | |
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86 | # Cache system | |
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87 | # | |
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88 | CONFIG_ICACHE_ENABLE=y | |
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89 | CONFIG_ICACHE_ASSO1=y | |
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90 | # CONFIG_ICACHE_ASSO2 is not set | |
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91 | # CONFIG_ICACHE_ASSO3 is not set | |
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92 | # CONFIG_ICACHE_ASSO4 is not set | |
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93 | # CONFIG_ICACHE_SZ1 is not set | |
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94 | # CONFIG_ICACHE_SZ2 is not set | |
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95 | CONFIG_ICACHE_SZ4=y | |
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96 | # CONFIG_ICACHE_SZ8 is not set | |
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97 | # CONFIG_ICACHE_SZ16 is not set | |
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98 | # CONFIG_ICACHE_SZ32 is not set | |
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99 | # CONFIG_ICACHE_SZ64 is not set | |
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100 | # CONFIG_ICACHE_SZ128 is not set | |
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101 | # CONFIG_ICACHE_SZ256 is not set | |
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102 | # CONFIG_ICACHE_LZ16 is not set | |
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103 | CONFIG_ICACHE_LZ32=y | |
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104 | CONFIG_DCACHE_ENABLE=y | |
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105 | CONFIG_DCACHE_ASSO1=y | |
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106 | # CONFIG_DCACHE_ASSO2 is not set | |
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107 | # CONFIG_DCACHE_ASSO3 is not set | |
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108 | # CONFIG_DCACHE_ASSO4 is not set | |
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109 | # CONFIG_DCACHE_SZ1 is not set | |
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110 | # CONFIG_DCACHE_SZ2 is not set | |
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111 | CONFIG_DCACHE_SZ4=y | |
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112 | # CONFIG_DCACHE_SZ8 is not set | |
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113 | # CONFIG_DCACHE_SZ16 is not set | |
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114 | # CONFIG_DCACHE_SZ32 is not set | |
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115 | # CONFIG_DCACHE_SZ64 is not set | |
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116 | # CONFIG_DCACHE_SZ128 is not set | |
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117 | # CONFIG_DCACHE_SZ256 is not set | |
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118 | # CONFIG_DCACHE_LZ16 is not set | |
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119 | CONFIG_DCACHE_LZ32=y | |
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120 | # CONFIG_DCACHE_SNOOP is not set | |
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121 | CONFIG_CACHE_FIXED=0 | |
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122 | ||
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123 | # | |
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124 | # MMU | |
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125 | # | |
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126 | CONFIG_MMU_ENABLE=y | |
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127 | # CONFIG_MMU_COMBINED is not set | |
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128 | CONFIG_MMU_SPLIT=y | |
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129 | # CONFIG_MMU_REPARRAY is not set | |
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130 | CONFIG_MMU_REPINCREMENT=y | |
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131 | # CONFIG_MMU_I2 is not set | |
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132 | # CONFIG_MMU_I4 is not set | |
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133 | CONFIG_MMU_I8=y | |
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134 | # CONFIG_MMU_I16 is not set | |
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135 | # CONFIG_MMU_I32 is not set | |
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136 | # CONFIG_MMU_D2 is not set | |
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137 | # CONFIG_MMU_D4 is not set | |
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138 | CONFIG_MMU_D8=y | |
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139 | # CONFIG_MMU_D16 is not set | |
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140 | # CONFIG_MMU_D32 is not set | |
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141 | CONFIG_MMU_FASTWB=y | |
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142 | CONFIG_MMU_PAGE_4K=y | |
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143 | # CONFIG_MMU_PAGE_8K is not set | |
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144 | # CONFIG_MMU_PAGE_16K is not set | |
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145 | # CONFIG_MMU_PAGE_32K is not set | |
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146 | # CONFIG_MMU_PAGE_PROG is not set | |
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147 | ||
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148 | # | |
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149 | # Debug Support Unit | |
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150 | # | |
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151 | # CONFIG_DSU_ENABLE is not set | |
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152 | ||
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153 | # | |
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154 | # Fault-tolerance | |
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155 | # | |
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156 | ||
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157 | # | |
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158 | # VHDL debug settings | |
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159 | # | |
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160 | # CONFIG_IU_DISAS is not set | |
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161 | # CONFIG_DEBUG_PC32 is not set | |
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162 | ||
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163 | # | |
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164 | # AMBA configuration | |
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165 | # | |
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166 | CONFIG_AHB_DEFMST=0 | |
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167 | CONFIG_AHB_RROBIN=y | |
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168 | # CONFIG_AHB_SPLIT is not set | |
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169 | CONFIG_AHB_IOADDR=FFF | |
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170 | CONFIG_APB_HADDR=800 | |
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171 | # CONFIG_AHB_MON is not set | |
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172 | ||
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173 | # | |
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174 | # Debug Link | |
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175 | # | |
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176 | CONFIG_DSU_UART=y | |
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177 | # CONFIG_DSU_JTAG is not set | |
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178 | ||
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179 | # | |
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180 | # Peripherals | |
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181 | # | |
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182 | ||
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183 | # | |
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184 | # Memory controllers | |
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185 | # | |
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186 | ||
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187 | # | |
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188 | # 8/32-bit PROM/SRAM controller | |
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189 | # | |
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190 | CONFIG_SRCTRL=y | |
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191 | # CONFIG_SRCTRL_8BIT is not set | |
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192 | CONFIG_SRCTRL_PROMWS=3 | |
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193 | CONFIG_SRCTRL_RAMWS=0 | |
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194 | CONFIG_SRCTRL_IOWS=0 | |
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195 | # CONFIG_SRCTRL_RMW is not set | |
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196 | CONFIG_SRCTRL_SRBANKS1=y | |
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197 | # CONFIG_SRCTRL_SRBANKS2 is not set | |
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198 | # CONFIG_SRCTRL_SRBANKS3 is not set | |
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199 | # CONFIG_SRCTRL_SRBANKS4 is not set | |
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200 | # CONFIG_SRCTRL_SRBANKS5 is not set | |
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201 | # CONFIG_SRCTRL_BANKSZ0 is not set | |
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202 | # CONFIG_SRCTRL_BANKSZ1 is not set | |
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203 | # CONFIG_SRCTRL_BANKSZ2 is not set | |
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204 | # CONFIG_SRCTRL_BANKSZ3 is not set | |
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205 | # CONFIG_SRCTRL_BANKSZ4 is not set | |
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206 | # CONFIG_SRCTRL_BANKSZ5 is not set | |
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207 | # CONFIG_SRCTRL_BANKSZ6 is not set | |
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208 | # CONFIG_SRCTRL_BANKSZ7 is not set | |
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209 | # CONFIG_SRCTRL_BANKSZ8 is not set | |
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210 | # CONFIG_SRCTRL_BANKSZ9 is not set | |
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211 | # CONFIG_SRCTRL_BANKSZ10 is not set | |
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212 | # CONFIG_SRCTRL_BANKSZ11 is not set | |
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213 | # CONFIG_SRCTRL_BANKSZ12 is not set | |
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214 | # CONFIG_SRCTRL_BANKSZ13 is not set | |
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215 | CONFIG_SRCTRL_ROMASEL=19 | |
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216 | ||
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217 | # | |
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218 | # Leon2 memory controller | |
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219 | # | |
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220 | CONFIG_MCTRL_LEON2=y | |
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221 | # CONFIG_MCTRL_8BIT is not set | |
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222 | # CONFIG_MCTRL_16BIT is not set | |
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223 | # CONFIG_MCTRL_5CS is not set | |
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224 | # CONFIG_MCTRL_SDRAM is not set | |
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225 | ||
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226 | # | |
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227 | # PC133 SDRAM controller | |
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228 | # | |
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229 | # CONFIG_SDCTRL is not set | |
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230 | ||
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231 | # | |
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232 | # On-chip RAM/ROM | |
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233 | # | |
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234 | # CONFIG_AHBROM_ENABLE is not set | |
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235 | # CONFIG_AHBRAM_ENABLE is not set | |
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236 | ||
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237 | # | |
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238 | # Ethernet | |
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239 | # | |
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240 | # CONFIG_GRETH_ENABLE is not set | |
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241 | ||
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242 | # | |
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243 | # CAN | |
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244 | # | |
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245 | # CONFIG_CAN_ENABLE is not set | |
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246 | ||
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247 | # | |
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248 | # PCI | |
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249 | # | |
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250 | # CONFIG_PCI_SIMPLE_TARGET is not set | |
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251 | # CONFIG_PCI_MASTER_TARGET is not set | |
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252 | # CONFIG_PCI_ARBITER is not set | |
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253 | # CONFIG_PCI_TRACE is not set | |
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254 | ||
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255 | # | |
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256 | # Spacewire | |
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257 | # | |
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258 | # CONFIG_SPW_ENABLE is not set | |
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259 | ||
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260 | # | |
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261 | # UARTs, timers and irq control | |
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262 | # | |
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263 | CONFIG_UART1_ENABLE=y | |
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264 | # CONFIG_UA1_FIFO1 is not set | |
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265 | # CONFIG_UA1_FIFO2 is not set | |
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266 | CONFIG_UA1_FIFO4=y | |
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267 | # CONFIG_UA1_FIFO8 is not set | |
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268 | # CONFIG_UA1_FIFO16 is not set | |
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269 | # CONFIG_UA1_FIFO32 is not set | |
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270 | # CONFIG_UART2_ENABLE is not set | |
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271 | CONFIG_IRQ3_ENABLE=y | |
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272 | # CONFIG_IRQ3_SEC is not set | |
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273 | CONFIG_GPT_ENABLE=y | |
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274 | CONFIG_GPT_NTIM=2 | |
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275 | CONFIG_GPT_SW=8 | |
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276 | CONFIG_GPT_TW=32 | |
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277 | CONFIG_GPT_IRQ=8 | |
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278 | CONFIG_GPT_SEPIRQ=y | |
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279 | CONFIG_GPT_WDOGEN=y | |
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280 | CONFIG_GPT_WDOG=FFFF | |
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281 | CONFIG_GRGPIO_ENABLE=y | |
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282 | CONFIG_GRGPIO_WIDTH=8 | |
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283 | CONFIG_GRGPIO_IMASK=0000 | |
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284 | ||
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285 | # | |
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286 | # VHDL Debugging | |
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287 | # | |
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288 | # CONFIG_DEBUG_UART is not set |
@@ -0,0 +1,50 | |||
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1 | #GRLIB=../.. | |
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2 | VHDLIB=../.. | |
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3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
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4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
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5 | TOP=leon3mp | |
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6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |
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7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |
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8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |
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9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |
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10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |
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11 | EFFORT=high | |
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12 | XSTOPT= | |
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13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
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14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
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15 | VHDLSYNFILES=config.vhd leon3mp.vhd | |
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16 | #VHDLSIMFILES=testbench.vhd | |
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17 | #SIMTOP=testbench | |
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18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
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19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |
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20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |
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21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |
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22 | CLEAN=soft-clean | |
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23 | ||
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24 | TECHLIBS = proasic3e | |
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25 | ||
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26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |
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27 | tmtc openchip hynix ihp gleichmann micron usbhc | |
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28 | ||
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29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |
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30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |
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31 | ./amba_lcd_16x2_ctrlr \ | |
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32 | ./general_purpose/lpp_AMR \ | |
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33 | ./general_purpose/lpp_balise \ | |
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34 | ./general_purpose/lpp_delay \ | |
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35 | ./lpp_bootloader \ | |
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36 | ./lpp_cna \ | |
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37 | ./lpp_uart \ | |
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38 | ./lpp_usb \ | |
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39 | ||
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40 | FILESKIP = i2cmst.vhd \ | |
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41 | APB_MULTI_DIODE.vhd \ | |
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42 | APB_MULTI_DIODE.vhd \ | |
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43 | Top_MatrixSpec.vhd \ | |
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44 | APB_FFT.vhd | |
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45 | ||
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46 | include $(GRLIB)/bin/Makefile | |
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47 | include $(GRLIB)/software/leon3/Makefile | |
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48 | ||
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49 | ################## project specific targets ########################## | |
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50 |
@@ -0,0 +1,182 | |||
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1 | ----------------------------------------------------------------------------- | |
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2 | -- LEON3 Demonstration design test bench configuration | |
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3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 2 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | ------------------------------------------------------------------------------ | |
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15 | ||
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16 | ||
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17 | library techmap; | |
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18 | use techmap.gencomp.all; | |
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19 | ||
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20 | package config is | |
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21 | ||
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22 | ||
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23 | -- Technology and synthesis options | |
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24 | constant CFG_FABTECH : integer := apa3e; | |
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25 | constant CFG_MEMTECH : integer := apa3e; | |
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26 | constant CFG_PADTECH : integer := inferred; | |
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27 | constant CFG_NOASYNC : integer := 0; | |
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28 | constant CFG_SCAN : integer := 0; | |
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29 | ||
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30 | -- Clock generator | |
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31 | constant CFG_CLKTECH : integer := inferred; | |
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32 | constant CFG_CLKMUL : integer := (1); | |
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33 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz | |
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34 | constant CFG_OCLKDIV : integer := (1); | |
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35 | constant CFG_PCIDLL : integer := 0; | |
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36 | constant CFG_PCISYSCLK: integer := 0; | |
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37 | constant CFG_CLK_NOFB : integer := 0; | |
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38 | ||
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39 | -- LEON3 processor core | |
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40 | constant CFG_LEON3 : integer := 1; | |
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41 | constant CFG_NCPU : integer := (1); | |
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42 | --constant CFG_NWIN : integer := (7); -- PLE | |
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43 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC | |
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44 | constant CFG_V8 : integer := 0; | |
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45 | constant CFG_MAC : integer := 0; | |
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46 | constant CFG_SVT : integer := 0; | |
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47 | constant CFG_RSTADDR : integer := 16#00000#; | |
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48 | constant CFG_LDDEL : integer := (1); | |
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49 | constant CFG_NWP : integer := (0); | |
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50 | constant CFG_PWD : integer := 1*2; | |
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51 | constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist | |
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52 | --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE | |
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53 | constant CFG_GRFPUSH : integer := 0; | |
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54 | constant CFG_ICEN : integer := 1; | |
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55 | constant CFG_ISETS : integer := 1; | |
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56 | constant CFG_ISETSZ : integer := 4; | |
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57 | constant CFG_ILINE : integer := 4; | |
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58 | constant CFG_IREPL : integer := 0; | |
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59 | constant CFG_ILOCK : integer := 0; | |
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60 | constant CFG_ILRAMEN : integer := 0; | |
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61 | constant CFG_ILRAMADDR: integer := 16#8E#; | |
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62 | constant CFG_ILRAMSZ : integer := 1; | |
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63 | constant CFG_DCEN : integer := 1; | |
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64 | constant CFG_DSETS : integer := 1; | |
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65 | constant CFG_DSETSZ : integer := 4; | |
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66 | constant CFG_DLINE : integer := 4; | |
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67 | constant CFG_DREPL : integer := 0; | |
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68 | constant CFG_DLOCK : integer := 0; | |
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69 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; | |
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70 | constant CFG_DFIXED : integer := 16#00F3#; | |
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71 | constant CFG_DLRAMEN : integer := 0; | |
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72 | constant CFG_DLRAMADDR: integer := 16#8F#; | |
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73 | constant CFG_DLRAMSZ : integer := 1; | |
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74 | constant CFG_MMUEN : integer := 0; | |
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75 | constant CFG_ITLBNUM : integer := 2; | |
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76 | constant CFG_DTLBNUM : integer := 2; | |
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77 | constant CFG_TLB_TYPE : integer := 1 + 0*2; | |
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78 | constant CFG_TLB_REP : integer := 1; | |
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79 | constant CFG_DSU : integer := 1; | |
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80 | constant CFG_ITBSZ : integer := 0; | |
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81 | constant CFG_ATBSZ : integer := 0; | |
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82 | constant CFG_LEON3FT_EN : integer := 0; | |
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83 | constant CFG_IUFT_EN : integer := 0; | |
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84 | constant CFG_FPUFT_EN : integer := 0; | |
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85 | constant CFG_RF_ERRINJ : integer := 0; | |
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86 | constant CFG_CACHE_FT_EN : integer := 0; | |
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87 | constant CFG_CACHE_ERRINJ : integer := 0; | |
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88 | constant CFG_LEON3_NETLIST: integer := 0; | |
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89 | constant CFG_DISAS : integer := 0 + 0; | |
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90 | constant CFG_PCLOW : integer := 2; | |
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91 | ||
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92 | -- AMBA settings | |
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93 | constant CFG_DEFMST : integer := (0); | |
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94 | constant CFG_RROBIN : integer := 1; | |
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95 | constant CFG_SPLIT : integer := 0; | |
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96 | constant CFG_AHBIO : integer := 16#FFF#; | |
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97 | constant CFG_APBADDR : integer := 16#800#; | |
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98 | constant CFG_AHB_MON : integer := 0; | |
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99 | constant CFG_AHB_MONERR : integer := 0; | |
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100 | constant CFG_AHB_MONWAR : integer := 0; | |
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101 | ||
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102 | -- DSU UART | |
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103 | constant CFG_AHB_UART : integer := 1; | |
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104 | ||
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105 | -- JTAG based DSU interface | |
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106 | constant CFG_AHB_JTAG : integer := 0; | |
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107 | ||
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108 | -- Ethernet DSU | |
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109 | constant CFG_DSU_ETH : integer := 0 + 0; | |
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110 | constant CFG_ETH_BUF : integer := 1; | |
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111 | constant CFG_ETH_IPM : integer := 16#C0A8#; | |
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112 | constant CFG_ETH_IPL : integer := 16#0033#; | |
|
113 | constant CFG_ETH_ENM : integer := 16#00007A#; | |
|
114 | constant CFG_ETH_ENL : integer := 16#CC0001#; | |
|
115 | ||
|
116 | -- LEON2 memory controller | |
|
117 | constant CFG_MCTRL_LEON2 : integer := 1; | |
|
118 | constant CFG_MCTRL_RAM8BIT : integer := 0; | |
|
119 | constant CFG_MCTRL_RAM16BIT : integer := 0; | |
|
120 | constant CFG_MCTRL_5CS : integer := 0; | |
|
121 | constant CFG_MCTRL_SDEN : integer := 0; | |
|
122 | constant CFG_MCTRL_SEPBUS : integer := 0; | |
|
123 | constant CFG_MCTRL_INVCLK : integer := 0; | |
|
124 | constant CFG_MCTRL_SD64 : integer := 0; | |
|
125 | constant CFG_MCTRL_PAGE : integer := 0 + 0; | |
|
126 | ||
|
127 | -- SSRAM controller | |
|
128 | constant CFG_SSCTRL : integer := 0; | |
|
129 | constant CFG_SSCTRLP16 : integer := 0; | |
|
130 | ||
|
131 | -- AHB ROM | |
|
132 | constant CFG_AHBROMEN : integer := 0; | |
|
133 | constant CFG_AHBROPIP : integer := 0; | |
|
134 | constant CFG_AHBRODDR : integer := 16#000#; | |
|
135 | constant CFG_ROMADDR : integer := 16#000#; | |
|
136 | constant CFG_ROMMASK : integer := 16#E00# + 16#000#; | |
|
137 | ||
|
138 | -- AHB RAM | |
|
139 | constant CFG_AHBRAMEN : integer := 0; | |
|
140 | constant CFG_AHBRSZ : integer := 1; | |
|
141 | constant CFG_AHBRADDR : integer := 16#A00#; | |
|
142 | ||
|
143 | -- Gaisler Ethernet core | |
|
144 | constant CFG_GRETH : integer := 0; | |
|
145 | constant CFG_GRETH1G : integer := 0; | |
|
146 | constant CFG_ETH_FIFO : integer := 8; | |
|
147 | ||
|
148 | -- CAN 2.0 interface | |
|
149 | constant CFG_CAN : integer := 0; | |
|
150 | constant CFG_CANIO : integer := 16#0#; | |
|
151 | constant CFG_CANIRQ : integer := 0; | |
|
152 | constant CFG_CANLOOP : integer := 0; | |
|
153 | constant CFG_CAN_SYNCRST : integer := 0; | |
|
154 | constant CFG_CANFT : integer := 0; | |
|
155 | ||
|
156 | -- UART 1 | |
|
157 | constant CFG_UART1_ENABLE : integer := 1; | |
|
158 | constant CFG_UART1_FIFO : integer := 1; | |
|
159 | ||
|
160 | -- LEON3 interrupt controller | |
|
161 | constant CFG_IRQ3_ENABLE : integer := 1; | |
|
162 | ||
|
163 | -- Modular timer | |
|
164 | constant CFG_GPT_ENABLE : integer := 1; | |
|
165 | constant CFG_GPT_NTIM : integer := (3); | |
|
166 | constant CFG_GPT_SW : integer := (8); | |
|
167 | constant CFG_GPT_TW : integer := (32); | |
|
168 | constant CFG_GPT_IRQ : integer := (8); | |
|
169 | constant CFG_GPT_SEPIRQ : integer := 1; | |
|
170 | constant CFG_GPT_WDOGEN : integer := 0; | |
|
171 | constant CFG_GPT_WDOG : integer := 16#0#; | |
|
172 | ||
|
173 | -- GPIO port | |
|
174 | constant CFG_GRGPIO_ENABLE : integer := 1; | |
|
175 | constant CFG_GRGPIO_IMASK : integer := 16#0000#; | |
|
176 | constant CFG_GRGPIO_WIDTH : integer := (7); | |
|
177 | ||
|
178 | -- GRLIB debugging | |
|
179 | constant CFG_DUART : integer := 0; | |
|
180 | ||
|
181 | ||
|
182 | end; |
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1 | ----------------------------------------------------------------------------- | |
|
2 | -- LEON3 Demonstration design | |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | ||
|
20 | ||
|
21 | LIBRARY ieee; | |
|
22 | USE ieee.std_logic_1164.ALL; | |
|
23 | LIBRARY grlib; | |
|
24 | USE grlib.amba.ALL; | |
|
25 | USE grlib.stdlib.ALL; | |
|
26 | LIBRARY techmap; | |
|
27 | USE techmap.gencomp.ALL; | |
|
28 | LIBRARY gaisler; | |
|
29 | USE gaisler.memctrl.ALL; | |
|
30 | USE gaisler.leon3.ALL; | |
|
31 | USE gaisler.uart.ALL; | |
|
32 | USE gaisler.misc.ALL; | |
|
33 | USE gaisler.spacewire.ALL; -- PLE | |
|
34 | LIBRARY esa; | |
|
35 | USE esa.memoryctrl.ALL; | |
|
36 | USE work.config.ALL; | |
|
37 | LIBRARY lpp; | |
|
38 | USE lpp.lpp_memory.ALL; | |
|
39 | USE lpp.lpp_ad_conv.ALL; | |
|
40 | USE lpp.lpp_lfr_pkg.ALL; | |
|
41 | USE lpp.iir_filter.ALL; | |
|
42 | USE lpp.general_purpose.ALL; | |
|
43 | USE lpp.lpp_lfr_time_management.ALL; | |
|
44 | ||
|
45 | ENTITY leon3mp IS | |
|
46 | GENERIC ( | |
|
47 | fabtech : INTEGER := CFG_FABTECH; | |
|
48 | memtech : INTEGER := CFG_MEMTECH; | |
|
49 | padtech : INTEGER := CFG_PADTECH; | |
|
50 | clktech : INTEGER := CFG_CLKTECH; | |
|
51 | disas : INTEGER := CFG_DISAS; -- Enable disassembly to console | |
|
52 | dbguart : INTEGER := CFG_DUART; -- Print UART on console | |
|
53 | pclow : INTEGER := CFG_PCLOW | |
|
54 | ); | |
|
55 | PORT ( | |
|
56 | clk100MHz : IN STD_ULOGIC; | |
|
57 | clk49_152MHz : IN STD_ULOGIC; | |
|
58 | reset : IN STD_ULOGIC; | |
|
59 | ||
|
60 | errorn : OUT STD_ULOGIC; | |
|
61 | ||
|
62 | -- UART AHB --------------------------------------------------------------- | |
|
63 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
|
64 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
|
65 | ||
|
66 | -- UART APB --------------------------------------------------------------- | |
|
67 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
|
68 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
|
69 | ||
|
70 | -- RAM -------------------------------------------------------------------- | |
|
71 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
|
72 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
73 | nSRAM_BE0 : OUT STD_LOGIC; | |
|
74 | nSRAM_BE1 : OUT STD_LOGIC; | |
|
75 | nSRAM_BE2 : OUT STD_LOGIC; | |
|
76 | nSRAM_BE3 : OUT STD_LOGIC; | |
|
77 | nSRAM_WE : OUT STD_LOGIC; | |
|
78 | nSRAM_CE : OUT STD_LOGIC; | |
|
79 | nSRAM_OE : OUT STD_LOGIC; | |
|
80 | ||
|
81 | -- SPW -------------------------------------------------------------------- | |
|
82 | spw1_din : IN STD_LOGIC; -- PLE | |
|
83 | spw1_sin : IN STD_LOGIC; -- PLE | |
|
84 | spw1_dout : OUT STD_LOGIC; -- PLE | |
|
85 | spw1_sout : OUT STD_LOGIC; -- PLE | |
|
86 | ||
|
87 | spw2_din : IN STD_LOGIC; -- JCPE --TODO | |
|
88 | spw2_sin : IN STD_LOGIC; -- JCPE --TODO | |
|
89 | spw2_dout : OUT STD_LOGIC; -- JCPE --TODO | |
|
90 | spw2_sout : OUT STD_LOGIC; -- JCPE --TODO | |
|
91 | ||
|
92 | -- ADC -------------------------------------------------------------------- | |
|
93 | bias_fail_sw : OUT STD_LOGIC; | |
|
94 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
95 | ADC_smpclk : OUT STD_LOGIC; | |
|
96 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
|
97 | ||
|
98 | --------------------------------------------------------------------------- | |
|
99 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) | |
|
100 | ); | |
|
101 | END; | |
|
102 | ||
|
103 | ARCHITECTURE Behavioral OF leon3mp IS | |
|
104 | ||
|
105 | --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | |
|
106 | -- CFG_GRETH+CFG_AHB_JTAG; | |
|
107 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ | |
|
108 | CFG_AHB_UART | |
|
109 | +2; | |
|
110 | -- 1 is for the SpaceWire module grspw, which is a master | |
|
111 | -- 1 is for the LFR | |
|
112 | ||
|
113 | CONSTANT maxahbm : INTEGER := maxahbmsp; | |
|
114 | ||
|
115 | --Clk & Rst g�n� | |
|
116 | SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
117 | SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
118 | SIGNAL resetnl : STD_ULOGIC; | |
|
119 | SIGNAL clk2x : STD_ULOGIC; | |
|
120 | SIGNAL lclk2x : STD_ULOGIC; | |
|
121 | SIGNAL lclk25MHz : STD_ULOGIC; | |
|
122 | SIGNAL lclk50MHz : STD_ULOGIC; | |
|
123 | SIGNAL lclk100MHz : STD_ULOGIC; | |
|
124 | SIGNAL clkm : STD_ULOGIC; | |
|
125 | SIGNAL rstn : STD_ULOGIC; | |
|
126 | SIGNAL rstraw : STD_ULOGIC; | |
|
127 | SIGNAL pciclk : STD_ULOGIC; | |
|
128 | SIGNAL sdclkl : STD_ULOGIC; | |
|
129 | SIGNAL cgi : clkgen_in_type; | |
|
130 | SIGNAL cgo : clkgen_out_type; | |
|
131 | --- AHB / APB | |
|
132 | SIGNAL apbi : apb_slv_in_type; | |
|
133 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
|
134 | SIGNAL ahbsi : ahb_slv_in_type; | |
|
135 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
|
136 | SIGNAL ahbmi : ahb_mst_in_type; | |
|
137 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
|
138 | --UART | |
|
139 | SIGNAL ahbuarti : uart_in_type; | |
|
140 | SIGNAL ahbuarto : uart_out_type; | |
|
141 | SIGNAL apbuarti : uart_in_type; | |
|
142 | SIGNAL apbuarto : uart_out_type; | |
|
143 | --MEM CTRLR | |
|
144 | SIGNAL memi : memory_in_type; | |
|
145 | SIGNAL memo : memory_out_type; | |
|
146 | SIGNAL wpo : wprot_out_type; | |
|
147 | SIGNAL sdo : sdram_out_type; | |
|
148 | SIGNAL ramcs : STD_ULOGIC; | |
|
149 | --IRQ | |
|
150 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
|
151 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
|
152 | --Timer | |
|
153 | SIGNAL gpti : gptimer_in_type; | |
|
154 | SIGNAL gpto : gptimer_out_type; | |
|
155 | --GPIO | |
|
156 | SIGNAL gpioi : gpio_in_type; | |
|
157 | SIGNAL gpioo : gpio_out_type; | |
|
158 | --DSU | |
|
159 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
|
160 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
|
161 | SIGNAL dsui : dsu_in_type; | |
|
162 | SIGNAL dsuo : dsu_out_type; | |
|
163 | ||
|
164 | --------------------------------------------------------------------- | |
|
165 | --- AJOUT TEST ------------------------Signaux---------------------- | |
|
166 | --------------------------------------------------------------------- | |
|
167 | ||
|
168 | --------------------------------------------------------------------- | |
|
169 | CONSTANT IOAEN : INTEGER := CFG_CAN; | |
|
170 | CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz | |
|
171 | ||
|
172 | -- time management signal | |
|
173 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
174 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
175 | ||
|
176 | -- Spacewire signals | |
|
177 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE | |
|
178 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE | |
|
179 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE | |
|
180 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
|
181 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
|
182 | SIGNAL spw_clk : STD_LOGIC; | |
|
183 | SIGNAL swni : grspw_in_type; -- PLE | |
|
184 | SIGNAL swno : grspw_out_type; -- PLE | |
|
185 | SIGNAL clkmn : STD_ULOGIC; -- PLE | |
|
186 | SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 | |
|
187 | ||
|
188 | -- AD Converter RHF1401 | |
|
189 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
|
190 | SIGNAL sample_val : STD_LOGIC; | |
|
191 | ----------------------------------------------------------------------------- | |
|
192 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
193 | ||
|
194 | BEGIN | |
|
195 | ||
|
196 | ||
|
197 | ---------------------------------------------------------------------- | |
|
198 | --- Reset and Clock generation ------------------------------------- | |
|
199 | ---------------------------------------------------------------------- | |
|
200 | ||
|
201 | vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); | |
|
202 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | |
|
203 | ||
|
204 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
|
205 | ||
|
206 | ||
|
207 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); | |
|
208 | ||
|
209 | clkgen0 : clkgen -- clock generator | |
|
210 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
|
211 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) | |
|
212 | PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
|
213 | ||
|
214 | PROCESS(lclk100MHz) | |
|
215 | BEGIN | |
|
216 | IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN | |
|
217 | lclk50MHz <= NOT lclk50MHz; | |
|
218 | END IF; | |
|
219 | END PROCESS; | |
|
220 | ||
|
221 | PROCESS(lclk50MHz) | |
|
222 | BEGIN | |
|
223 | IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN | |
|
224 | lclk25MHz <= NOT lclk25MHz; | |
|
225 | END IF; | |
|
226 | END PROCESS; | |
|
227 | ||
|
228 | lclk2x <= lclk50MHz; | |
|
229 | spw_clk <= lclk50MHz; | |
|
230 | ||
|
231 | ---------------------------------------------------------------------- | |
|
232 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
|
233 | ---------------------------------------------------------------------- | |
|
234 | ||
|
235 | l3 : IF CFG_LEON3 = 1 GENERATE | |
|
236 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
|
237 | u0 : leon3s -- LEON3 processor | |
|
238 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
|
239 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
|
240 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
|
241 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
|
242 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
|
243 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
|
244 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
|
245 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
|
246 | END GENERATE; | |
|
247 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
|
248 | ||
|
249 | dsugen : IF CFG_DSU = 1 GENERATE | |
|
250 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
|
251 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
|
252 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
|
253 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
|
254 | dsui.enable <= '1'; | |
|
255 | dsui.break <= '0'; | |
|
256 | led(2) <= dsuo.active; | |
|
257 | END GENERATE; | |
|
258 | END GENERATE; | |
|
259 | ||
|
260 | nodsu : IF CFG_DSU = 0 GENERATE | |
|
261 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; | |
|
262 | END GENERATE; | |
|
263 | ||
|
264 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
|
265 | irqctrl0 : irqmp -- interrupt controller | |
|
266 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
|
267 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
|
268 | END GENERATE; | |
|
269 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
|
270 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
|
271 | irqi(i).irl <= "0000"; | |
|
272 | END GENERATE; | |
|
273 | apbo(2) <= apb_none; | |
|
274 | END GENERATE; | |
|
275 | ||
|
276 | ---------------------------------------------------------------------- | |
|
277 | --- Memory controllers --------------------------------------------- | |
|
278 | ---------------------------------------------------------------------- | |
|
279 | memctrlr : mctrl GENERIC MAP ( | |
|
280 | hindex => 0, | |
|
281 | pindex => 0, | |
|
282 | paddr => 0, | |
|
283 | srbanks => 1 | |
|
284 | ) | |
|
285 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
|
286 | ||
|
287 | memi.brdyn <= '1'; | |
|
288 | memi.bexcn <= '1'; | |
|
289 | memi.writen <= '1'; | |
|
290 | memi.wrn <= "1111"; | |
|
291 | memi.bwidth <= "10"; | |
|
292 | ||
|
293 | bdr : FOR i IN 0 TO 3 GENERATE | |
|
294 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
|
295 | PORT MAP ( | |
|
296 | data(31-i*8 DOWNTO 24-i*8), | |
|
297 | memo.data(31-i*8 DOWNTO 24-i*8), | |
|
298 | memo.bdrive(i), | |
|
299 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
|
300 | END GENERATE; | |
|
301 | ||
|
302 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
|
303 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
|
304 | ||
|
305 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); | |
|
306 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
|
307 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
|
308 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
|
309 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
|
310 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
|
311 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
|
312 | ||
|
313 | ---------------------------------------------------------------------- | |
|
314 | --- AHB CONTROLLER ------------------------------------------------- | |
|
315 | ---------------------------------------------------------------------- | |
|
316 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
|
317 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
|
318 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
|
319 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
|
320 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
|
321 | ||
|
322 | ---------------------------------------------------------------------- | |
|
323 | --- AHB UART ------------------------------------------------------- | |
|
324 | ---------------------------------------------------------------------- | |
|
325 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
|
326 | dcom0 : ahbuart | |
|
327 | GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) | |
|
328 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); | |
|
329 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
|
330 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
|
331 | led(0) <= NOT ahbuarti.rxd; | |
|
332 | led(1) <= NOT ahbuarto.txd; | |
|
333 | END GENERATE; | |
|
334 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
|
335 | ||
|
336 | ---------------------------------------------------------------------- | |
|
337 | --- APB Bridge ----------------------------------------------------- | |
|
338 | ---------------------------------------------------------------------- | |
|
339 | apb0 : apbctrl -- AHB/APB bridge | |
|
340 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
|
341 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
|
342 | ||
|
343 | ---------------------------------------------------------------------- | |
|
344 | --- GPT Timer ------------------------------------------------------ | |
|
345 | ---------------------------------------------------------------------- | |
|
346 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
|
347 | timer0 : gptimer -- timer unit | |
|
348 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
|
349 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
|
350 | nbits => CFG_GPT_TW) | |
|
351 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
|
352 | gpti.dhalt <= dsuo.tstop; | |
|
353 | gpti.extclk <= '0'; | |
|
354 | END GENERATE; | |
|
355 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
|
356 | ||
|
357 | ||
|
358 | ---------------------------------------------------------------------- | |
|
359 | --- APB UART ------------------------------------------------------- | |
|
360 | ---------------------------------------------------------------------- | |
|
361 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
|
362 | uart1 : apbuart -- UART 1 | |
|
363 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
|
364 | fifosize => CFG_UART1_FIFO) | |
|
365 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
|
366 | apbuarti.rxd <= urxd1; | |
|
367 | apbuarti.extclk <= '0'; | |
|
368 | utxd1 <= apbuarto.txd; | |
|
369 | apbuarti.ctsn <= '0'; | |
|
370 | END GENERATE; | |
|
371 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
|
372 | ||
|
373 | ------------------------------------------------------------------------------- | |
|
374 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
|
375 | ------------------------------------------------------------------------------- | |
|
376 | apb_lfr_time_management_1: apb_lfr_time_management | |
|
377 | GENERIC MAP ( | |
|
378 | pindex => 6, | |
|
379 | paddr => 6, | |
|
380 | pmask => 16#fff#, | |
|
381 | pirq => 12) | |
|
382 | PORT MAP ( | |
|
383 | clk25MHz => clkm, | |
|
384 | clk49_152MHz => clk49_152MHz, | |
|
385 | resetn => rstn, | |
|
386 | grspw_tick => swno.tickout, | |
|
387 | apbi => apbi, | |
|
388 | apbo => apbo(6), | |
|
389 | coarse_time => coarse_time, | |
|
390 | fine_time => fine_time); | |
|
391 | ||
|
392 | ----------------------------------------------------------------------- | |
|
393 | --- SpaceWire -------------------------------------------------------- | |
|
394 | ----------------------------------------------------------------------- | |
|
395 | ||
|
396 | spw_rxtxclk <= spw_clk; | |
|
397 | spw_rxclkn <= NOT spw_rxtxclk; | |
|
398 | ||
|
399 | -- PADS for SPW1 | |
|
400 | spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) | |
|
401 | PORT MAP (spw1_din, dtmp(0)); | |
|
402 | spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) | |
|
403 | PORT MAP (spw1_sin, stmp(0)); | |
|
404 | spw1_txd_pad : outpad GENERIC MAP (tech => padtech) | |
|
405 | PORT MAP (spw1_dout, swno.d(0)); | |
|
406 | spw1_txs_pad : outpad GENERIC MAP (tech => padtech) | |
|
407 | PORT MAP (spw1_sout, swno.s(0)); | |
|
408 | -- PADS FOR SPW2 | |
|
409 | spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) | |
|
410 | PORT MAP (spw2_din, dtmp(1)); | |
|
411 | spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) | |
|
412 | PORT MAP (spw2_sin, stmp(1)); | |
|
413 | spw2_txd_pad : outpad GENERIC MAP (tech => padtech) | |
|
414 | PORT MAP (spw2_dout, swno.d(1)); | |
|
415 | spw2_txs_pad : outpad GENERIC MAP (tech => padtech) | |
|
416 | PORT MAP (spw2_sout, swno.s(1)); | |
|
417 | ||
|
418 | -- GRSPW PHY | |
|
419 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
|
420 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
|
421 | spw_phy0 : grspw_phy | |
|
422 | GENERIC MAP( | |
|
423 | tech => fabtech, | |
|
424 | rxclkbuftype => 1, | |
|
425 | scantest => 0) | |
|
426 | PORT MAP( | |
|
427 | rxrst => swno.rxrst, | |
|
428 | di => dtmp(j), | |
|
429 | si => stmp(j), | |
|
430 | rxclko => spw_rxclk(j), | |
|
431 | do => swni.d(j), | |
|
432 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
|
433 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
|
434 | END GENERATE spw_inputloop; | |
|
435 | ||
|
436 | -- SPW core | |
|
437 | sw0 : grspwm | |
|
438 | GENERIC MAP( | |
|
439 | tech => apa3e, | |
|
440 | hindex => 1, | |
|
441 | pindex => 5, | |
|
442 | paddr => 5, | |
|
443 | pirq => 11, | |
|
444 | sysfreq => 25000, -- CPU_FREQ | |
|
445 | rmap => 1, | |
|
446 | rmapcrc => 1, | |
|
447 | fifosize1 => 16, | |
|
448 | fifosize2 => 16, | |
|
449 | rxclkbuftype => 1, | |
|
450 | rxunaligned => 0, | |
|
451 | rmapbufs => 4, | |
|
452 | ft => 0, | |
|
453 | netlist => 0, | |
|
454 | ports => 2, | |
|
455 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
|
456 | memtech => apa3e, | |
|
457 | destkey => 2, | |
|
458 | spwcore => 1 | |
|
459 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
|
460 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
|
461 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
|
462 | ) | |
|
463 | PORT MAP(rstn, clkm, spw_rxclk(0), | |
|
464 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
|
465 | ahbmi, ahbmo(1), apbi, apbo(5), | |
|
466 | swni, swno); | |
|
467 | ||
|
468 | swni.tickin <= '0'; | |
|
469 | swni.rmapen <= '1'; | |
|
470 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz | |
|
471 | swni.tickinraw <= '0'; | |
|
472 | swni.timein <= (OTHERS => '0'); | |
|
473 | swni.dcrstval <= (OTHERS => '0'); | |
|
474 | swni.timerrstval <= (OTHERS => '0'); | |
|
475 | ||
|
476 | ------------------------------------------------------------------------------- | |
|
477 | -- LFR | |
|
478 | ------------------------------------------------------------------------------- | |
|
479 | lpp_lfr_1 : lpp_lfr | |
|
480 | GENERIC MAP ( | |
|
481 | Mem_use => use_RAM, | |
|
482 | nb_data_by_buffer_size => 32, | |
|
483 | nb_word_by_buffer_size => 30, | |
|
484 | nb_snapshot_param_size => 32, | |
|
485 | delta_vector_size => 32, | |
|
486 | delta_vector_size_f0_2 => 7, -- log2(96) | |
|
487 | pindex => 15, | |
|
488 | paddr => 15, | |
|
489 | pmask => 16#fff#, | |
|
490 | pirq_ms => 6, | |
|
491 | pirq_wfp => 14, | |
|
492 | hindex => 2, | |
|
493 | top_lfr_version => X"00000002") | |
|
494 | PORT MAP ( | |
|
495 | clk => clkm, | |
|
496 | rstn => rstn, | |
|
497 | sample_B => sample(2 DOWNTO 0), | |
|
498 | sample_E => sample(7 DOWNTO 3), | |
|
499 | sample_val => sample_val, | |
|
500 | apbi => apbi, | |
|
501 | apbo => apbo(15), | |
|
502 | ahbi => ahbmi, | |
|
503 | ahbo => ahbmo(2), | |
|
504 | coarse_time => coarse_time, | |
|
505 | fine_time => fine_time, | |
|
506 | data_shaping_BW => bias_fail_sw); | |
|
507 | ||
|
508 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |
|
509 | GENERIC MAP ( | |
|
510 | ChanelCount => 8, | |
|
511 | ncycle_cnv_high => 79, | |
|
512 | ncycle_cnv => 500) | |
|
513 | PORT MAP ( | |
|
514 | cnv_clk => clk49_152MHz, | |
|
515 | cnv_rstn => rstn, | |
|
516 | cnv => ADC_smpclk, | |
|
517 | clk => clkm, | |
|
518 | rstn => rstn, | |
|
519 | ADC_data => ADC_data, | |
|
520 | ADC_nOE => ADC_OEB_bar_CH, | |
|
521 | sample => sample, | |
|
522 | sample_val => sample_val); | |
|
523 | ||
|
524 | END Behavioral; |
@@ -0,0 +1,98 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ------------------------------------------------------------------------------- | |
|
23 | -- 1.0 - initial version | |
|
24 | ------------------------------------------------------------------------------- | |
|
25 | ||
|
26 | LIBRARY ieee; | |
|
27 | USE ieee.std_logic_1164.ALL; | |
|
28 | USE ieee.numeric_std.ALL; | |
|
29 | ||
|
30 | ||
|
31 | ENTITY lpp_waveform_dma_genvalid IS | |
|
32 | PORT ( | |
|
33 | HCLK : IN STD_LOGIC; | |
|
34 | HRESETn : IN STD_LOGIC; | |
|
35 | run : IN STD_LOGIC; | |
|
36 | ||
|
37 | valid_in : IN STD_LOGIC; | |
|
38 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
39 | ||
|
40 | ack_in : IN STD_LOGIC; | |
|
41 | valid_out : OUT STD_LOGIC; | |
|
42 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
43 | error : OUT STD_LOGIC | |
|
44 | ); | |
|
45 | END; | |
|
46 | ||
|
47 | ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS | |
|
48 | TYPE state_fsm IS (IDLE, VALID); | |
|
49 | SIGNAL state : state_fsm; | |
|
50 | BEGIN | |
|
51 | ||
|
52 | FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) | |
|
53 | BEGIN | |
|
54 | IF HRESETn = '0' THEN | |
|
55 | state <= IDLE; | |
|
56 | valid_out <= '0'; | |
|
57 | error <= '0'; | |
|
58 | time_out <= (OTHERS => '0'); | |
|
59 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
|
60 | CASE state IS | |
|
61 | WHEN IDLE => | |
|
62 | ||
|
63 | valid_out <= '0'; | |
|
64 | error <= '0'; | |
|
65 | IF run = '1' AND valid_in = '1' THEN | |
|
66 | state <= VALID; | |
|
67 | valid_out <= '1'; | |
|
68 | time_out <= time_in; | |
|
69 | END IF; | |
|
70 | ||
|
71 | WHEN VALID => | |
|
72 | IF run = '0' THEN | |
|
73 | state <= IDLE; | |
|
74 | valid_out <= '0'; | |
|
75 | error <= '0'; | |
|
76 | ELSE | |
|
77 | IF valid_in = '1' THEN | |
|
78 | IF ack_in = '1' THEN | |
|
79 | state <= VALID; | |
|
80 | valid_out <= '1'; | |
|
81 | time_out <= time_in; | |
|
82 | ELSE | |
|
83 | state <= IDLE; | |
|
84 | error <= '1'; | |
|
85 | valid_out <= '0'; | |
|
86 | END IF; | |
|
87 | ELSIF ack_in = '1' THEN | |
|
88 | state <= IDLE; | |
|
89 | valid_out <= '0'; | |
|
90 | END IF; | |
|
91 | END IF; | |
|
92 | ||
|
93 | WHEN OTHERS => NULL; | |
|
94 | END CASE; | |
|
95 | END IF; | |
|
96 | END PROCESS FSM_SELECT_ADDRESS; | |
|
97 | ||
|
98 | END Behavioral; |
@@ -0,0 +1,117 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Jean-christophe PELLION | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.std_logic_1164.ALL; | |
|
24 | USE IEEE.numeric_std.ALL; | |
|
25 | ||
|
26 | LIBRARY lpp; | |
|
27 | USE lpp.lpp_waveform_pkg.ALL; | |
|
28 | USE lpp.general_purpose.ALL; | |
|
29 | ||
|
30 | ENTITY lpp_waveform_fifo_arbiter_reg IS | |
|
31 | GENERIC( | |
|
32 | data_size : INTEGER; | |
|
33 | data_nb : INTEGER | |
|
34 | ); | |
|
35 | PORT( | |
|
36 | clk : IN STD_LOGIC; | |
|
37 | rstn : IN STD_LOGIC; | |
|
38 | --------------------------------------------------------------------------- | |
|
39 | run : IN STD_LOGIC; | |
|
40 | ||
|
41 | max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); | |
|
42 | ||
|
43 | enable : IN STD_LOGIC; | |
|
44 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); | |
|
45 | ||
|
46 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
47 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) | |
|
48 | ); | |
|
49 | END ENTITY; | |
|
50 | ||
|
51 | ||
|
52 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS | |
|
53 | ||
|
54 | TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |
|
55 | SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0); | |
|
56 | ||
|
57 | SIGNAL reg_sel : INTEGER; | |
|
58 | SIGNAL reg_sel_s : INTEGER; | |
|
59 | ||
|
60 | BEGIN | |
|
61 | ||
|
62 | all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE | |
|
63 | PROCESS (clk, rstn) | |
|
64 | BEGIN -- PROCESS | |
|
65 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
66 | reg(I) <= 0; | |
|
67 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
68 | IF run = '0' THEN | |
|
69 | reg(I) <= 0; | |
|
70 | ELSE | |
|
71 | IF sel(I) = '1' THEN | |
|
72 | reg(I) <= reg_sel_s; | |
|
73 | END IF; | |
|
74 | END IF; | |
|
75 | END IF; | |
|
76 | END PROCESS; | |
|
77 | END GENERATE all_reg; | |
|
78 | ||
|
79 | reg_sel <= reg(0) WHEN sel(0) = '1' ELSE | |
|
80 | reg(1) WHEN sel(1) = '1' ELSE | |
|
81 | reg(2) WHEN sel(2) = '1' ELSE | |
|
82 | reg(3); | |
|
83 | ||
|
84 | reg_sel_s <= reg_sel WHEN enable = '0' ELSE | |
|
85 | reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE | |
|
86 | 0; | |
|
87 | ||
|
88 | data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size)); | |
|
89 | data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size)); | |
|
90 | ||
|
91 | END ARCHITECTURE; | |
|
92 | ||
|
93 | ||
|
94 | ||
|
95 | ||
|
96 | ||
|
97 | ||
|
98 | ||
|
99 | ||
|
100 | ||
|
101 | ||
|
102 | ||
|
103 | ||
|
104 | ||
|
105 | ||
|
106 | ||
|
107 | ||
|
108 | ||
|
109 | ||
|
110 | ||
|
111 | ||
|
112 | ||
|
113 | ||
|
114 | ||
|
115 | ||
|
116 | ||
|
117 |
@@ -0,0 +1,143 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Jean-christophe PELLION | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.std_logic_1164.ALL; | |
|
24 | USE IEEE.numeric_std.ALL; | |
|
25 | LIBRARY lpp; | |
|
26 | USE lpp.lpp_memory.ALL; | |
|
27 | USE lpp.iir_filter.ALL; | |
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |
|
29 | ||
|
30 | LIBRARY techmap; | |
|
31 | USE techmap.gencomp.ALL; | |
|
32 | ||
|
33 | ENTITY lpp_waveform_fifo_latencyCorrection IS | |
|
34 | GENERIC( | |
|
35 | tech : INTEGER := 0 | |
|
36 | ); | |
|
37 | PORT( | |
|
38 | clk : IN STD_LOGIC; | |
|
39 | rstn : IN STD_LOGIC; | |
|
40 | --------------------------------------------------------------------------- | |
|
41 | run : IN STD_LOGIC; | |
|
42 | ||
|
43 | --------------------------------------------------------------------------- | |
|
44 | empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b | |
|
45 | empty : OUT STD_LOGIC; | |
|
46 | data_ren : IN STD_LOGIC; | |
|
47 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
48 | --------------------------------------------------------------------------- | |
|
49 | empty_almost_fifo : IN STD_LOGIC; | |
|
50 | empty_fifo : IN STD_LOGIC; | |
|
51 | data_ren_fifo : OUT STD_LOGIC; | |
|
52 | rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
53 | ); | |
|
54 | END ENTITY; | |
|
55 | ||
|
56 | ||
|
57 | ARCHITECTURE ar_lpp_waveform_fifo_latencyCorrection OF lpp_waveform_fifo_latencyCorrection IS | |
|
58 | SIGNAL data_ren_fifo_s : STD_LOGIC; | |
|
59 | -- SIGNAL rdata_s : STD_LOGIC; | |
|
60 | ||
|
61 | SIGNAL reg_full : STD_LOGIC; | |
|
62 | SIGNAL empty_almost_reg : STD_LOGIC; | |
|
63 | BEGIN | |
|
64 | ||
|
65 | PROCESS (clk, rstn) | |
|
66 | BEGIN -- PROCESS | |
|
67 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
68 | empty_almost_reg <= '1'; | |
|
69 | empty <= '1'; | |
|
70 | data_ren_fifo_s <= '1'; | |
|
71 | rdata <= (OTHERS => '0'); | |
|
72 | reg_full <= '0'; | |
|
73 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
74 | IF run = '0' THEN | |
|
75 | empty_almost_reg <= '1'; | |
|
76 | empty <= '1'; | |
|
77 | data_ren_fifo_s <= '1'; | |
|
78 | rdata <= (OTHERS => '0'); | |
|
79 | reg_full <= '0'; | |
|
80 | ELSE | |
|
81 | ||
|
82 | IF data_ren_fifo_s = '0' THEN | |
|
83 | reg_full <= '1'; | |
|
84 | ELSIF data_ren = '0' THEN | |
|
85 | reg_full <= '0'; | |
|
86 | END IF; | |
|
87 | ||
|
88 | IF data_ren_fifo_s = '0' THEN | |
|
89 | rdata <= rdata_fifo; | |
|
90 | END IF; | |
|
91 | ||
|
92 | IF (reg_full = '0' OR data_ren = '0') AND empty_fifo = '0' THEN | |
|
93 | data_ren_fifo_s <= '0'; | |
|
94 | ELSE | |
|
95 | data_ren_fifo_s <= '1'; | |
|
96 | END IF; | |
|
97 | ||
|
98 | IF empty_fifo = '1' AND ((reg_full = '0') OR ( data_ren = '0')) THEN | |
|
99 | empty <= '1'; | |
|
100 | ELSE | |
|
101 | empty <= '0'; | |
|
102 | END IF; | |
|
103 | ||
|
104 | IF empty_almost_reg = '0' AND data_ren = '0' AND empty_almost_fifo = '1' THEN | |
|
105 | empty_almost_reg <= '1'; | |
|
106 | ELSIF empty_almost_reg = '1' AND empty_almost_fifo = '0' THEN | |
|
107 | empty_almost_reg <= '0'; | |
|
108 | END IF; | |
|
109 | ||
|
110 | END IF; | |
|
111 | END IF; | |
|
112 | END PROCESS; | |
|
113 | ||
|
114 | empty_almost <= empty_almost_reg; | |
|
115 | data_ren_fifo <= data_ren_fifo_s; | |
|
116 | ||
|
117 | END ARCHITECTURE; | |
|
118 | ||
|
119 | ||
|
120 | ||
|
121 | ||
|
122 | ||
|
123 | ||
|
124 | ||
|
125 | ||
|
126 | ||
|
127 | ||
|
128 | ||
|
129 | ||
|
130 | ||
|
131 | ||
|
132 | ||
|
133 | ||
|
134 | ||
|
135 | ||
|
136 | ||
|
137 | ||
|
138 | ||
|
139 | ||
|
140 | ||
|
141 | ||
|
142 | ||
|
143 |
@@ -0,0 +1,188 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Jean-christophe PELLION | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.std_logic_1164.ALL; | |
|
24 | USE IEEE.numeric_std.ALL; | |
|
25 | LIBRARY lpp; | |
|
26 | USE lpp.lpp_memory.ALL; | |
|
27 | USE lpp.iir_filter.ALL; | |
|
28 | USE lpp.lpp_waveform_pkg.ALL; | |
|
29 | ||
|
30 | LIBRARY techmap; | |
|
31 | USE techmap.gencomp.ALL; | |
|
32 | ||
|
33 | ENTITY lpp_waveform_fifo_withoutLatency IS | |
|
34 | GENERIC( | |
|
35 | tech : INTEGER := 0 | |
|
36 | ); | |
|
37 | PORT( | |
|
38 | clk : IN STD_LOGIC; | |
|
39 | rstn : IN STD_LOGIC; | |
|
40 | --------------------------------------------------------------------------- | |
|
41 | run : IN STD_LOGIC; | |
|
42 | ||
|
43 | --------------------------------------------------------------------------- | |
|
44 | empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |
|
45 | empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
46 | data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
47 | rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
48 | rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
49 | rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
50 | rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
51 | ||
|
52 | --------------------------------------------------------------------------- | |
|
53 | full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b | |
|
54 | full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
55 | data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
56 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
57 | ); | |
|
58 | END ENTITY; | |
|
59 | ||
|
60 | ||
|
61 | ARCHITECTURE ar_lpp_waveform_fifo_withoutLatency OF lpp_waveform_fifo_withoutLatency IS | |
|
62 | SIGNAL empty_almost_s : STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
63 | SIGNAL empty_s : STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
64 | SIGNAL data_ren_s : STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
65 | SIGNAL rdata_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
66 | ||
|
67 | BEGIN | |
|
68 | ||
|
69 | ||
|
70 | ||
|
71 | ||
|
72 | lpp_waveform_fifo_latencyCorrection_0: lpp_waveform_fifo_latencyCorrection | |
|
73 | GENERIC MAP ( | |
|
74 | tech => tech) | |
|
75 | PORT MAP ( | |
|
76 | clk => clk, | |
|
77 | rstn => rstn, | |
|
78 | run => run, | |
|
79 | ||
|
80 | empty_almost => empty_almost(0), | |
|
81 | empty => empty(0), | |
|
82 | data_ren => data_ren(0), | |
|
83 | rdata => rdata_0, | |
|
84 | ||
|
85 | empty_almost_fifo => empty_almost_s(0), | |
|
86 | empty_fifo => empty_s(0), | |
|
87 | data_ren_fifo => data_ren_s(0), | |
|
88 | rdata_fifo => rdata_s); | |
|
89 | ||
|
90 | lpp_waveform_fifo_latencyCorrection_1: lpp_waveform_fifo_latencyCorrection | |
|
91 | GENERIC MAP ( | |
|
92 | tech => tech) | |
|
93 | PORT MAP ( | |
|
94 | clk => clk, | |
|
95 | rstn => rstn, | |
|
96 | run => run, | |
|
97 | ||
|
98 | empty_almost => empty_almost(1), | |
|
99 | empty => empty(1), | |
|
100 | data_ren => data_ren(1), | |
|
101 | rdata => rdata_1, | |
|
102 | ||
|
103 | empty_almost_fifo => empty_almost_s(1), | |
|
104 | empty_fifo => empty_s(1), | |
|
105 | data_ren_fifo => data_ren_s(1), | |
|
106 | rdata_fifo => rdata_s); | |
|
107 | ||
|
108 | lpp_waveform_fifo_latencyCorrection_2: lpp_waveform_fifo_latencyCorrection | |
|
109 | GENERIC MAP ( | |
|
110 | tech => tech) | |
|
111 | PORT MAP ( | |
|
112 | clk => clk, | |
|
113 | rstn => rstn, | |
|
114 | run => run, | |
|
115 | ||
|
116 | empty_almost => empty_almost(2), | |
|
117 | empty => empty(2), | |
|
118 | data_ren => data_ren(2), | |
|
119 | rdata => rdata_2, | |
|
120 | ||
|
121 | empty_almost_fifo => empty_almost_s(2), | |
|
122 | empty_fifo => empty_s(2), | |
|
123 | data_ren_fifo => data_ren_s(2), | |
|
124 | rdata_fifo => rdata_s); | |
|
125 | ||
|
126 | lpp_waveform_fifo_latencyCorrection_3: lpp_waveform_fifo_latencyCorrection | |
|
127 | GENERIC MAP ( | |
|
128 | tech => tech) | |
|
129 | PORT MAP ( | |
|
130 | clk => clk, | |
|
131 | rstn => rstn, | |
|
132 | run => run, | |
|
133 | ||
|
134 | empty_almost => empty_almost(3), | |
|
135 | empty => empty(3), | |
|
136 | data_ren => data_ren(3), | |
|
137 | rdata => rdata_3, | |
|
138 | ||
|
139 | empty_almost_fifo => empty_almost_s(3), | |
|
140 | empty_fifo => empty_s(3), | |
|
141 | data_ren_fifo => data_ren_s(3), | |
|
142 | rdata_fifo => rdata_s); | |
|
143 | ||
|
144 | lpp_waveform_fifo_1: lpp_waveform_fifo | |
|
145 | GENERIC MAP ( | |
|
146 | tech => tech) | |
|
147 | PORT MAP ( | |
|
148 | clk => clk, | |
|
149 | rstn => rstn, | |
|
150 | run => run, | |
|
151 | ||
|
152 | empty_almost => empty_almost_s, | |
|
153 | empty => empty_s, | |
|
154 | data_ren => data_ren_s, | |
|
155 | rdata => rdata_s, | |
|
156 | ||
|
157 | full_almost => full_almost, | |
|
158 | full => full, | |
|
159 | data_wen => data_wen, | |
|
160 | wdata => wdata); | |
|
161 | ||
|
162 | END ARCHITECTURE; | |
|
163 | ||
|
164 | ||
|
165 | ||
|
166 | ||
|
167 | ||
|
168 | ||
|
169 | ||
|
170 | ||
|
171 | ||
|
172 | ||
|
173 | ||
|
174 | ||
|
175 | ||
|
176 | ||
|
177 | ||
|
178 | ||
|
179 | ||
|
180 | ||
|
181 | ||
|
182 | ||
|
183 | ||
|
184 | ||
|
185 | ||
|
186 | ||
|
187 | ||
|
188 |
@@ -49,6 +49,8 ARCHITECTURE Behavioral OF lfr_time_mana | |||
|
49 | 49 | |
|
50 | 50 | SIGNAL nb_time_code_missing : INTEGER; |
|
51 | 51 | SIGNAL coarse_time_s : INTEGER; |
|
52 | ||
|
53 | SIGNAL new_coarsetime_s : STD_LOGIC; | |
|
52 | 54 | |
|
53 | 55 | BEGIN |
|
54 | 56 | |
@@ -72,9 +74,15 BEGIN | |||
|
72 | 74 | coarse_time_s <= 0; |
|
73 | 75 | coarse_time_new <= '0'; |
|
74 | 76 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
77 | IF new_coarsetime = '1' THEN | |
|
78 | new_coarsetime_s <= '1'; | |
|
79 | ELSIF new_timecode = '1' THEN | |
|
80 | new_coarsetime_s <= '0'; | |
|
81 | END IF; | |
|
82 | ||
|
75 | 83 |
|
|
76 | 84 | coarse_time_new <= '1'; |
|
77 | IF new_coarsetime = '1' THEN | |
|
85 | IF new_coarsetime_s = '1' THEN | |
|
78 | 86 | coarse_time_s <= to_integer(unsigned(coarsetime_reg)); |
|
79 | 87 | ELSE |
|
80 | 88 | coarse_time_s <= coarse_time_s + 1; |
@@ -131,6 +131,7 PACKAGE lpp_dma_pkg IS | |||
|
131 | 131 | send : IN STD_LOGIC; |
|
132 | 132 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 133 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
134 | ren : OUT STD_LOGIC; | |
|
134 | 135 | send_ok : OUT STD_LOGIC; |
|
135 | 136 | send_ko : OUT STD_LOGIC); |
|
136 | 137 | END COMPONENT; |
@@ -167,8 +167,10 BEGIN -- beh | |||
|
167 | 167 | |
|
168 | 168 | DMAIn.Data <= data; |
|
169 | 169 | |
|
170 | ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |
|
171 | '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE | |
|
170 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |
|
171 | -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE | |
|
172 | -- '1'; | |
|
173 | ren <= '0' WHEN state = SEND_DATA ELSE | |
|
172 | 174 | '1'; |
|
173 | ||
|
174 | END beh; No newline at end of file | |
|
175 | ||
|
176 | END beh; |
@@ -48,8 +48,8 ENTITY lpp_dma_send_1word IS | |||
|
48 | 48 | -- |
|
49 | 49 | send : IN STD_LOGIC; |
|
50 | 50 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
51 | ||
|
52 | 51 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
52 | ren : OUT STD_LOGIC; | |
|
53 | 53 | -- |
|
54 | 54 | send_ok : OUT STD_LOGIC; |
|
55 | 55 | send_ko : OUT STD_LOGIC |
@@ -79,7 +79,9 BEGIN -- beh | |||
|
79 | 79 | send_ok <= '0'; |
|
80 | 80 | send_ko <= '0'; |
|
81 | 81 | DMAIn.Lock <= '0'; |
|
82 | ren <= '1'; | |
|
82 | 83 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
84 | ren <= '1'; | |
|
83 | 85 | CASE state IS |
|
84 | 86 | WHEN IDLE => |
|
85 | 87 | DMAIn.Store <= '1'; |
@@ -97,6 +99,7 BEGIN -- beh | |||
|
97 | 99 | DMAIn.Request <= '0'; |
|
98 | 100 | DMAIn.Store <= '0'; |
|
99 | 101 | state <= SEND_DATA; |
|
102 | ren <= '0'; | |
|
100 | 103 | END IF; |
|
101 | 104 | WHEN SEND_DATA => |
|
102 | 105 | IF DMAOut.Fault = '1' THEN |
@@ -106,9 +109,9 BEGIN -- beh | |||
|
106 | 109 | ELSIF DMAOut.Ready = '1' THEN |
|
107 | 110 | DMAIn.Request <= '0'; |
|
108 | 111 | DMAIn.Store <= '0'; |
|
109 | send_ok <= '1'; | |
|
110 | send_ko <= '0'; | |
|
111 | state <= IDLE; | |
|
112 | send_ok <= '1'; | |
|
113 | send_ko <= '0'; | |
|
114 | state <= IDLE; | |
|
112 | 115 | END IF; |
|
113 | 116 | WHEN ERROR0 => |
|
114 | 117 | state <= ERROR1; |
@@ -82,6 +82,7 ARCHITECTURE Behavioral OF lpp_dma_singl | |||
|
82 | 82 | |
|
83 | 83 | SIGNAL single_send_ok : STD_LOGIC; |
|
84 | 84 | SIGNAL single_send_ko : STD_LOGIC; |
|
85 | SIGNAL single_ren : STD_LOGIC; | |
|
85 | 86 | ----------------------------------------------------------------------------- |
|
86 | 87 | -- SEND SINGLE MODULE |
|
87 | 88 | SIGNAL burst_dmai : DMA_In_Type; |
@@ -112,16 +113,26 BEGIN | |||
|
112 | 113 | AHBIn => AHB_Master_In, |
|
113 | 114 | AHBOut => AHB_Master_Out); |
|
114 | 115 | ----------------------------------------------------------------------------- |
|
115 | ||
|
116 | ||
|
117 | ----------------------------------------------------------------------------- | |
|
118 | ----------------------------------------------------------------------------- | |
|
119 | -- LE PROBLEME EST LA !!!!! | |
|
120 | ----------------------------------------------------------------------------- | |
|
121 | ----------------------------------------------------------------------------- | |
|
122 | -- C'est le signal valid_burst qui n'est pas assez long. | |
|
123 | ----------------------------------------------------------------------------- | |
|
116 | 124 | single_send <= send WHEN valid_burst = '0' ELSE '0'; |
|
117 | 125 | burst_send <= send WHEN valid_burst = '1' ELSE '0'; |
|
118 | 126 | DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; |
|
119 | 127 | |
|
120 | done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE | |
|
121 |
|
|
|
128 | -- TODO : verifier | |
|
129 | done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko; | |
|
130 | --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE | |
|
131 | -- burst_send_ok OR burst_send_ko; | |
|
122 | 132 | |
|
123 | ren <= burst_ren WHEN valid_burst = '1' ELSE | |
|
124 | NOT single_send_ok; | |
|
133 | --ren <= burst_ren WHEN valid_burst = '1' ELSE | |
|
134 | -- NOT single_send_ok; | |
|
135 | ren <= burst_ren AND single_ren; | |
|
125 | 136 | |
|
126 | 137 | ----------------------------------------------------------------------------- |
|
127 | 138 | -- SEND 1 word by DMA |
@@ -136,6 +147,7 BEGIN | |||
|
136 | 147 | send => single_send, |
|
137 | 148 | address => address, |
|
138 | 149 | data => data, |
|
150 | ren => single_ren, | |
|
139 | 151 | |
|
140 | 152 | send_ok => single_send_ok, -- TODO |
|
141 | 153 | send_ko => single_send_ko -- TODO |
@@ -26,9 +26,10 ENTITY lpp_lfr IS | |||
|
26 | 26 | GENERIC ( |
|
27 | 27 | Mem_use : INTEGER := use_RAM; |
|
28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
|
29 | 30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | 31 | delta_vector_size : INTEGER := 20; |
|
31 |
delta_vector_size_f0_2 : INTEGER := |
|
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
|
32 | 33 | |
|
33 | 34 | pindex : INTEGER := 4; |
|
34 | 35 | paddr : INTEGER := 4; |
@@ -36,7 +37,9 ENTITY lpp_lfr IS | |||
|
36 | 37 | pirq_ms : INTEGER := 0; |
|
37 | 38 | pirq_wfp : INTEGER := 1; |
|
38 | 39 | |
|
39 | hindex : INTEGER := 2 | |
|
40 | hindex : INTEGER := 2; | |
|
41 | ||
|
42 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
40 | 43 | |
|
41 | 44 | ); |
|
42 | 45 | PORT ( |
@@ -120,6 +123,7 ARCHITECTURE beh OF lpp_lfr IS | |||
|
120 | 123 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
121 | 124 | |
|
122 | 125 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
126 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
123 | 127 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
124 | 128 | SIGNAL enable_f0 : STD_LOGIC; |
|
125 | 129 | SIGNAL enable_f1 : STD_LOGIC; |
@@ -186,7 +190,18 ARCHITECTURE beh OF lpp_lfr IS | |||
|
186 | 190 | SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | 191 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
188 | 192 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
189 | ||
|
193 | ||
|
194 | ----------------------------------------------------------------------------- | |
|
195 | -- DMA_REG | |
|
196 | ----------------------------------------------------------------------------- | |
|
197 | SIGNAL ongoing_reg : STD_LOGIC; | |
|
198 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
199 | SIGNAL dma_send_reg : STD_LOGIC; | |
|
200 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
|
201 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
202 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
203 | ||
|
204 | ||
|
190 | 205 | ----------------------------------------------------------------------------- |
|
191 | 206 | -- DMA |
|
192 | 207 | ----------------------------------------------------------------------------- |
@@ -196,6 +211,7 ARCHITECTURE beh OF lpp_lfr IS | |||
|
196 | 211 | SIGNAL dma_ren : STD_LOGIC; |
|
197 | 212 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | 213 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
214 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
199 | 215 | |
|
200 | 216 | BEGIN |
|
201 | 217 | |
@@ -232,6 +248,7 BEGIN | |||
|
232 | 248 | lpp_lfr_apbreg_1: lpp_lfr_apbreg |
|
233 | 249 | GENERIC MAP ( |
|
234 | 250 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
251 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
|
235 | 252 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
236 | 253 | delta_vector_size => delta_vector_size, |
|
237 | 254 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
@@ -239,7 +256,8 BEGIN | |||
|
239 | 256 | paddr => paddr, |
|
240 | 257 | pmask => pmask, |
|
241 | 258 | pirq_ms => pirq_ms, |
|
242 |
pirq_wfp => pirq_wfp |
|
|
259 | pirq_wfp => pirq_wfp, | |
|
260 | top_lfr_version => top_lfr_version) | |
|
243 | 261 | PORT MAP ( |
|
244 | 262 | HCLK => clk, |
|
245 | 263 | HRESETn => rstn, |
@@ -279,6 +297,7 BEGIN | |||
|
279 | 297 | delta_f1 => delta_f1, |
|
280 | 298 | delta_f2 => delta_f2, |
|
281 | 299 | nb_data_by_buffer => nb_data_by_buffer, |
|
300 | nb_word_by_buffer => nb_word_by_buffer, | |
|
282 | 301 | nb_snapshot_param => nb_snapshot_param, |
|
283 | 302 | enable_f0 => enable_f0, |
|
284 | 303 | enable_f1 => enable_f1, |
@@ -299,7 +318,8 BEGIN | |||
|
299 | 318 | GENERIC MAP ( |
|
300 | 319 | tech => inferred, |
|
301 | 320 | data_size => 6*16, |
|
302 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
|
321 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
|
322 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
|
303 | 323 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
304 | 324 | delta_vector_size => delta_vector_size, |
|
305 | 325 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
@@ -325,6 +345,7 BEGIN | |||
|
325 | 345 | burst_f2 => burst_f2, |
|
326 | 346 | |
|
327 | 347 | nb_data_by_buffer => nb_data_by_buffer, |
|
348 | nb_word_by_buffer => nb_word_by_buffer, | |
|
328 | 349 | nb_snapshot_param => nb_snapshot_param, |
|
329 | 350 | status_full => status_full, |
|
330 | 351 | status_full_ack => status_full_ack, |
@@ -386,34 +407,30 BEGIN | |||
|
386 | 407 | PROCESS (clk, rstn) |
|
387 | 408 | BEGIN -- PROCESS |
|
388 | 409 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
389 | data_f0_addr_out <= (OTHERS => '0'); | |
|
390 | 410 | data_f0_data_out_valid <= '0'; |
|
391 | 411 | data_f0_data_out_valid_burst <= '0'; |
|
392 | data_f1_addr_out <= (OTHERS => '0'); | |
|
393 | 412 | data_f1_data_out_valid <= '0'; |
|
394 | 413 | data_f1_data_out_valid_burst <= '0'; |
|
395 | data_f2_addr_out <= (OTHERS => '0'); | |
|
396 | 414 | data_f2_data_out_valid <= '0'; |
|
397 | 415 | data_f2_data_out_valid_burst <= '0'; |
|
398 | data_f3_addr_out <= (OTHERS => '0'); | |
|
399 | 416 | data_f3_data_out_valid <= '0'; |
|
400 | 417 | data_f3_data_out_valid_burst <= '0'; |
|
401 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
402 | data_f0_addr_out <= data_f0_addr_out_s; | |
|
418 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
403 | 419 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
404 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
|
405 | data_f1_addr_out <= data_f1_addr_out_s; | |
|
420 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
|
406 | 421 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
407 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
|
408 | data_f2_addr_out <= data_f2_addr_out_s; | |
|
422 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
|
409 | 423 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
410 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
|
411 | data_f3_addr_out <= data_f3_addr_out_s; | |
|
424 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
|
412 | 425 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
413 | 426 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
414 | 427 | END IF; |
|
415 | 428 | END PROCESS; |
|
416 | ||
|
429 | ||
|
430 | data_f0_addr_out <= data_f0_addr_out_s; | |
|
431 | data_f1_addr_out <= data_f1_addr_out_s; | |
|
432 | data_f2_addr_out <= data_f2_addr_out_s; | |
|
433 | data_f3_addr_out <= data_f3_addr_out_s; | |
|
417 | 434 |
|
|
418 | 435 | ----------------------------------------------------------------------------- |
|
419 | 436 | -- RoundRobin Selection For DMA |
@@ -430,17 +447,46 BEGIN | |||
|
430 | 447 | rstn => rstn, |
|
431 | 448 | in_valid => dma_rr_valid, |
|
432 | 449 | out_grant => dma_rr_grant); |
|
433 | ||
|
450 | ||
|
451 | ||
|
452 | ----------------------------------------------------------------------------- | |
|
453 | -- in : dma_rr_grant | |
|
454 | -- send | |
|
455 | -- out : dma_sel | |
|
456 | -- dma_valid_burst | |
|
457 | -- dma_sel_valid | |
|
458 | ----------------------------------------------------------------------------- | |
|
434 | 459 | PROCESS (clk, rstn) |
|
435 | 460 | BEGIN -- PROCESS |
|
436 | 461 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
437 | dma_sel <= (OTHERS => '0'); | |
|
462 | dma_sel <= (OTHERS => '0'); | |
|
463 | dma_send <= '0'; | |
|
464 | dma_valid_burst <= '0'; | |
|
438 | 465 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
439 | IF dma_sel = "0000" OR dma_send = '1' THEN | |
|
466 | -- IF dma_sel = "0000" OR dma_send = '1' THEN | |
|
467 | IF dma_sel = "0000" OR dma_done = '1' THEN | |
|
440 | 468 | dma_sel <= dma_rr_grant; |
|
469 | IF dma_rr_grant(0) = '1' THEN | |
|
470 | dma_send <= '1'; | |
|
471 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
|
472 | dma_sel_valid <= data_f0_data_out_valid; | |
|
473 | ELSIF dma_rr_grant(1) = '1' THEN | |
|
474 | dma_send <= '1'; | |
|
475 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
|
476 | dma_sel_valid <= data_f1_data_out_valid; | |
|
477 | ELSIF dma_rr_grant(2) = '1' THEN | |
|
478 | dma_send <= '1'; | |
|
479 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
|
480 | dma_sel_valid <= data_f2_data_out_valid; | |
|
481 | ELSIF dma_rr_grant(3) = '1' THEN | |
|
482 | dma_send <= '1'; | |
|
483 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
|
484 | dma_sel_valid <= data_f3_data_out_valid; | |
|
485 | END IF; | |
|
441 | 486 | ELSE |
|
442 |
dma_sel <= dma_sel; |
|
|
443 | END IF; | |
|
487 | dma_sel <= dma_sel; | |
|
488 | dma_send <= '0'; | |
|
489 | END IF; | |
|
444 | 490 | END IF; |
|
445 | 491 | END PROCESS; |
|
446 | 492 | |
@@ -454,25 +500,69 BEGIN | |||
|
454 | 500 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
455 | 501 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
456 | 502 | data_f3_data_out ; |
|
457 | ||
|
458 | dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE | |
|
459 | data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE | |
|
460 | data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE | |
|
461 | data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE | |
|
462 | '0'; | |
|
503 | ||
|
504 | --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE | |
|
505 | -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE | |
|
506 | -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE | |
|
507 | -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE | |
|
508 | -- '0'; | |
|
463 | 509 | |
|
464 | dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE | |
|
465 | data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE | |
|
466 | data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE | |
|
467 | data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE | |
|
468 | '0'; | |
|
510 | --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE | |
|
511 | -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE | |
|
512 | -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE | |
|
513 | -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE | |
|
514 | -- '0'; | |
|
515 | ||
|
516 | -- TODO | |
|
517 | --dma_send <= dma_sel_valid OR dma_valid_burst; | |
|
469 | 518 | |
|
470 | dma_send <= dma_sel_valid OR dma_valid_burst; | |
|
471 | ||
|
519 | --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1'; | |
|
520 | --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1'; | |
|
521 | --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1'; | |
|
522 | --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1'; | |
|
523 | ||
|
472 | 524 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
473 | 525 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
474 | 526 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
475 | 527 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
528 | ||
|
529 | ||
|
530 | --PROCESS (clk, rstn) | |
|
531 | --BEGIN -- PROCESS | |
|
532 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
533 | -- ongoing_reg <= '0'; | |
|
534 | -- dma_sel_reg <= (OTHERS => '0'); | |
|
535 | -- dma_send_reg <= '0'; | |
|
536 | -- dma_valid_burst_reg <= '0'; | |
|
537 | -- dma_address_reg <= (OTHERS => '0'); | |
|
538 | -- dma_data_reg <= (OTHERS => '0'); | |
|
539 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
540 | -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN | |
|
541 | -- ongoing_reg <= '1'; | |
|
542 | -- dma_valid_burst_reg <= dma_valid_burst; | |
|
543 | -- dma_sel_reg <= dma_sel; | |
|
544 | -- ELSE | |
|
545 | -- IF dma_done = '1' THEN | |
|
546 | -- ongoing_reg <= '0'; | |
|
547 | -- END IF; | |
|
548 | -- END IF; | |
|
549 | -- dma_send_reg <= dma_send; | |
|
550 | -- dma_address_reg <= dma_address; | |
|
551 | -- dma_data_reg <= dma_data; | |
|
552 | -- END IF; | |
|
553 | --END PROCESS; | |
|
554 | ||
|
555 | dma_data_2 <= dma_data; | |
|
556 | --PROCESS (clk, rstn) | |
|
557 | --BEGIN -- PROCESS | |
|
558 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
559 | -- dma_data_2 <= (OTHERS => '0'); | |
|
560 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
561 | -- dma_data_2 <= dma_data; | |
|
562 | ||
|
563 | -- END IF; | |
|
564 | --END PROCESS; | |
|
565 | ||
|
476 | 566 | |
|
477 | 567 | ----------------------------------------------------------------------------- |
|
478 | 568 | -- DMA |
@@ -488,12 +578,12 BEGIN | |||
|
488 | 578 | AHB_Master_In => ahbi, |
|
489 | 579 | AHB_Master_Out => ahbo, |
|
490 | 580 | |
|
491 | send => dma_send, | |
|
492 | valid_burst => dma_valid_burst, | |
|
581 | send => dma_send,--_reg, | |
|
582 | valid_burst => dma_valid_burst,--_reg, | |
|
493 | 583 | done => dma_done, |
|
494 | 584 | ren => dma_ren, |
|
495 | address => dma_address, | |
|
496 | data => dma_data); | |
|
585 | address => dma_address,--_reg, | |
|
586 | data => dma_data_2);--_reg); | |
|
497 | 587 | |
|
498 | 588 | ----------------------------------------------------------------------------- |
|
499 | 589 | -- Matrix Spectral - TODO |
@@ -37,6 +37,7 USE techmap.gencomp.ALL; | |||
|
37 | 37 | ENTITY lpp_lfr_apbreg IS |
|
38 | 38 | GENERIC ( |
|
39 | 39 | nb_data_by_buffer_size : INTEGER := 11; |
|
40 | nb_word_by_buffer_size : INTEGER := 11; | |
|
40 | 41 | nb_snapshot_param_size : INTEGER := 11; |
|
41 | 42 | delta_vector_size : INTEGER := 20; |
|
42 | 43 | delta_vector_size_f0_2 : INTEGER := 3; |
@@ -45,7 +46,8 ENTITY lpp_lfr_apbreg IS | |||
|
45 | 46 | paddr : INTEGER := 4; |
|
46 | 47 | pmask : INTEGER := 16#fff#; |
|
47 | 48 | pirq_ms : INTEGER := 0; |
|
48 |
pirq_wfp : INTEGER := 1 |
|
|
49 | pirq_wfp : INTEGER := 1; | |
|
50 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
49 | 51 | PORT ( |
|
50 | 52 | -- AMBA AHB system signals |
|
51 | 53 | HCLK : IN STD_ULOGIC; |
@@ -101,6 +103,7 ENTITY lpp_lfr_apbreg IS | |||
|
101 | 103 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
102 | 104 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
103 | 105 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
106 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
104 | 107 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
105 | 108 | |
|
106 | 109 | enable_f0 : OUT STD_LOGIC; |
@@ -164,6 +167,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
164 | 167 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | 168 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
166 | 169 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
170 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
167 | 171 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
168 | 172 | enable_f0 : STD_LOGIC; |
|
169 | 173 | enable_f1 : STD_LOGIC; |
@@ -212,6 +216,7 BEGIN -- beh | |||
|
212 | 216 | delta_f1 <= reg_wp.delta_f1; |
|
213 | 217 | delta_f2 <= reg_wp.delta_f2; |
|
214 | 218 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
219 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; | |
|
215 | 220 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
216 | 221 | |
|
217 | 222 | enable_f0 <= reg_wp.enable_f0; |
@@ -293,10 +298,11 BEGIN -- beh | |||
|
293 | 298 | |
|
294 | 299 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
295 | 300 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
296 | ||
|
297 | reg_wp.status_full <= reg_wp.status_full OR status_full; | |
|
298 | reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; | |
|
299 | reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; | |
|
301 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
|
302 | reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
|
303 | reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
|
304 | reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
305 | END LOOP all_status; | |
|
300 | 306 | |
|
301 | 307 | paddr := "000000"; |
|
302 | 308 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
@@ -347,7 +353,9 BEGIN -- beh | |||
|
347 | 353 | WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
348 | 354 | WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
349 | 355 | WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
350 | -- | |
|
356 | WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; | |
|
357 | ---------------------------------------------------- | |
|
358 | WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0); | |
|
351 | 359 | WHEN OTHERS => NULL; |
|
352 | 360 | END CASE; |
|
353 | 361 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
@@ -399,21 +407,22 BEGIN -- beh | |||
|
399 | 407 | WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
400 | 408 | WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
401 | 409 | WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
410 | WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
402 | 411 | -- |
|
403 | 412 | WHEN OTHERS => NULL; |
|
404 | 413 | END CASE; |
|
405 | 414 | END IF; |
|
406 | 415 | END IF; |
|
407 | 416 | |
|
408 | apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
409 | ready_matrix_f0_1 OR | |
|
410 | ready_matrix_f1 OR | |
|
411 | ready_matrix_f2) | |
|
417 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
|
418 | ready_matrix_f0_1 OR | |
|
419 | ready_matrix_f1 OR | |
|
420 | ready_matrix_f2) | |
|
412 | 421 | ) |
|
413 | 422 | OR |
|
414 | 423 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR |
|
415 | 424 | error_bad_component_error) |
|
416 | ); | |
|
425 | )); | |
|
417 | 426 | |
|
418 | 427 | apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR |
|
419 | 428 | status_full(1) OR status_full_err(1) OR status_new_err(1) OR |
@@ -75,6 +75,7 PACKAGE lpp_lfr_pkg IS | |||
|
75 | 75 | GENERIC ( |
|
76 | 76 | Mem_use : INTEGER; |
|
77 | 77 | nb_data_by_buffer_size : INTEGER; |
|
78 | nb_word_by_buffer_size : INTEGER; | |
|
78 | 79 | nb_snapshot_param_size : INTEGER; |
|
79 | 80 | delta_vector_size : INTEGER; |
|
80 | 81 | delta_vector_size_f0_2 : INTEGER; |
@@ -83,7 +84,9 PACKAGE lpp_lfr_pkg IS | |||
|
83 | 84 | pmask : INTEGER; |
|
84 | 85 | pirq_ms : INTEGER; |
|
85 | 86 | pirq_wfp : INTEGER; |
|
86 |
hindex : INTEGER |
|
|
87 | hindex : INTEGER; | |
|
88 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
89 | ); | |
|
87 | 90 | PORT ( |
|
88 | 91 | clk : IN STD_LOGIC; |
|
89 | 92 | rstn : IN STD_LOGIC; |
@@ -102,6 +105,7 PACKAGE lpp_lfr_pkg IS | |||
|
102 | 105 | COMPONENT lpp_lfr_apbreg |
|
103 | 106 | GENERIC ( |
|
104 | 107 | nb_data_by_buffer_size : INTEGER; |
|
108 | nb_word_by_buffer_size : INTEGER; | |
|
105 | 109 | nb_snapshot_param_size : INTEGER; |
|
106 | 110 | delta_vector_size : INTEGER; |
|
107 | 111 | delta_vector_size_f0_2 : INTEGER; |
@@ -109,7 +113,8 PACKAGE lpp_lfr_pkg IS | |||
|
109 | 113 | paddr : INTEGER; |
|
110 | 114 | pmask : INTEGER; |
|
111 | 115 | pirq_ms : INTEGER; |
|
112 |
pirq_wfp : INTEGER |
|
|
116 | pirq_wfp : INTEGER; | |
|
117 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
113 | 118 | PORT ( |
|
114 | 119 | HCLK : IN STD_ULOGIC; |
|
115 | 120 | HRESETn : IN STD_ULOGIC; |
@@ -149,6 +154,7 PACKAGE lpp_lfr_pkg IS | |||
|
149 | 154 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
150 | 155 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
151 | 156 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
157 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
152 | 158 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
153 | 159 | enable_f0 : OUT STD_LOGIC; |
|
154 | 160 | enable_f1 : OUT STD_LOGIC; |
@@ -41,7 +41,8 ENTITY lpp_waveform IS | |||
|
41 | 41 | GENERIC ( |
|
42 | 42 | tech : INTEGER := inferred; |
|
43 | 43 | data_size : INTEGER := 96; --16*6 |
|
44 | nb_data_by_buffer_size : INTEGER := 11; | |
|
44 | nb_data_by_buffer_size : INTEGER := 11; | |
|
45 | nb_word_by_buffer_size : INTEGER := 11; | |
|
45 | 46 | nb_snapshot_param_size : INTEGER := 11; |
|
46 | 47 | delta_vector_size : INTEGER := 20; |
|
47 | 48 | delta_vector_size_f0_2 : INTEGER := 3); |
@@ -73,6 +74,7 ENTITY lpp_waveform IS | |||
|
73 | 74 | burst_f2 : IN STD_LOGIC; |
|
74 | 75 | |
|
75 | 76 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
77 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
76 | 78 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
77 | 79 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
78 | 80 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -314,10 +316,10 BEGIN -- beh | |||
|
314 | 316 | rstn => rstn, |
|
315 | 317 | run => run, |
|
316 | 318 | nb_data_by_buffer => nb_data_by_buffer, |
|
317 | data_in_valid => valid_out, | |
|
318 | data_in_ack => valid_ack, | |
|
319 | data_in => data_out, | |
|
320 | time_in => time_out_2, | |
|
319 | data_in_valid => valid_out, | |
|
320 | data_in_ack => valid_ack, | |
|
321 | data_in => data_out, | |
|
322 | time_in => time_out_2, | |
|
321 | 323 | |
|
322 | 324 | data_out => wdata, |
|
323 | 325 | data_out_wen => data_wen, |
@@ -332,49 +334,57 BEGIN -- beh | |||
|
332 | 334 | |
|
333 | 335 | empty => empty, |
|
334 | 336 | empty_almost => empty_almost, |
|
335 |
|
|
|
337 | ||
|
336 | 338 | data_ren => data_ren, |
|
337 | 339 | rdata => rdata, |
|
338 | 340 | |
|
339 |
|
|
|
341 | ||
|
340 | 342 | full_almost => full_almost, |
|
341 | 343 | full => full, |
|
342 | 344 | data_wen => data_wen, |
|
343 | 345 | wdata => wdata); |
|
344 | 346 | |
|
345 | ||
|
347 | data_f0_data_out <= rdata; | |
|
348 | data_f1_data_out <= rdata; | |
|
349 | data_f2_data_out <= rdata; | |
|
350 | data_f3_data_out <= rdata; | |
|
351 | ||
|
352 | --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency | |
|
353 | -- GENERIC MAP ( | |
|
354 | -- tech => tech) | |
|
355 | -- PORT MAP ( | |
|
356 | -- clk => clk, | |
|
357 | -- rstn => rstn, | |
|
358 | -- run => run, | |
|
359 | ||
|
360 | -- empty_almost => empty_almost, | |
|
361 | -- empty => empty, | |
|
362 | -- data_ren => data_ren, | |
|
363 | ||
|
364 | -- rdata_0 => data_f0_data_out, | |
|
365 | -- rdata_1 => data_f1_data_out, | |
|
366 | -- rdata_2 => data_f2_data_out, | |
|
367 | -- rdata_3 => data_f3_data_out, | |
|
368 | ||
|
369 | -- full_almost => full_almost, | |
|
370 | -- full => full, | |
|
371 | -- data_wen => data_wen, | |
|
372 | -- wdata => wdata); | |
|
346 | 373 | |
|
347 | 374 | |
|
348 | 375 | |
|
349 | ----------------------------------------------------------------------------- | |
|
350 | -- TODO : set the alterance : time, data, data, ..... | |
|
351 | ----------------------------------------------------------------------------- | |
|
352 | ||
|
353 | 376 | |
|
354 | ----------------------------------------------------------------------------- | |
|
355 | -- | |
|
356 | ----------------------------------------------------------------------------- | |
|
357 | ||
|
358 | 377 |
|
|
359 | 378 | data_f2_data_out_ren & |
|
360 | 379 | data_f1_data_out_ren & |
|
361 | 380 | data_f0_data_out_ren; |
|
362 | 381 | |
|
363 | data_f3_data_out <= rdata; | |
|
364 | data_f2_data_out <= rdata; | |
|
365 | data_f1_data_out <= rdata; | |
|
366 | data_f0_data_out <= rdata; | |
|
367 | ||
|
368 | ||
|
369 | ||
|
370 | ||
|
371 | ||
|
372 | 382 | ----------------------------------------------------------------------------- |
|
373 | -- TODO | |
|
383 | -- TODO : set the alterance : time, data, data, ..... | |
|
374 | 384 | ----------------------------------------------------------------------------- |
|
375 | 385 | lpp_waveform_gen_address_1 : lpp_waveform_genaddress |
|
376 | 386 | GENERIC MAP ( |
|
377 |
nb_data_by_buffer_size => nb_d |
|
|
387 | nb_data_by_buffer_size => nb_word_by_buffer_size) | |
|
378 | 388 | PORT MAP ( |
|
379 | 389 | clk => clk, |
|
380 | 390 | rstn => rstn, |
@@ -383,7 +393,7 BEGIN -- beh | |||
|
383 | 393 | ------------------------------------------------------------------------- |
|
384 | 394 | -- CONFIG |
|
385 | 395 | ------------------------------------------------------------------------- |
|
386 |
nb_data_by_buffer => nb_d |
|
|
396 | nb_data_by_buffer => nb_word_by_buffer, | |
|
387 | 397 | |
|
388 | 398 | addr_data_f0 => addr_data_f0, |
|
389 | 399 | addr_data_f1 => addr_data_f1, |
@@ -41,15 +41,15 ENTITY lpp_waveform_fifo IS | |||
|
41 | 41 | run : IN STD_LOGIC; |
|
42 | 42 | |
|
43 | 43 | --------------------------------------------------------------------------- |
|
44 | empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |
|
45 | empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
46 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
44 | empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |
|
45 | empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
46 | data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
47 | 47 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
48 | 48 | |
|
49 | 49 | --------------------------------------------------------------------------- |
|
50 | full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b | |
|
51 | full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
52 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
50 | full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b | |
|
51 | full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
52 | data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); | |
|
53 | 53 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
54 | 54 | ); |
|
55 | 55 | END ENTITY; |
@@ -59,39 +59,39 ARCHITECTURE ar_lpp_waveform_fifo OF lpp | |||
|
59 | 59 | |
|
60 | 60 | SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); |
|
61 | 61 | SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); |
|
62 |
SIGNAL data_mem_re |
|
|
63 |
SIGNAL data_mem_we |
|
|
62 | SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
63 | SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
64 | 64 | |
|
65 | 65 | SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
66 | 66 | SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
67 |
SIGNAL re |
|
|
68 |
SIGNAL we |
|
|
67 | SIGNAL re : STD_LOGIC; | |
|
68 | SIGNAL we : STD_LOGIC; | |
|
69 | 69 | |
|
70 | 70 | BEGIN |
|
71 | 71 | |
|
72 | 72 | SRAM : syncram_2p |
|
73 | 73 | GENERIC MAP(tech, 7, 32) |
|
74 |
PORT MAP(clk, re |
|
|
75 |
clk, we |
|
|
74 | PORT MAP(clk, re, data_addr_r, rdata, | |
|
75 | clk, we, data_addr_w, wdata); | |
|
76 | 76 | |
|
77 |
re |
|
|
78 |
data_mem_re |
|
|
79 |
data_mem_re |
|
|
80 |
data_mem_re |
|
|
77 | re <= data_mem_re(3) OR | |
|
78 | data_mem_re(2) OR | |
|
79 | data_mem_re(1) OR | |
|
80 | data_mem_re(0); | |
|
81 | 81 | |
|
82 |
we |
|
|
83 |
|
|
|
84 |
|
|
|
85 |
|
|
|
82 | we <= data_mem_we(3) OR | |
|
83 | data_mem_we(2) OR | |
|
84 | data_mem_we(1) OR | |
|
85 | data_mem_we(0); | |
|
86 | 86 | |
|
87 |
data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re |
|
|
88 |
data_mem_addr_r(1) WHEN data_mem_re |
|
|
89 |
data_mem_addr_r(2) WHEN data_mem_re |
|
|
87 | data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE | |
|
88 | data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE | |
|
89 | data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE | |
|
90 | 90 | data_mem_addr_r(3); |
|
91 | 91 | |
|
92 |
data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we |
|
|
93 |
data_mem_addr_w(1) WHEN data_mem_we |
|
|
94 |
data_mem_addr_w(2) WHEN data_mem_we |
|
|
92 | data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE | |
|
93 | data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE | |
|
94 | data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE | |
|
95 | 95 | data_mem_addr_w(3); |
|
96 | 96 | |
|
97 | 97 | gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE |
@@ -105,8 +105,8 BEGIN | |||
|
105 | 105 | run => run, |
|
106 | 106 | ren => data_ren(I), |
|
107 | 107 | wen => data_wen(I), |
|
108 |
mem_re => data_mem_re |
|
|
109 |
mem_we => data_mem_we |
|
|
108 | mem_re => data_mem_re(I), | |
|
109 | mem_we => data_mem_we(I), | |
|
110 | 110 | mem_addr_ren => data_mem_addr_r(I), |
|
111 | 111 | mem_addr_wen => data_mem_addr_w(I), |
|
112 | 112 | empty_almost => empty_almost(I), |
@@ -58,83 +58,155 END ENTITY; | |||
|
58 | 58 | |
|
59 | 59 | |
|
60 | 60 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
|
61 | ||
|
61 | ----------------------------------------------------------------------------- | |
|
62 | -- DATA MUX | |
|
62 | 63 | ----------------------------------------------------------------------------- |
|
63 | -- DATA FLOW | |
|
64 | ----------------------------------------------------------------------------- | |
|
64 | SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
65 | SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
66 | SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
67 | SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |
|
65 | 68 | TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
66 |
SIGNAL |
|
|
67 |
SIGNAL |
|
|
68 |
SIGNAL data_ |
|
|
69 |
SIGNAL data_ |
|
|
70 |
SIGNAL data_ |
|
|
71 | SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0); | |
|
72 | SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
69 | SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0); | |
|
70 | SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0); | |
|
71 | SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0); | |
|
72 | SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0); | |
|
73 | SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0); | |
|
74 | ||
|
75 | ----------------------------------------------------------------------------- | |
|
76 | -- RR and SELECTION | |
|
77 | ----------------------------------------------------------------------------- | |
|
78 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
79 | SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
80 | SIGNAL no_sel : STD_LOGIC; | |
|
81 | ||
|
82 | ----------------------------------------------------------------------------- | |
|
83 | -- REG | |
|
73 | 84 | ----------------------------------------------------------------------------- |
|
74 | -- CHANNEL SELECTION (RoundRobin) | |
|
85 | SIGNAL count_enable : STD_LOGIC; | |
|
86 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
87 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
88 | ||
|
89 | SIGNAL shift_data_enable : STD_LOGIC; | |
|
90 | SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
91 | SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
92 | ||
|
93 | SIGNAL shift_time_enable : STD_LOGIC; | |
|
94 | SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
95 | SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
96 | ||
|
97 | BEGIN | |
|
98 | ||
|
75 | 99 |
|
|
76 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
77 | SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
78 | ----------------------------------------------------------------------------- | |
|
79 | -- FSM CONTROL | |
|
100 | -- CONTROL | |
|
80 | 101 | ----------------------------------------------------------------------------- |
|
81 | TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |
|
82 | SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0); | |
|
83 | SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0); | |
|
84 | SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0); | |
|
85 | -- SHIFT_DATA --------------------------------------------------------------- | |
|
86 | SIGNAL shift_data_pre : INTEGER; | |
|
87 | SIGNAL shift_data : INTEGER; | |
|
88 | SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0); | |
|
89 | -- SHIFT_TIME --------------------------------------------------------------- | |
|
90 | SIGNAL reg_shift_time_pre : INTEGER; | |
|
91 | SIGNAL shift_time_pre : INTEGER; | |
|
92 | SIGNAL shift_time : INTEGER; | |
|
93 | SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0); | |
|
94 | -- COUNT_DATA --------------------------------------------------------------- | |
|
95 | SIGNAL count_data_pre : INTEGER; | |
|
96 | SIGNAL count_data : INTEGER; | |
|
97 | SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0); | |
|
98 | ||
|
99 | BEGIN | |
|
102 | PROCESS (clk, rstn) | |
|
103 | BEGIN -- PROCESS | |
|
104 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
105 | count_enable <= '0'; | |
|
106 | shift_time_enable <= '0'; | |
|
107 | shift_data_enable <= '0'; | |
|
108 | data_in_ack <= (OTHERS => '0'); | |
|
109 | data_out_wen <= (OTHERS => '1'); | |
|
110 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
111 | IF run = '0' OR no_sel = '1' THEN | |
|
112 | count_enable <= '0'; | |
|
113 | shift_time_enable <= '0'; | |
|
114 | shift_data_enable <= '0'; | |
|
115 | data_in_ack <= (OTHERS => '0'); | |
|
116 | data_out_wen <= (OTHERS => '1'); | |
|
117 | ELSE | |
|
118 | --COUNT | |
|
119 | IF shift_data_s = "10" THEN | |
|
120 | count_enable <= '1'; | |
|
121 | ELSE | |
|
122 | count_enable <= '0'; | |
|
123 | END IF; | |
|
124 | --DATA | |
|
125 | IF shift_time_s = "10" THEN | |
|
126 | shift_data_enable <= '1'; | |
|
127 | ELSE | |
|
128 | shift_data_enable <= '0'; | |
|
129 | END IF; | |
|
100 | 130 | |
|
101 | ----------------------------------------------------------------------------- | |
|
102 | -- DATA FLOW | |
|
103 | ----------------------------------------------------------------------------- | |
|
131 | --TIME | |
|
132 | IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR | |
|
133 | shift_time_s = "00" OR | |
|
134 | shift_time_s = "01" | |
|
135 | THEN | |
|
136 | shift_time_enable <= '1'; | |
|
137 | ELSE | |
|
138 | shift_time_enable <= '0'; | |
|
139 | END IF; | |
|
140 | ||
|
141 | --ACK | |
|
142 | IF shift_data_s = "10" THEN | |
|
143 | data_in_ack <= sel; | |
|
144 | ELSE | |
|
145 | data_in_ack <= (OTHERS => '0'); | |
|
146 | END IF; | |
|
147 | ||
|
148 | --VALID OUT | |
|
149 | all_wen: FOR I IN 3 DOWNTO 0 LOOP | |
|
150 | IF sel(I) = '1' AND count_enable = '0' THEN | |
|
151 | data_out_wen(I) <= '0'; | |
|
152 | ELSE | |
|
153 | data_out_wen(I) <= '1'; | |
|
154 | END IF; | |
|
155 | END LOOP all_wen; | |
|
104 | 156 | |
|
157 | END IF; | |
|
158 | END IF; | |
|
159 | END PROCESS; | |
|
105 | 160 | |
|
106 | all_input : FOR I IN 3 DOWNTO 0 GENERATE | |
|
107 | ||
|
108 | all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE | |
|
109 | time_temp_0(I)(J) <= time_in(I,J); | |
|
110 |
|
|
|
111 |
|
|
|
112 | END GENERATE J_47DOWNTO32; | |
|
113 | J_63DOWNTO48: IF J+32 > 47 GENERATE | |
|
114 | time_temp_1(I)(J) <= '0'; | |
|
115 |
|
|
|
116 | data_temp_0(I)(J) <= data_in(I,J); | |
|
117 | data_temp_1(I)(J) <= data_in(I,J+32); | |
|
118 | data_temp_2(I)(J) <= data_in(I,J+32*2); | |
|
119 | END GENERATE all_bit_of_time; | |
|
120 | ||
|
121 | data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE | |
|
122 | time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE | |
|
123 | data_temp_0(I) WHEN shift_data = 0 ELSE | |
|
124 | data_temp_1(I) WHEN shift_data = 1 ELSE | |
|
125 | data_temp_2(I); | |
|
126 | END GENERATE all_input; | |
|
161 | ----------------------------------------------------------------------------- | |
|
162 | -- DATA MUX | |
|
163 | ----------------------------------------------------------------------------- | |
|
164 | all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE | |
|
165 | I_time_in: IF I < 48 GENERATE | |
|
166 | data_0_v(I) <= time_in(0,I); | |
|
167 | data_1_v(I) <= time_in(1,I); | |
|
168 | data_2_v(I) <= time_in(2,I); | |
|
169 | data_3_v(I) <= time_in(3,I); | |
|
170 | END GENERATE I_time_in; | |
|
171 | I_null: IF (I > 47) AND (I < 32*2) GENERATE | |
|
172 | data_0_v(I) <= '0'; | |
|
173 | data_1_v(I) <= '0'; | |
|
174 | data_2_v(I) <= '0'; | |
|
175 | data_3_v(I) <= '0'; | |
|
176 | END GENERATE I_null; | |
|
177 | I_data_in: IF I > 32*2-1 GENERATE | |
|
178 | data_0_v(I) <= data_in(0,I-32*2); | |
|
179 | data_1_v(I) <= data_in(1,I-32*2); | |
|
180 | data_2_v(I) <= data_in(2,I-32*2); | |
|
181 | data_3_v(I) <= data_in(3,I-32*2); | |
|
182 | END GENERATE I_data_in; | |
|
183 | END GENERATE all_bit_data_in; | |
|
127 | 184 | |
|
128 | data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE | |
|
129 | data_temp_v(1) WHEN sel_input = "0010" ELSE | |
|
130 | data_temp_v(2) WHEN sel_input = "0100" ELSE | |
|
131 | data_temp_v(3); | |
|
185 | all_word: FOR J IN 4 DOWNTO 0 GENERATE | |
|
186 | all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE | |
|
187 | data_0(J)(I) <= data_0_v(J*32+I); | |
|
188 | data_1(J)(I) <= data_1_v(J*32+I); | |
|
189 | data_2(J)(I) <= data_2_v(J*32+I); | |
|
190 | data_3(J)(I) <= data_3_v(J*32+I); | |
|
191 | END GENERATE all_data_bit; | |
|
192 | END GENERATE all_word; | |
|
132 | 193 | |
|
194 | data_sel <= data_0 WHEN sel(0) = '1' ELSE | |
|
195 | data_1 WHEN sel(1) = '1' ELSE | |
|
196 | data_2 WHEN sel(2) = '1' ELSE | |
|
197 | data_3; | |
|
198 | ||
|
199 | data_out <= data_sel(0) WHEN shift_time = "00" ELSE | |
|
200 | data_sel(1) WHEN shift_time = "01" ELSE | |
|
201 | data_sel(2) WHEN shift_data = "00" ELSE | |
|
202 | data_sel(3) WHEN shift_data = "01" ELSE | |
|
203 | data_sel(4); | |
|
204 | ||
|
205 | ||
|
133 | 206 |
|
|
134 | -- CHANNEL SELECTION (RoundRobin) | |
|
207 | -- RR and SELECTION | |
|
135 | 208 | ----------------------------------------------------------------------------- |
|
136 | 209 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
|
137 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); | |
|
138 | 210 | valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); |
|
139 | 211 | END GENERATE all_input_rr; |
|
140 | 212 | |
@@ -143,103 +215,59 BEGIN | |||
|
143 | 215 | clk => clk, |
|
144 | 216 | rstn => rstn, |
|
145 | 217 | in_valid => valid_in_rr, |
|
146 |
out_grant => |
|
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | -- FSM CONTROL | |
|
150 | ----------------------------------------------------------------------------- | |
|
151 | ||
|
152 | PROCESS (clk, rstn) | |
|
153 | BEGIN -- PROCESS | |
|
154 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
155 | reg_shift_data <= (0, 0, 0, 0); | |
|
156 | reg_shift_time <= (0, 0, 0, 0); | |
|
157 | reg_count_data <= (0, 0, 0, 0); | |
|
158 | sel_input <= (OTHERS => '0'); | |
|
159 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
160 | IF run = '0' THEN | |
|
161 | reg_shift_data <= (0, 0, 0, 0); | |
|
162 | reg_shift_time <= (0, 0, 0, 0); | |
|
163 | reg_count_data <= (0, 0, 0, 0); | |
|
164 | sel_input <= (OTHERS => '0'); | |
|
165 | ELSE | |
|
166 | sel_input <= valid_out_rr; | |
|
218 | out_grant => sel); | |
|
167 | 219 | |
|
168 | IF count_data_pre = 0 THEN -- first buffer data | |
|
169 | IF shift_time_pre < 2 THEN -- TIME not completly send | |
|
170 | reg_shift_time <= reg_shift_time_s; | |
|
171 | ELSE | |
|
172 | reg_shift_data <= reg_shift_data_s; | |
|
173 | IF shift_data_pre = 2 THEN | |
|
174 | reg_count_data <= reg_count_data_s; | |
|
175 | END IF; | |
|
176 | END IF; | |
|
177 | ELSE | |
|
178 | reg_shift_data <= reg_shift_data_s; | |
|
179 | IF shift_data_pre = 2 THEN | |
|
180 | reg_count_data <= reg_count_data_s; | |
|
181 | IF count_data = 0 THEN | |
|
182 | reg_shift_time <= reg_shift_time_s; | |
|
183 | END IF; | |
|
184 | END IF; | |
|
185 | END IF; | |
|
186 | END IF; | |
|
187 | END IF; | |
|
188 | END PROCESS; | |
|
220 | no_sel <= '1' WHEN sel = "0000" ELSE '0'; | |
|
189 | 221 | |
|
190 | 222 | ----------------------------------------------------------------------------- |
|
191 | data_out_wen <= NOT sel_input; | |
|
192 | data_in_ack <= sel_input; | |
|
193 | ||
|
194 | -- SHIFT_DATA --------------------------------------------------------------- | |
|
195 | shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE | |
|
196 | reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE | |
|
197 | reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE | |
|
198 | reg_shift_data(3); | |
|
199 | ||
|
200 | shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0; | |
|
201 | ||
|
202 | reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s | |
|
203 | reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s | |
|
204 | reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s | |
|
205 | reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s | |
|
206 | ||
|
207 | -- SHIFT_TIME --------------------------------------------------------------- | |
|
208 | shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE | |
|
209 | reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE | |
|
210 | reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE | |
|
211 | reg_shift_time(3); | |
|
212 | ||
|
213 | shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0; | |
|
223 | -- REG | |
|
224 | ----------------------------------------------------------------------------- | |
|
225 | reg_count_i: lpp_waveform_fifo_arbiter_reg | |
|
226 | GENERIC MAP ( | |
|
227 | data_size => nb_data_by_buffer_size, | |
|
228 | data_nb => 4) | |
|
229 | PORT MAP ( | |
|
230 | clk => clk, | |
|
231 | rstn => rstn, | |
|
232 | run => run, | |
|
233 | max_count => nb_data_by_buffer, | |
|
234 | enable => count_enable, | |
|
235 | sel => sel, | |
|
236 | data => count, | |
|
237 | data_s => count_s); | |
|
214 | 238 | |
|
215 | reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s | |
|
216 | reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s | |
|
217 | reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s | |
|
218 | reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s | |
|
239 | reg_shift_data_i: lpp_waveform_fifo_arbiter_reg | |
|
240 | GENERIC MAP ( | |
|
241 | data_size => 2, | |
|
242 | data_nb => 4) | |
|
243 | PORT MAP ( | |
|
244 | clk => clk, | |
|
245 | rstn => rstn, | |
|
246 | run => run, | |
|
247 | max_count => "10", -- 2 | |
|
248 | enable => shift_data_enable, | |
|
249 | sel => sel, | |
|
250 | data => shift_data, | |
|
251 | data_s => shift_data_s); | |
|
219 | 252 | |
|
220 | -- COUNT_DATA --------------------------------------------------------------- | |
|
221 | count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE | |
|
222 | reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE | |
|
223 | reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE | |
|
224 | reg_count_data(3); | |
|
225 | ||
|
226 | count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0; | |
|
227 | 253 | |
|
228 | reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s | |
|
229 | reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s | |
|
230 | reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s | |
|
231 | reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s | |
|
232 | ----------------------------------------------------------------------------- | |
|
254 | reg_shift_time_i: lpp_waveform_fifo_arbiter_reg | |
|
255 | GENERIC MAP ( | |
|
256 | data_size => 2, | |
|
257 | data_nb => 4) | |
|
258 | PORT MAP ( | |
|
259 | clk => clk, | |
|
260 | rstn => rstn, | |
|
261 | run => run, | |
|
262 | max_count => "10", -- 2 | |
|
263 | enable => shift_time_enable, | |
|
264 | sel => sel, | |
|
265 | data => shift_time, | |
|
266 | data_s => shift_time_s); | |
|
267 | ||
|
268 | ||
|
233 | 269 |
|
|
234 | PROCESS (clk, rstn) | |
|
235 | BEGIN -- PROCESS | |
|
236 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
237 | reg_shift_time_pre <= 0; | |
|
238 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
239 | reg_shift_time_pre <= shift_time_pre; | |
|
240 | END IF; | |
|
241 | END PROCESS ; | |
|
242 | ||
|
270 | ||
|
243 | 271 | END ARCHITECTURE; |
|
244 | 272 | |
|
245 | 273 |
@@ -1,237 +1,255 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ------------------------------------------------------------------------------- | |
|
23 | LIBRARY IEEE; | |
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | ||
|
27 | LIBRARY grlib; | |
|
28 | USE grlib.amba.ALL; | |
|
29 | USE grlib.stdlib.ALL; | |
|
30 | USE grlib.devices.ALL; | |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
32 | ||
|
33 | LIBRARY lpp; | |
|
34 | USE lpp.lpp_waveform_pkg.ALL; | |
|
35 | ||
|
36 | LIBRARY techmap; | |
|
37 | USE techmap.gencomp.ALL; | |
|
38 | ||
|
39 | ENTITY lpp_waveform_genaddress IS | |
|
40 | ||
|
41 | GENERIC ( | |
|
42 | nb_data_by_buffer_size : INTEGER); | |
|
43 | ||
|
44 | PORT ( | |
|
45 | clk : IN STD_LOGIC; | |
|
46 | rstn : IN STD_LOGIC; | |
|
47 | run : IN STD_LOGIC; | |
|
48 | ------------------------------------------------------------------------- | |
|
49 | -- CONFIG | |
|
50 | ------------------------------------------------------------------------- | |
|
51 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
52 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
53 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
54 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
55 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
56 | ------------------------------------------------------------------------- | |
|
57 | -- CTRL | |
|
58 | ------------------------------------------------------------------------- | |
|
59 | empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
60 | empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
61 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
62 | ||
|
63 | ------------------------------------------------------------------------- | |
|
64 | -- STATUS | |
|
65 | ------------------------------------------------------------------------- | |
|
66 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
67 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
68 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
69 | ||
|
70 | ------------------------------------------------------------------------- | |
|
71 | -- ADDR DATA OUT | |
|
72 | ------------------------------------------------------------------------- | |
|
73 | data_f0_data_out_valid_burst : OUT STD_LOGIC; | |
|
74 | data_f1_data_out_valid_burst : OUT STD_LOGIC; | |
|
75 | data_f2_data_out_valid_burst : OUT STD_LOGIC; | |
|
76 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
|
77 | ||
|
78 | data_f0_data_out_valid : OUT STD_LOGIC; | |
|
79 | data_f1_data_out_valid : OUT STD_LOGIC; | |
|
80 | data_f2_data_out_valid : OUT STD_LOGIC; | |
|
81 | data_f3_data_out_valid : OUT STD_LOGIC; | |
|
82 | ||
|
83 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
87 | ||
|
88 | ); | |
|
89 | ||
|
90 | END lpp_waveform_genaddress; | |
|
91 | ||
|
92 | ARCHITECTURE beh OF lpp_waveform_genaddress IS | |
|
93 | ----------------------------------------------------------------------------- | |
|
94 | -- Valid gen | |
|
95 | ----------------------------------------------------------------------------- | |
|
96 |
SIGNAL addr_ |
|
|
97 | SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
98 | SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
99 | ||
|
100 | ----------------------------------------------------------------------------- | |
|
101 | -- Register | |
|
102 | ----------------------------------------------------------------------------- | |
|
103 | SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0); | |
|
104 | SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0); | |
|
105 | SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0); | |
|
106 | SIGNAL data_addr_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
|
107 |
SIGNAL data_addr_ |
|
|
108 |
SIGNAL data_addr_ |
|
|
109 | ||
|
110 | ----------------------------------------------------------------------------- | |
|
111 | -- | |
|
112 | ----------------------------------------------------------------------------- | |
|
113 | SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
114 | ||
|
115 | TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
116 | SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0); | |
|
117 |
SIGNAL |
|
|
118 | ||
|
119 | BEGIN -- beh | |
|
120 | ||
|
121 | ----------------------------------------------------------------------------- | |
|
122 | -- valid gen | |
|
123 | ----------------------------------------------------------------------------- | |
|
124 | data_f0_data_out_valid <= data_out_valid(0); | |
|
125 | data_f1_data_out_valid <= data_out_valid(1); | |
|
126 | data_f2_data_out_valid <= data_out_valid(2); | |
|
127 | data_f3_data_out_valid <= data_out_valid(3); | |
|
128 | ||
|
129 | data_f0_data_out_valid_burst <= data_out_valid_burst(0); | |
|
130 |
data_f |
|
|
131 |
data_f |
|
|
132 |
data_f |
|
|
133 | ||
|
134 | ||
|
135 | all_bit_data_valid_out: FOR I IN 3 DOWNTO 0 GENERATE | |
|
136 | addr_burst_avail(I) <= '1' WHEN data_addr_v_pre(I,2) = '0' AND | |
|
137 | data_addr_v_pre(I,3) = '0' AND | |
|
138 | data_addr_v_pre(I,4) = '0' AND | |
|
139 | data_addr_v_pre(I,5) = '0' ELSE '0'; | |
|
140 |
|
|
|
141 | data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE | |
|
142 | '0' WHEN empty(I) = '1' ELSE | |
|
143 | '0' WHEN addr_burst_avail(I) = '1' ELSE | |
|
144 | '0' WHEN (run = '0') ELSE | |
|
145 | '1'; | |
|
146 | ||
|
147 | data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE | |
|
148 | '0' WHEN empty(I) = '1' ELSE | |
|
149 | '0' WHEN addr_burst_avail(I) = '0' ELSE | |
|
150 |
|
|
|
151 | '0' WHEN (run = '0') ELSE | |
|
152 | '1'; | |
|
153 | END GENERATE all_bit_data_valid_out; | |
|
154 | ||
|
155 | ----------------------------------------------------------------------------- | |
|
156 | -- Register | |
|
157 | ----------------------------------------------------------------------------- | |
|
158 | all_data_bit: FOR J IN 31 DOWNTO 0 GENERATE | |
|
159 | all_data_addr: FOR I IN 3 DOWNTO 0 GENERATE | |
|
160 | PROCESS (clk, rstn) | |
|
161 | BEGIN -- PROCESS | |
|
162 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
163 | data_addr_v_reg(I,J) <= '0'; | |
|
164 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
165 | IF run = '1' AND status_full_ack(I) = '0' THEN | |
|
166 | data_addr_v_reg(I,J) <= data_addr_v_pre(I,J); | |
|
167 | ELSE | |
|
168 | data_addr_v_reg(I,J) <= data_addr_v_base(I,J); | |
|
169 | END IF; | |
|
170 | END IF; | |
|
171 | END PROCESS; | |
|
172 | ||
|
173 | data_addr_v_pre(I,J) <= data_addr_v_reg(I,J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J); | |
|
174 | ||
|
175 | END GENERATE all_data_addr; | |
|
176 | ||
|
177 | data_addr_reg(J) <= data_addr_v_reg(0,J) WHEN data_ren(0) = '1' ELSE | |
|
178 | data_addr_v_reg(1,J) WHEN data_ren(1) = '1' ELSE | |
|
179 | data_addr_v_reg(2,J) WHEN data_ren(2) = '1' ELSE | |
|
180 | data_addr_v_reg(3,J); | |
|
181 | ||
|
182 | data_addr_v_base(0,J) <= addr_data_f0(J); | |
|
183 | data_addr_v_base(1,J) <= addr_data_f1(J); | |
|
184 | data_addr_v_base(2,J) <= addr_data_f2(J); | |
|
185 | data_addr_v_base(3,J) <= addr_data_f3(J); | |
|
186 | ||
|
187 | data_f0_addr_out(J) <= data_addr_v_reg(0,J); | |
|
188 | data_f1_addr_out(J) <= data_addr_v_reg(1,J); | |
|
189 | data_f2_addr_out(J) <= data_addr_v_reg(2,J); | |
|
190 | data_f3_addr_out(J) <= data_addr_v_reg(3,J); | |
|
191 | ||
|
192 | END GENERATE all_data_bit; | |
|
193 | ||
|
194 | ||
|
195 | ||
|
196 | ||
|
197 | ----------------------------------------------------------------------------- | |
|
198 | -- ADDER | |
|
199 | ----------------------------------------------------------------------------- | |
|
200 | ||
|
201 | data_addr_pre <= data_addr_reg + 1; | |
|
202 | ||
|
203 | ----------------------------------------------------------------------------- | |
|
204 | -- FULL STATUS | |
|
205 | ----------------------------------------------------------------------------- | |
|
206 | all_status: FOR I IN 3 DOWNTO 0 GENERATE | |
|
207 | all_bit_addr: FOR J IN 31 DOWNTO 0 GENERATE | |
|
208 | addr_v_p(I)(J) <= data_addr_v_pre(I,J); | |
|
209 | addr_v_b(I)(J) <= data_addr_v_base(I,J); | |
|
210 | END GENERATE all_bit_addr; | |
|
211 | ||
|
212 | PROCESS (clk, rstn) | |
|
213 | BEGIN -- PROCESS | |
|
214 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
215 | status_full_s(I) <= '0'; | |
|
216 | status_full_err(I) <= '0'; | |
|
217 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
218 | IF run = '1' AND status_full_ack(I) = '0' THEN | |
|
219 | IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN | |
|
220 | status_full_s(I) <= '1'; | |
|
221 | IF status_full_s(I) = '1' AND data_ren(I)= '1' THEN | |
|
222 | status_full_err(I) <= '1'; | |
|
223 | END IF; | |
|
224 | END IF; | |
|
225 | ELSE | |
|
226 | status_full_s(I) <= '0'; | |
|
227 | status_full_err(I) <= '0'; | |
|
228 | END IF; | |
|
229 | END IF; | |
|
230 | END PROCESS; | |
|
231 | ||
|
232 | END GENERATE all_status; | |
|
233 | ||
|
234 | status_full <= status_full_s; | |
|
235 | ||
|
236 | ||
|
237 | END beh; | |
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ------------------------------------------------------------------------------- | |
|
23 | LIBRARY IEEE; | |
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |
|
25 | USE ieee.numeric_std.ALL; | |
|
26 | ||
|
27 | LIBRARY grlib; | |
|
28 | USE grlib.amba.ALL; | |
|
29 | USE grlib.stdlib.ALL; | |
|
30 | USE grlib.devices.ALL; | |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
32 | ||
|
33 | LIBRARY lpp; | |
|
34 | USE lpp.lpp_waveform_pkg.ALL; | |
|
35 | ||
|
36 | LIBRARY techmap; | |
|
37 | USE techmap.gencomp.ALL; | |
|
38 | ||
|
39 | ENTITY lpp_waveform_genaddress IS | |
|
40 | ||
|
41 | GENERIC ( | |
|
42 | nb_data_by_buffer_size : INTEGER); | |
|
43 | ||
|
44 | PORT ( | |
|
45 | clk : IN STD_LOGIC; | |
|
46 | rstn : IN STD_LOGIC; | |
|
47 | run : IN STD_LOGIC; | |
|
48 | ------------------------------------------------------------------------- | |
|
49 | -- CONFIG | |
|
50 | ------------------------------------------------------------------------- | |
|
51 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
52 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
53 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
54 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
55 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
56 | ------------------------------------------------------------------------- | |
|
57 | -- CTRL | |
|
58 | ------------------------------------------------------------------------- | |
|
59 | empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
60 | empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
61 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
62 | ||
|
63 | ------------------------------------------------------------------------- | |
|
64 | -- STATUS | |
|
65 | ------------------------------------------------------------------------- | |
|
66 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
67 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
68 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
69 | ||
|
70 | ------------------------------------------------------------------------- | |
|
71 | -- ADDR DATA OUT | |
|
72 | ------------------------------------------------------------------------- | |
|
73 | data_f0_data_out_valid_burst : OUT STD_LOGIC; | |
|
74 | data_f1_data_out_valid_burst : OUT STD_LOGIC; | |
|
75 | data_f2_data_out_valid_burst : OUT STD_LOGIC; | |
|
76 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
|
77 | ||
|
78 | data_f0_data_out_valid : OUT STD_LOGIC; | |
|
79 | data_f1_data_out_valid : OUT STD_LOGIC; | |
|
80 | data_f2_data_out_valid : OUT STD_LOGIC; | |
|
81 | data_f3_data_out_valid : OUT STD_LOGIC; | |
|
82 | ||
|
83 | data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
86 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
87 | ||
|
88 | ); | |
|
89 | ||
|
90 | END lpp_waveform_genaddress; | |
|
91 | ||
|
92 | ARCHITECTURE beh OF lpp_waveform_genaddress IS | |
|
93 | SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0); | |
|
94 | SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0); | |
|
95 | SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0); | |
|
96 | SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0); | |
|
97 | ----------------------------------------------------------------------------- | |
|
98 | -- Valid gen | |
|
99 | ----------------------------------------------------------------------------- | |
|
100 | SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
101 | SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
102 | SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
103 | ||
|
104 | ----------------------------------------------------------------------------- | |
|
105 | -- Register | |
|
106 | ----------------------------------------------------------------------------- | |
|
107 | SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); | |
|
108 | SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); | |
|
109 | SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); | |
|
110 | SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO | |
|
111 | SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO | |
|
112 | SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO | |
|
113 | ||
|
114 | ----------------------------------------------------------------------------- | |
|
115 | -- | |
|
116 | ----------------------------------------------------------------------------- | |
|
117 | SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
118 | ||
|
119 | TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0); | |
|
120 | SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0); | |
|
121 | SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0); | |
|
122 | ||
|
123 | SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0); | |
|
124 | ||
|
125 | BEGIN -- beh | |
|
126 | ||
|
127 | ----------------------------------------------------------------------------- | |
|
128 | -- valid gen | |
|
129 | ----------------------------------------------------------------------------- | |
|
130 | data_f0_data_out_valid <= data_out_valid(0); | |
|
131 | data_f1_data_out_valid <= data_out_valid(1); | |
|
132 | data_f2_data_out_valid <= data_out_valid(2); | |
|
133 | data_f3_data_out_valid <= data_out_valid(3); | |
|
134 | ||
|
135 | data_f0_data_out_valid_burst <= data_out_valid_burst(0); | |
|
136 | data_f1_data_out_valid_burst <= data_out_valid_burst(1); | |
|
137 | data_f2_data_out_valid_burst <= data_out_valid_burst(2); | |
|
138 | data_f3_data_out_valid_burst <= data_out_valid_burst(3); | |
|
139 | ||
|
140 | ||
|
141 | ||
|
142 | all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE | |
|
143 | addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I)); | |
|
144 | ||
|
145 | addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000") | |
|
146 | AND (UNSIGNED(addr_avail(I)) > 15) | |
|
147 | ELSE '0'; | |
|
148 | ||
|
149 | data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE | |
|
150 | '0' WHEN empty(I) = '1' ELSE | |
|
151 | '0' WHEN addr_burst_avail(I) = '1' ELSE | |
|
152 | '0' WHEN (run = '0') ELSE | |
|
153 | '1'; | |
|
154 | ||
|
155 | data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE | |
|
156 | '0' WHEN empty(I) = '1' ELSE | |
|
157 | '0' WHEN addr_burst_avail(I) = '0' ELSE | |
|
158 | '0' WHEN empty_almost(I) = '1' ELSE | |
|
159 | '0' WHEN (run = '0') ELSE | |
|
160 | '1'; | |
|
161 | END GENERATE all_bit_data_valid_out; | |
|
162 | ||
|
163 | ----------------------------------------------------------------------------- | |
|
164 | -- Register | |
|
165 | ----------------------------------------------------------------------------- | |
|
166 | all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE | |
|
167 | all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE | |
|
168 | PROCESS (clk, rstn) | |
|
169 | BEGIN -- PROCESS | |
|
170 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
171 | data_addr_v_reg(I, J) <= '0'; | |
|
172 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
173 | IF run = '1' AND status_full_ack(I) = '0' THEN | |
|
174 | data_addr_v_reg(I, J) <= data_addr_v_pre(I, J); | |
|
175 | ELSE | |
|
176 | data_addr_v_reg(I, J) <= data_addr_v_base(I, J); | |
|
177 | END IF; | |
|
178 | END IF; | |
|
179 | END PROCESS; | |
|
180 | ||
|
181 | data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J); | |
|
182 | ||
|
183 | END GENERATE all_data_addr; | |
|
184 | ||
|
185 | data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE | |
|
186 | data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE | |
|
187 | data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE | |
|
188 | data_addr_v_reg(3, J); | |
|
189 | ||
|
190 | data_addr_v_base(0, J) <= addr_data_f0_s(J); | |
|
191 | data_addr_v_base(1, J) <= addr_data_f1_s(J); | |
|
192 | data_addr_v_base(2, J) <= addr_data_f2_s(J); | |
|
193 | data_addr_v_base(3, J) <= addr_data_f3_s(J); | |
|
194 | ||
|
195 | data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ; | |
|
196 | data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ; | |
|
197 | data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ; | |
|
198 | data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ; | |
|
199 | ||
|
200 | END GENERATE all_data_bit; | |
|
201 | ||
|
202 | addr_data_f0_s <= addr_data_f0(31 DOWNTO 2); | |
|
203 | addr_data_f1_s <= addr_data_f1(31 DOWNTO 2); | |
|
204 | addr_data_f2_s <= addr_data_f2(31 DOWNTO 2); | |
|
205 | addr_data_f3_s <= addr_data_f3(31 DOWNTO 2); | |
|
206 | ||
|
207 | data_f0_addr_out(1 DOWNTO 0) <= "00"; | |
|
208 | data_f1_addr_out(1 DOWNTO 0) <= "00"; | |
|
209 | data_f2_addr_out(1 DOWNTO 0) <= "00"; | |
|
210 | data_f3_addr_out(1 DOWNTO 0) <= "00"; | |
|
211 | ||
|
212 | ||
|
213 | ||
|
214 | ||
|
215 | ----------------------------------------------------------------------------- | |
|
216 | -- ADDER | |
|
217 | ----------------------------------------------------------------------------- | |
|
218 | ||
|
219 | data_addr_pre <= data_addr_reg + 1; | |
|
220 | ||
|
221 | ----------------------------------------------------------------------------- | |
|
222 | -- FULL STATUS | |
|
223 | ----------------------------------------------------------------------------- | |
|
224 | all_status : FOR I IN 3 DOWNTO 0 GENERATE | |
|
225 | all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE | |
|
226 | addr_v_p(I)(J) <= data_addr_v_pre(I, J); | |
|
227 | addr_v_b(I)(J) <= data_addr_v_base(I, J); | |
|
228 | END GENERATE all_bit_addr; | |
|
229 | ||
|
230 | PROCESS (clk, rstn) | |
|
231 | BEGIN -- PROCESS | |
|
232 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
233 | status_full_s(I) <= '0'; | |
|
234 | status_full_err(I) <= '0'; | |
|
235 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
236 | IF run = '1' AND status_full_ack(I) = '0' THEN | |
|
237 | IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN | |
|
238 | status_full_s(I) <= '1'; | |
|
239 | IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN | |
|
240 | status_full_err(I) <= '1'; | |
|
241 | END IF; | |
|
242 | END IF; | |
|
243 | ELSE | |
|
244 | status_full_s(I) <= '0'; | |
|
245 | status_full_err(I) <= '0'; | |
|
246 | END IF; | |
|
247 | END IF; | |
|
248 | END PROCESS; | |
|
249 | ||
|
250 | END GENERATE all_status; | |
|
251 | ||
|
252 | status_full <= status_full_s; | |
|
253 | ||
|
254 | ||
|
255 | END beh; |
@@ -105,6 +105,7 PACKAGE lpp_waveform_pkg IS | |||
|
105 | 105 | tech : INTEGER; |
|
106 | 106 | data_size : INTEGER; |
|
107 | 107 | nb_data_by_buffer_size : INTEGER; |
|
108 | nb_word_by_buffer_size : INTEGER; | |
|
108 | 109 | nb_snapshot_param_size : INTEGER; |
|
109 | 110 | delta_vector_size : INTEGER; |
|
110 | 111 | delta_vector_size_f0_2 : INTEGER); |
@@ -126,6 +127,7 PACKAGE lpp_waveform_pkg IS | |||
|
126 | 127 | burst_f1 : IN STD_LOGIC; |
|
127 | 128 | burst_f2 : IN STD_LOGIC; |
|
128 | 129 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
129 | 131 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
130 | 132 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
131 | 133 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -238,6 +240,43 PACKAGE lpp_waveform_pkg IS | |||
|
238 | 240 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
239 | 241 | END COMPONENT; |
|
240 | 242 | |
|
243 | COMPONENT lpp_waveform_fifo_latencyCorrection | |
|
244 | GENERIC ( | |
|
245 | tech : INTEGER); | |
|
246 | PORT ( | |
|
247 | clk : IN STD_LOGIC; | |
|
248 | rstn : IN STD_LOGIC; | |
|
249 | run : IN STD_LOGIC; | |
|
250 | empty_almost : OUT STD_LOGIC; | |
|
251 | empty : OUT STD_LOGIC; | |
|
252 | data_ren : IN STD_LOGIC; | |
|
253 | rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
254 | empty_almost_fifo : IN STD_LOGIC; | |
|
255 | empty_fifo : IN STD_LOGIC; | |
|
256 | data_ren_fifo : OUT STD_LOGIC; | |
|
257 | rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
258 | END COMPONENT; | |
|
259 | ||
|
260 | COMPONENT lpp_waveform_fifo_withoutLatency | |
|
261 | GENERIC ( | |
|
262 | tech : INTEGER); | |
|
263 | PORT ( | |
|
264 | clk : IN STD_LOGIC; | |
|
265 | rstn : IN STD_LOGIC; | |
|
266 | run : IN STD_LOGIC; | |
|
267 | empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
268 | empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
269 | data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
270 | rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
271 | rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
272 | rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
273 | rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
274 | full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
275 | full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
276 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
277 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
278 | END COMPONENT; | |
|
279 | ||
|
241 | 280 |
|
|
242 | 281 | -- GEN ADDRESS |
|
243 | 282 | ----------------------------------------------------------------------------- |
@@ -273,5 +312,22 PACKAGE lpp_waveform_pkg IS | |||
|
273 | 312 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
274 | 313 | END COMPONENT; |
|
275 | 314 | |
|
315 | ----------------------------------------------------------------------------- | |
|
316 | -- lpp_waveform_fifo_arbiter_reg | |
|
317 | ----------------------------------------------------------------------------- | |
|
318 | COMPONENT lpp_waveform_fifo_arbiter_reg | |
|
319 | GENERIC ( | |
|
320 | data_size : INTEGER; | |
|
321 | data_nb : INTEGER); | |
|
322 | PORT ( | |
|
323 | clk : IN STD_LOGIC; | |
|
324 | rstn : IN STD_LOGIC; | |
|
325 | run : IN STD_LOGIC; | |
|
326 | max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); | |
|
327 | enable : IN STD_LOGIC; | |
|
328 | sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); | |
|
329 | data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
330 | data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); | |
|
331 | END COMPONENT; | |
|
276 | 332 | |
|
277 | 333 | END lpp_waveform_pkg; |
@@ -129,8 +129,8 BEGIN -- beh | |||
|
129 | 129 | BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot |
|
130 | 130 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
131 | 131 | counter_delta_snapshot <= 0; |
|
132 |
first_decount <= ' |
|
|
133 |
first_init <= ' |
|
|
132 | first_decount <= '1'; | |
|
133 | first_init <= '1'; | |
|
134 | 134 | start_snapshot_f0_pre <= '0'; |
|
135 | 135 | start_snapshot_f1 <= '0'; |
|
136 | 136 | start_snapshot_f2 <= '0'; |
@@ -1,6 +1,8 | |||
|
1 | 1 | lpp_waveform_pkg.vhd |
|
2 | 2 | lpp_waveform.vhd |
|
3 | 3 | lpp_waveform_burst.vhd |
|
4 | lpp_waveform_fifo_withoutLatency.vhd | |
|
5 | lpp_waveform_fifo_latencyCorrection.vhd | |
|
4 | 6 | lpp_waveform_fifo.vhd |
|
5 | 7 | lpp_waveform_fifo_arbiter.vhd |
|
6 | 8 | lpp_waveform_fifo_ctrl.vhd |
@@ -8,3 +10,4 lpp_waveform_snapshot.vhd | |||
|
8 | 10 | lpp_waveform_snapshot_controler.vhd |
|
9 | 11 | lpp_waveform_genaddress.vhd |
|
10 | 12 | lpp_waveform_dma_genvalid.vhd |
|
13 | lpp_waveform_fifo_arbiter_reg.vhd |
|
1 | NO CONTENT: file was removed |
|
1 | NO CONTENT: file was removed |
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