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Update Sample transformation from ADC to IIR_FILTER
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
130 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134
135
135 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
136 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137
138
138 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
139 SIGNAL rstn : STD_LOGIC;
140 SIGNAL rstn : STD_LOGIC;
140 BEGIN -- beh
141 BEGIN -- beh
141
142
142 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
143 -- CLK
144 -- CLK
144 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
145 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146
147
147 PROCESS(clk100MHz)
148 PROCESS(clk100MHz)
148 BEGIN
149 BEGIN
149 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 clk_50_s <= NOT clk_50_s;
151 clk_50_s <= NOT clk_50_s;
151 END IF;
152 END IF;
152 END PROCESS;
153 END PROCESS;
153
154
154 PROCESS(clk_50_s)
155 PROCESS(clk_50_s)
155 BEGIN
156 BEGIN
156 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 clk_25 <= NOT clk_25;
158 clk_25 <= NOT clk_25;
158 END IF;
159 END IF;
159 END PROCESS;
160 END PROCESS;
160
161
161 PROCESS(clk49_152MHz)
162 PROCESS(clk49_152MHz)
162 BEGIN
163 BEGIN
163 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 clk_24 <= NOT clk_24;
165 clk_24 <= NOT clk_24;
165 END IF;
166 END IF;
166 END PROCESS;
167 END PROCESS;
167
168
168 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
169
170
170 PROCESS (clk_25, rstn)
171 PROCESS (clk_25, rstn)
171 BEGIN -- PROCESS
172 BEGIN -- PROCESS
172 IF rstn = '0' THEN -- asynchronous reset (active low)
173 IF rstn = '0' THEN -- asynchronous reset (active low)
173 led(0) <= '0';
174 led(0) <= '0';
174 led(1) <= '0';
175 led(1) <= '0';
175 led(2) <= '0';
176 led(2) <= '0';
176 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 led(0) <= '0';
178 led(0) <= '0';
178 led(1) <= '1';
179 led(1) <= '1';
179 led(2) <= '1';
180 led(2) <= '1';
180 END IF;
181 END IF;
181 END PROCESS;
182 END PROCESS;
182
183
183 --
184 --
184 leon3_soc_1 : leon3_soc
185 leon3_soc_1 : leon3_soc
185 GENERIC MAP (
186 GENERIC MAP (
186 fabtech => apa3e,
187 fabtech => apa3e,
187 memtech => apa3e,
188 memtech => apa3e,
188 padtech => inferred,
189 padtech => inferred,
189 clktech => inferred,
190 clktech => inferred,
190 disas => 0,
191 disas => 0,
191 dbguart => 0,
192 dbguart => 0,
192 pclow => 2,
193 pclow => 2,
193 clk_freq => 25000,
194 clk_freq => 25000,
194 NB_CPU => 1,
195 NB_CPU => 1,
195 ENABLE_FPU => 1,
196 ENABLE_FPU => 1,
196 FPU_NETLIST => 0,
197 FPU_NETLIST => 0,
197 ENABLE_DSU => 1,
198 ENABLE_DSU => 1,
198 ENABLE_AHB_UART => 1,
199 ENABLE_AHB_UART => 1,
199 ENABLE_APB_UART => 1,
200 ENABLE_APB_UART => 1,
200 ENABLE_IRQMP => 1,
201 ENABLE_IRQMP => 1,
201 ENABLE_GPT => 1,
202 ENABLE_GPT => 1,
202 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_APB_SLAVE => NB_APB_SLAVE)
205 NB_APB_SLAVE => NB_APB_SLAVE)
205 PORT MAP (
206 PORT MAP (
206 clk => clk_25,
207 clk => clk_25,
207 reset => rstn,
208 reset => rstn,
208 errorn => OPEN,
209 errorn => OPEN,
209
210
210 ahbrxd => TAG1,
211 ahbrxd => TAG1,
211 ahbtxd => TAG3,
212 ahbtxd => TAG3,
212 urxd1 => TAG2,
213 urxd1 => TAG2,
213 utxd1 => TAG4,
214 utxd1 => TAG4,
214
215
215 address => address,
216 address => address,
216 data => data,
217 data => data,
217 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_WE => nSRAM_WE,
222 nSRAM_WE => nSRAM_WE,
222 nSRAM_CE => nSRAM_CE,
223 nSRAM_CE => nSRAM_CE,
223 nSRAM_OE => nSRAM_OE,
224 nSRAM_OE => nSRAM_OE,
224
225
225 apbi_ext => apbi_ext,
226 apbi_ext => apbi_ext,
226 apbo_ext => apbo_ext,
227 apbo_ext => apbo_ext,
227 ahbi_s_ext => ahbi_s_ext,
228 ahbi_s_ext => ahbi_s_ext,
228 ahbo_s_ext => ahbo_s_ext,
229 ahbo_s_ext => ahbo_s_ext,
229 ahbi_m_ext => ahbi_m_ext,
230 ahbi_m_ext => ahbi_m_ext,
230 ahbo_m_ext => ahbo_m_ext);
231 ahbo_m_ext => ahbo_m_ext);
231
232
232
233
233 -------------------------------------------------------------------------------
234 -------------------------------------------------------------------------------
234 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -------------------------------------------------------------------------------
236 -------------------------------------------------------------------------------
236 apb_lfr_time_management_1 : apb_lfr_time_management
237 apb_lfr_time_management_1 : apb_lfr_time_management
237 GENERIC MAP (
238 GENERIC MAP (
238 pindex => 6,
239 pindex => 6,
239 paddr => 6,
240 paddr => 6,
240 pmask => 16#fff#,
241 pmask => 16#fff#,
241 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 PORT MAP (
244 PORT MAP (
244 clk25MHz => clk_25,
245 clk25MHz => clk_25,
245 clk24_576MHz => clk_24, -- 49.152MHz/2
246 clk24_576MHz => clk_24, -- 49.152MHz/2
246 resetn => rstn,
247 resetn => rstn,
247 grspw_tick => swno.tickout,
248 grspw_tick => swno.tickout,
248 apbi => apbi_ext,
249 apbi => apbi_ext,
249 apbo => apbo_ext(6),
250 apbo => apbo_ext(6),
250 coarse_time => coarse_time,
251 coarse_time => coarse_time,
251 fine_time => fine_time);
252 fine_time => fine_time);
252
253
253 -----------------------------------------------------------------------
254 -----------------------------------------------------------------------
254 --- SpaceWire --------------------------------------------------------
255 --- SpaceWire --------------------------------------------------------
255 -----------------------------------------------------------------------
256 -----------------------------------------------------------------------
256
257
257 -- SPW_EN <= '1';
258 -- SPW_EN <= '1';
258
259
259 spw_clk <= clk_50_s;
260 spw_clk <= clk_50_s;
260 spw_rxtxclk <= spw_clk;
261 spw_rxtxclk <= spw_clk;
261 spw_rxclkn <= NOT spw_rxtxclk;
262 spw_rxclkn <= NOT spw_rxtxclk;
262
263
263 -- PADS for SPW1
264 -- PADS for SPW1
264 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 PORT MAP (spw1_din, dtmp(0));
266 PORT MAP (spw1_din, dtmp(0));
266 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 PORT MAP (spw1_sin, stmp(0));
268 PORT MAP (spw1_sin, stmp(0));
268 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 PORT MAP (spw1_dout, swno.d(0));
270 PORT MAP (spw1_dout, swno.d(0));
270 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 PORT MAP (spw1_sout, swno.s(0));
272 PORT MAP (spw1_sout, swno.s(0));
272 -- PADS FOR SPW2
273 -- PADS FOR SPW2
273 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 PORT MAP (spw2_sin, dtmp(1));
275 PORT MAP (spw2_sin, dtmp(1));
275 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 PORT MAP (spw2_din, stmp(1));
277 PORT MAP (spw2_din, stmp(1));
277 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 PORT MAP (spw2_dout, swno.d(1));
279 PORT MAP (spw2_dout, swno.d(1));
279 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 PORT MAP (spw2_sout, swno.s(1));
281 PORT MAP (spw2_sout, swno.s(1));
281
282
282 -- GRSPW PHY
283 -- GRSPW PHY
283 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_phy0 : grspw_phy
286 spw_phy0 : grspw_phy
286 GENERIC MAP(
287 GENERIC MAP(
287 tech => apa3e,
288 tech => apa3e,
288 rxclkbuftype => 1,
289 rxclkbuftype => 1,
289 scantest => 0)
290 scantest => 0)
290 PORT MAP(
291 PORT MAP(
291 rxrst => swno.rxrst,
292 rxrst => swno.rxrst,
292 di => dtmp(j),
293 di => dtmp(j),
293 si => stmp(j),
294 si => stmp(j),
294 rxclko => spw_rxclk(j),
295 rxclko => spw_rxclk(j),
295 do => swni.d(j),
296 do => swni.d(j),
296 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 END GENERATE spw_inputloop;
299 END GENERATE spw_inputloop;
299
300
300 -- SPW core
301 -- SPW core
301 sw0 : grspwm GENERIC MAP(
302 sw0 : grspwm GENERIC MAP(
302 tech => apa3e,
303 tech => apa3e,
303 hindex => 1,
304 hindex => 1,
304 pindex => 5,
305 pindex => 5,
305 paddr => 5,
306 paddr => 5,
306 pirq => 11,
307 pirq => 11,
307 sysfreq => 25000, -- CPU_FREQ
308 sysfreq => 25000, -- CPU_FREQ
308 rmap => 1,
309 rmap => 1,
309 rmapcrc => 1,
310 rmapcrc => 1,
310 fifosize1 => 16,
311 fifosize1 => 16,
311 fifosize2 => 16,
312 fifosize2 => 16,
312 rxclkbuftype => 1,
313 rxclkbuftype => 1,
313 rxunaligned => 0,
314 rxunaligned => 0,
314 rmapbufs => 4,
315 rmapbufs => 4,
315 ft => 0,
316 ft => 0,
316 netlist => 0,
317 netlist => 0,
317 ports => 2,
318 ports => 2,
318 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 memtech => apa3e,
320 memtech => apa3e,
320 destkey => 2,
321 destkey => 2,
321 spwcore => 1
322 spwcore => 1
322 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 )
326 )
326 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 swni, swno);
330 swni, swno);
330
331
331 swni.tickin <= '0';
332 swni.tickin <= '0';
332 swni.rmapen <= '1';
333 swni.rmapen <= '1';
333 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.tickinraw <= '0';
335 swni.tickinraw <= '0';
335 swni.timein <= (OTHERS => '0');
336 swni.timein <= (OTHERS => '0');
336 swni.dcrstval <= (OTHERS => '0');
337 swni.dcrstval <= (OTHERS => '0');
337 swni.timerrstval <= (OTHERS => '0');
338 swni.timerrstval <= (OTHERS => '0');
338
339
339 -------------------------------------------------------------------------------
340 -------------------------------------------------------------------------------
340 -- LFR ------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
341 -------------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
342 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 GENERIC MAP (
344 GENERIC MAP (
344 Mem_use => use_RAM,
345 Mem_use => use_RAM,
345 nb_data_by_buffer_size => 32,
346 nb_data_by_buffer_size => 32,
346 nb_word_by_buffer_size => 30,
347 nb_word_by_buffer_size => 30,
347 nb_snapshot_param_size => 32,
348 nb_snapshot_param_size => 32,
348 delta_vector_size => 32,
349 delta_vector_size => 32,
349 delta_vector_size_f0_2 => 7, -- log2(96)
350 delta_vector_size_f0_2 => 7, -- log2(96)
350 pindex => 15,
351 pindex => 15,
351 paddr => 15,
352 paddr => 15,
352 pmask => 16#fff#,
353 pmask => 16#fff#,
353 pirq_ms => 6,
354 pirq_ms => 6,
354 pirq_wfp => 14,
355 pirq_wfp => 14,
355 hindex => 2,
356 hindex => 2,
356 top_lfr_version => X"00010A") -- aa.bb.cc version
357 top_lfr_version => X"00010B") -- aa.bb.cc version
357 -- AA : BOARD NUMBER
358 -- AA : BOARD NUMBER
358 -- 0 => MINI_LFR
359 -- 0 => MINI_LFR
359 -- 1 => EM
360 -- 1 => EM
360 PORT MAP (
361 PORT MAP (
361 clk => clk_25,
362 clk => clk_25,
362 rstn => rstn,
363 rstn => rstn,
363 sample_B => sample(2 DOWNTO 0),
364 sample_B => sample_s(2 DOWNTO 0),
364 sample_E => sample(7 DOWNTO 3),
365 sample_E => sample_s(7 DOWNTO 3),
365 sample_val => sample_val,
366 sample_val => sample_val,
366 apbi => apbi_ext,
367 apbi => apbi_ext,
367 apbo => apbo_ext(15),
368 apbo => apbo_ext(15),
368 ahbi => ahbi_m_ext,
369 ahbi => ahbi_m_ext,
369 ahbo => ahbo_m_ext(2),
370 ahbo => ahbo_m_ext(2),
370 coarse_time => coarse_time,
371 coarse_time => coarse_time,
371 fine_time => fine_time,
372 fine_time => fine_time,
372 data_shaping_BW => bias_fail_sw,
373 data_shaping_BW => bias_fail_sw,
373 observation_reg => observation_reg);
374 observation_reg => observation_reg);
374
375
376
377 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
378 sample_s(I) <= sample(I) & '0' & '0';
379 END GENERATE all_sample;
380
375 -----------------------------------------------------------------------------
381 -----------------------------------------------------------------------------
376 --
382 --
377 -----------------------------------------------------------------------------
383 -----------------------------------------------------------------------------
378 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
384 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
379 GENERIC MAP (
385 GENERIC MAP (
380 ChanelCount => 8,
386 ChanelCount => 8,
381 ncycle_cnv_high => 40, -- TODO : 79
387 ncycle_cnv_high => 40, -- TODO : 79
382 ncycle_cnv => 250) -- TODO : 500
388 ncycle_cnv => 250) -- TODO : 500
383 PORT MAP (
389 PORT MAP (
384 cnv_clk => clk_24, -- TODO : 49.152
390 cnv_clk => clk_24, -- TODO : 49.152
385 cnv_rstn => rstn, -- ok
391 cnv_rstn => rstn, -- ok
386 cnv => ADC_smpclk, -- ok
392 cnv => ADC_smpclk, -- ok
387 clk => clk_25, -- ok
393 clk => clk_25, -- ok
388 rstn => rstn, -- ok
394 rstn => rstn, -- ok
389 ADC_data => ADC_data, -- ok
395 ADC_data => ADC_data, -- ok
390 ADC_nOE => ADC_OEB_bar_CH, -- ok
396 ADC_nOE => ADC_OEB_bar_CH, -- ok
391 sample => sample, -- ok
397 sample => sample, -- ok
392 sample_val => sample_val); -- ok
398 sample_val => sample_val); -- ok
393
399
394 TAG8 <= ADC_smpclk;
400 TAG8 <= ADC_smpclk;
395
401
396 END beh;
402 END beh;
Show file before | Show file after | Hide comments
@@ -1,580 +1,587
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
171
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
173
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
175
176
176 BEGIN -- beh
177 BEGIN -- beh
177
178
178 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
179 -- CLK
180 -- CLK
180 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
181
182
182 PROCESS(clk_50)
183 PROCESS(clk_50)
183 BEGIN
184 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
186 clk_50_s <= NOT clk_50_s;
186 END IF;
187 END IF;
187 END PROCESS;
188 END PROCESS;
188
189
189 PROCESS(clk_50_s)
190 PROCESS(clk_50_s)
190 BEGIN
191 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
193 clk_25 <= NOT clk_25;
193 END IF;
194 END IF;
194 END PROCESS;
195 END PROCESS;
195
196
196 PROCESS(clk_49)
197 PROCESS(clk_49)
197 BEGIN
198 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
200 clk_24 <= NOT clk_24;
200 END IF;
201 END IF;
201 END PROCESS;
202 END PROCESS;
202
203
203 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
204
205
205 PROCESS (clk_25, reset)
206 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
207 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
209 LED0 <= '0';
209 LED1 <= '0';
210 LED1 <= '0';
210 LED2 <= '0';
211 LED2 <= '0';
211 --IO1 <= '0';
212 --IO1 <= '0';
212 --IO2 <= '1';
213 --IO2 <= '1';
213 --IO3 <= '0';
214 --IO3 <= '0';
214 --IO4 <= '0';
215 --IO4 <= '0';
215 --IO5 <= '0';
216 --IO5 <= '0';
216 --IO6 <= '0';
217 --IO6 <= '0';
217 --IO7 <= '0';
218 --IO7 <= '0';
218 --IO8 <= '0';
219 --IO8 <= '0';
219 --IO9 <= '0';
220 --IO9 <= '0';
220 --IO10 <= '0';
221 --IO10 <= '0';
221 --IO11 <= '0';
222 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
224 LED0 <= '0';
224 LED1 <= '1';
225 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
227 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
229 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
230 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
231 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
232 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
233 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
234 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
235 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
236 --IO10 <= ADC_SDO(7);
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 END IF;
238 END IF;
238 END PROCESS;
239 END PROCESS;
239
240
240 PROCESS (clk_24, reset)
241 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
242 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
244 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s ;
246 I00_s <= NOT I00_s ;
246 END IF;
247 END IF;
247 END PROCESS;
248 END PROCESS;
248 -- IO0 <= I00_s;
249 -- IO0 <= I00_s;
249
250
250 --UARTs
251 --UARTs
251 nCTS1 <= '1';
252 nCTS1 <= '1';
252 nCTS2 <= '1';
253 nCTS2 <= '1';
253 nDCD2 <= '1';
254 nDCD2 <= '1';
254
255
255 --EXT CONNECTOR
256 --EXT CONNECTOR
256
257
257 --SPACE WIRE
258 --SPACE WIRE
258
259
259 leon3_soc_1 : leon3_soc
260 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
261 GENERIC MAP (
261 fabtech => apa3e,
262 fabtech => apa3e,
262 memtech => apa3e,
263 memtech => apa3e,
263 padtech => inferred,
264 padtech => inferred,
264 clktech => inferred,
265 clktech => inferred,
265 disas => 0,
266 disas => 0,
266 dbguart => 0,
267 dbguart => 0,
267 pclow => 2,
268 pclow => 2,
268 clk_freq => 25000,
269 clk_freq => 25000,
269 NB_CPU => 1,
270 NB_CPU => 1,
270 ENABLE_FPU => 1,
271 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
272 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
273 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
277 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
281 PORT MAP (
281 clk => clk_25,
282 clk => clk_25,
282 reset => reset,
283 reset => reset,
283 errorn => errorn,
284 errorn => errorn,
284 ahbrxd => TXD1,
285 ahbrxd => TXD1,
285 ahbtxd => RXD1,
286 ahbtxd => RXD1,
286 urxd1 => TXD2,
287 urxd1 => TXD2,
287 utxd1 => RXD2,
288 utxd1 => RXD2,
288 address => SRAM_A,
289 address => SRAM_A,
289 data => SRAM_DQ,
290 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
297 nSRAM_OE => SRAM_nOE,
297
298
298 apbi_ext => apbi_ext,
299 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
300 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
304 ahbo_m_ext => ahbo_m_ext);
304
305
305 -------------------------------------------------------------------------------
306 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
310 GENERIC MAP (
310 pindex => 6,
311 pindex => 6,
311 paddr => 6,
312 paddr => 6,
312 pmask => 16#fff#,
313 pmask => 16#fff#,
313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 PORT MAP (
316 PORT MAP (
316 clk25MHz => clk_25,
317 clk25MHz => clk_25,
317 clk24_576MHz => clk_24, -- 49.152MHz/2
318 clk24_576MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
319 resetn => reset,
319 grspw_tick => swno.tickout,
320 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
321 apbi => apbi_ext,
321 apbo => apbo_ext(6),
322 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
323 coarse_time => coarse_time,
323 fine_time => fine_time);
324 fine_time => fine_time);
324
325
325 -----------------------------------------------------------------------
326 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
328
329
329 SPW_EN <= '1';
330 SPW_EN <= '1';
330
331
331 spw_clk <= clk_50_s;
332 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
333 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334 spw_rxclkn <= NOT spw_rxtxclk;
334
335
335 -- PADS for SPW1
336 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
345 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
354
354 -- GRSPW PHY
355 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
358 spw_phy0 : grspw_phy
358 GENERIC MAP(
359 GENERIC MAP(
359 tech => apa3e,
360 tech => apa3e,
360 rxclkbuftype => 1,
361 rxclkbuftype => 1,
361 scantest => 0)
362 scantest => 0)
362 PORT MAP(
363 PORT MAP(
363 rxrst => swno.rxrst,
364 rxrst => swno.rxrst,
364 di => dtmp(j),
365 di => dtmp(j),
365 si => stmp(j),
366 si => stmp(j),
366 rxclko => spw_rxclk(j),
367 rxclko => spw_rxclk(j),
367 do => swni.d(j),
368 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
371 END GENERATE spw_inputloop;
371
372
372 -- SPW core
373 -- SPW core
373 sw0 : grspwm GENERIC MAP(
374 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
375 tech => apa3e,
375 hindex => 1,
376 hindex => 1,
376 pindex => 5,
377 pindex => 5,
377 paddr => 5,
378 paddr => 5,
378 pirq => 11,
379 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
380 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
381 rmap => 1,
381 rmapcrc => 1,
382 rmapcrc => 1,
382 fifosize1 => 16,
383 fifosize1 => 16,
383 fifosize2 => 16,
384 fifosize2 => 16,
384 rxclkbuftype => 1,
385 rxclkbuftype => 1,
385 rxunaligned => 0,
386 rxunaligned => 0,
386 rmapbufs => 4,
387 rmapbufs => 4,
387 ft => 0,
388 ft => 0,
388 netlist => 0,
389 netlist => 0,
389 ports => 2,
390 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
392 memtech => apa3e,
392 destkey => 2,
393 destkey => 2,
393 spwcore => 1
394 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
398 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
402 swni, swno);
402
403
403 swni.tickin <= '0';
404 swni.tickin <= '0';
404 swni.rmapen <= '1';
405 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
407 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
408 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
410
411
411 -------------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
415 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
416 GENERIC MAP (
416 Mem_use => use_RAM,
417 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
418 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
419 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
420 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
423 pindex => 15,
423 paddr => 15,
424 paddr => 15,
424 pmask => 16#fff#,
425 pmask => 16#fff#,
425 pirq_ms => 6,
426 pirq_ms => 6,
426 pirq_wfp => 14,
427 pirq_wfp => 14,
427 hindex => 2,
428 hindex => 2,
428 top_lfr_version => X"00010A") -- aa.bb.cc version
429 top_lfr_version => X"00010A") -- aa.bb.cc version
429 PORT MAP (
430 PORT MAP (
430 clk => clk_25,
431 clk => clk_25,
431 rstn => reset,
432 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
433 sample_B => sample_s(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
434 sample_E => sample_s(7 DOWNTO 3),
434 sample_val => sample_val,
435 sample_val => sample_val,
435 apbi => apbi_ext,
436 apbi => apbi_ext,
436 apbo => apbo_ext(15),
437 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
438 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
439 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
440 coarse_time => coarse_time,
440 fine_time => fine_time,
441 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
442 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
443 observation_reg => observation_reg);
443
444
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 sample_s(I) <= sample(I) & '0' & '0';
447 END GENERATE all_sample;
448
449
450
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
452 GENERIC MAP(
446 ChannelCount => 8,
453 ChannelCount => 8,
447 SampleNbBits => 14,
454 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
457 PORT MAP (
451 -- CONV
458 -- CONV
452 cnv_clk => clk_24,
459 cnv_clk => clk_24,
453 cnv_rstn => reset,
460 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
461 cnv => ADC_nCS_sig,
455 -- DATA
462 -- DATA
456 clk => clk_25,
463 clk => clk_25,
457 rstn => reset,
464 rstn => reset,
458 sck => ADC_CLK_sig,
465 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
466 sdo => ADC_SDO_sig,
460 -- SAMPLE
467 -- SAMPLE
461 sample => sample,
468 sample => sample,
462 sample_val => sample_val);
469 sample_val => sample_val);
463
470
464 --IO10 <= ADC_SDO_sig(5);
471 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
472 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
473 --IO8 <= ADC_SDO_sig(3);
467
474
468 ADC_nCS <= ADC_nCS_sig;
475 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
476 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
477 ADC_SDO_sig <= ADC_SDO;
471
478
472 ----------------------------------------------------------------------
479 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
481 ----------------------------------------------------------------------
475
482
476 grgpio0 : grgpio
483 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
486
480 --pio_pad_0 : iopad
487 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
490 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
493 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
496 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
499 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
502 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
505 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
506 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
508 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
509 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
511
505 PROCESS (clk_25, reset)
512 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
513 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
514 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
515 IO0 <= '0';
509 IO1 <= '0';
516 IO1 <= '0';
510 IO2 <= '0';
517 IO2 <= '0';
511 IO3 <= '0';
518 IO3 <= '0';
512 IO4 <= '0';
519 IO4 <= '0';
513 IO5 <= '0';
520 IO5 <= '0';
514 IO6 <= '0';
521 IO6 <= '0';
515 IO7 <= '0';
522 IO7 <= '0';
516 IO8 <= '0';
523 IO8 <= '0';
517 IO9 <= '0';
524 IO9 <= '0';
518 IO10 <= '0';
525 IO10 <= '0';
519 IO11 <= '0';
526 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
528 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
529 WHEN "00" =>
523 IO0 <= observation_reg(0 );
530 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
531 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
532 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
533 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
534 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
535 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
536 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
537 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
538 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
539 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
540 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
541 IO11 <= observation_reg(11);
535 WHEN "01" =>
542 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
543 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
544 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
545 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
546 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
547 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
548 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
549 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
550 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
551 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
552 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
553 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
554 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
555 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
556 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
564 IO8 <= '0';
558 IO9 <= '0';
565 IO9 <= '0';
559 IO10 <= '0';
566 IO10 <= '0';
560 IO11 <= '0';
567 IO11 <= '0';
561 WHEN "11" =>
568 WHEN "11" =>
562 IO0 <= '0';
569 IO0 <= '0';
563 IO1 <= '0';
570 IO1 <= '0';
564 IO2 <= '0';
571 IO2 <= '0';
565 IO3 <= '0';
572 IO3 <= '0';
566 IO4 <= '0';
573 IO4 <= '0';
567 IO5 <= '0';
574 IO5 <= '0';
568 IO6 <= '0';
575 IO6 <= '0';
569 IO7 <= '0';
576 IO7 <= '0';
570 IO8 <= '0';
577 IO8 <= '0';
571 IO9 <= '0';
578 IO9 <= '0';
572 IO10 <= '0';
579 IO10 <= '0';
573 IO11 <= '0';
580 IO11 <= '0';
574 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
575 END CASE;
582 END CASE;
576
583
577 END IF;
584 END IF;
578 END PROCESS;
585 END PROCESS;
579
586
580 END beh;
587 END beh;
Show file before | Show file after | Hide comments
@@ -1,764 +1,764
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
75
76 ---- debug FIFO_IN
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
85
86 ----debug FIFO OUT
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
95
96 ----debug DMA IN
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
105 );
106 END lpp_lfr;
106 END lpp_lfr;
107
107
108 ARCHITECTURE beh OF lpp_lfr IS
108 ARCHITECTURE beh OF lpp_lfr IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
116 --
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
130 --
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
134
135 -- SM
135 -- SM
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -- WFP
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
181
182 SIGNAL run : STD_LOGIC;
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
208
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 --
210 --
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
227
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 -- DMA RR
229 -- DMA RR
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 -- DMA_REG
241 -- DMA_REG
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
249
250
250
251 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
252 -- DMA
252 -- DMA
253 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- DEBUG
263 -- DEBUG
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265 --
265 --
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270
270
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 -- MS
281 -- MS
282 -----------------------------------------------------------------------------
282 -----------------------------------------------------------------------------
283
283
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL data_ms_valid : STD_LOGIC;
286 SIGNAL data_ms_valid : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
290
290
291 SIGNAL run_ms : STD_LOGIC;
291 SIGNAL run_ms : STD_LOGIC;
292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
293
293
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298
298
299
299
300 BEGIN
300 BEGIN
301
301
302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
302 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
303 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
304
304
305 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
305 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
306 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 END GENERATE all_channel;
307 --END GENERATE all_channel;
308
308
309 -----------------------------------------------------------------------------
309 -----------------------------------------------------------------------------
310 lpp_lfr_filter_1 : lpp_lfr_filter
310 lpp_lfr_filter_1 : lpp_lfr_filter
311 GENERIC MAP (
311 GENERIC MAP (
312 Mem_use => Mem_use)
312 Mem_use => Mem_use)
313 PORT MAP (
313 PORT MAP (
314 sample => sample_s,
314 sample => sample_s,
315 sample_val => sample_val,
315 sample_val => sample_val,
316 clk => clk,
316 clk => clk,
317 rstn => rstn,
317 rstn => rstn,
318 data_shaping_SP0 => data_shaping_SP0,
318 data_shaping_SP0 => data_shaping_SP0,
319 data_shaping_SP1 => data_shaping_SP1,
319 data_shaping_SP1 => data_shaping_SP1,
320 data_shaping_R0 => data_shaping_R0,
320 data_shaping_R0 => data_shaping_R0,
321 data_shaping_R1 => data_shaping_R1,
321 data_shaping_R1 => data_shaping_R1,
322 sample_f0_val => sample_f0_val,
322 sample_f0_val => sample_f0_val,
323 sample_f1_val => sample_f1_val,
323 sample_f1_val => sample_f1_val,
324 sample_f2_val => sample_f2_val,
324 sample_f2_val => sample_f2_val,
325 sample_f3_val => sample_f3_val,
325 sample_f3_val => sample_f3_val,
326 sample_f0_wdata => sample_f0_data,
326 sample_f0_wdata => sample_f0_data,
327 sample_f1_wdata => sample_f1_data,
327 sample_f1_wdata => sample_f1_data,
328 sample_f2_wdata => sample_f2_data,
328 sample_f2_wdata => sample_f2_data,
329 sample_f3_wdata => sample_f3_data);
329 sample_f3_wdata => sample_f3_data);
330
330
331 -----------------------------------------------------------------------------
331 -----------------------------------------------------------------------------
332 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
332 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
333 GENERIC MAP (
333 GENERIC MAP (
334 nb_data_by_buffer_size => nb_data_by_buffer_size,
334 nb_data_by_buffer_size => nb_data_by_buffer_size,
335 nb_word_by_buffer_size => nb_word_by_buffer_size,
335 nb_word_by_buffer_size => nb_word_by_buffer_size,
336 nb_snapshot_param_size => nb_snapshot_param_size,
336 nb_snapshot_param_size => nb_snapshot_param_size,
337 delta_vector_size => delta_vector_size,
337 delta_vector_size => delta_vector_size,
338 delta_vector_size_f0_2 => delta_vector_size_f0_2,
338 delta_vector_size_f0_2 => delta_vector_size_f0_2,
339 pindex => pindex,
339 pindex => pindex,
340 paddr => paddr,
340 paddr => paddr,
341 pmask => pmask,
341 pmask => pmask,
342 pirq_ms => pirq_ms,
342 pirq_ms => pirq_ms,
343 pirq_wfp => pirq_wfp,
343 pirq_wfp => pirq_wfp,
344 top_lfr_version => top_lfr_version)
344 top_lfr_version => top_lfr_version)
345 PORT MAP (
345 PORT MAP (
346 HCLK => clk,
346 HCLK => clk,
347 HRESETn => rstn,
347 HRESETn => rstn,
348 apbi => apbi,
348 apbi => apbi,
349 apbo => apbo,
349 apbo => apbo,
350
350
351 run_ms => run_ms,
351 run_ms => run_ms,
352
352
353 ready_matrix_f0_0 => ready_matrix_f0_0,
353 ready_matrix_f0_0 => ready_matrix_f0_0,
354 ready_matrix_f0_1 => ready_matrix_f0_1,
354 ready_matrix_f0_1 => ready_matrix_f0_1,
355 ready_matrix_f1 => ready_matrix_f1,
355 ready_matrix_f1 => ready_matrix_f1,
356 ready_matrix_f2 => ready_matrix_f2,
356 ready_matrix_f2 => ready_matrix_f2,
357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 error_bad_component_error => error_bad_component_error,
358 error_bad_component_error => error_bad_component_error,
359 debug_reg => debug_reg,
359 debug_reg => debug_reg,
360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 status_ready_matrix_f1 => status_ready_matrix_f1,
362 status_ready_matrix_f1 => status_ready_matrix_f1,
363 status_ready_matrix_f2 => status_ready_matrix_f2,
363 status_ready_matrix_f2 => status_ready_matrix_f2,
364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 status_error_bad_component_error => status_error_bad_component_error,
365 status_error_bad_component_error => status_error_bad_component_error,
366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 config_active_interruption_onError => config_active_interruption_onError,
367 config_active_interruption_onError => config_active_interruption_onError,
368
368
369 matrix_time_f0_0 => matrix_time_f0_0,
369 matrix_time_f0_0 => matrix_time_f0_0,
370 matrix_time_f0_1 => matrix_time_f0_1,
370 matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f1 => matrix_time_f1,
371 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
372 matrix_time_f2 => matrix_time_f2,
373
373
374 addr_matrix_f0_0 => addr_matrix_f0_0,
374 addr_matrix_f0_0 => addr_matrix_f0_0,
375 addr_matrix_f0_1 => addr_matrix_f0_1,
375 addr_matrix_f0_1 => addr_matrix_f0_1,
376 addr_matrix_f1 => addr_matrix_f1,
376 addr_matrix_f1 => addr_matrix_f1,
377 addr_matrix_f2 => addr_matrix_f2,
377 addr_matrix_f2 => addr_matrix_f2,
378 status_full => status_full,
378 status_full => status_full,
379 status_full_ack => status_full_ack,
379 status_full_ack => status_full_ack,
380 status_full_err => status_full_err,
380 status_full_err => status_full_err,
381 status_new_err => status_new_err,
381 status_new_err => status_new_err,
382 data_shaping_BW => data_shaping_BW,
382 data_shaping_BW => data_shaping_BW,
383 data_shaping_SP0 => data_shaping_SP0,
383 data_shaping_SP0 => data_shaping_SP0,
384 data_shaping_SP1 => data_shaping_SP1,
384 data_shaping_SP1 => data_shaping_SP1,
385 data_shaping_R0 => data_shaping_R0,
385 data_shaping_R0 => data_shaping_R0,
386 data_shaping_R1 => data_shaping_R1,
386 data_shaping_R1 => data_shaping_R1,
387 delta_snapshot => delta_snapshot,
387 delta_snapshot => delta_snapshot,
388 delta_f0 => delta_f0,
388 delta_f0 => delta_f0,
389 delta_f0_2 => delta_f0_2,
389 delta_f0_2 => delta_f0_2,
390 delta_f1 => delta_f1,
390 delta_f1 => delta_f1,
391 delta_f2 => delta_f2,
391 delta_f2 => delta_f2,
392 nb_data_by_buffer => nb_data_by_buffer,
392 nb_data_by_buffer => nb_data_by_buffer,
393 nb_word_by_buffer => nb_word_by_buffer,
393 nb_word_by_buffer => nb_word_by_buffer,
394 nb_snapshot_param => nb_snapshot_param,
394 nb_snapshot_param => nb_snapshot_param,
395 enable_f0 => enable_f0,
395 enable_f0 => enable_f0,
396 enable_f1 => enable_f1,
396 enable_f1 => enable_f1,
397 enable_f2 => enable_f2,
397 enable_f2 => enable_f2,
398 enable_f3 => enable_f3,
398 enable_f3 => enable_f3,
399 burst_f0 => burst_f0,
399 burst_f0 => burst_f0,
400 burst_f1 => burst_f1,
400 burst_f1 => burst_f1,
401 burst_f2 => burst_f2,
401 burst_f2 => burst_f2,
402 run => run,
402 run => run,
403 addr_data_f0 => addr_data_f0,
403 addr_data_f0 => addr_data_f0,
404 addr_data_f1 => addr_data_f1,
404 addr_data_f1 => addr_data_f1,
405 addr_data_f2 => addr_data_f2,
405 addr_data_f2 => addr_data_f2,
406 addr_data_f3 => addr_data_f3,
406 addr_data_f3 => addr_data_f3,
407 start_date => start_date,
407 start_date => start_date,
408 ---------------------------------------------------------------------------
408 ---------------------------------------------------------------------------
409 debug_reg0 => debug_reg0,
409 debug_reg0 => debug_reg0,
410 debug_reg1 => debug_reg1,
410 debug_reg1 => debug_reg1,
411 debug_reg2 => debug_reg2,
411 debug_reg2 => debug_reg2,
412 debug_reg3 => debug_reg3,
412 debug_reg3 => debug_reg3,
413 debug_reg4 => debug_reg4,
413 debug_reg4 => debug_reg4,
414 debug_reg5 => debug_reg5,
414 debug_reg5 => debug_reg5,
415 debug_reg6 => debug_reg6,
415 debug_reg6 => debug_reg6,
416 debug_reg7 => debug_reg7);
416 debug_reg7 => debug_reg7);
417
417
418 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
418 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
419 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
419 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
420 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
420 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
421 -----------------------------------------------------------------------------
421 -----------------------------------------------------------------------------
422 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
422 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
423 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
423 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
424 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
424 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
425 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
425 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
426
426
427
427
428 -----------------------------------------------------------------------------
428 -----------------------------------------------------------------------------
429 lpp_waveform_1 : lpp_waveform
429 lpp_waveform_1 : lpp_waveform
430 GENERIC MAP (
430 GENERIC MAP (
431 tech => inferred,
431 tech => inferred,
432 data_size => 6*16,
432 data_size => 6*16,
433 nb_data_by_buffer_size => nb_data_by_buffer_size,
433 nb_data_by_buffer_size => nb_data_by_buffer_size,
434 nb_word_by_buffer_size => nb_word_by_buffer_size,
434 nb_word_by_buffer_size => nb_word_by_buffer_size,
435 nb_snapshot_param_size => nb_snapshot_param_size,
435 nb_snapshot_param_size => nb_snapshot_param_size,
436 delta_vector_size => delta_vector_size,
436 delta_vector_size => delta_vector_size,
437 delta_vector_size_f0_2 => delta_vector_size_f0_2
437 delta_vector_size_f0_2 => delta_vector_size_f0_2
438 )
438 )
439 PORT MAP (
439 PORT MAP (
440 clk => clk,
440 clk => clk,
441 rstn => rstn,
441 rstn => rstn,
442
442
443 reg_run => run,
443 reg_run => run,
444 reg_start_date => start_date,
444 reg_start_date => start_date,
445 reg_delta_snapshot => delta_snapshot,
445 reg_delta_snapshot => delta_snapshot,
446 reg_delta_f0 => delta_f0,
446 reg_delta_f0 => delta_f0,
447 reg_delta_f0_2 => delta_f0_2,
447 reg_delta_f0_2 => delta_f0_2,
448 reg_delta_f1 => delta_f1,
448 reg_delta_f1 => delta_f1,
449 reg_delta_f2 => delta_f2,
449 reg_delta_f2 => delta_f2,
450
450
451 enable_f0 => enable_f0,
451 enable_f0 => enable_f0,
452 enable_f1 => enable_f1,
452 enable_f1 => enable_f1,
453 enable_f2 => enable_f2,
453 enable_f2 => enable_f2,
454 enable_f3 => enable_f3,
454 enable_f3 => enable_f3,
455 burst_f0 => burst_f0,
455 burst_f0 => burst_f0,
456 burst_f1 => burst_f1,
456 burst_f1 => burst_f1,
457 burst_f2 => burst_f2,
457 burst_f2 => burst_f2,
458
458
459 nb_data_by_buffer => nb_data_by_buffer,
459 nb_data_by_buffer => nb_data_by_buffer,
460 nb_word_by_buffer => nb_word_by_buffer,
460 nb_word_by_buffer => nb_word_by_buffer,
461 nb_snapshot_param => nb_snapshot_param,
461 nb_snapshot_param => nb_snapshot_param,
462 status_full => status_full,
462 status_full => status_full,
463 status_full_ack => status_full_ack,
463 status_full_ack => status_full_ack,
464 status_full_err => status_full_err,
464 status_full_err => status_full_err,
465 status_new_err => status_new_err,
465 status_new_err => status_new_err,
466
466
467 coarse_time => coarse_time,
467 coarse_time => coarse_time,
468 fine_time => fine_time,
468 fine_time => fine_time,
469
469
470 --f0
470 --f0
471 addr_data_f0 => addr_data_f0,
471 addr_data_f0 => addr_data_f0,
472 data_f0_in_valid => sample_f0_val,
472 data_f0_in_valid => sample_f0_val,
473 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
473 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
474 --f1
474 --f1
475 addr_data_f1 => addr_data_f1,
475 addr_data_f1 => addr_data_f1,
476 data_f1_in_valid => sample_f1_val,
476 data_f1_in_valid => sample_f1_val,
477 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
477 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
478 --f2
478 --f2
479 addr_data_f2 => addr_data_f2,
479 addr_data_f2 => addr_data_f2,
480 data_f2_in_valid => sample_f2_val,
480 data_f2_in_valid => sample_f2_val,
481 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
481 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
482 --f3
482 --f3
483 addr_data_f3 => addr_data_f3,
483 addr_data_f3 => addr_data_f3,
484 data_f3_in_valid => sample_f3_val,
484 data_f3_in_valid => sample_f3_val,
485 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
485 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
486 -- OUTPUT -- DMA interface
486 -- OUTPUT -- DMA interface
487 --f0
487 --f0
488 data_f0_addr_out => data_f0_addr_out_s,
488 data_f0_addr_out => data_f0_addr_out_s,
489 data_f0_data_out => data_f0_data_out,
489 data_f0_data_out => data_f0_data_out,
490 data_f0_data_out_valid => data_f0_data_out_valid_s,
490 data_f0_data_out_valid => data_f0_data_out_valid_s,
491 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
491 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
492 data_f0_data_out_ren => data_f0_data_out_ren,
492 data_f0_data_out_ren => data_f0_data_out_ren,
493 --f1
493 --f1
494 data_f1_addr_out => data_f1_addr_out_s,
494 data_f1_addr_out => data_f1_addr_out_s,
495 data_f1_data_out => data_f1_data_out,
495 data_f1_data_out => data_f1_data_out,
496 data_f1_data_out_valid => data_f1_data_out_valid_s,
496 data_f1_data_out_valid => data_f1_data_out_valid_s,
497 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
497 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
498 data_f1_data_out_ren => data_f1_data_out_ren,
498 data_f1_data_out_ren => data_f1_data_out_ren,
499 --f2
499 --f2
500 data_f2_addr_out => data_f2_addr_out_s,
500 data_f2_addr_out => data_f2_addr_out_s,
501 data_f2_data_out => data_f2_data_out,
501 data_f2_data_out => data_f2_data_out,
502 data_f2_data_out_valid => data_f2_data_out_valid_s,
502 data_f2_data_out_valid => data_f2_data_out_valid_s,
503 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
503 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
504 data_f2_data_out_ren => data_f2_data_out_ren,
504 data_f2_data_out_ren => data_f2_data_out_ren,
505 --f3
505 --f3
506 data_f3_addr_out => data_f3_addr_out_s,
506 data_f3_addr_out => data_f3_addr_out_s,
507 data_f3_data_out => data_f3_data_out,
507 data_f3_data_out => data_f3_data_out,
508 data_f3_data_out_valid => data_f3_data_out_valid_s,
508 data_f3_data_out_valid => data_f3_data_out_valid_s,
509 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
509 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
510 data_f3_data_out_ren => data_f3_data_out_ren ,
510 data_f3_data_out_ren => data_f3_data_out_ren ,
511
511
512 -------------------------------------------------------------------------
512 -------------------------------------------------------------------------
513 observation_reg => OPEN
513 observation_reg => OPEN
514
514
515 );
515 );
516
516
517
517
518 -----------------------------------------------------------------------------
518 -----------------------------------------------------------------------------
519 -- TEMP
519 -- TEMP
520 -----------------------------------------------------------------------------
520 -----------------------------------------------------------------------------
521
521
522 PROCESS (clk, rstn)
522 PROCESS (clk, rstn)
523 BEGIN -- PROCESS
523 BEGIN -- PROCESS
524 IF rstn = '0' THEN -- asynchronous reset (active low)
524 IF rstn = '0' THEN -- asynchronous reset (active low)
525 data_f0_data_out_valid <= '0';
525 data_f0_data_out_valid <= '0';
526 data_f0_data_out_valid_burst <= '0';
526 data_f0_data_out_valid_burst <= '0';
527 data_f1_data_out_valid <= '0';
527 data_f1_data_out_valid <= '0';
528 data_f1_data_out_valid_burst <= '0';
528 data_f1_data_out_valid_burst <= '0';
529 data_f2_data_out_valid <= '0';
529 data_f2_data_out_valid <= '0';
530 data_f2_data_out_valid_burst <= '0';
530 data_f2_data_out_valid_burst <= '0';
531 data_f3_data_out_valid <= '0';
531 data_f3_data_out_valid <= '0';
532 data_f3_data_out_valid_burst <= '0';
532 data_f3_data_out_valid_burst <= '0';
533 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
533 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
534 data_f0_data_out_valid <= data_f0_data_out_valid_s;
534 data_f0_data_out_valid <= data_f0_data_out_valid_s;
535 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
535 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
536 data_f1_data_out_valid <= data_f1_data_out_valid_s;
536 data_f1_data_out_valid <= data_f1_data_out_valid_s;
537 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
537 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
538 data_f2_data_out_valid <= data_f2_data_out_valid_s;
538 data_f2_data_out_valid <= data_f2_data_out_valid_s;
539 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
539 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
540 data_f3_data_out_valid <= data_f3_data_out_valid_s;
540 data_f3_data_out_valid <= data_f3_data_out_valid_s;
541 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
541 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
542 END IF;
542 END IF;
543 END PROCESS;
543 END PROCESS;
544
544
545 data_f0_addr_out <= data_f0_addr_out_s;
545 data_f0_addr_out <= data_f0_addr_out_s;
546 data_f1_addr_out <= data_f1_addr_out_s;
546 data_f1_addr_out <= data_f1_addr_out_s;
547 data_f2_addr_out <= data_f2_addr_out_s;
547 data_f2_addr_out <= data_f2_addr_out_s;
548 data_f3_addr_out <= data_f3_addr_out_s;
548 data_f3_addr_out <= data_f3_addr_out_s;
549
549
550 -----------------------------------------------------------------------------
550 -----------------------------------------------------------------------------
551 -- RoundRobin Selection For DMA
551 -- RoundRobin Selection For DMA
552 -----------------------------------------------------------------------------
552 -----------------------------------------------------------------------------
553
553
554 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
554 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
555 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
555 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
556 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
556 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
557 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
557 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
558
558
559 RR_Arbiter_4_1 : RR_Arbiter_4
559 RR_Arbiter_4_1 : RR_Arbiter_4
560 PORT MAP (
560 PORT MAP (
561 clk => clk,
561 clk => clk,
562 rstn => rstn,
562 rstn => rstn,
563 in_valid => dma_rr_valid,
563 in_valid => dma_rr_valid,
564 out_grant => dma_rr_grant_s);
564 out_grant => dma_rr_grant_s);
565
565
566 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
566 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
567 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
567 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
568 dma_rr_valid_ms(2) <= '0';
568 dma_rr_valid_ms(2) <= '0';
569 dma_rr_valid_ms(3) <= '0';
569 dma_rr_valid_ms(3) <= '0';
570
570
571 RR_Arbiter_4_2 : RR_Arbiter_4
571 RR_Arbiter_4_2 : RR_Arbiter_4
572 PORT MAP (
572 PORT MAP (
573 clk => clk,
573 clk => clk,
574 rstn => rstn,
574 rstn => rstn,
575 in_valid => dma_rr_valid_ms,
575 in_valid => dma_rr_valid_ms,
576 out_grant => dma_rr_grant_ms);
576 out_grant => dma_rr_grant_ms);
577
577
578 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
578 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
579
579
580
580
581 -----------------------------------------------------------------------------
581 -----------------------------------------------------------------------------
582 -- in : dma_rr_grant
582 -- in : dma_rr_grant
583 -- send
583 -- send
584 -- out : dma_sel
584 -- out : dma_sel
585 -- dma_valid_burst
585 -- dma_valid_burst
586 -- dma_sel_valid
586 -- dma_sel_valid
587 -----------------------------------------------------------------------------
587 -----------------------------------------------------------------------------
588 PROCESS (clk, rstn)
588 PROCESS (clk, rstn)
589 BEGIN -- PROCESS
589 BEGIN -- PROCESS
590 IF rstn = '0' THEN -- asynchronous reset (active low)
590 IF rstn = '0' THEN -- asynchronous reset (active low)
591 dma_sel <= (OTHERS => '0');
591 dma_sel <= (OTHERS => '0');
592 dma_send <= '0';
592 dma_send <= '0';
593 dma_valid_burst <= '0';
593 dma_valid_burst <= '0';
594 data_ms_done <= '0';
594 data_ms_done <= '0';
595 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
595 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
596 IF run = '1' THEN
596 IF run = '1' THEN
597 data_ms_done <= '0';
597 data_ms_done <= '0';
598 IF dma_sel = "00000" OR dma_done = '1' THEN
598 IF dma_sel = "00000" OR dma_done = '1' THEN
599 dma_sel <= dma_rr_grant;
599 dma_sel <= dma_rr_grant;
600 IF dma_rr_grant(0) = '1' THEN
600 IF dma_rr_grant(0) = '1' THEN
601 dma_send <= '1';
601 dma_send <= '1';
602 dma_valid_burst <= data_f0_data_out_valid_burst;
602 dma_valid_burst <= data_f0_data_out_valid_burst;
603 dma_sel_valid <= data_f0_data_out_valid;
603 dma_sel_valid <= data_f0_data_out_valid;
604 ELSIF dma_rr_grant(1) = '1' THEN
604 ELSIF dma_rr_grant(1) = '1' THEN
605 dma_send <= '1';
605 dma_send <= '1';
606 dma_valid_burst <= data_f1_data_out_valid_burst;
606 dma_valid_burst <= data_f1_data_out_valid_burst;
607 dma_sel_valid <= data_f1_data_out_valid;
607 dma_sel_valid <= data_f1_data_out_valid;
608 ELSIF dma_rr_grant(2) = '1' THEN
608 ELSIF dma_rr_grant(2) = '1' THEN
609 dma_send <= '1';
609 dma_send <= '1';
610 dma_valid_burst <= data_f2_data_out_valid_burst;
610 dma_valid_burst <= data_f2_data_out_valid_burst;
611 dma_sel_valid <= data_f2_data_out_valid;
611 dma_sel_valid <= data_f2_data_out_valid;
612 ELSIF dma_rr_grant(3) = '1' THEN
612 ELSIF dma_rr_grant(3) = '1' THEN
613 dma_send <= '1';
613 dma_send <= '1';
614 dma_valid_burst <= data_f3_data_out_valid_burst;
614 dma_valid_burst <= data_f3_data_out_valid_burst;
615 dma_sel_valid <= data_f3_data_out_valid;
615 dma_sel_valid <= data_f3_data_out_valid;
616 ELSIF dma_rr_grant(4) = '1' THEN
616 ELSIF dma_rr_grant(4) = '1' THEN
617 dma_send <= '1';
617 dma_send <= '1';
618 dma_valid_burst <= data_ms_valid_burst;
618 dma_valid_burst <= data_ms_valid_burst;
619 dma_sel_valid <= data_ms_valid;
619 dma_sel_valid <= data_ms_valid;
620 END IF;
620 END IF;
621
621
622 IF dma_sel(4) = '1' THEN
622 IF dma_sel(4) = '1' THEN
623 data_ms_done <= '1';
623 data_ms_done <= '1';
624 END IF;
624 END IF;
625 ELSE
625 ELSE
626 dma_sel <= dma_sel;
626 dma_sel <= dma_sel;
627 dma_send <= '0';
627 dma_send <= '0';
628 END IF;
628 END IF;
629 ELSE
629 ELSE
630 data_ms_done <= '0';
630 data_ms_done <= '0';
631 dma_sel <= (OTHERS => '0');
631 dma_sel <= (OTHERS => '0');
632 dma_send <= '0';
632 dma_send <= '0';
633 dma_valid_burst <= '0';
633 dma_valid_burst <= '0';
634 END IF;
634 END IF;
635 END IF;
635 END IF;
636 END PROCESS;
636 END PROCESS;
637
637
638
638
639 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
639 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
640 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
640 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
641 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
641 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
642 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
642 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
643 data_ms_addr;
643 data_ms_addr;
644
644
645 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
645 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
646 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
646 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
647 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
647 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
648 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
648 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
649 data_ms_data;
649 data_ms_data;
650
650
651 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
651 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
652 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
652 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
653 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
653 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
654 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
654 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
655 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
655 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
656
656
657 dma_data_2 <= dma_data;
657 dma_data_2 <= dma_data;
658
658
659
659
660
660
661
661
662
662
663 -----------------------------------------------------------------------------
663 -----------------------------------------------------------------------------
664 -- DEBUG -- DMA IN
664 -- DEBUG -- DMA IN
665 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
665 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
666 --debug_f0_data_dma_in <= dma_data;
666 --debug_f0_data_dma_in <= dma_data;
667 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
667 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
668 --debug_f1_data_dma_in <= dma_data;
668 --debug_f1_data_dma_in <= dma_data;
669 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
669 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
670 --debug_f2_data_dma_in <= dma_data;
670 --debug_f2_data_dma_in <= dma_data;
671 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
671 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
672 --debug_f3_data_dma_in <= dma_data;
672 --debug_f3_data_dma_in <= dma_data;
673 -----------------------------------------------------------------------------
673 -----------------------------------------------------------------------------
674
674
675 -----------------------------------------------------------------------------
675 -----------------------------------------------------------------------------
676 -- DMA
676 -- DMA
677 -----------------------------------------------------------------------------
677 -----------------------------------------------------------------------------
678 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
678 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
679 GENERIC MAP (
679 GENERIC MAP (
680 tech => inferred,
680 tech => inferred,
681 hindex => hindex)
681 hindex => hindex)
682 PORT MAP (
682 PORT MAP (
683 HCLK => clk,
683 HCLK => clk,
684 HRESETn => rstn,
684 HRESETn => rstn,
685 run => run,
685 run => run,
686 AHB_Master_In => ahbi,
686 AHB_Master_In => ahbi,
687 AHB_Master_Out => ahbo,
687 AHB_Master_Out => ahbo,
688
688
689 send => dma_send,
689 send => dma_send,
690 valid_burst => dma_valid_burst,
690 valid_burst => dma_valid_burst,
691 done => dma_done,
691 done => dma_done,
692 ren => dma_ren,
692 ren => dma_ren,
693 address => dma_address,
693 address => dma_address,
694 data => dma_data_2);
694 data => dma_data_2);
695
695
696 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
697 -- Matrix Spectral
697 -- Matrix Spectral
698 -----------------------------------------------------------------------------
698 -----------------------------------------------------------------------------
699 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
699 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
700 NOT(sample_f0_val) & NOT(sample_f0_val);
700 NOT(sample_f0_val) & NOT(sample_f0_val);
701 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
701 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
702 NOT(sample_f1_val) & NOT(sample_f1_val);
702 NOT(sample_f1_val) & NOT(sample_f1_val);
703 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
703 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
704 NOT(sample_f3_val) & NOT(sample_f3_val);
704 NOT(sample_f3_val) & NOT(sample_f3_val);
705
705
706 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
706 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
707 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
707 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
708 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
708 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
709
709
710 -------------------------------------------------------------------------------
710 -------------------------------------------------------------------------------
711
711
712 ms_softandhard_rstn <= rstn AND run_ms AND run;
712 ms_softandhard_rstn <= rstn AND run_ms AND run;
713
713
714 -----------------------------------------------------------------------------
714 -----------------------------------------------------------------------------
715 lpp_lfr_ms_1 : lpp_lfr_ms
715 lpp_lfr_ms_1 : lpp_lfr_ms
716 GENERIC MAP (
716 GENERIC MAP (
717 Mem_use => Mem_use)
717 Mem_use => Mem_use)
718 PORT MAP (
718 PORT MAP (
719 clk => clk,
719 clk => clk,
720 rstn => ms_softandhard_rstn, --rstn,
720 rstn => ms_softandhard_rstn, --rstn,
721
721
722 coarse_time => coarse_time,
722 coarse_time => coarse_time,
723 fine_time => fine_time,
723 fine_time => fine_time,
724
724
725 sample_f0_wen => sample_f0_wen,
725 sample_f0_wen => sample_f0_wen,
726 sample_f0_wdata => sample_f0_wdata,
726 sample_f0_wdata => sample_f0_wdata,
727 sample_f1_wen => sample_f1_wen,
727 sample_f1_wen => sample_f1_wen,
728 sample_f1_wdata => sample_f1_wdata,
728 sample_f1_wdata => sample_f1_wdata,
729 sample_f3_wen => sample_f3_wen,
729 sample_f3_wen => sample_f3_wen,
730 sample_f3_wdata => sample_f3_wdata,
730 sample_f3_wdata => sample_f3_wdata,
731
731
732 dma_addr => data_ms_addr, --
732 dma_addr => data_ms_addr, --
733 dma_data => data_ms_data, --
733 dma_data => data_ms_data, --
734 dma_valid => data_ms_valid, --
734 dma_valid => data_ms_valid, --
735 dma_valid_burst => data_ms_valid_burst, --
735 dma_valid_burst => data_ms_valid_burst, --
736 dma_ren => data_ms_ren, --
736 dma_ren => data_ms_ren, --
737 dma_done => data_ms_done, --
737 dma_done => data_ms_done, --
738
738
739 ready_matrix_f0_0 => ready_matrix_f0_0,
739 ready_matrix_f0_0 => ready_matrix_f0_0,
740 ready_matrix_f0_1 => ready_matrix_f0_1,
740 ready_matrix_f0_1 => ready_matrix_f0_1,
741 ready_matrix_f1 => ready_matrix_f1,
741 ready_matrix_f1 => ready_matrix_f1,
742 ready_matrix_f2 => ready_matrix_f2,
742 ready_matrix_f2 => ready_matrix_f2,
743 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
743 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
744 error_bad_component_error => error_bad_component_error,
744 error_bad_component_error => error_bad_component_error,
745 debug_reg => observation_reg, --debug_reg,
745 debug_reg => observation_reg, --debug_reg,
746 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
746 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
747 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
747 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
748 status_ready_matrix_f1 => status_ready_matrix_f1,
748 status_ready_matrix_f1 => status_ready_matrix_f1,
749 status_ready_matrix_f2 => status_ready_matrix_f2,
749 status_ready_matrix_f2 => status_ready_matrix_f2,
750 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
750 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
751 status_error_bad_component_error => status_error_bad_component_error,
751 status_error_bad_component_error => status_error_bad_component_error,
752 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
752 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
753 config_active_interruption_onError => config_active_interruption_onError,
753 config_active_interruption_onError => config_active_interruption_onError,
754 addr_matrix_f0_0 => addr_matrix_f0_0,
754 addr_matrix_f0_0 => addr_matrix_f0_0,
755 addr_matrix_f0_1 => addr_matrix_f0_1,
755 addr_matrix_f0_1 => addr_matrix_f0_1,
756 addr_matrix_f1 => addr_matrix_f1,
756 addr_matrix_f1 => addr_matrix_f1,
757 addr_matrix_f2 => addr_matrix_f2,
757 addr_matrix_f2 => addr_matrix_f2,
758
758
759 matrix_time_f0_0 => matrix_time_f0_0,
759 matrix_time_f0_0 => matrix_time_f0_0,
760 matrix_time_f0_1 => matrix_time_f0_1,
760 matrix_time_f0_1 => matrix_time_f0_1,
761 matrix_time_f1 => matrix_time_f1,
761 matrix_time_f1 => matrix_time_f1,
762 matrix_time_f2 => matrix_time_f2);
762 matrix_time_f2 => matrix_time_f2);
763
763
764 END beh;
764 END beh;
Show file before | Show file after | Hide comments
@@ -1,701 +1,702
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr_WFP_nMS IS
25 ENTITY lpp_lfr_WFP_nMS IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
75
76 ---- debug FIFO_IN
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
85
86 ----debug FIFO OUT
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
95
96 ----debug DMA IN
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
105 );
106 END lpp_lfr_WFP_nMS;
106 END lpp_lfr_WFP_nMS;
107
107
108 ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS
108 ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 -- SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
116 --
117 -- SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 -- SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 -- SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 -- SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 -- SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 -- SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
130 --
131 --SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 --SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 --SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 --SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 --SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 --SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
134
135 -- SM
135 -- SM
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -- WFP
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
181
182 SIGNAL run : STD_LOGIC;
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
208
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 --
210 --
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
227
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 -- DMA RR
229 -- DMA RR
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 -- DMA_REG
241 -- DMA_REG
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
249
250
250
251 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
252 -- DMA
252 -- DMA
253 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- DEBUG
263 -- DEBUG
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265 --
265 --
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270
270
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 -- MS
281 -- MS
282 -----------------------------------------------------------------------------
282 -----------------------------------------------------------------------------
283
283
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL data_ms_valid : STD_LOGIC;
286 SIGNAL data_ms_valid : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
290
290
291 SIGNAL run_ms : STD_LOGIC;
291 SIGNAL run_ms : STD_LOGIC;
292 --SIGNAL ms_softandhard_rstn : STD_LOGIC;
292 --SIGNAL ms_softandhard_rstn : STD_LOGIC;
293
293
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298
298
299
299
300 BEGIN
300 BEGIN
301
301
302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
302 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
303 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
304
304
305 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
305 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
306 -- --sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 END GENERATE all_channel;
307 -- sample_s(i) <= sample(i) & '0' & '0';
308 --END GENERATE all_channel;
308
309
309 -----------------------------------------------------------------------------
310 -----------------------------------------------------------------------------
310 lpp_lfr_filter_1 : lpp_lfr_filter
311 lpp_lfr_filter_1 : lpp_lfr_filter
311 GENERIC MAP (
312 GENERIC MAP (
312 Mem_use => Mem_use)
313 Mem_use => Mem_use)
313 PORT MAP (
314 PORT MAP (
314 sample => sample_s,
315 sample => sample_s,
315 sample_val => sample_val,
316 sample_val => sample_val,
316 clk => clk,
317 clk => clk,
317 rstn => rstn,
318 rstn => rstn,
318 data_shaping_SP0 => data_shaping_SP0,
319 data_shaping_SP0 => data_shaping_SP0,
319 data_shaping_SP1 => data_shaping_SP1,
320 data_shaping_SP1 => data_shaping_SP1,
320 data_shaping_R0 => data_shaping_R0,
321 data_shaping_R0 => data_shaping_R0,
321 data_shaping_R1 => data_shaping_R1,
322 data_shaping_R1 => data_shaping_R1,
322 sample_f0_val => sample_f0_val,
323 sample_f0_val => sample_f0_val,
323 sample_f1_val => sample_f1_val,
324 sample_f1_val => sample_f1_val,
324 sample_f2_val => sample_f2_val,
325 sample_f2_val => sample_f2_val,
325 sample_f3_val => sample_f3_val,
326 sample_f3_val => sample_f3_val,
326 sample_f0_wdata => sample_f0_data,
327 sample_f0_wdata => sample_f0_data,
327 sample_f1_wdata => sample_f1_data,
328 sample_f1_wdata => sample_f1_data,
328 sample_f2_wdata => sample_f2_data,
329 sample_f2_wdata => sample_f2_data,
329 sample_f3_wdata => sample_f3_data);
330 sample_f3_wdata => sample_f3_data);
330
331
331 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
332 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
333 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
333 GENERIC MAP (
334 GENERIC MAP (
334 nb_data_by_buffer_size => nb_data_by_buffer_size,
335 nb_data_by_buffer_size => nb_data_by_buffer_size,
335 nb_word_by_buffer_size => nb_word_by_buffer_size,
336 nb_word_by_buffer_size => nb_word_by_buffer_size,
336 nb_snapshot_param_size => nb_snapshot_param_size,
337 nb_snapshot_param_size => nb_snapshot_param_size,
337 delta_vector_size => delta_vector_size,
338 delta_vector_size => delta_vector_size,
338 delta_vector_size_f0_2 => delta_vector_size_f0_2,
339 delta_vector_size_f0_2 => delta_vector_size_f0_2,
339 pindex => pindex,
340 pindex => pindex,
340 paddr => paddr,
341 paddr => paddr,
341 pmask => pmask,
342 pmask => pmask,
342 pirq_ms => pirq_ms,
343 pirq_ms => pirq_ms,
343 pirq_wfp => pirq_wfp,
344 pirq_wfp => pirq_wfp,
344 top_lfr_version => top_lfr_version)
345 top_lfr_version => top_lfr_version)
345 PORT MAP (
346 PORT MAP (
346 HCLK => clk,
347 HCLK => clk,
347 HRESETn => rstn,
348 HRESETn => rstn,
348 apbi => apbi,
349 apbi => apbi,
349 apbo => apbo,
350 apbo => apbo,
350
351
351 run_ms => run_ms,
352 run_ms => run_ms,
352
353
353 ready_matrix_f0_0 => ready_matrix_f0_0,
354 ready_matrix_f0_0 => ready_matrix_f0_0,
354 ready_matrix_f0_1 => ready_matrix_f0_1,
355 ready_matrix_f0_1 => ready_matrix_f0_1,
355 ready_matrix_f1 => ready_matrix_f1,
356 ready_matrix_f1 => ready_matrix_f1,
356 ready_matrix_f2 => ready_matrix_f2,
357 ready_matrix_f2 => ready_matrix_f2,
357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 error_bad_component_error => error_bad_component_error,
359 error_bad_component_error => error_bad_component_error,
359 debug_reg => debug_reg,
360 debug_reg => debug_reg,
360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 status_ready_matrix_f1 => status_ready_matrix_f1,
363 status_ready_matrix_f1 => status_ready_matrix_f1,
363 status_ready_matrix_f2 => status_ready_matrix_f2,
364 status_ready_matrix_f2 => status_ready_matrix_f2,
364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 status_error_bad_component_error => status_error_bad_component_error,
366 status_error_bad_component_error => status_error_bad_component_error,
366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 config_active_interruption_onError => config_active_interruption_onError,
368 config_active_interruption_onError => config_active_interruption_onError,
368
369
369 matrix_time_f0_0 => matrix_time_f0_0,
370 matrix_time_f0_0 => matrix_time_f0_0,
370 matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
373 matrix_time_f2 => matrix_time_f2,
373
374
374 addr_matrix_f0_0 => addr_matrix_f0_0,
375 addr_matrix_f0_0 => addr_matrix_f0_0,
375 addr_matrix_f0_1 => addr_matrix_f0_1,
376 addr_matrix_f0_1 => addr_matrix_f0_1,
376 addr_matrix_f1 => addr_matrix_f1,
377 addr_matrix_f1 => addr_matrix_f1,
377 addr_matrix_f2 => addr_matrix_f2,
378 addr_matrix_f2 => addr_matrix_f2,
378 status_full => status_full,
379 status_full => status_full,
379 status_full_ack => status_full_ack,
380 status_full_ack => status_full_ack,
380 status_full_err => status_full_err,
381 status_full_err => status_full_err,
381 status_new_err => status_new_err,
382 status_new_err => status_new_err,
382 data_shaping_BW => data_shaping_BW,
383 data_shaping_BW => data_shaping_BW,
383 data_shaping_SP0 => data_shaping_SP0,
384 data_shaping_SP0 => data_shaping_SP0,
384 data_shaping_SP1 => data_shaping_SP1,
385 data_shaping_SP1 => data_shaping_SP1,
385 data_shaping_R0 => data_shaping_R0,
386 data_shaping_R0 => data_shaping_R0,
386 data_shaping_R1 => data_shaping_R1,
387 data_shaping_R1 => data_shaping_R1,
387 delta_snapshot => delta_snapshot,
388 delta_snapshot => delta_snapshot,
388 delta_f0 => delta_f0,
389 delta_f0 => delta_f0,
389 delta_f0_2 => delta_f0_2,
390 delta_f0_2 => delta_f0_2,
390 delta_f1 => delta_f1,
391 delta_f1 => delta_f1,
391 delta_f2 => delta_f2,
392 delta_f2 => delta_f2,
392 nb_data_by_buffer => nb_data_by_buffer,
393 nb_data_by_buffer => nb_data_by_buffer,
393 nb_word_by_buffer => nb_word_by_buffer,
394 nb_word_by_buffer => nb_word_by_buffer,
394 nb_snapshot_param => nb_snapshot_param,
395 nb_snapshot_param => nb_snapshot_param,
395 enable_f0 => enable_f0,
396 enable_f0 => enable_f0,
396 enable_f1 => enable_f1,
397 enable_f1 => enable_f1,
397 enable_f2 => enable_f2,
398 enable_f2 => enable_f2,
398 enable_f3 => enable_f3,
399 enable_f3 => enable_f3,
399 burst_f0 => burst_f0,
400 burst_f0 => burst_f0,
400 burst_f1 => burst_f1,
401 burst_f1 => burst_f1,
401 burst_f2 => burst_f2,
402 burst_f2 => burst_f2,
402 run => run,
403 run => run,
403 addr_data_f0 => addr_data_f0,
404 addr_data_f0 => addr_data_f0,
404 addr_data_f1 => addr_data_f1,
405 addr_data_f1 => addr_data_f1,
405 addr_data_f2 => addr_data_f2,
406 addr_data_f2 => addr_data_f2,
406 addr_data_f3 => addr_data_f3,
407 addr_data_f3 => addr_data_f3,
407 start_date => start_date,
408 start_date => start_date,
408 ---------------------------------------------------------------------------
409 ---------------------------------------------------------------------------
409 debug_reg0 => debug_reg0,
410 debug_reg0 => debug_reg0,
410 debug_reg1 => debug_reg1,
411 debug_reg1 => debug_reg1,
411 debug_reg2 => debug_reg2,
412 debug_reg2 => debug_reg2,
412 debug_reg3 => debug_reg3,
413 debug_reg3 => debug_reg3,
413 debug_reg4 => debug_reg4,
414 debug_reg4 => debug_reg4,
414 debug_reg5 => debug_reg5,
415 debug_reg5 => debug_reg5,
415 debug_reg6 => debug_reg6,
416 debug_reg6 => debug_reg6,
416 debug_reg7 => debug_reg7);
417 debug_reg7 => debug_reg7);
417
418
418 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
419 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
419 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
420 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
420 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
421 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
421 -----------------------------------------------------------------------------
422 -----------------------------------------------------------------------------
422 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
423 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
423 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
424 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
424 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
425 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
425 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
426 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
426
427
427
428
428 -----------------------------------------------------------------------------
429 -----------------------------------------------------------------------------
429 lpp_waveform_1 : lpp_waveform
430 lpp_waveform_1 : lpp_waveform
430 GENERIC MAP (
431 GENERIC MAP (
431 tech => inferred,
432 tech => inferred,
432 data_size => 6*16,
433 data_size => 6*16,
433 nb_data_by_buffer_size => nb_data_by_buffer_size,
434 nb_data_by_buffer_size => nb_data_by_buffer_size,
434 nb_word_by_buffer_size => nb_word_by_buffer_size,
435 nb_word_by_buffer_size => nb_word_by_buffer_size,
435 nb_snapshot_param_size => nb_snapshot_param_size,
436 nb_snapshot_param_size => nb_snapshot_param_size,
436 delta_vector_size => delta_vector_size,
437 delta_vector_size => delta_vector_size,
437 delta_vector_size_f0_2 => delta_vector_size_f0_2
438 delta_vector_size_f0_2 => delta_vector_size_f0_2
438 )
439 )
439 PORT MAP (
440 PORT MAP (
440 clk => clk,
441 clk => clk,
441 rstn => rstn,
442 rstn => rstn,
442
443
443 reg_run => run,
444 reg_run => run,
444 reg_start_date => start_date,
445 reg_start_date => start_date,
445 reg_delta_snapshot => delta_snapshot,
446 reg_delta_snapshot => delta_snapshot,
446 reg_delta_f0 => delta_f0,
447 reg_delta_f0 => delta_f0,
447 reg_delta_f0_2 => delta_f0_2,
448 reg_delta_f0_2 => delta_f0_2,
448 reg_delta_f1 => delta_f1,
449 reg_delta_f1 => delta_f1,
449 reg_delta_f2 => delta_f2,
450 reg_delta_f2 => delta_f2,
450
451
451 enable_f0 => enable_f0,
452 enable_f0 => enable_f0,
452 enable_f1 => enable_f1,
453 enable_f1 => enable_f1,
453 enable_f2 => enable_f2,
454 enable_f2 => enable_f2,
454 enable_f3 => enable_f3,
455 enable_f3 => enable_f3,
455 burst_f0 => burst_f0,
456 burst_f0 => burst_f0,
456 burst_f1 => burst_f1,
457 burst_f1 => burst_f1,
457 burst_f2 => burst_f2,
458 burst_f2 => burst_f2,
458
459
459 nb_data_by_buffer => nb_data_by_buffer,
460 nb_data_by_buffer => nb_data_by_buffer,
460 nb_word_by_buffer => nb_word_by_buffer,
461 nb_word_by_buffer => nb_word_by_buffer,
461 nb_snapshot_param => nb_snapshot_param,
462 nb_snapshot_param => nb_snapshot_param,
462 status_full => status_full,
463 status_full => status_full,
463 status_full_ack => status_full_ack,
464 status_full_ack => status_full_ack,
464 status_full_err => status_full_err,
465 status_full_err => status_full_err,
465 status_new_err => status_new_err,
466 status_new_err => status_new_err,
466
467
467 coarse_time => coarse_time,
468 coarse_time => coarse_time,
468 fine_time => fine_time,
469 fine_time => fine_time,
469
470
470 --f0
471 --f0
471 addr_data_f0 => addr_data_f0,
472 addr_data_f0 => addr_data_f0,
472 data_f0_in_valid => sample_f0_val,
473 data_f0_in_valid => sample_f0_val,
473 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
474 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
474 --f1
475 --f1
475 addr_data_f1 => addr_data_f1,
476 addr_data_f1 => addr_data_f1,
476 data_f1_in_valid => sample_f1_val,
477 data_f1_in_valid => sample_f1_val,
477 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
478 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
478 --f2
479 --f2
479 addr_data_f2 => addr_data_f2,
480 addr_data_f2 => addr_data_f2,
480 data_f2_in_valid => sample_f2_val,
481 data_f2_in_valid => sample_f2_val,
481 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
482 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
482 --f3
483 --f3
483 addr_data_f3 => addr_data_f3,
484 addr_data_f3 => addr_data_f3,
484 data_f3_in_valid => sample_f3_val,
485 data_f3_in_valid => sample_f3_val,
485 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
486 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
486 -- OUTPUT -- DMA interface
487 -- OUTPUT -- DMA interface
487 --f0
488 --f0
488 data_f0_addr_out => data_f0_addr_out_s,
489 data_f0_addr_out => data_f0_addr_out_s,
489 data_f0_data_out => data_f0_data_out,
490 data_f0_data_out => data_f0_data_out,
490 data_f0_data_out_valid => data_f0_data_out_valid_s,
491 data_f0_data_out_valid => data_f0_data_out_valid_s,
491 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
492 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
492 data_f0_data_out_ren => data_f0_data_out_ren,
493 data_f0_data_out_ren => data_f0_data_out_ren,
493 --f1
494 --f1
494 data_f1_addr_out => data_f1_addr_out_s,
495 data_f1_addr_out => data_f1_addr_out_s,
495 data_f1_data_out => data_f1_data_out,
496 data_f1_data_out => data_f1_data_out,
496 data_f1_data_out_valid => data_f1_data_out_valid_s,
497 data_f1_data_out_valid => data_f1_data_out_valid_s,
497 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
498 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
498 data_f1_data_out_ren => data_f1_data_out_ren,
499 data_f1_data_out_ren => data_f1_data_out_ren,
499 --f2
500 --f2
500 data_f2_addr_out => data_f2_addr_out_s,
501 data_f2_addr_out => data_f2_addr_out_s,
501 data_f2_data_out => data_f2_data_out,
502 data_f2_data_out => data_f2_data_out,
502 data_f2_data_out_valid => data_f2_data_out_valid_s,
503 data_f2_data_out_valid => data_f2_data_out_valid_s,
503 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
504 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
504 data_f2_data_out_ren => data_f2_data_out_ren,
505 data_f2_data_out_ren => data_f2_data_out_ren,
505 --f3
506 --f3
506 data_f3_addr_out => data_f3_addr_out_s,
507 data_f3_addr_out => data_f3_addr_out_s,
507 data_f3_data_out => data_f3_data_out,
508 data_f3_data_out => data_f3_data_out,
508 data_f3_data_out_valid => data_f3_data_out_valid_s,
509 data_f3_data_out_valid => data_f3_data_out_valid_s,
509 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
510 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
510 data_f3_data_out_ren => data_f3_data_out_ren ,
511 data_f3_data_out_ren => data_f3_data_out_ren ,
511
512
512 -------------------------------------------------------------------------
513 -------------------------------------------------------------------------
513 observation_reg => OPEN
514 observation_reg => OPEN
514
515
515 );
516 );
516
517
517
518
518 -----------------------------------------------------------------------------
519 -----------------------------------------------------------------------------
519 -- TEMP
520 -- TEMP
520 -----------------------------------------------------------------------------
521 -----------------------------------------------------------------------------
521
522
522 PROCESS (clk, rstn)
523 PROCESS (clk, rstn)
523 BEGIN -- PROCESS
524 BEGIN -- PROCESS
524 IF rstn = '0' THEN -- asynchronous reset (active low)
525 IF rstn = '0' THEN -- asynchronous reset (active low)
525 data_f0_data_out_valid <= '0';
526 data_f0_data_out_valid <= '0';
526 data_f0_data_out_valid_burst <= '0';
527 data_f0_data_out_valid_burst <= '0';
527 data_f1_data_out_valid <= '0';
528 data_f1_data_out_valid <= '0';
528 data_f1_data_out_valid_burst <= '0';
529 data_f1_data_out_valid_burst <= '0';
529 data_f2_data_out_valid <= '0';
530 data_f2_data_out_valid <= '0';
530 data_f2_data_out_valid_burst <= '0';
531 data_f2_data_out_valid_burst <= '0';
531 data_f3_data_out_valid <= '0';
532 data_f3_data_out_valid <= '0';
532 data_f3_data_out_valid_burst <= '0';
533 data_f3_data_out_valid_burst <= '0';
533 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
534 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
534 data_f0_data_out_valid <= data_f0_data_out_valid_s;
535 data_f0_data_out_valid <= data_f0_data_out_valid_s;
535 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
536 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
536 data_f1_data_out_valid <= data_f1_data_out_valid_s;
537 data_f1_data_out_valid <= data_f1_data_out_valid_s;
537 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
538 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
538 data_f2_data_out_valid <= data_f2_data_out_valid_s;
539 data_f2_data_out_valid <= data_f2_data_out_valid_s;
539 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
540 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
540 data_f3_data_out_valid <= data_f3_data_out_valid_s;
541 data_f3_data_out_valid <= data_f3_data_out_valid_s;
541 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
542 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
542 END IF;
543 END IF;
543 END PROCESS;
544 END PROCESS;
544
545
545 data_f0_addr_out <= data_f0_addr_out_s;
546 data_f0_addr_out <= data_f0_addr_out_s;
546 data_f1_addr_out <= data_f1_addr_out_s;
547 data_f1_addr_out <= data_f1_addr_out_s;
547 data_f2_addr_out <= data_f2_addr_out_s;
548 data_f2_addr_out <= data_f2_addr_out_s;
548 data_f3_addr_out <= data_f3_addr_out_s;
549 data_f3_addr_out <= data_f3_addr_out_s;
549
550
550 -----------------------------------------------------------------------------
551 -----------------------------------------------------------------------------
551 -- RoundRobin Selection For DMA
552 -- RoundRobin Selection For DMA
552 -----------------------------------------------------------------------------
553 -----------------------------------------------------------------------------
553
554
554 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
555 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
555 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
556 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
556 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
557 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
557 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
558 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
558
559
559 RR_Arbiter_4_1 : RR_Arbiter_4
560 RR_Arbiter_4_1 : RR_Arbiter_4
560 PORT MAP (
561 PORT MAP (
561 clk => clk,
562 clk => clk,
562 rstn => rstn,
563 rstn => rstn,
563 in_valid => dma_rr_valid,
564 in_valid => dma_rr_valid,
564 out_grant => dma_rr_grant_s);
565 out_grant => dma_rr_grant_s);
565
566
566 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
567 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
567 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
568 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
568 dma_rr_valid_ms(2) <= '0';
569 dma_rr_valid_ms(2) <= '0';
569 dma_rr_valid_ms(3) <= '0';
570 dma_rr_valid_ms(3) <= '0';
570
571
571 RR_Arbiter_4_2 : RR_Arbiter_4
572 RR_Arbiter_4_2 : RR_Arbiter_4
572 PORT MAP (
573 PORT MAP (
573 clk => clk,
574 clk => clk,
574 rstn => rstn,
575 rstn => rstn,
575 in_valid => dma_rr_valid_ms,
576 in_valid => dma_rr_valid_ms,
576 out_grant => dma_rr_grant_ms);
577 out_grant => dma_rr_grant_ms);
577
578
578 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
579 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
579
580
580
581
581 -----------------------------------------------------------------------------
582 -----------------------------------------------------------------------------
582 -- in : dma_rr_grant
583 -- in : dma_rr_grant
583 -- send
584 -- send
584 -- out : dma_sel
585 -- out : dma_sel
585 -- dma_valid_burst
586 -- dma_valid_burst
586 -- dma_sel_valid
587 -- dma_sel_valid
587 -----------------------------------------------------------------------------
588 -----------------------------------------------------------------------------
588 PROCESS (clk, rstn)
589 PROCESS (clk, rstn)
589 BEGIN -- PROCESS
590 BEGIN -- PROCESS
590 IF rstn = '0' THEN -- asynchronous reset (active low)
591 IF rstn = '0' THEN -- asynchronous reset (active low)
591 dma_sel <= (OTHERS => '0');
592 dma_sel <= (OTHERS => '0');
592 dma_send <= '0';
593 dma_send <= '0';
593 dma_valid_burst <= '0';
594 dma_valid_burst <= '0';
594 data_ms_done <= '0';
595 data_ms_done <= '0';
595 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
596 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
596 IF run = '1' THEN
597 IF run = '1' THEN
597 data_ms_done <= '0';
598 data_ms_done <= '0';
598 IF dma_sel = "00000" OR dma_done = '1' THEN
599 IF dma_sel = "00000" OR dma_done = '1' THEN
599 dma_sel <= dma_rr_grant;
600 dma_sel <= dma_rr_grant;
600 IF dma_rr_grant(0) = '1' THEN
601 IF dma_rr_grant(0) = '1' THEN
601 dma_send <= '1';
602 dma_send <= '1';
602 dma_valid_burst <= data_f0_data_out_valid_burst;
603 dma_valid_burst <= data_f0_data_out_valid_burst;
603 dma_sel_valid <= data_f0_data_out_valid;
604 dma_sel_valid <= data_f0_data_out_valid;
604 ELSIF dma_rr_grant(1) = '1' THEN
605 ELSIF dma_rr_grant(1) = '1' THEN
605 dma_send <= '1';
606 dma_send <= '1';
606 dma_valid_burst <= data_f1_data_out_valid_burst;
607 dma_valid_burst <= data_f1_data_out_valid_burst;
607 dma_sel_valid <= data_f1_data_out_valid;
608 dma_sel_valid <= data_f1_data_out_valid;
608 ELSIF dma_rr_grant(2) = '1' THEN
609 ELSIF dma_rr_grant(2) = '1' THEN
609 dma_send <= '1';
610 dma_send <= '1';
610 dma_valid_burst <= data_f2_data_out_valid_burst;
611 dma_valid_burst <= data_f2_data_out_valid_burst;
611 dma_sel_valid <= data_f2_data_out_valid;
612 dma_sel_valid <= data_f2_data_out_valid;
612 ELSIF dma_rr_grant(3) = '1' THEN
613 ELSIF dma_rr_grant(3) = '1' THEN
613 dma_send <= '1';
614 dma_send <= '1';
614 dma_valid_burst <= data_f3_data_out_valid_burst;
615 dma_valid_burst <= data_f3_data_out_valid_burst;
615 dma_sel_valid <= data_f3_data_out_valid;
616 dma_sel_valid <= data_f3_data_out_valid;
616 ELSIF dma_rr_grant(4) = '1' THEN
617 ELSIF dma_rr_grant(4) = '1' THEN
617 dma_send <= '1';
618 dma_send <= '1';
618 dma_valid_burst <= data_ms_valid_burst;
619 dma_valid_burst <= data_ms_valid_burst;
619 dma_sel_valid <= data_ms_valid;
620 dma_sel_valid <= data_ms_valid;
620 END IF;
621 END IF;
621
622
622 IF dma_sel(4) = '1' THEN
623 IF dma_sel(4) = '1' THEN
623 data_ms_done <= '1';
624 data_ms_done <= '1';
624 END IF;
625 END IF;
625 ELSE
626 ELSE
626 dma_sel <= dma_sel;
627 dma_sel <= dma_sel;
627 dma_send <= '0';
628 dma_send <= '0';
628 END IF;
629 END IF;
629 ELSE
630 ELSE
630 data_ms_done <= '0';
631 data_ms_done <= '0';
631 dma_sel <= (OTHERS => '0');
632 dma_sel <= (OTHERS => '0');
632 dma_send <= '0';
633 dma_send <= '0';
633 dma_valid_burst <= '0';
634 dma_valid_burst <= '0';
634 END IF;
635 END IF;
635 END IF;
636 END IF;
636 END PROCESS;
637 END PROCESS;
637
638
638
639
639 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
640 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
640 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
641 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
641 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
642 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
642 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
643 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
643 data_ms_addr;
644 data_ms_addr;
644
645
645 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
646 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
646 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
647 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
647 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
648 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
648 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
649 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
649 data_ms_data;
650 data_ms_data;
650
651
651 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
652 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
652 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
653 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
653 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
654 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
654 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
655 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
655 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
656 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
656
657
657 dma_data_2 <= dma_data;
658 dma_data_2 <= dma_data;
658
659
659 -----------------------------------------------------------------------------
660 -----------------------------------------------------------------------------
660 -- DMA
661 -- DMA
661 -----------------------------------------------------------------------------
662 -----------------------------------------------------------------------------
662 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
663 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
663 GENERIC MAP (
664 GENERIC MAP (
664 tech => inferred,
665 tech => inferred,
665 hindex => hindex)
666 hindex => hindex)
666 PORT MAP (
667 PORT MAP (
667 HCLK => clk,
668 HCLK => clk,
668 HRESETn => rstn,
669 HRESETn => rstn,
669 run => run,
670 run => run,
670 AHB_Master_In => ahbi,
671 AHB_Master_In => ahbi,
671 AHB_Master_Out => ahbo,
672 AHB_Master_Out => ahbo,
672
673
673 send => dma_send,
674 send => dma_send,
674 valid_burst => dma_valid_burst,
675 valid_burst => dma_valid_burst,
675 done => dma_done,
676 done => dma_done,
676 ren => dma_ren,
677 ren => dma_ren,
677 address => dma_address,
678 address => dma_address,
678 data => dma_data_2);
679 data => dma_data_2);
679
680
680 -----------------------------------------------------------------------------
681 -----------------------------------------------------------------------------
681 -- Matrix Spectral
682 -- Matrix Spectral
682 -----------------------------------------------------------------------------
683 -----------------------------------------------------------------------------
683 data_ms_addr <= (OTHERS => '0');
684 data_ms_addr <= (OTHERS => '0');
684 data_ms_data <= (OTHERS => '0');
685 data_ms_data <= (OTHERS => '0');
685 data_ms_valid <= '0';
686 data_ms_valid <= '0';
686 data_ms_valid_burst <= '0';
687 data_ms_valid_burst <= '0';
687
688
688 ready_matrix_f0_0 <= '0';
689 ready_matrix_f0_0 <= '0';
689 ready_matrix_f0_1 <= '0';
690 ready_matrix_f0_1 <= '0';
690 ready_matrix_f1 <= '0';
691 ready_matrix_f1 <= '0';
691 ready_matrix_f2 <= '0';
692 ready_matrix_f2 <= '0';
692 error_anticipating_empty_fifo <= '0';
693 error_anticipating_empty_fifo <= '0';
693 error_bad_component_error <= '0';
694 error_bad_component_error <= '0';
694 observation_reg <= (OTHERS => '0');
695 observation_reg <= (OTHERS => '0');
695
696
696 matrix_time_f2 <= (OTHERS => '0');
697 matrix_time_f2 <= (OTHERS => '0');
697 matrix_time_f1 <= (OTHERS => '0');
698 matrix_time_f1 <= (OTHERS => '0');
698 matrix_time_f0_1 <= (OTHERS => '0');
699 matrix_time_f0_1 <= (OTHERS => '0');
699 matrix_time_f0_0 <= (OTHERS => '0');
700 matrix_time_f0_0 <= (OTHERS => '0');
700
701
701 END beh;
702 END beh;
Show file before | Show file after | Hide comments
@@ -1,323 +1,323
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER
19 Mem_use : INTEGER
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27
27
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34
34
35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 dma_valid : OUT STD_LOGIC;
37 dma_valid : OUT STD_LOGIC;
38 dma_valid_burst : OUT STD_LOGIC;
38 dma_valid_burst : OUT STD_LOGIC;
39 dma_ren : IN STD_LOGIC;
39 dma_ren : IN STD_LOGIC;
40 dma_done : IN STD_LOGIC;
40 dma_done : IN STD_LOGIC;
41
41
42 ready_matrix_f0_0 : OUT STD_LOGIC;
42 ready_matrix_f0_0 : OUT STD_LOGIC;
43 ready_matrix_f0_1 : OUT STD_LOGIC;
43 ready_matrix_f0_1 : OUT STD_LOGIC;
44 ready_matrix_f1 : OUT STD_LOGIC;
44 ready_matrix_f1 : OUT STD_LOGIC;
45 ready_matrix_f2 : OUT STD_LOGIC;
45 ready_matrix_f2 : OUT STD_LOGIC;
46 error_anticipating_empty_fifo : OUT STD_LOGIC;
46 error_anticipating_empty_fifo : OUT STD_LOGIC;
47 error_bad_component_error : OUT STD_LOGIC;
47 error_bad_component_error : OUT STD_LOGIC;
48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 status_ready_matrix_f0_0 : IN STD_LOGIC;
49 status_ready_matrix_f0_0 : IN STD_LOGIC;
50 status_ready_matrix_f0_1 : IN STD_LOGIC;
50 status_ready_matrix_f0_1 : IN STD_LOGIC;
51 status_ready_matrix_f1 : IN STD_LOGIC;
51 status_ready_matrix_f1 : IN STD_LOGIC;
52 status_ready_matrix_f2 : IN STD_LOGIC;
52 status_ready_matrix_f2 : IN STD_LOGIC;
53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
54 status_error_bad_component_error : IN STD_LOGIC;
54 status_error_bad_component_error : IN STD_LOGIC;
55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
56 config_active_interruption_onError : IN STD_LOGIC;
56 config_active_interruption_onError : IN STD_LOGIC;
57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61
61
62 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
62 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
63 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
63 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
64 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
64 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
65 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
65 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
66 END COMPONENT;
66 END COMPONENT;
67
67
68 COMPONENT lpp_lfr_ms_fsmdma
68 COMPONENT lpp_lfr_ms_fsmdma
69 PORT (
69 PORT (
70 HCLK : IN STD_ULOGIC;
70 HCLK : IN STD_ULOGIC;
71 HRESETn : IN STD_ULOGIC;
71 HRESETn : IN STD_ULOGIC;
72 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
72 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
73 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 fifo_empty : IN STD_LOGIC;
74 fifo_empty : IN STD_LOGIC;
75 fifo_ren : OUT STD_LOGIC;
75 fifo_ren : OUT STD_LOGIC;
76 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 header_val : IN STD_LOGIC;
77 header_val : IN STD_LOGIC;
78 header_ack : OUT STD_LOGIC;
78 header_ack : OUT STD_LOGIC;
79 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 dma_valid : OUT STD_LOGIC;
81 dma_valid : OUT STD_LOGIC;
82 dma_valid_burst : OUT STD_LOGIC;
82 dma_valid_burst : OUT STD_LOGIC;
83 dma_ren : IN STD_LOGIC;
83 dma_ren : IN STD_LOGIC;
84 dma_done : IN STD_LOGIC;
84 dma_done : IN STD_LOGIC;
85 ready_matrix_f0_0 : OUT STD_LOGIC;
85 ready_matrix_f0_0 : OUT STD_LOGIC;
86 ready_matrix_f0_1 : OUT STD_LOGIC;
86 ready_matrix_f0_1 : OUT STD_LOGIC;
87 ready_matrix_f1 : OUT STD_LOGIC;
87 ready_matrix_f1 : OUT STD_LOGIC;
88 ready_matrix_f2 : OUT STD_LOGIC;
88 ready_matrix_f2 : OUT STD_LOGIC;
89 error_anticipating_empty_fifo : OUT STD_LOGIC;
89 error_anticipating_empty_fifo : OUT STD_LOGIC;
90 error_bad_component_error : OUT STD_LOGIC;
90 error_bad_component_error : OUT STD_LOGIC;
91 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 status_ready_matrix_f0_0 : IN STD_LOGIC;
92 status_ready_matrix_f0_0 : IN STD_LOGIC;
93 status_ready_matrix_f0_1 : IN STD_LOGIC;
93 status_ready_matrix_f0_1 : IN STD_LOGIC;
94 status_ready_matrix_f1 : IN STD_LOGIC;
94 status_ready_matrix_f1 : IN STD_LOGIC;
95 status_ready_matrix_f2 : IN STD_LOGIC;
95 status_ready_matrix_f2 : IN STD_LOGIC;
96 status_error_anticipating_empty_fifo : IN STD_LOGIC;
96 status_error_anticipating_empty_fifo : IN STD_LOGIC;
97 status_error_bad_component_error : IN STD_LOGIC;
97 status_error_bad_component_error : IN STD_LOGIC;
98 config_active_interruption_onNewMatrix : IN STD_LOGIC;
98 config_active_interruption_onNewMatrix : IN STD_LOGIC;
99 config_active_interruption_onError : IN STD_LOGIC;
99 config_active_interruption_onError : IN STD_LOGIC;
100 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104
104
105 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
105 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
106 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
106 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
108 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
109 );
109 );
110 END COMPONENT;
110 END COMPONENT;
111
111
112
112
113 COMPONENT lpp_lfr_filter
113 COMPONENT lpp_lfr_filter
114 GENERIC (
114 GENERIC (
115 Mem_use : INTEGER);
115 Mem_use : INTEGER);
116 PORT (
116 PORT (
117 sample : IN Samples(7 DOWNTO 0);
117 sample : IN Samples(7 DOWNTO 0);
118 sample_val : IN STD_LOGIC;
118 sample_val : IN STD_LOGIC;
119 clk : IN STD_LOGIC;
119 clk : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
121 data_shaping_SP0 : IN STD_LOGIC;
121 data_shaping_SP0 : IN STD_LOGIC;
122 data_shaping_SP1 : IN STD_LOGIC;
122 data_shaping_SP1 : IN STD_LOGIC;
123 data_shaping_R0 : IN STD_LOGIC;
123 data_shaping_R0 : IN STD_LOGIC;
124 data_shaping_R1 : IN STD_LOGIC;
124 data_shaping_R1 : IN STD_LOGIC;
125 sample_f0_val : OUT STD_LOGIC;
125 sample_f0_val : OUT STD_LOGIC;
126 sample_f1_val : OUT STD_LOGIC;
126 sample_f1_val : OUT STD_LOGIC;
127 sample_f2_val : OUT STD_LOGIC;
127 sample_f2_val : OUT STD_LOGIC;
128 sample_f3_val : OUT STD_LOGIC;
128 sample_f3_val : OUT STD_LOGIC;
129 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
132 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
133 END COMPONENT;
133 END COMPONENT;
134
134
135 COMPONENT lpp_lfr
135 COMPONENT lpp_lfr
136 GENERIC (
136 GENERIC (
137 Mem_use : INTEGER;
137 Mem_use : INTEGER;
138 nb_data_by_buffer_size : INTEGER;
138 nb_data_by_buffer_size : INTEGER;
139 nb_word_by_buffer_size : INTEGER;
139 nb_word_by_buffer_size : INTEGER;
140 nb_snapshot_param_size : INTEGER;
140 nb_snapshot_param_size : INTEGER;
141 delta_vector_size : INTEGER;
141 delta_vector_size : INTEGER;
142 delta_vector_size_f0_2 : INTEGER;
142 delta_vector_size_f0_2 : INTEGER;
143 pindex : INTEGER;
143 pindex : INTEGER;
144 paddr : INTEGER;
144 paddr : INTEGER;
145 pmask : INTEGER;
145 pmask : INTEGER;
146 pirq_ms : INTEGER;
146 pirq_ms : INTEGER;
147 pirq_wfp : INTEGER;
147 pirq_wfp : INTEGER;
148 hindex : INTEGER;
148 hindex : INTEGER;
149 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
149 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
150 );
150 );
151 PORT (
151 PORT (
152 clk : IN STD_LOGIC;
152 clk : IN STD_LOGIC;
153 rstn : IN STD_LOGIC;
153 rstn : IN STD_LOGIC;
154 sample_B : IN Samples14v(2 DOWNTO 0);
154 sample_B : IN Samples(2 DOWNTO 0);
155 sample_E : IN Samples14v(4 DOWNTO 0);
155 sample_E : IN Samples(4 DOWNTO 0);
156 sample_val : IN STD_LOGIC;
156 sample_val : IN STD_LOGIC;
157 apbi : IN apb_slv_in_type;
157 apbi : IN apb_slv_in_type;
158 apbo : OUT apb_slv_out_type;
158 apbo : OUT apb_slv_out_type;
159 ahbi : IN AHB_Mst_In_Type;
159 ahbi : IN AHB_Mst_In_Type;
160 ahbo : OUT AHB_Mst_Out_Type;
160 ahbo : OUT AHB_Mst_Out_Type;
161 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
161 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
162 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
162 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
163 data_shaping_BW : OUT STD_LOGIC;
163 data_shaping_BW : OUT STD_LOGIC;
164 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
164 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
165 );
165 );
166 END COMPONENT;
166 END COMPONENT;
167
167
168 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
169 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
169 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
170 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
171 COMPONENT lpp_lfr_WFP_nMS
171 COMPONENT lpp_lfr_WFP_nMS
172 GENERIC (
172 GENERIC (
173 Mem_use : INTEGER;
173 Mem_use : INTEGER;
174 nb_data_by_buffer_size : INTEGER;
174 nb_data_by_buffer_size : INTEGER;
175 nb_word_by_buffer_size : INTEGER;
175 nb_word_by_buffer_size : INTEGER;
176 nb_snapshot_param_size : INTEGER;
176 nb_snapshot_param_size : INTEGER;
177 delta_vector_size : INTEGER;
177 delta_vector_size : INTEGER;
178 delta_vector_size_f0_2 : INTEGER;
178 delta_vector_size_f0_2 : INTEGER;
179 pindex : INTEGER;
179 pindex : INTEGER;
180 paddr : INTEGER;
180 paddr : INTEGER;
181 pmask : INTEGER;
181 pmask : INTEGER;
182 pirq_ms : INTEGER;
182 pirq_ms : INTEGER;
183 pirq_wfp : INTEGER;
183 pirq_wfp : INTEGER;
184 hindex : INTEGER;
184 hindex : INTEGER;
185 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
185 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
186 PORT (
186 PORT (
187 clk : IN STD_LOGIC;
187 clk : IN STD_LOGIC;
188 rstn : IN STD_LOGIC;
188 rstn : IN STD_LOGIC;
189 sample_B : IN Samples14v(2 DOWNTO 0);
189 sample_B : IN Samples(2 DOWNTO 0);
190 sample_E : IN Samples14v(4 DOWNTO 0);
190 sample_E : IN Samples(4 DOWNTO 0);
191 sample_val : IN STD_LOGIC;
191 sample_val : IN STD_LOGIC;
192 apbi : IN apb_slv_in_type;
192 apbi : IN apb_slv_in_type;
193 apbo : OUT apb_slv_out_type;
193 apbo : OUT apb_slv_out_type;
194 ahbi : IN AHB_Mst_In_Type;
194 ahbi : IN AHB_Mst_In_Type;
195 ahbo : OUT AHB_Mst_Out_Type;
195 ahbo : OUT AHB_Mst_Out_Type;
196 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
197 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
198 data_shaping_BW : OUT STD_LOGIC;
198 data_shaping_BW : OUT STD_LOGIC;
199 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
199 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
200 END COMPONENT;
200 END COMPONENT;
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202
202
203
203
204 COMPONENT lpp_lfr_apbreg
204 COMPONENT lpp_lfr_apbreg
205 GENERIC (
205 GENERIC (
206 nb_data_by_buffer_size : INTEGER;
206 nb_data_by_buffer_size : INTEGER;
207 nb_word_by_buffer_size : INTEGER;
207 nb_word_by_buffer_size : INTEGER;
208 nb_snapshot_param_size : INTEGER;
208 nb_snapshot_param_size : INTEGER;
209 delta_vector_size : INTEGER;
209 delta_vector_size : INTEGER;
210 delta_vector_size_f0_2 : INTEGER;
210 delta_vector_size_f0_2 : INTEGER;
211 pindex : INTEGER;
211 pindex : INTEGER;
212 paddr : INTEGER;
212 paddr : INTEGER;
213 pmask : INTEGER;
213 pmask : INTEGER;
214 pirq_ms : INTEGER;
214 pirq_ms : INTEGER;
215 pirq_wfp : INTEGER;
215 pirq_wfp : INTEGER;
216 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
216 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
217 PORT (
217 PORT (
218 HCLK : IN STD_ULOGIC;
218 HCLK : IN STD_ULOGIC;
219 HRESETn : IN STD_ULOGIC;
219 HRESETn : IN STD_ULOGIC;
220 apbi : IN apb_slv_in_type;
220 apbi : IN apb_slv_in_type;
221 apbo : OUT apb_slv_out_type;
221 apbo : OUT apb_slv_out_type;
222 run_ms : OUT STD_LOGIC;
222 run_ms : OUT STD_LOGIC;
223 ready_matrix_f0_0 : IN STD_LOGIC;
223 ready_matrix_f0_0 : IN STD_LOGIC;
224 ready_matrix_f0_1 : IN STD_LOGIC;
224 ready_matrix_f0_1 : IN STD_LOGIC;
225 ready_matrix_f1 : IN STD_LOGIC;
225 ready_matrix_f1 : IN STD_LOGIC;
226 ready_matrix_f2 : IN STD_LOGIC;
226 ready_matrix_f2 : IN STD_LOGIC;
227 error_anticipating_empty_fifo : IN STD_LOGIC;
227 error_anticipating_empty_fifo : IN STD_LOGIC;
228 error_bad_component_error : IN STD_LOGIC;
228 error_bad_component_error : IN STD_LOGIC;
229 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
229 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
230 status_ready_matrix_f0_0 : OUT STD_LOGIC;
230 status_ready_matrix_f0_0 : OUT STD_LOGIC;
231 status_ready_matrix_f0_1 : OUT STD_LOGIC;
231 status_ready_matrix_f0_1 : OUT STD_LOGIC;
232 status_ready_matrix_f1 : OUT STD_LOGIC;
232 status_ready_matrix_f1 : OUT STD_LOGIC;
233 status_ready_matrix_f2 : OUT STD_LOGIC;
233 status_ready_matrix_f2 : OUT STD_LOGIC;
234 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
234 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
235 status_error_bad_component_error : OUT STD_LOGIC;
235 status_error_bad_component_error : OUT STD_LOGIC;
236 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
236 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
237 config_active_interruption_onError : OUT STD_LOGIC;
237 config_active_interruption_onError : OUT STD_LOGIC;
238 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
238 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
240 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
240 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
241 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
241 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
242
242
243 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
243 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
244 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
244 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
245 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
245 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
246 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
246 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
247
247
248 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
248 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
249 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
250 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
252 data_shaping_BW : OUT STD_LOGIC;
252 data_shaping_BW : OUT STD_LOGIC;
253 data_shaping_SP0 : OUT STD_LOGIC;
253 data_shaping_SP0 : OUT STD_LOGIC;
254 data_shaping_SP1 : OUT STD_LOGIC;
254 data_shaping_SP1 : OUT STD_LOGIC;
255 data_shaping_R0 : OUT STD_LOGIC;
255 data_shaping_R0 : OUT STD_LOGIC;
256 data_shaping_R1 : OUT STD_LOGIC;
256 data_shaping_R1 : OUT STD_LOGIC;
257 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
257 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
258 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
258 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
259 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
259 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
260 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
260 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
261 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
261 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
262 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
262 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
263 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
263 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
264 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
264 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
265 enable_f0 : OUT STD_LOGIC;
265 enable_f0 : OUT STD_LOGIC;
266 enable_f1 : OUT STD_LOGIC;
266 enable_f1 : OUT STD_LOGIC;
267 enable_f2 : OUT STD_LOGIC;
267 enable_f2 : OUT STD_LOGIC;
268 enable_f3 : OUT STD_LOGIC;
268 enable_f3 : OUT STD_LOGIC;
269 burst_f0 : OUT STD_LOGIC;
269 burst_f0 : OUT STD_LOGIC;
270 burst_f1 : OUT STD_LOGIC;
270 burst_f1 : OUT STD_LOGIC;
271 burst_f2 : OUT STD_LOGIC;
271 burst_f2 : OUT STD_LOGIC;
272 run : OUT STD_LOGIC;
272 run : OUT STD_LOGIC;
273 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
273 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
274 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
274 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
275 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
275 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
276 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
276 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
277 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
278 ---------------------------------------------------------------------------
278 ---------------------------------------------------------------------------
279 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
279 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
280 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
280 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
281 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
281 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
283 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
283 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
284 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
284 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
286 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
286 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
287 END COMPONENT;
287 END COMPONENT;
288
288
289 COMPONENT lpp_top_ms
289 COMPONENT lpp_top_ms
290 GENERIC (
290 GENERIC (
291 Mem_use : INTEGER;
291 Mem_use : INTEGER;
292 nb_burst_available_size : INTEGER;
292 nb_burst_available_size : INTEGER;
293 nb_snapshot_param_size : INTEGER;
293 nb_snapshot_param_size : INTEGER;
294 delta_snapshot_size : INTEGER;
294 delta_snapshot_size : INTEGER;
295 delta_f2_f0_size : INTEGER;
295 delta_f2_f0_size : INTEGER;
296 delta_f2_f1_size : INTEGER;
296 delta_f2_f1_size : INTEGER;
297 pindex : INTEGER;
297 pindex : INTEGER;
298 paddr : INTEGER;
298 paddr : INTEGER;
299 pmask : INTEGER;
299 pmask : INTEGER;
300 pirq_ms : INTEGER;
300 pirq_ms : INTEGER;
301 pirq_wfp : INTEGER;
301 pirq_wfp : INTEGER;
302 hindex_wfp : INTEGER;
302 hindex_wfp : INTEGER;
303 hindex_ms : INTEGER);
303 hindex_ms : INTEGER);
304 PORT (
304 PORT (
305 clk : IN STD_LOGIC;
305 clk : IN STD_LOGIC;
306 rstn : IN STD_LOGIC;
306 rstn : IN STD_LOGIC;
307 sample_B : IN Samples14v(2 DOWNTO 0);
307 sample_B : IN Samples14v(2 DOWNTO 0);
308 sample_E : IN Samples14v(4 DOWNTO 0);
308 sample_E : IN Samples14v(4 DOWNTO 0);
309 sample_val : IN STD_LOGIC;
309 sample_val : IN STD_LOGIC;
310 apbi : IN apb_slv_in_type;
310 apbi : IN apb_slv_in_type;
311 apbo : OUT apb_slv_out_type;
311 apbo : OUT apb_slv_out_type;
312 ahbi_ms : IN AHB_Mst_In_Type;
312 ahbi_ms : IN AHB_Mst_In_Type;
313 ahbo_ms : OUT AHB_Mst_Out_Type;
313 ahbo_ms : OUT AHB_Mst_Out_Type;
314 data_shaping_BW : OUT STD_LOGIC;
314 data_shaping_BW : OUT STD_LOGIC;
315 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
315 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
316 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
316 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
317 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
317 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
318 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
318 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
319
319
320 );
320 );
321 END COMPONENT;
321 END COMPONENT;
322
322
323 END lpp_lfr_pkg;
323 END lpp_lfr_pkg;
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