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Dirty sync.
Jeandet Alexis -
r278:2db6d24e2968 alexis
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1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 library esa;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
23
24 Library UNISIM;
25 use UNISIM.vcomponents.all;
26
27
28 use work.config.all;
29 --==================================================================
30 --
31 --
32 -- FPGA FREQ = 100MHz
33 --
34 --
35 --==================================================================
36
37 entity BeagleSynth_MCTRL is
38 generic (
39 fabtech : integer := CFG_FABTECH;
40 memtech : integer := CFG_MEMTECH;
41 padtech : integer := CFG_PADTECH;
42 clktech : integer := CFG_CLKTECH
43 );
44 port (
45 reset : in std_ulogic;
46 clk : in std_ulogic;
47 DAC_nCLR : out std_ulogic;
48 DAC_nCS : out std_ulogic;
49 CAL_IN_SCK : out std_ulogic;
50 DAC_SDI : out std_ulogic_vector(7 downto 0);
51 TXD : out std_ulogic;
52 RXD : in std_ulogic;
53 urxd1 : in std_ulogic;
54 utxd1 : out std_ulogic;
55 LED : out std_ulogic_vector(2 downto 0);
56 --------------------------------------------------------
57 ---- SDRAM
58 ---- For SDRAM config have a look on leon3-altera-ep1c20
59 ---- design from GRLIB, the IS42S32400E is similar to
60 ---- MT48LC4M32B2.
61 --------------------------------------------------------
62 sdcke : out std_logic; -- clk en
63 sdcsn : out std_logic; -- chip sel
64 sdwen : out std_logic; -- write en
65 sdrasn : out std_logic; -- row addr stb
66 sdcasn : out std_logic; -- col addr stb
67 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
68 sdclk : out std_logic; -- sdram clk output
69 sdba : out std_logic_vector (1 downto 0); -- bank select address
70 Address : out std_logic_vector(11 downto 0); -- sdram address
71 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
72 );
73 end;
74
75 architecture rtl of BeagleSynth_MCTRL is
76 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
77 CFG_GRETH+CFG_AHB_JTAG;
78 constant maxahbm : integer := maxahbmsp;
79 constant IOAEN : integer := CFG_CAN;
80 constant boardfreq : integer := 100000;
81
82 signal clk2x : std_ulogic;
83 signal lclk : std_ulogic;
84 signal clkm : std_ulogic;
85 signal rstn : std_ulogic;
86 signal rst : std_ulogic;
87 signal rstraw : std_ulogic;
88 signal pciclk : std_ulogic;
89 signal sdclkl : std_ulogic;
90 signal sdclkl_DDR2 : std_ulogic;
91 signal cgi : clkgen_in_type;
92 signal cgo : clkgen_out_type;
93
94 --- AHB / APB
95 signal apbi : apb_slv_in_type;
96 signal apbo : apb_slv_out_vector := (others => apb_none);
97 signal ahbsi : ahb_slv_in_type;
98 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
99 signal ahbmi : ahb_mst_in_type;
100 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
101
102 --- MEM CTRLR
103 signal memi : memory_in_type;
104 signal memo : memory_out_type;
105 signal wpo : wprot_out_type;
106 signal sdi : sdctrl_in_type;
107 signal sdo : sdram_out_type;
108
109 --UART
110 signal ahbuarti : uart_in_type;
111 signal ahbuarto : uart_out_type;
112 signal apbuarti : uart_in_type;
113 signal apbuarto : uart_out_type;
114
115 signal led2int : std_logic;
116
117 begin
118
119 DAC_nCLR <= '1';
120 DAC_nCS <= '1';
121 CAL_IN_SCK <= '1';
122 DAC_SDI <= (others =>'1');
123
124 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
125 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
126 --rstn <= reset;
127 --lclk <= clk;
128 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
129
130 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
131 clkgen0 : clkgen -- clock generator
132 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
133 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
134
135 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
136 --sdclk <= sdclkl;
137 sdclk <= sdclkl_DDR2;
138
139 LED(1) <= not cgo.clklock;
140 LED(0) <= cgo.clklock;
141
142 ODDR2_inst : ODDR2
143 generic map(
144 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
145 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
146 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
147 port map (
148 Q => sdclkl_DDR2, -- 1-bit output data
149 C0 => sdclkl, -- 1-bit clock input
150 C1 => not sdclkl, -- 1-bit clock input
151 CE => '1', -- 1-bit clock enable input
152 D0 => '1', -- 1-bit data input (associated with C0)
153 D1 => '0', -- 1-bit data input (associated with C1)
154 R => '0', -- 1-bit reset input
155 S => '0' -- 1-bit set input
156 );
157
158 ----------------------------------------------------------------------
159 --- AHB CONTROLLER -------------------------------------------------
160 ----------------------------------------------------------------------
161
162 ahb0 : ahbctrl -- AHB arbiter/multiplexer
163 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
164 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
165 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
166 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
167
168 ----------------------------------------------------------------------
169 --- AHB UART -------------------------------------------------------
170 ----------------------------------------------------------------------
171
172 dcomgen : if CFG_AHB_UART = 1 generate
173 dcom0: ahbuart -- Debug UART
174 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
175 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
176 ahbuarti.rxd <= RXD;
177 TXD <= ahbuarto.txd;
178 end generate;
179 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
180
181 ----------------------------------------------------------------------
182 --- APB Bridge -----------------------------------------------------
183 ----------------------------------------------------------------------
184
185 apb0 : apbctrl -- AHB/APB bridge
186 generic map (hindex => 1, haddr => CFG_APBADDR)
187 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
188
189 ----------------------------------------------------------------------
190 --- APB UART -------------------------------------------------------
191 ----------------------------------------------------------------------
192
193 ua1 : if CFG_UART1_ENABLE /= 0 generate
194 uart1 : apbuart -- UART 1
195 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
196 fifosize => CFG_UART1_FIFO)
197 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
198 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
199 apbuarti.ctsn <= '0';
200 end generate;
201 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
202
203
204
205
206 --div0: Clk_divider
207 -- generic map( 100000000,1)
208 -- Port map( clkm,rstn,LED(2));
209
210 LED(2) <= led2int;
211
212 process(clkm,rstn)
213 begin
214 if rstn = '0' then
215 led2int <= '0';
216 elsif clkm'event and clkm='1' then
217 led2int <= not led2int;
218 end if;
219 end process;
220
221
222
223
224 memi.writen <= '1';
225 memi.wrn <= "1111";
226 memi.bwidth <= "00";
227 memi.brdyn <= '1';
228 memi.bexcn <= '1';
229
230 mctrl0 : mctrl
231 generic map (
232 hindex => 0,
233 pindex => 0,
234 paddr => 0,
235 srbanks => 1,
236 ram8 => 1,
237 ram16 => 1,
238 sden => 1,
239 invclk => 0,
240 sepbus => 0,
241 pageburst => 0)
242 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
243
244 -- SDRAM controller
245 sdwen_pad : outpad generic map (tech => padtech)
246 port map (sdwen, sdo.sdwen);
247 sdras_pad : outpad generic map (tech => padtech)
248 port map (sdrasn, sdo.rasn);
249 sdcas_pad : outpad generic map (tech => padtech)
250 port map (sdcasn, sdo.casn);
251 sddqm_pad : outpadv generic map (width =>4, tech => padtech)
252 port map (sddqm, sdo.dqm(3 downto 0));
253 sdba <= "00";
254
255 sdcsn_pad : outpad generic map (tech => padtech)
256 port map (sdcsn, sdo.sdcsn(0));
257
258 sdcke_pad : outpad generic map (tech => padtech)
259 port map (sdcke, sdo.sdcke(0));
260
261 addr_pad : outpadv generic map (width => 12, tech => padtech)
262 port map (address, memo.address(11 downto 0));
263
264 bdr : for i in 0 to 3 generate
265 data_pad : iopadv generic map (tech => padtech, width => 8)
266 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
267 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
268 end generate;
269
270
271 end rtl;
272
273
274
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:26:29 12/07/2013
6 -- Design Name:
7 -- Module Name: DAC8581 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.numeric_std.all;
23 library LPP;
24 use lpp.lpp_cna.all;
25
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 use IEEE.NUMERIC_STD.ALL;
29
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 --library UNISIM;
33 --use UNISIM.VComponents.all;
34
35 entity DAC8581 is
36 generic(clkfreq : integer := 100);
37 Port ( clk : in STD_LOGIC;
38 rstn : in STD_LOGIC;
39 smpclk : in STD_LOGIC;
40 sclk : out STD_LOGIC;
41 csn : out STD_LOGIC;
42 sdo : out STD_LOGIC;
43 smp_in : in STD_LOGIC_VECTOR (15 downto 0)
44 );
45 end DAC8581;
46
47 architecture Behavioral of DAC8581 is
48
49
50 signal smpclk_reg : std_logic;
51 signal sclk_gen : std_logic_vector(3 downto 0);
52 signal sclk_net : std_logic;
53 signal load : std_logic;
54 signal data_sreg : std_logic_vector(15 downto 0);
55 signal csn_sreg : std_logic_vector(15 downto 0);
56 begin
57
58
59
60 sclk_net <= sclk_gen(1);
61 sclk <= sclk_net;
62
63 process(rstn,clk)
64 begin
65 if rstn ='0' then
66 smpclk_reg <= '0';
67 sclk_gen <= "0000";
68 load <= '0';
69 elsif clk'event and clk = '1' then
70 smpclk_reg <= smpclk;
71 sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1);
72 if smpclk_reg = '0' and smpclk = '1' then
73 load <= '1';
74 else
75 load <= '0';
76 end if;
77
78 end if;
79 end process;
80
81 process(load,sclk_net)
82 begin
83 if load ='1' then
84 data_sreg <= smp_in;
85 csn_sreg <= (others => '0');
86 elsif sclk_net'event and sclk_net = '1' then
87 data_sreg <= data_sreg(14 downto 0) & '1';
88 csn_sreg <= csn_sreg(14 downto 0) & '1';
89 end if;
90 end process;
91
92 process(rstn,sclk_net)
93 begin
94 if rstn ='0' then
95 sdo <= '1';
96 csn <= '1';
97 elsif sclk_net'event and sclk_net = '0' then
98 sdo <= data_sreg(15);
99 csn <= csn_sreg(15);
100 end if;
101 end process;
102
103
104
105 end Behavioral;
106
107
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:20:11 12/08/2013
6 -- Design Name:
7 -- Module Name: GPMC_SLAVE - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.numeric_std.all;
23 library grlib, techmap;
24 use grlib.stdlib.all;
25 use techmap.gencomp.all;
26 use techmap.allclkgen.all;
27 library lpp;
28 use lpp.general_purpose.all;
29
30 entity GPMC_ASYNC_SLAVE is
31 generic (
32 memtech : integer := 0;
33 padtech : integer := 0
34 );
35 Port (
36 clk : in STD_LOGIC;
37 reset : in STD_LOGIC;
38 GPMC_AD : inout std_logic_vector(15 downto 0);
39 GPMC_A : in std_logic_vector(19 downto 0);
40 GPMC_CLK_MUX0 : in std_ulogic;
41 GPMC_WEN : in std_ulogic;
42 GPMC_OEN_REN : in std_ulogic;
43 GPMC_ADVN_ALE : in std_ulogic;
44 GPMC_CSN : in std_ulogic_vector(2 downto 0);
45 GPMC_BE0N_CLE : in std_ulogic;
46 GPMC_BE1N : in std_ulogic;
47 GPMC_WAIT0 : out std_ulogic;
48 GPMC_WPN : in std_ulogic
49 );
50 end GPMC_ASYNC_SLAVE;
51
52 architecture Behavioral of GPMC_ASYNC_SLAVE is
53 constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
54
55 signal data_out :std_logic_vector(15 downto 0);
56 signal data_in :std_logic_vector(15 downto 0);
57
58 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
59 signal RAMarray : RAMarrayT:=(others => VectInit);
60 signal ramindex : integer range 0 to 255;
61
62 begin
63
64 data_pad : iopadv generic map (tech=> padtech,width => 16)
65 port map (
66 pad => GPMC_AD(15 downto 0),
67 o => data_in(15 downto 0),
68 en => GPMC_OEN_REN,
69 i => data_out(15 downto 0)
70 );
71
72 GPMC_WAIT0 <= '1';
73
74 data_out <= RAMarray(ramindex);
75
76 process(reset,GPMC_CLK_MUX0)
77 begin
78 if reset = '0' then
79 --data_out <= (others => '0');
80 ramindex <= 0;
81 elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
82 if GPMC_ADVN_ALE = '0' then
83 ramindex <= to_integer(unsigned(GPMC_A(19 downto 1)));
84 end if;
85
86 if GPMC_WEN = '0' then
87 RAMarray(ramindex) <= data_in;
88 end if;
89 end if;
90 end process;
91
92 end Behavioral;
93
94
95
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1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 library esa;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
23 use lpp.lpp_cna.all;
24 use lpp.lpp_memory.all;
25
26 Library UNISIM;
27 use UNISIM.vcomponents.all;
28
29 use work.config.all;
30
31 entity beagleSigGen is
32 generic (
33 memtech : integer := CFG_MEMTECH;
34 padtech : integer := CFG_PADTECH;
35 clktech : integer := CFG_CLKTECH
36 );
37 Port (
38 clk : in STD_LOGIC;
39 rstn : in STD_LOGIC;
40 CAL_IN_SCK : out std_ulogic;
41 DAC_nCS : out std_ulogic;
42 DAC_SDI : out std_logic_vector(7 downto 0);
43 address : in std_logic_vector(2 downto 0);
44 DATA : in std_logic_vector(15 downto 0);
45 REN_debug : out std_logic;
46 WEN : in std_logic;
47 FIFO_FULL : out std_logic_vector(7 downto 0);
48 FIFO_EMPTY : out std_logic_vector(7 downto 0)
49 );
50 end beagleSigGen;
51
52 architecture Behavioral of beagleSigGen is
53
54
55 signal FIFO_FULL_net : std_logic_vector(7 downto 0);
56 signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
57 signal FIFO_WEN : std_logic_vector(7 downto 0);
58 signal FIFO_REN : std_logic;
59
60
61 subtype TAB16 is std_logic_vector(15 downto 0);
62 type FIFOout_t is array(7 downto 0) of TAB16;
63
64 signal FIFO_out : FIFOout_t;
65 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
66 signal smpclk : std_logic;
67 signal smpclk_reg : std_logic;
68 signal DAC_SDO : std_logic;
69 signal DATA_reg : std_logic_vector(15 downto 0);
70
71 begin
72
73
74
75 FIFO_FULL <= FIFO_FULL_net;
76 FIFO_EMPTY <= FIFO_EMPTY_net;
77
78 --fron_fifo1: lpp_fifo
79 -- generic map(
80 -- tech => memtech,
81 -- Mem_use => 1, --use RAM not CELS
82 -- DataSz => 16,
83 -- AddrSz => 8
84 -- )
85 -- port map(
86 -- rstn => rstn,
87 -- ReUse => '0',
88 -- rclk => clk,
89 -- ren => FIFO_REN,
90 -- rdata => FIFO_out(0),
91 -- empty => FIFO_EMPTY_net(0),
92 -- raddr => open,
93 -- wclk => clk,
94 -- wen => FIFO_WEN(0),
95 -- wdata => DATA_reg,
96 -- full => FIFO_FULL_net(0),
97 -- waddr => open
98 -- );
99 --fron_fifo2: lpp_fifo
100 -- generic map(
101 -- tech => memtech,
102 -- Mem_use => 1, --use RAM not CELS
103 -- DataSz => 16,
104 -- AddrSz => 8
105 -- )
106 -- port map(
107 -- rstn => rstn,
108 -- ReUse => '0',
109 -- rclk => clk,
110 -- ren => FIFO_REN,
111 -- rdata => FIFO_out(1),
112 -- empty => FIFO_EMPTY_net(1),
113 -- raddr => open,
114 -- wclk => clk,
115 -- wen => FIFO_WEN(1),
116 -- wdata => DATA_reg,
117 -- full => FIFO_FULL_net(1),
118 -- waddr => open
119 -- );
120 --fron_fifo3: lpp_fifo
121 -- generic map(
122 -- tech => memtech,
123 -- Mem_use => 1, --use RAM not CELS
124 -- DataSz => 16,
125 -- AddrSz => 8
126 -- )
127 -- port map(
128 -- rstn => rstn,
129 -- ReUse => '0',
130 -- rclk => clk,
131 -- ren => FIFO_REN,
132 -- rdata => FIFO_out(2),
133 -- empty => FIFO_EMPTY_net(2),
134 -- raddr => open,
135 -- wclk => clk,
136 -- wen => FIFO_WEN(2),
137 -- wdata => DATA_reg,
138 -- full => FIFO_FULL_net(2),
139 -- waddr => open
140 -- );
141 --fron_fifo4: lpp_fifo
142 -- generic map(
143 -- tech => memtech,
144 -- Mem_use => 1, --use RAM not CELS
145 -- DataSz => 16,
146 -- AddrSz => 8
147 -- )
148 -- port map(
149 -- rstn => rstn,
150 -- ReUse => '0',
151 -- rclk => clk,
152 -- ren => FIFO_REN,
153 -- rdata => FIFO_out(3),
154 -- empty => FIFO_EMPTY_net(3),
155 -- raddr => open,
156 -- wclk => clk,
157 -- wen => FIFO_WEN(3),
158 -- wdata => DATA_reg,
159 -- full => FIFO_FULL_net(3),
160 -- waddr => open
161 -- );
162 --fron_fifo5: lpp_fifo
163 -- generic map(
164 -- tech => memtech,
165 -- Mem_use => 1, --use RAM not CELS
166 -- DataSz => 16,
167 -- AddrSz => 8
168 -- )
169 -- port map(
170 -- rstn => rstn,
171 -- ReUse => '0',
172 -- rclk => clk,
173 -- ren => FIFO_REN,
174 -- rdata => FIFO_out(4),
175 -- empty => FIFO_EMPTY_net(4),
176 -- raddr => open,
177 -- wclk => clk,
178 -- wen => FIFO_WEN(4),
179 -- wdata => DATA_reg,
180 -- full => FIFO_FULL_net(4),
181 -- waddr => open
182 -- );
183 --fron_fifo6: lpp_fifo
184 -- generic map(
185 -- tech => memtech,
186 -- Mem_use => 1, --use RAM not CELS
187 -- DataSz => 16,
188 -- AddrSz => 8
189 -- )
190 -- port map(
191 -- rstn => rstn,
192 -- ReUse => '0',
193 -- rclk => clk,
194 -- ren => FIFO_REN,
195 -- rdata => FIFO_out(5),
196 -- empty => FIFO_EMPTY_net(5),
197 -- raddr => open,
198 -- wclk => clk,
199 -- wen => FIFO_WEN(5),
200 -- wdata => DATA_reg,
201 -- full => FIFO_FULL_net(5),
202 -- waddr => open
203 -- );
204 --fron_fifo7: lpp_fifo
205 -- generic map(
206 -- tech => memtech,
207 -- Mem_use => 1, --use RAM not CELS
208 -- DataSz => 16,
209 -- AddrSz => 8
210 -- )
211 -- port map(
212 -- rstn => rstn,
213 -- ReUse => '0',
214 -- rclk => clk,
215 -- ren => FIFO_REN,
216 -- rdata => FIFO_out(6),
217 -- empty => FIFO_EMPTY_net(6),
218 -- raddr => open,
219 -- wclk => clk,
220 -- wen => FIFO_WEN(6),
221 -- wdata => DATA_reg,
222 -- full => FIFO_FULL_net(6),
223 -- waddr => open
224 -- );
225 --fron_fifo8: lpp_fifo
226 -- generic map(
227 -- tech => memtech,
228 -- Mem_use => 1, --use RAM not CELS
229 -- DataSz => 16,
230 -- AddrSz => 8
231 -- )
232 -- port map(
233 -- rstn => rstn,
234 -- ReUse => '0',
235 -- rclk => clk,
236 -- ren => FIFO_REN,
237 -- rdata => FIFO_out(7),
238 -- empty => FIFO_EMPTY_net(7),
239 -- raddr => open,
240 -- wclk => clk,
241 -- wen => FIFO_WEN(7),
242 -- wdata => DATA_reg,
243 -- full => FIFO_FULL_net(7),
244 -- waddr => open
245 -- );
246
247 REN_debug <= FIFO_REN;
248
249 process(clk,rstn)
250 begin
251 if rstn = '0' then
252 DATA_reg <= (others => '0');
253 FIFO_WEN <= (others => '0');
254 elsif clk'event and clk = '1' then
255 if WEN = '0' then
256 DATA_reg <= DATA;
257 case address is
258 when "000"=>
259 FIFO_WEN <= "11111110";
260 FIFO_out(0) <= DATA;
261 when "001"=>
262 FIFO_WEN <= "11111101";
263 FIFO_out(1) <= DATA;
264 when "010"=>
265 FIFO_WEN <= "11111011";
266 FIFO_out(2) <= DATA;
267 when "011"=>
268 FIFO_WEN <= "11110111";
269 FIFO_out(3) <= DATA;
270 when "100"=>
271 FIFO_WEN <= "11101111";
272 FIFO_out(4) <= DATA;
273 when "101"=>
274 FIFO_WEN <= "11011111";
275 FIFO_out(5) <= DATA;
276 when "110"=>
277 FIFO_WEN <= "10111111";
278 FIFO_out(6) <= DATA;
279 when "111"=>
280 FIFO_WEN <= "01111111";
281 FIFO_out(7) <= DATA;
282 when others =>
283 FIFO_WEN <= "11111111";
284 end case;
285 end if;
286 end if;
287 end process;
288
289 all_bits: FOR I in 15 downto 0 GENERATE
290 all_chans: FOR J in 7 downto 0 GENERATE
291 DAC_DATA(J,I) <= FIFO_out(J)(I);
292 end GENERATE;
293 end GENERATE;
294
295
296
297 process(clk,rstn)
298 begin
299 if rstn = '0' then
300 FIFO_REN <= '1';
301 smpclk_reg <= '0';
302 elsif clk'event and clk = '1' then
303 smpclk_reg <= smpclk;
304 if smpclk = '1' and smpclk_reg = '0' then
305 FIFO_REN <= '0';
306 else
307 FIFO_REN <= '1';
308 end if;
309 end if;
310 end process;
311
312
313 DAC0 : DAC8581
314 generic map(150,8)
315 Port map(
316 clk => clk,
317 rstn => rstn,
318 smpclk => smpclk,
319 sclk => CAL_IN_SCK,
320 csn => DAC_nCS,
321 sdo => DAC_SDI,
322 smp_in => DAC_DATA
323 );
324
325
326
327 smpclk0: Clk_divider
328 GENERIC map(OSC_freqHz => 150000000,
329 TargetFreq_Hz => 32000)
330 PORT map(
331 clk => clk,
332 reset => rstn,
333 clk_divided => smpclk
334 );
335
336
337 end Behavioral;
338
Show file before | Show file after | Hide comments
@@ -2,8 +2,7
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
3 NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
4 NET "CLKM" TNM_NET = "clkm_net";
4 NET "CLKM" TNM_NET = "clkm_net";
5 TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
5 TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 6 ns HIGH 33%;
6
7
6
8 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
7 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
9 NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
8 NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
@@ -133,6 +132,8 NET "GPMC_A(18)" LOC = "J1"| slew=FAST
133 NET "GPMC_A(19)" LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL;
132 NET "GPMC_A(19)" LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL;
134
133
135 NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE;
134 NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE;
135 NET "GPMC_CLK_MUX0" TNM_NET = "GPMC_CLK_MUX0_net";
136 TIMESPEC "TS_GPMC_CLK_MUX0_net" = PERIOD "GPMC_CLK_MUX0_net" 8 ns HIGH 50%;
136 NET "GPMC_CLK_MUX0" LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL;
137 NET "GPMC_CLK_MUX0" LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL;
137 NET "GPMC_WEN" LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL;
138 NET "GPMC_WEN" LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL;
138 NET "GPMC_OEN_REN" LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL;
139 NET "GPMC_OEN_REN" LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL;
Show file before | Show file after | Hide comments
@@ -59,15 +59,15 entity BeagleSynth is
59 --------------------------------------------------------
59 --------------------------------------------------------
60 GPMC_AD : inout std_logic_vector(15 downto 0);
60 GPMC_AD : inout std_logic_vector(15 downto 0);
61 GPMC_A : in std_logic_vector(19 downto 0);
61 GPMC_A : in std_logic_vector(19 downto 0);
62 GPMC_CLK_MUX0 : in std_ulogic;
62 GPMC_CLK_MUX0 : in std_logic;
63 GPMC_WEN : in std_ulogic;
63 GPMC_WEN : in std_logic;
64 GPMC_OEN_REN : in std_ulogic;
64 GPMC_OEN_REN : in std_logic;
65 GPMC_ADVN_ALE : in std_ulogic;
65 GPMC_ADVN_ALE : in std_logic;
66 GPMC_CSN : in std_ulogic_vector(2 downto 0);
66 GPMC_CSN : in std_logic_vector(2 downto 0);
67 GPMC_BE0N_CLE : in std_ulogic;
67 GPMC_BE0N_CLE : in std_logic;
68 GPMC_BE1N : in std_ulogic;
68 GPMC_BE1N : in std_logic;
69 GPMC_WAIT0 : in std_ulogic;
69 GPMC_WAIT0 : out std_logic;
70 GPMC_WPN : in std_ulogic;
70 GPMC_WPN : in std_logic;
71
71
72 --------------------------------------------------------
72 --------------------------------------------------------
73 ---- SDRAM
73 ---- SDRAM
@@ -75,15 +75,15 entity BeagleSynth is
75 ---- design from GRLIB, the IS42S32400E is similar to
75 ---- design from GRLIB, the IS42S32400E is similar to
76 ---- MT48LC4M32B2.
76 ---- MT48LC4M32B2.
77 --------------------------------------------------------
77 --------------------------------------------------------
78 sdcke : out std_logic; -- clk en
78 sdcke : out std_logic; -- clk en
79 sdcsn : out std_logic; -- chip sel
79 sdcsn : out std_logic; -- chip sel
80 sdwen : out std_logic; -- write en
80 sdwen : out std_logic; -- write en
81 sdrasn : out std_logic; -- row addr stb
81 sdrasn : out std_logic; -- row addr stb
82 sdcasn : out std_logic; -- col addr stb
82 sdcasn : out std_logic; -- col addr stb
83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
84 sdclk : out std_logic; -- sdram clk output
84 sdclk : out std_logic; -- sdram clk output
85 sdba : out std_logic_vector (1 downto 0); -- bank select address
85 sdba : out std_logic_vector (1 downto 0); -- bank select address
86 Address : out std_logic_vector(11 downto 0); -- sdram address
86 Address : out std_logic_vector(11 downto 0); -- sdram address
87 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
87 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
88 );
88 );
89 end;
89 end;
@@ -107,53 +107,33 signal sdclkl_DDR2 : std_ulogic;
107 signal cgi : clkgen_in_type;
107 signal cgi : clkgen_in_type;
108 signal cgo : clkgen_out_type;
108 signal cgo : clkgen_out_type;
109
109
110 --- AHB / APB
111 signal apbi : apb_slv_in_type;
112 signal apbo : apb_slv_out_vector := (others => apb_none);
113 signal ahbsi : ahb_slv_in_type;
114 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
115 signal ahbmi : ahb_mst_in_type;
116 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
117
118 --- MEM CTRLR
119 signal sdi : sdctrl_in_type;
120 signal sdo : sdctrl_out_type;
121
122 --UART
123 signal ahbuarti : uart_in_type;
124 signal ahbuarto : uart_out_type;
125 signal apbuarti : uart_in_type;
126 signal apbuarto : uart_out_type;
127
128 signal led2int : std_logic;
129
130
131 signal DAC0_DATA : std_logic_vector(15 downto 0);
132 signal DAC1_DATA : std_logic_vector(15 downto 0);
133 signal DAC2_DATA : std_logic_vector(15 downto 0);
134 signal DAC3_DATA : std_logic_vector(15 downto 0);
135 signal DAC4_DATA : std_logic_vector(15 downto 0);
136 signal DAC5_DATA : std_logic_vector(15 downto 0);
137 signal DAC6_DATA : std_logic_vector(15 downto 0);
138 signal DAC7_DATA : std_logic_vector(15 downto 0);
139
110
140 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
111 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
141 signal smpclk : std_logic;
112 signal smpclk : std_logic;
142 signal smpclk_reg : std_logic;
113 signal smpclk_reg : std_logic;
143 signal DAC_SDO : std_logic;
114 signal DAC_SDO : std_logic;
144
115
116 signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0);
117 signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0);
118 signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0);
119 signal GPMC_SLAVE_WEN : std_logic;
120
145 signal gpmc_clk : std_logic;
121 signal gpmc_clk : std_logic;
122
123 attribute keep : boolean;
124 attribute syn_keep : boolean;
125 attribute syn_preserve : boolean;
126 attribute syn_keep of clkm : signal is true;
127 attribute syn_preserve of clkm : signal is true;
128 attribute keep of clkm : signal is true;
146 begin
129 begin
147
130
148 DAC_nCLR <= '1';
131 DAC_nCLR <= '1';
149 --DAC_nCS <= SYNC;
132
150 --CAL_IN_SCK <= '1';
151 --DAC_SDI <= (others =>'1');
152
133
153 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
134 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
154 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
135 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
155 --rstn <= reset;
136
156 --lclk <= clk;
157 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
137 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
158
138
159 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
139 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
@@ -161,183 +141,33 resetn_pad : inpad generic map (tech =>
161 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
141 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
162 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
163
143
164 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
165 --sdclk <= sdclkl;
166 sdclk <= sdclkl_DDR2;
167
168 LED(1) <= not cgo.clklock;
169 LED(0) <= cgo.clklock;
170
171 ODDR2_inst : ODDR2
172 generic map(
173 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
174 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
175 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
176 port map (
177 Q => sdclkl_DDR2, -- 1-bit output data
178 C0 => sdclkl, -- 1-bit clock input
179 C1 => not sdclkl, -- 1-bit clock input
180 CE => '1', -- 1-bit clock enable input
181 D0 => '1', -- 1-bit data input (associated with C0)
182 D1 => '0', -- 1-bit data input (associated with C1)
183 R => '0', -- 1-bit reset input
184 S => '0' -- 1-bit set input
185 );
186
187 ----------------------------------------------------------------------
188 --- AHB CONTROLLER -------------------------------------------------
189 ----------------------------------------------------------------------
190
191 ahb0 : ahbctrl -- AHB arbiter/multiplexer
192 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
193 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
194 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
195 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
196
197 ----------------------------------------------------------------------
198 --- AHB UART -------------------------------------------------------
199 ----------------------------------------------------------------------
200
201 dcomgen : if CFG_AHB_UART = 1 generate
202 dcom0: ahbuart -- Debug UART
203 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
204 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
205 ahbuarti.rxd <= RXD;
206 TXD <= ahbuarto.txd;
207 end generate;
208 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
209
210 ----------------------------------------------------------------------
211 --- APB Bridge -----------------------------------------------------
212 ----------------------------------------------------------------------
213
214 apb0 : apbctrl -- AHB/APB bridge
215 generic map (hindex => 1, haddr => CFG_APBADDR)
216 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
217
218 ----------------------------------------------------------------------
219 --- APB UART -------------------------------------------------------
220 ----------------------------------------------------------------------
221
222 ua1 : if CFG_UART1_ENABLE /= 0 generate
223 uart1 : apbuart -- UART 1
224 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
225 fifosize => CFG_UART1_FIFO)
226 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
227 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
228 apbuarti.ctsn <= '0';
229 end generate;
230 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
231
232
233
234
235 --div0: Clk_divider
236 -- generic map( 100000000,1)
237 -- Port map( clkm,rstn,LED(2));
238
239 LED(2) <= led2int;
240
241 process(clkm,rstn)
242 begin
243 if rstn = '0' then
244 led2int <= '0';
245 elsif clkm'event and clkm='1' then
246 led2int <= not led2int;
247 end if;
248 end process;
249
250
144
251
145
252
146
253 sdc : sdctrl
147 DAC0 : entity work.beagleSigGen
254 generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
148 generic map(
255 invclk => 0,sdbits =>32)
149 memtech,
256 port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
150 padtech,
257
151 clktech
258
152 )
259
260 --Alternative data pad instantiation with vectored bdrive
261 sd_pad : iopadvv generic map (tech=> padtech,width => 32)
262 port map (
263 data(31 downto 0),
264 sdo.data(31 downto 0),
265 sdo.vbdrive(31 downto 0),
266 sdi.data(31 downto 0));
267
268
269 -- connect memory controller outputs to entity output signals
270 Address <= sdo.address(13 downto 2);
271 --sdba <= sdo.address(16 downto 15);
272 sdba <= "00";
273 sdcke <= sdo.sdcke(0);
274 sdwen <= sdo.sdwen;
275 sdcsn <= sdo.sdcsn(0);
276 sdrasn <= sdo.rasn;
277 sdcasn <= sdo.casn;
278 sddqm <= sdo.dqm(3 downto 0);
279
280
281 DAC0 : DAC8581
282 generic map(100,8)
283 Port map(
153 Port map(
284 clk => clkm,
154 clk => clkm,
285 rstn => rstn,
155 rstn => rstn,
286 smpclk => smpclk,
156 CAL_IN_SCK => CAL_IN_SCK,
287 sclk => CAL_IN_SCK,
157 DAC_nCS => DAC_nCS,
288 csn => DAC_nCS,
158 DAC_SDI => DAC_SDI,
289 sdo => DAC_SDI,
159 address => GPMC_SLAVE_ADDRESS(3 downto 1),
290 smp_in => DAC_DATA
160 DATA => GPMC_SLAVE_DATA,
161 WEN => GPMC_SLAVE_WEN,
162 REN_debug => LED(1),
163 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
164 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
291 );
165 );
292
166
293
294
167
295 smpclk0: Clk_divider
168
296 GENERIC map(OSC_freqHz => 50000000,
169 LED(0) <= GPMC_SLAVE_WEN;
297 TargetFreq_Hz => 256000)
170 LED(2) <= GPMC_WEN;
298 PORT map( clk => clkm,
299 reset => rstn,
300 clk_divided => smpclk
301 );
302
303 all_bits: FOR I in 15 downto 0 GENERATE
304 DAC_DATA(0,I) <= DAC0_DATA(I);
305 DAC_DATA(1,I) <= DAC1_DATA(I);
306 DAC_DATA(2,I) <= DAC2_DATA(I);
307 DAC_DATA(3,I) <= DAC3_DATA(I);
308 DAC_DATA(4,I) <= DAC4_DATA(I);
309 DAC_DATA(5,I) <= DAC5_DATA(I);
310 DAC_DATA(6,I) <= DAC6_DATA(I);
311 DAC_DATA(7,I) <= DAC7_DATA(I);
312 end GENERATE;
313
314 process(clkm,rstn)
315 begin
316 if rstn ='0' then
317 DAC0_DATA <= X"0000";
318 DAC1_DATA <= X"0000";
319 DAC2_DATA <= X"0000";
320 DAC3_DATA <= X"0000";
321 DAC4_DATA <= X"0000";
322 DAC5_DATA <= X"0000";
323 DAC6_DATA <= X"0000";
324 DAC7_DATA <= X"0000";
325 smpclk_reg <= smpclk;
326 elsif clkm'event and clkm = '1' then
327 smpclk_reg <= smpclk;
328 if smpclk_reg = '0' and smpclk = '1' then
329 DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
330 DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
331 DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
332 DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
333 DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
334 DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
335 DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
336 DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
337 -- DAC_DATA <= "0100000000000000";
338 end if;
339 end if;
340 end process;
341
171
342 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
172 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
343 GPMCS0: entity work.GPMC_SLAVE
173 GPMCS0: entity work.GPMC_SLAVE
@@ -345,9 +175,13 GPMCS0: entity work.GPMC_SLAVE
345 Port map(
175 Port map(
346 clk => clkm,
176 clk => clkm,
347 reset => rstn,
177 reset => rstn,
178 STATUS => GPMC_SLAVE_STATUS,
179 DATA => GPMC_SLAVE_DATA,
180 ADDRESS => GPMC_SLAVE_ADDRESS,
181 WEN => GPMC_SLAVE_WEN,
348 GPMC_AD => GPMC_AD,
182 GPMC_AD => GPMC_AD,
349 GPMC_A => GPMC_A,
183 GPMC_A => GPMC_A,
350 GPMC_CLK_MUX0 => gpmc_clk,
184 GPMC_CLK => gpmc_clk,
351 GPMC_WEN => GPMC_WEN,
185 GPMC_WEN => GPMC_WEN,
352 GPMC_OEN_REN => GPMC_OEN_REN,
186 GPMC_OEN_REN => GPMC_OEN_REN,
353 GPMC_ADVN_ALE => GPMC_ADVN_ALE,
187 GPMC_ADVN_ALE => GPMC_ADVN_ALE,
@@ -355,7 +189,7 GPMCS0: entity work.GPMC_SLAVE
355 GPMC_BE0N_CLE => GPMC_BE0N_CLE,
189 GPMC_BE0N_CLE => GPMC_BE0N_CLE,
356 GPMC_BE1N => GPMC_BE1N,
190 GPMC_BE1N => GPMC_BE1N,
357 GPMC_WAIT0 => GPMC_WAIT0,
191 GPMC_WAIT0 => GPMC_WAIT0,
358 GPMC_WPN => GPMC_WAIT0
192 GPMC_WPN => GPMC_WPN
359 );
193 );
360
194
361 end rtl;
195 end rtl;
Show file before | Show file after | Hide comments
@@ -35,51 +35,73 entity GPMC_SLAVE is
35 Port (
35 Port (
36 clk : in STD_LOGIC;
36 clk : in STD_LOGIC;
37 reset : in STD_LOGIC;
37 reset : in STD_LOGIC;
38 STATUS : in STD_LOGIC_VECTOR(15 downto 0);
39 DATA : out STD_LOGIC_VECTOR(15 downto 0);
40 ADDRESS : out std_logic_vector(19 downto 0);
41 WEN : out STD_LOGIC;
38 GPMC_AD : inout std_logic_vector(15 downto 0);
42 GPMC_AD : inout std_logic_vector(15 downto 0);
39 GPMC_A : in std_logic_vector(19 downto 0);
43 GPMC_A : in std_logic_vector(19 downto 0);
40 GPMC_CLK_MUX0 : in std_ulogic;
44 GPMC_CLK : in std_logic;
41 GPMC_WEN : in std_ulogic;
45 GPMC_WEN : in std_logic;
42 GPMC_OEN_REN : in std_ulogic;
46 GPMC_OEN_REN : in std_logic;
43 GPMC_ADVN_ALE : in std_ulogic;
47 GPMC_ADVN_ALE : in std_logic;
44 GPMC_CSN : in std_ulogic_vector(2 downto 0);
48 GPMC_CSN : in std_logic_vector(2 downto 0);
45 GPMC_BE0N_CLE : in std_ulogic;
49 GPMC_BE0N_CLE : in std_logic;
46 GPMC_BE1N : in std_ulogic;
50 GPMC_BE1N : in std_logic;
47 GPMC_WAIT0 : in std_ulogic;
51 GPMC_WAIT0 : out std_logic;
48 GPMC_WPN : in std_ulogic
52 GPMC_WPN : in std_logic
49 );
53 );
50 end GPMC_SLAVE;
54 end GPMC_SLAVE;
51
55
52 architecture Behavioral of GPMC_SLAVE is
56 architecture Behavioral of GPMC_SLAVE is
53 constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
57
58 signal data_out : std_logic_vector(15 downto 0) := (others => '0');
59 signal data_in : std_logic_vector(15 downto 0) := (others => '0');
54
60
55 signal data_out :std_logic_vector(15 downto 0);
61 signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0');
56 signal data_in :std_logic_vector(15 downto 0);
62 signal data_r : std_logic_vector(15 downto 0) := (others => '0');
57
63
58 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
64
59 signal RAMarray : RAMarrayT:=(others => VectInit);
65 signal outen : std_logic := '0';
60 signal ramindex : integer range 0 to 255;
66
61
67
62 begin
68 begin
63
69
70 outen <= GPMC_OEN_REN or GPMC_CSN(0);
71 data_out <= STATUS;
72
64 data_pad : iopadv generic map (tech=> padtech,width => 16)
73 data_pad : iopadv generic map (tech=> padtech,width => 16)
65 port map (
74 port map (
66 pad => GPMC_AD(15 downto 0),
75 pad => GPMC_AD(15 downto 0),
67 o => data_in(15 downto 0),
76 o => data_in(15 downto 0),
68 en => GPMC_OEN_REN,
77 en => outen,
69 i => data_out(15 downto 0)
78 i => data_out(15 downto 0)
70 );
79 );
71
80
72 process(reset,GPMC_CLK_MUX0)
81 GPMC_WAIT0 <= '1';
82
83
84
85 process(reset,clk)
73 begin
86 begin
74 if reset = '0' then
87 if reset = '0' then
75 data_out <= (others => '0');
88 WEN <= '1';
76 ramindex <= 0;
89 GPMC_CLK_reg <= "0000";
77 elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
90 ADDRESS <= (others => '0');
78 ramindex <= to_integer(unsigned(GPMC_A));
91 elsif clk'event and clk = '1' then
79 data_out <= RAMarray(ramindex);
92 GPMC_CLK_reg(0) <= GPMC_CLK;
80 if GPMC_WEN = '0' then
93 if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then
81 RAMarray(ramindex) <= data_in;
94 if GPMC_WEN = '0' then
95 WEN <= '0';
96 DATA <= data_in;
97 end if;
98 if GPMC_ADVN_ALE = '0' then
99 ADDRESS <= GPMC_A;
100 end if;
101 else
102 WEN <= '1';
82 end if;
103 end if;
104
83 end if;
105 end if;
84 end process;
106 end process;
85
107
Show file before | Show file after | Hide comments
@@ -17,7 +17,7 VHDLOPTSYNFILES=
17
17
18
18
19 VHDLSYNFILES= \
19 VHDLSYNFILES= \
20 config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd
20 config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd beagleSigGen.vhd GPMC_ASYNC_SLAVE.vhd
21 #VHDLSIMFILES=testbench.vhd
21 #VHDLSIMFILES=testbench.vhd
22 #SIMTOP=testbench
22 #SIMTOP=testbench
23 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
23 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
Show file before | Show file after | Hide comments
@@ -24,7 +24,7 package config is
24 -- ON Spartan 6 VCO freq must be between 400MHz and 1GHz
24 -- ON Spartan 6 VCO freq must be between 400MHz and 1GHz
25 constant CFG_CLKTECH : integer := spartan6;
25 constant CFG_CLKTECH : integer := spartan6;
26 constant CFG_CLKMUL : integer := (6);
26 constant CFG_CLKMUL : integer := (6);
27 constant CFG_CLKDIV : integer := (12);
27 constant CFG_CLKDIV : integer := (4);
28 constant CFG_OCLKDIV : integer := (1);
28 constant CFG_OCLKDIV : integer := (1);
29 constant CFG_PCIDLL : integer := 0;
29 constant CFG_PCIDLL : integer := 0;
30 constant CFG_PCISYSCLK: integer := 0;
30 constant CFG_PCISYSCLK: integer := 0;
Show file before | Show file after | Hide comments
@@ -53,14 +53,17 signal smpclk_reg : std_logic;
53 signal sclk_gen : std_logic_vector(3 downto 0);
53 signal sclk_gen : std_logic_vector(3 downto 0);
54 signal sclk_net : std_logic;
54 signal sclk_net : std_logic;
55 signal load : std_logic;
55 signal load : std_logic;
56 signal load_reg : std_logic;
56 signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
57 signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
57 signal csn_sreg : std_logic_vector(15 downto 0);
58
58
59 signal csn_sreg : std_logic;
60 signal shift_counter : integer range 0 to 16;
61 signal sdo_int : STD_LOGIC_VECTOR (ChanCount-1 downto 0);
59 begin
62 begin
60
63
61
64
62
65
63 sclk_net <= sclk_gen(1);
66 sclk_net <= sclk_gen(2);
64 sclk <= sclk_net;
67 sclk <= sclk_net;
65
68
66 process(rstn,clk)
69 process(rstn,clk)
@@ -84,17 +87,37 end process;
84 process(load,sclk_net)
87 process(load,sclk_net)
85 begin
88 begin
86 if load ='1' then
89 if load ='1' then
87 data_sreg <= smp_in;
90 load_reg <= '1';
88 csn_sreg <= (others => '0');
91 elsif sclk_net'event and sclk_net = '1' then
89
92 load_reg <= '0';
90 elsif sclk_net'event and sclk_net = '1' then
93 end if;
91 all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
94 end process;
92 all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
95
93 data_sreg(I,J+1) <= data_sreg(I,J);
96 process(rstn,sclk_net)
94 END LOOP all_bits0;
97 begin
95 data_sreg(I,0) <= '1';
98 if rstn ='0' then
96 END LOOP all_chanel0;
99 data_sreg <= smp_in;
97 csn_sreg <= csn_sreg(14 downto 0) & '1';
100 csn_sreg <= '1';
101 elsif sclk_net'event and sclk_net = '1' then
102 if load_reg = '1' then
103 data_sreg <= smp_in;
104 shift_counter <= 0;
105 csn_sreg <= '1';
106 else
107 all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
108 all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
109 data_sreg(I,J+1) <= data_sreg(I,J);
110 END LOOP all_bits0;
111 data_sreg(I,0) <= '1';
112 END LOOP all_chanel0;
113 if shift_counter /= 16 then
114 shift_counter <= shift_counter + 1;
115 csn_sreg <= '0';
116 else
117 csn_sreg <= '1';
118 end if;
119
120 end if;
98 end if;
121 end if;
99 end process;
122 end process;
100
123
@@ -102,14 +125,16 process(rstn,sclk_net)
102 begin
125 begin
103 if rstn ='0' then
126 if rstn ='0' then
104 all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
127 all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
105 sdo(I) <= '1';
128 sdo_int(I) <= '1';
129 sdo(I) <= '1';
106 END LOOP all_chanel2;
130 END LOOP all_chanel2;
107 csn <= '1';
131 csn <= '1';
108 elsif sclk_net'event and sclk_net = '0' then
132 elsif sclk_net'event and sclk_net = '0' then
109 all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
133 all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
110 sdo(I) <= data_sreg(I,15);
134 sdo_int(I) <= data_sreg(I,15);
111 END LOOP all_chanel1;
135 END LOOP all_chanel1;
112 csn <= csn_sreg(15);
136 sdo <= sdo_int;
137 csn <= csn_sreg;
113 end if;
138 end if;
114 end process;
139 end process;
115
140
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@@ -43,6 +43,11 if [ -d "$GRLIBPATH" ]; then
43 else
43 else
44 echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
44 echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
45 fi
45 fi
46 if(grep -q $LPP_PATCHPATH/lib/staging $1/lib/libs.txt); then
47 echo "No need to Patch $1/lib/libs.txt..."
48 else
49 echo $LPP_PATCHPATH/lib/staging >>$1/lib/libs.txt
50 fi
46 echo
51 echo
47 echo
52 echo
48 echo
53 echo
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