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Working bbone GPMC_interface interface
Jeandet Alexis -
r282:252bd09e4210 alexis
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@@ -154,7 +154,7 DAC0 : entity work.beagleSigGen
154 154 CAL_IN_SCK => CAL_IN_SCK,
155 155 DAC_nCS => DAC_nCS,
156 156 DAC_SDI => DAC_SDI,
157 address => GPMC_SLAVE_ADDRESS(3 downto 1),
157 address => GPMC_SLAVE_ADDRESS(19 downto 1),
158 158 DATA => GPMC_SLAVE_DATA,
159 159 WEN => GPMC_SLAVE_WEN,
160 160 REN_debug => open,
@@ -164,8 +164,8 DAC0 : entity work.beagleSigGen
164 164
165 165
166 166
167 --LED(0) <= GPMC_SLAVE_ADDRESS(1);
168 --LED(1) <= GPMC_SLAVE_ADDRESS(2);
167 LED(0) <= GPMC_SLAVE_STATUS(0);
168 LED(1) <= GPMC_SLAVE_STATUS(8);
169 169 LED(2) <= GPMC_SLAVE_WEN;
170 170
171 171 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
@@ -178,8 +178,8 GPMCS0: entity work.GPMC_SLAVE
178 178 DATA => GPMC_SLAVE_DATA,
179 179 ADDRESS => GPMC_SLAVE_ADDRESS,
180 180 WEN => GPMC_SLAVE_WEN,
181 SMP_CKL => LED(0),
182 SMP_WEN => LED(1),
181 SMP_CKL => open,
182 SMP_WEN => open,
183 183 GPMC_AD => GPMC_AD,
184 184 GPMC_A => GPMC_A,
185 185 GPMC_CLK => gpmc_clk,
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@@ -40,7 +40,7 entity beagleSigGen is
40 40 CAL_IN_SCK : out std_ulogic;
41 41 DAC_nCS : out std_ulogic;
42 42 DAC_SDI : out std_logic_vector(7 downto 0);
43 address : in std_logic_vector(2 downto 0);
43 address : in std_logic_vector(18 downto 0);
44 44 DATA : in std_logic_vector(15 downto 0);
45 45 REN_debug : out std_logic;
46 46 WEN : in std_logic;
@@ -51,23 +51,28 end beagleSigGen;
51 51
52 52 architecture Behavioral of beagleSigGen is
53 53
54 subtype TAB16 is std_logic_vector(15 downto 0);
55 type FIFOout_t is array(7 downto 0) of TAB16;
54 56
55 57 signal FIFO_FULL_net : std_logic_vector(7 downto 0);
56 58 signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
57 signal FIFO_WEN : std_logic_vector(7 downto 0);
58 signal FIFO_REN : std_logic;
59 59
60
61 subtype TAB16 is std_logic_vector(15 downto 0);
62 type FIFOout_t is array(7 downto 0) of TAB16;
60 signal FIFO_WEN : std_logic_vector(7 downto 0);
61 signal FIFO_REN : std_logic;
63 62
64 63 signal FIFO_out : FIFOout_t;
64
65 65 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
66 66 signal smpclk : std_logic;
67 67 signal smpclk_reg : std_logic;
68 68 signal DAC_SDO : std_logic;
69 69 signal DATA_reg : std_logic_vector(15 downto 0);
70 70
71 Constant clk_TRIGER_MAX : integer := (150000000/(2*4096))+1;
72 signal clk_TRIGER : integer range 0 to clk_TRIGER_MAX := clk_TRIGER_MAX;
73 signal cpt1 : integer;
74 signal clk_TRIGER_load : std_logic;
75
71 76 begin
72 77
73 78
@@ -75,174 +80,55 begin
75 80 FIFO_FULL <= FIFO_FULL_net;
76 81 FIFO_EMPTY <= FIFO_EMPTY_net;
77 82
78 fron_fifo1: lpp_fifo
79 generic map(
80 tech => memtech,
81 Mem_use => 1, --use RAM not CELS
82 DataSz => 16,
83 AddrSz => 8
84 )
85 port map(
86 rstn => rstn,
87 ReUse => '0',
88 rclk => clk,
89 ren => FIFO_REN,
90 rdata => FIFO_out(0),
91 empty => FIFO_EMPTY_net(0),
92 raddr => open,
93 wclk => clk,
94 wen => FIFO_WEN(0),
95 wdata => DATA_reg,
96 full => FIFO_FULL_net(0),
97 waddr => open
98 );
99 fron_fifo2: lpp_fifo
83 FIFOlp : FOR I IN 0 to 7 GENERATE
84 front_fifoN: lpp_fifo
100 85 generic map(
101 86 tech => memtech,
102 87 Mem_use => 1, --use RAM not CELS
103 88 DataSz => 16,
104 AddrSz => 8
105 )
106 port map(
107 rstn => rstn,
108 ReUse => '0',
109 rclk => clk,
110 ren => FIFO_REN,
111 rdata => FIFO_out(1),
112 empty => FIFO_EMPTY_net(1),
113 raddr => open,
114 wclk => clk,
115 wen => FIFO_WEN(1),
116 wdata => DATA_reg,
117 full => FIFO_FULL_net(1),
118 waddr => open
119 );
120 fron_fifo3: lpp_fifo
121 generic map(
122 tech => memtech,
123 Mem_use => 1, --use RAM not CELS
124 DataSz => 16,
125 AddrSz => 8
126 )
127 port map(
128 rstn => rstn,
129 ReUse => '0',
130 rclk => clk,
131 ren => FIFO_REN,
132 rdata => FIFO_out(2),
133 empty => FIFO_EMPTY_net(2),
134 raddr => open,
135 wclk => clk,
136 wen => FIFO_WEN(2),
137 wdata => DATA_reg,
138 full => FIFO_FULL_net(2),
139 waddr => open
140 );
141 fron_fifo4: lpp_fifo
142 generic map(
143 tech => memtech,
144 Mem_use => 1, --use RAM not CELS
145 DataSz => 16,
146 AddrSz => 8
89 AddrSz => 12
147 90 )
148 91 port map(
149 92 rstn => rstn,
150 93 ReUse => '0',
151 94 rclk => clk,
152 95 ren => FIFO_REN,
153 rdata => FIFO_out(3),
154 empty => FIFO_EMPTY_net(3),
155 raddr => open,
156 wclk => clk,
157 wen => FIFO_WEN(3),
158 wdata => DATA_reg,
159 full => FIFO_FULL_net(3),
160 waddr => open
161 );
162 fron_fifo5: lpp_fifo
163 generic map(
164 tech => memtech,
165 Mem_use => 1, --use RAM not CELS
166 DataSz => 16,
167 AddrSz => 8
168 )
169 port map(
170 rstn => rstn,
171 ReUse => '0',
172 rclk => clk,
173 ren => FIFO_REN,
174 rdata => FIFO_out(4),
175 empty => FIFO_EMPTY_net(4),
176 raddr => open,
177 wclk => clk,
178 wen => FIFO_WEN(4),
179 wdata => DATA_reg,
180 full => FIFO_FULL_net(4),
181 waddr => open
182 );
183 fron_fifo6: lpp_fifo
184 generic map(
185 tech => memtech,
186 Mem_use => 1, --use RAM not CELS
187 DataSz => 16,
188 AddrSz => 8
189 )
190 port map(
191 rstn => rstn,
192 ReUse => '0',
193 rclk => clk,
194 ren => FIFO_REN,
195 rdata => FIFO_out(5),
196 empty => FIFO_EMPTY_net(5),
96 rdata => FIFO_out(I),
97 empty => FIFO_EMPTY_net(I),
197 98 raddr => open,
198 99 wclk => clk,
199 wen => FIFO_WEN(5),
100 wen => FIFO_WEN(I),
200 101 wdata => DATA_reg,
201 full => FIFO_FULL_net(5),
102 full => FIFO_FULL_net(I),
202 103 waddr => open
203 104 );
204 fron_fifo7: lpp_fifo
205 generic map(
206 tech => memtech,
207 Mem_use => 1, --use RAM not CELS
208 DataSz => 16,
209 AddrSz => 8
210 )
211 port map(
212 rstn => rstn,
213 ReUse => '0',
214 rclk => clk,
215 ren => FIFO_REN,
216 rdata => FIFO_out(6),
217 empty => FIFO_EMPTY_net(6),
218 raddr => open,
219 wclk => clk,
220 wen => FIFO_WEN(6),
221 wdata => DATA_reg,
222 full => FIFO_FULL_net(6),
223 waddr => open
224 );
225 fron_fifo8: lpp_fifo
226 generic map(
227 tech => memtech,
228 Mem_use => 1, --use RAM not CELS
229 DataSz => 16,
230 AddrSz => 8
231 )
232 port map(
233 rstn => rstn,
234 ReUse => '0',
235 rclk => clk,
236 ren => FIFO_REN,
237 rdata => FIFO_out(7),
238 empty => FIFO_EMPTY_net(7),
239 raddr => open,
240 wclk => clk,
241 wen => FIFO_WEN(7),
242 wdata => DATA_reg,
243 full => FIFO_FULL_net(7),
244 waddr => open
245 );
105 END GENERATE;
106
107 --FIFOlp : FOR I IN 0 to 7 GENERATE
108 --front_fifoN: FIFO_pipeline
109 --generic map(
110 -- tech => memtech,
111 -- fifoCount => 8,
112 -- Mem_use => 1, --use RAM not CELS
113 -- DataSz => 16,
114 -- abits => 10
115 -- )
116 --port map(
117 -- rstn => rstn,
118 -- ReUse => '0',
119 -- rclk => clk,
120 -- ren => FIFO_REN,
121 -- rdata => FIFO_out(I),
122 -- empty => FIFO_EMPTY_net(I),
123 -- raddr => open,
124 -- wclk => clk,
125 -- wen => FIFO_WEN(I),
126 -- wdata => DATA_reg,
127 -- full => FIFO_FULL_net(I),
128 -- waddr => open
129 --);
130 --END GENERATE;
131
246 132
247 133 REN_debug <= FIFO_REN;
248 134
@@ -250,30 +136,42 process(clk,rstn)
250 136 begin
251 137 if rstn = '0' then
252 138 DATA_reg <= (others => '0');
253 FIFO_WEN <= (others => '0');
139 FIFO_WEN <= (others => '1');
140 clk_TRIGER <= clk_TRIGER_MAX;
141 clk_TRIGER_load <= '0';
254 142 elsif clk'event and clk = '1' then
255 143 if WEN = '0' then
256 144 DATA_reg <= DATA;
257 case address is
258 when "000"=>
145 case address(3 downto 0) is
146 when "0000"=>
259 147 FIFO_WEN <= "11111110";
260 when "001"=>
148 when "0001"=>
261 149 FIFO_WEN <= "11111101";
262 when "010"=>
150 when "0010"=>
263 151 FIFO_WEN <= "11111011";
264 when "011"=>
152 when "0011"=>
265 153 FIFO_WEN <= "11110111";
266 when "100"=>
154 when "0100"=>
267 155 FIFO_WEN <= "11101111";
268 when "101"=>
156 when "0101"=>
269 157 FIFO_WEN <= "11011111";
270 when "110"=>
158 when "0110"=>
271 159 FIFO_WEN <= "10111111";
272 when "111"=>
160 when "0111"=>
273 161 FIFO_WEN <= "01111111";
274 162 when others =>
275 163 FIFO_WEN <= "11111111";
276 164 end case;
165 else
166 FIFO_WEN <= "11111111";
167 end if;
168 if WEN = '0' then
169 if address(3 downto 0) = "1000" then
170 clk_TRIGER <= to_integer(unsigned(DATA));
171 clk_TRIGER_load <= '1';
172 end if;
173 else
174 clk_TRIGER_load <= '0';
277 175 end if;
278 176 end if;
279 177 end process;
@@ -292,9 +190,9 begin
292 190 FIFO_REN <= '1';
293 191 smpclk_reg <= '0';
294 192 elsif clk'event and clk = '1' then
295 smpclk_reg <= smpclk;
296 if smpclk = '1' and smpclk_reg = '0' then
297 FIFO_REN <= '0';
193 smpclk_reg <= smpclk;
194 if smpclk = '1' and smpclk_reg = '0' and FIFO_EMPTY_net = X"00" then
195 FIFO_REN <= '0' ;
298 196 else
299 197 FIFO_REN <= '1';
300 198 end if;
@@ -316,14 +214,29 DAC0 : DAC8581
316 214
317 215
318 216
319 smpclk0: Clk_divider
320 GENERIC map(OSC_freqHz => 150000000,
321 TargetFreq_Hz => 256000)
322 PORT map(
323 clk => clk,
324 reset => rstn,
325 clk_divided => smpclk
326 );
217 --smpclk0: Clk_divider
218 -- GENERIC map(OSC_freqHz => 150000000,
219 -- TargetFreq_Hz => 256000)
220 -- PORT map(
221 -- clk => clk,
222 -- reset => rstn,
223 -- clk_divided => smpclk
224 -- );
225
226 process(rstn,clk)
227 begin
228 if rstn = '0' then
229 cpt1 <= 0;
230 smpclk <= '0';
231 elsif clk'event and clk = '1' then
232 if cpt1 = clk_TRIGER or clk_TRIGER_load = '1' then
233 smpclk <= not smpclk;
234 cpt1 <= 0;
235 else
236 cpt1 <= cpt1 + 1;
237 end if;
238 end if;
239 end process;
327 240
328 241
329 242 end Behavioral;
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@@ -71,7 +71,7 fifos : for i in 0 to fifoCount-1 genera
71 71 Mem_use => Mem_use,
72 72 Enable_ReUse => '0',
73 73 DataSz => DataSz,
74 abits => abits
74 AddrSz => abits
75 75 )
76 76 port map(
77 77 rstn => rstn,
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