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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 --TAG1 : IN STD_ULOGIC; -- DSU rx data
56 --TAG1 : IN STD_ULOGIC; -- DSU rx data
57 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- DAC --------------------------------------------------------------------
85 -- DAC --------------------------------------------------------------------
86 DAC_SDO : OUT STD_LOGIC;
86 DAC_SDO : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
87 DAC_SCK : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
88 DAC_SYNC : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
89 DAC_CAL_EN : OUT STD_LOGIC;
90 -- HK ---------------------------------------------------------------------
90 -- HK ---------------------------------------------------------------------
91 HK_smpclk : OUT STD_LOGIC;
91 HK_smpclk : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ---------------------------------------------------------------------------
94 ---------------------------------------------------------------------------
95 TAG8 : OUT STD_LOGIC;
95 TAG8 : OUT STD_LOGIC;
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 );
97 );
98
98
99 END LFR_em;
99 END LFR_em;
100
100
101
101
102 ARCHITECTURE beh OF LFR_em IS
102 ARCHITECTURE beh OF LFR_em IS
103
103
104 --==========================================================================
104 --==========================================================================
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
106 -- when enabled, chip enable polarity should be reversed and bank size also
106 -- when enabled, chip enable polarity should be reversed and bank size also
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
109 --==========================================================================
109 --==========================================================================
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
111 --==========================================================================
111 --==========================================================================
112
112
113 SIGNAL clk_50_s : STD_LOGIC := '0';
113 SIGNAL clk_50_s : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
114 SIGNAL clk_25 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
115 SIGNAL clk_24 : STD_LOGIC := '0';
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119
119
120 -- CONSTANTS
120 -- CONSTANTS
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
121 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125
125
126 SIGNAL apbi_ext : apb_slv_in_type;
126 SIGNAL apbi_ext : apb_slv_in_type;
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132
132
133 -- Spacewire signals
133 -- Spacewire signals
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
137 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
138 SIGNAL spw_rxclkn : STD_ULOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
139 SIGNAL spw_clk : STD_LOGIC;
140 SIGNAL swni : grspw_in_type;
140 SIGNAL swni : grspw_in_type;
141 SIGNAL swno : grspw_out_type;
141 SIGNAL swno : grspw_out_type;
142
142
143 --GPIO
143 --GPIO
144 SIGNAL gpioi : gpio_in_type;
144 SIGNAL gpioi : gpio_in_type;
145 SIGNAL gpioo : gpio_out_type;
145 SIGNAL gpioo : gpio_out_type;
146
146
147 -- AD Converter ADS7886
147 -- AD Converter ADS7886
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
148 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
149 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 SIGNAL sample_val : STD_LOGIC;
150 SIGNAL sample_val : STD_LOGIC;
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
157 SIGNAL rstn_25 : STD_LOGIC;
157 SIGNAL rstn_25 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
158 SIGNAL rstn_24 : STD_LOGIC;
159
159
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
160 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
161 SIGNAL LFR_rstn : STD_LOGIC;
162
162
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
163 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 ----------------------------------------------------------------------------
164 ----------------------------------------------------------------------------
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL nSRAM_READY : STD_LOGIC;
166 SIGNAL nSRAM_READY : STD_LOGIC;
167
167
168 BEGIN -- beh
168 BEGIN -- beh
169
169
170 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
171 -- CLK
171 -- CLK
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
173 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
174 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175
175
176 PROCESS(clk100MHz)
176 PROCESS(clk100MHz)
177 BEGIN
177 BEGIN
178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
178 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
179 clk_50_s <= NOT clk_50_s;
179 clk_50_s <= NOT clk_50_s;
180 END IF;
180 END IF;
181 END PROCESS;
181 END PROCESS;
182
182
183 PROCESS(clk_50_s)
183 PROCESS(clk_50_s)
184 BEGIN
184 BEGIN
185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
185 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
186 clk_25 <= NOT clk_25;
186 clk_25 <= NOT clk_25;
187 END IF;
187 END IF;
188 END PROCESS;
188 END PROCESS;
189
189
190 PROCESS(clk49_152MHz)
190 PROCESS(clk49_152MHz)
191 BEGIN
191 BEGIN
192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
193 clk_24 <= NOT clk_24;
193 clk_24 <= NOT clk_24;
194 END IF;
194 END IF;
195 END PROCESS;
195 END PROCESS;
196
196
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198
198
199 PROCESS (clk_25, rstn_25)
199 PROCESS (clk_25, rstn_25)
200 BEGIN -- PROCESS
200 BEGIN -- PROCESS
201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
201 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
202 led(0) <= '0';
202 led(0) <= '0';
203 led(1) <= '0';
203 led(1) <= '0';
204 led(2) <= '0';
204 led(2) <= '0';
205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
205 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
206 led(0) <= '0';
206 led(0) <= '0';
207 led(1) <= '1';
207 led(1) <= '1';
208 led(2) <= '1';
208 led(2) <= '1';
209 END IF;
209 END IF;
210 END PROCESS;
210 END PROCESS;
211
211
212 --
212 --
213 leon3_soc_1 : leon3_soc
213 leon3_soc_1 : leon3_soc
214 GENERIC MAP (
214 GENERIC MAP (
215 fabtech => apa3e,
215 fabtech => apa3e,
216 memtech => apa3e,
216 memtech => apa3e,
217 padtech => inferred,
217 padtech => inferred,
218 clktech => inferred,
218 clktech => inferred,
219 disas => 0,
219 disas => 0,
220 dbguart => 0,
220 dbguart => 0,
221 pclow => 2,
221 pclow => 2,
222 clk_freq => 25000,
222 clk_freq => 25000,
223 IS_RADHARD => 0,
223 IS_RADHARD => 0,
224 NB_CPU => 1,
224 NB_CPU => 1,
225 ENABLE_FPU => 1,
225 ENABLE_FPU => 1,
226 FPU_NETLIST => 0,
226 FPU_NETLIST => 0,
227 ENABLE_DSU => 1,
227 ENABLE_DSU => 1,
228 ENABLE_AHB_UART => 0,
228 ENABLE_AHB_UART => 0,
229 ENABLE_APB_UART => 1,
229 ENABLE_APB_UART => 1,
230 ENABLE_IRQMP => 1,
230 ENABLE_IRQMP => 1,
231 ENABLE_GPT => 1,
231 ENABLE_GPT => 1,
232 NB_AHB_MASTER => NB_AHB_MASTER,
232 NB_AHB_MASTER => NB_AHB_MASTER,
233 NB_AHB_SLAVE => NB_AHB_SLAVE,
233 NB_AHB_SLAVE => NB_AHB_SLAVE,
234 NB_APB_SLAVE => NB_APB_SLAVE,
234 NB_APB_SLAVE => NB_APB_SLAVE,
235 ADDRESS_SIZE => 20,
235 ADDRESS_SIZE => 20,
236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
236 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
237 BYPASS_EDAC_MEMCTRLR => '0',
237 BYPASS_EDAC_MEMCTRLR => '0',
238 SRBANKSZ => 9,
238 SRBANKSZ => 9,
239 SLOW_TIMING_EMULATION => 0
239 SLOW_TIMING_EMULATION => 0
240 )
240 )
241 PORT MAP (
241 PORT MAP (
242 clk => clk_25,
242 clk => clk_25,
243 reset => rstn_25,
243 reset => rstn_25,
244 errorn => OPEN,
244 errorn => OPEN,
245
245
246 ahbrxd => OPEN,
246 ahbrxd => OPEN,
247 ahbtxd => OPEN,
247 ahbtxd => OPEN,
248 urxd1 => TAG2,
248 urxd1 => TAG2,
249 utxd1 => TAG4,
249 utxd1 => TAG4,
250
250
251 address => address,
251 address => address,
252 data => data,
252 data => data,
253 nSRAM_BE0 => nSRAM_BE0,
253 nSRAM_BE0 => nSRAM_BE0,
254 nSRAM_BE1 => nSRAM_BE1,
254 nSRAM_BE1 => nSRAM_BE1,
255 nSRAM_BE2 => nSRAM_BE2,
255 nSRAM_BE2 => nSRAM_BE2,
256 nSRAM_BE3 => nSRAM_BE3,
256 nSRAM_BE3 => nSRAM_BE3,
257 nSRAM_WE => nSRAM_WE,
257 nSRAM_WE => nSRAM_WE,
258 nSRAM_CE => nSRAM_CE_s,
258 nSRAM_CE => nSRAM_CE_s,
259 nSRAM_OE => nSRAM_OE,
259 nSRAM_OE => nSRAM_OE,
260 nSRAM_READY => nSRAM_READY,
260 nSRAM_READY => nSRAM_READY,
261 SRAM_MBE => OPEN,
261 SRAM_MBE => OPEN,
262
262
263 apbi_ext => apbi_ext,
263 apbi_ext => apbi_ext,
264 apbo_ext => apbo_ext,
264 apbo_ext => apbo_ext,
265 ahbi_s_ext => ahbi_s_ext,
265 ahbi_s_ext => ahbi_s_ext,
266 ahbo_s_ext => ahbo_s_ext,
266 ahbo_s_ext => ahbo_s_ext,
267 ahbi_m_ext => ahbi_m_ext,
267 ahbi_m_ext => ahbi_m_ext,
268 ahbo_m_ext => ahbo_m_ext);
268 ahbo_m_ext => ahbo_m_ext);
269
269
270 PROCESS (clk_25, rstn_25)
270 PROCESS (clk_25, rstn_25)
271 BEGIN -- PROCESS
271 BEGIN -- PROCESS
272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
273 nSRAM_READY <= '1';
273 nSRAM_READY <= '1';
274 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
274 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
275 nSRAM_READY <= '1';
275 nSRAM_READY <= '1';
276 END IF;
276 END IF;
277 END PROCESS;
277 END PROCESS;
278
278
279 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
279 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
280 nSRAM_CE <= not nSRAM_CE_s(0);
280 nSRAM_CE <= not nSRAM_CE_s(0);
281 END GENERATE;
281 END GENERATE;
282
282
283 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
283 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
284 nSRAM_CE <= nSRAM_CE_s(0);
284 nSRAM_CE <= nSRAM_CE_s(0);
285 END GENERATE;
285 END GENERATE;
286
286
287 -------------------------------------------------------------------------------
287 -------------------------------------------------------------------------------
288 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
288 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
289 -------------------------------------------------------------------------------
289 -------------------------------------------------------------------------------
290 apb_lfr_management_1 : apb_lfr_management
290 apb_lfr_management_1 : apb_lfr_management
291 GENERIC MAP (
291 GENERIC MAP (
292 tech => apa3e,
292 tech => apa3e,
293 pindex => 6,
293 pindex => 6,
294 paddr => 6,
294 paddr => 6,
295 pmask => 16#fff#,
295 pmask => 16#fff#,
296 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
296 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
297 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
297 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
298 PORT MAP (
298 PORT MAP (
299 clk25MHz => clk_25,
299 clk25MHz => clk_25,
300 resetn_25MHz => rstn_25, -- TODO
300 resetn_25MHz => rstn_25, -- TODO
301 -- clk24_576MHz => clk_24, -- 49.152MHz/2
301 -- clk24_576MHz => clk_24, -- 49.152MHz/2
302 -- resetn_24_576MHz => rstn_24, -- TODO
302 -- resetn_24_576MHz => rstn_24, -- TODO
303
303
304 grspw_tick => swno.tickout,
304 grspw_tick => swno.tickout,
305 apbi => apbi_ext,
305 apbi => apbi_ext,
306 apbo => apbo_ext(6),
306 apbo => apbo_ext(6),
307
307
308 HK_sample => sample_s(8),
308 HK_sample => sample_s(8),
309 HK_val => sample_val,
309 HK_val => sample_val,
310 HK_sel => HK_SEL,
310 HK_sel => HK_SEL,
311
311
312 DAC_SDO => DAC_SDO,
312 DAC_SDO => DAC_SDO,
313 DAC_SCK => DAC_SCK,
313 DAC_SCK => DAC_SCK,
314 DAC_SYNC => DAC_SYNC,
314 DAC_SYNC => DAC_SYNC,
315 DAC_CAL_EN => DAC_CAL_EN,
315 DAC_CAL_EN => DAC_CAL_EN,
316
316
317 coarse_time => coarse_time,
317 coarse_time => coarse_time,
318 fine_time => fine_time,
318 fine_time => fine_time,
319 LFR_soft_rstn => LFR_soft_rstn
319 LFR_soft_rstn => LFR_soft_rstn
320 );
320 );
321
321
322 -----------------------------------------------------------------------
322 -----------------------------------------------------------------------
323 --- SpaceWire --------------------------------------------------------
323 --- SpaceWire --------------------------------------------------------
324 -----------------------------------------------------------------------
324 -----------------------------------------------------------------------
325
325
326 -- SPW_EN <= '1';
326 -- SPW_EN <= '1';
327
327
328 spw_clk <= clk_50_s;
328 spw_clk <= clk_50_s;
329 spw_rxtxclk <= spw_clk;
329 spw_rxtxclk <= spw_clk;
330 spw_rxclkn <= NOT spw_rxtxclk;
330 spw_rxclkn <= NOT spw_rxtxclk;
331
331
332 -- PADS for SPW1
332 -- PADS for SPW1
333 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
333 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
334 PORT MAP (spw1_din, dtmp(0));
334 PORT MAP (spw1_din, dtmp(0));
335 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
335 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
336 PORT MAP (spw1_sin, stmp(0));
336 PORT MAP (spw1_sin, stmp(0));
337 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
337 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
338 PORT MAP (spw1_dout, swno.d(0));
338 PORT MAP (spw1_dout, swno.d(0));
339 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
339 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (spw1_sout, swno.s(0));
340 PORT MAP (spw1_sout, swno.s(0));
341 -- PADS FOR SPW2
341 -- PADS FOR SPW2
342 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
342 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
343 PORT MAP (spw2_din, dtmp(1));
343 PORT MAP (spw2_din, dtmp(1));
344 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
344 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 PORT MAP (spw2_sin, stmp(1));
345 PORT MAP (spw2_sin, stmp(1));
346 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
346 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
347 PORT MAP (spw2_dout, swno.d(1));
347 PORT MAP (spw2_dout, swno.d(1));
348 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
348 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
349 PORT MAP (spw2_sout, swno.s(1));
349 PORT MAP (spw2_sout, swno.s(1));
350
350
351 -- GRSPW PHY
351 -- GRSPW PHY
352 --spw1_input: if CFG_SPW_GRSPW = 1 generate
352 --spw1_input: if CFG_SPW_GRSPW = 1 generate
353 spw_inputloop : FOR j IN 0 TO 1 GENERATE
353 spw_inputloop : FOR j IN 0 TO 1 GENERATE
354 spw_phy0 : grspw_phy
354 spw_phy0 : grspw_phy
355 GENERIC MAP(
355 GENERIC MAP(
356 tech => apa3e,
356 tech => apa3e,
357 rxclkbuftype => 1,
357 rxclkbuftype => 1,
358 scantest => 0)
358 scantest => 0)
359 PORT MAP(
359 PORT MAP(
360 rxrst => swno.rxrst,
360 rxrst => swno.rxrst,
361 di => dtmp(j),
361 di => dtmp(j),
362 si => stmp(j),
362 si => stmp(j),
363 rxclko => spw_rxclk(j),
363 rxclko => spw_rxclk(j),
364 do => swni.d(j),
364 do => swni.d(j),
365 ndo => swni.nd(j*5+4 DOWNTO j*5),
365 ndo => swni.nd(j*5+4 DOWNTO j*5),
366 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
366 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
367 END GENERATE spw_inputloop;
367 END GENERATE spw_inputloop;
368
368
369 -- SPW core
369 -- SPW core
370 sw0 : grspwm GENERIC MAP(
370 sw0 : grspwm GENERIC MAP(
371 tech => apa3e,
371 tech => apa3e,
372 hindex => 1,
372 hindex => 1,
373 pindex => 5,
373 pindex => 5,
374 paddr => 5,
374 paddr => 5,
375 pirq => 11,
375 pirq => 11,
376 sysfreq => 25000, -- CPU_FREQ
376 sysfreq => 25000, -- CPU_FREQ
377 rmap => 1,
377 rmap => 1,
378 rmapcrc => 1,
378 rmapcrc => 1,
379 fifosize1 => 16,
379 fifosize1 => 16,
380 fifosize2 => 16,
380 fifosize2 => 16,
381 rxclkbuftype => 1,
381 rxclkbuftype => 1,
382 rxunaligned => 0,
382 rxunaligned => 0,
383 rmapbufs => 4,
383 rmapbufs => 4,
384 ft => 0,
384 ft => 0,
385 netlist => 0,
385 netlist => 0,
386 ports => 2,
386 ports => 2,
387 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
387 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
388 memtech => apa3e,
388 memtech => apa3e,
389 destkey => 2,
389 destkey => 2,
390 spwcore => 1
390 spwcore => 1
391 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
391 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
392 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
392 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
393 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
393 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
394 )
394 )
395 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
395 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
396 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
396 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
397 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
397 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
398 swni, swno);
398 swni, swno);
399
399
400 swni.tickin <= '0';
400 swni.tickin <= '0';
401 swni.rmapen <= '1';
401 swni.rmapen <= '1';
402 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
402 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
403 swni.tickinraw <= '0';
403 swni.tickinraw <= '0';
404 swni.timein <= (OTHERS => '0');
404 swni.timein <= (OTHERS => '0');
405 swni.dcrstval <= (OTHERS => '0');
405 swni.dcrstval <= (OTHERS => '0');
406 swni.timerrstval <= (OTHERS => '0');
406 swni.timerrstval <= (OTHERS => '0');
407
407
408 -------------------------------------------------------------------------------
408 -------------------------------------------------------------------------------
409 -- LFR ------------------------------------------------------------------------
409 -- LFR ------------------------------------------------------------------------
410 -------------------------------------------------------------------------------
410 -------------------------------------------------------------------------------
411 LFR_rstn <= LFR_soft_rstn AND rstn_25;
411 LFR_rstn <= LFR_soft_rstn AND rstn_25;
412
412
413 lpp_lfr_1 : lpp_lfr
413 lpp_lfr_1 : lpp_lfr
414 GENERIC MAP (
414 GENERIC MAP (
415 Mem_use => use_RAM,
415 Mem_use => use_RAM,
416 tech => inferred,
416 tech => inferred,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 --nb_word_by_buffer_size => 30,
418 --nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"010158", -- aa.bb.cc version
428 top_lfr_version => X"010159", -- aa.bb.cc version
429 -- AA : BOARD NUMBER
429 -- AA : BOARD NUMBER
430 -- 0 => MINI_LFR
430 -- 0 => MINI_LFR
431 -- 1 => EM
431 -- 1 => EM
432 DEBUG_FORCE_DATA_DMA => 0,
432 DEBUG_FORCE_DATA_DMA => 0,
433 RTL_DESIGN_LIGHT => 1,
433 RTL_DESIGN_LIGHT => 1,
434 WINDOWS_HAANNING_PARAM_SIZE => 10)
434 WINDOWS_HAANNING_PARAM_SIZE => 10)
435 PORT MAP (
435 PORT MAP (
436 clk => clk_25,
436 clk => clk_25,
437 rstn => LFR_rstn,
437 rstn => LFR_rstn,
438 sample_B => sample_s(2 DOWNTO 0),
438 sample_B => sample_s(2 DOWNTO 0),
439 sample_E => sample_s(7 DOWNTO 3),
439 sample_E => sample_s(7 DOWNTO 3),
440 sample_val => sample_val,
440 sample_val => sample_val,
441 apbi => apbi_ext,
441 apbi => apbi_ext,
442 apbo => apbo_ext(15),
442 apbo => apbo_ext(15),
443 ahbi => ahbi_m_ext,
443 ahbi => ahbi_m_ext,
444 ahbo => ahbo_m_ext(2),
444 ahbo => ahbo_m_ext(2),
445 coarse_time => coarse_time,
445 coarse_time => coarse_time,
446 fine_time => fine_time,
446 fine_time => fine_time,
447 data_shaping_BW => bias_fail_sw,
447 data_shaping_BW => bias_fail_sw,
448 debug_vector => OPEN,
448 debug_vector => OPEN,
449 debug_vector_ms => OPEN); --,
449 debug_vector_ms => OPEN); --,
450 --observation_vector_0 => OPEN,
450 --observation_vector_0 => OPEN,
451 --observation_vector_1 => OPEN,
451 --observation_vector_1 => OPEN,
452 --observation_reg => observation_reg);
452 --observation_reg => observation_reg);
453
453
454
454
455 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
455 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
456 sample_s(I) <= sample(I) & '0' & '0';
456 sample_s(I) <= sample(I) & '0' & '0';
457 END GENERATE all_sample;
457 END GENERATE all_sample;
458 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
458 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
459
459
460 -----------------------------------------------------------------------------
460 -----------------------------------------------------------------------------
461 --
461 --
462 -----------------------------------------------------------------------------
462 -----------------------------------------------------------------------------
463 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
463 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
464 GENERIC MAP (
464 GENERIC MAP (
465 ChanelCount => 9,
465 ChanelCount => 9,
466 ncycle_cnv_high => 12,
466 ncycle_cnv_high => 12,
467 ncycle_cnv => 25,
467 ncycle_cnv => 25,
468 FILTER_ENABLED => 16#FF#)
468 FILTER_ENABLED => 16#FF#)
469 PORT MAP (
469 PORT MAP (
470 cnv_clk => clk_24,
470 cnv_clk => clk_24,
471 cnv_rstn => rstn_24,
471 cnv_rstn => rstn_24,
472 cnv => ADC_smpclk_s,
472 cnv => ADC_smpclk_s,
473 clk => clk_25,
473 clk => clk_25,
474 rstn => rstn_25,
474 rstn => rstn_25,
475 ADC_data => ADC_data,
475 ADC_data => ADC_data,
476 ADC_nOE => ADC_OEB_bar_CH_s,
476 ADC_nOE => ADC_OEB_bar_CH_s,
477 sample => sample,
477 sample => sample,
478 sample_val => sample_val);
478 sample_val => sample_val);
479
479
480 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
480 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
481
481
482 ADC_smpclk <= ADC_smpclk_s;
482 ADC_smpclk <= ADC_smpclk_s;
483 HK_smpclk <= ADC_smpclk_s;
483 HK_smpclk <= ADC_smpclk_s;
484
484
485 TAG8 <= ADC_smpclk_s;
485 TAG8 <= ADC_smpclk_s;
486
486
487 -----------------------------------------------------------------------------
487 -----------------------------------------------------------------------------
488 -- HK
488 -- HK
489 -----------------------------------------------------------------------------
489 -----------------------------------------------------------------------------
490 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
490 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
491
491
492 END beh;
492 END beh;
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@@ -1,108 +1,111
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 use ieee.math_real.all;
26 use ieee.math_real.all;
27 USE ieee.numeric_std.ALL;
27 USE ieee.numeric_std.ALL;
28
28
29 LIBRARY lpp;
29 LIBRARY lpp;
30 USE lpp.general_purpose.ALL;
30 USE lpp.general_purpose.ALL;
31 USE lpp.window_function_pkg.ALL;
31 USE lpp.window_function_pkg.ALL;
32
32
33 ENTITY WF_processing IS
33 ENTITY WF_processing IS
34 GENERIC (
34 GENERIC (
35 SIZE_DATA : INTEGER := 16;
35 SIZE_DATA : INTEGER := 16;
36 SIZE_PARAM : INTEGER := 10;
36 SIZE_PARAM : INTEGER := 10;
37 NB_POINT_BY_WINDOW : INTEGER := 256
37 NB_POINT_BY_WINDOW : INTEGER := 256
38 );
38 );
39
39
40 PORT (
40 PORT (
41 clk : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43 --ctrl
43 --ctrl
44 restart_window : IN STD_LOGIC;
44 restart_window : IN STD_LOGIC;
45 --data_in
45 --data_in
46 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
46 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
47 data_in_valid : IN STD_LOGIC;
47 data_in_valid : IN STD_LOGIC;
48 --data_out
48 --data_out
49 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
49 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
50 data_out_valid : OUT STD_LOGIC;
50 data_out_valid : OUT STD_LOGIC;
51
51
52 --window parameter interface
52 --window parameter interface
53 param_in : IN STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
53 param_in : IN STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
54 param_index : OUT INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1
54 param_index : OUT INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1;
55 PARAM_ALL_POSITIVE : IN STD_LOGIC
55 );
56 );
56
57
57 END WF_processing;
58 END WF_processing;
58
59
59 ARCHITECTURE beh OF WF_processing IS
60 ARCHITECTURE beh OF WF_processing IS
60 CONSTANT NB_BITS_COUNTER : INTEGER := INTEGER(ceil(log2(REAL(NB_POINT_BY_WINDOW))));
61 CONSTANT NB_BITS_COUNTER : INTEGER := INTEGER(ceil(log2(REAL(NB_POINT_BY_WINDOW))));
61
62
62 SIGNAL data_x_param : STD_LOGIC_VECTOR(SIZE_DATA + SIZE_PARAM - 1 DOWNTO 0);
63 SIGNAL data_x_param : STD_LOGIC_VECTOR(SIZE_DATA + SIZE_PARAM - 1 DOWNTO 0);
63 SIGNAL windows_counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
64 SIGNAL windows_counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
64
65
65 BEGIN
66 BEGIN
66
67
67 WINDOWS_counter: general_counter
68 WINDOWS_counter: general_counter
68 GENERIC MAP (
69 GENERIC MAP (
69 CYCLIC => '1',
70 CYCLIC => '1',
70 NB_BITS_COUNTER => NB_BITS_COUNTER,
71 NB_BITS_COUNTER => NB_BITS_COUNTER,
71 RST_VALUE => 0)
72 RST_VALUE => 0)
72 PORT MAP (
73 PORT MAP (
73 clk => clk,
74 clk => clk,
74 rstn => rstn,
75 rstn => rstn,
75 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_POINT_BY_WINDOW-1, NB_BITS_COUNTER)),
76 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_POINT_BY_WINDOW-1, NB_BITS_COUNTER)),
76 set => restart_window,
77 set => restart_window,
77 set_value => STD_LOGIC_VECTOR(to_unsigned(0, NB_BITS_COUNTER)),
78 set_value => STD_LOGIC_VECTOR(to_unsigned(0, NB_BITS_COUNTER)),
78 add1 => data_in_valid,
79 add1 => data_in_valid,
79 counter => windows_counter_s);
80 counter => windows_counter_s);
80
81
81 param_index <= to_integer(UNSIGNED(windows_counter_s));
82 param_index <= to_integer(UNSIGNED(windows_counter_s));
82
83
83 WINDOWS_Multiplier : Multiplier
84 WINDOWS_Multiplier : Multiplier
84 GENERIC MAP (
85 GENERIC MAP (
85 Input_SZ_A => SIZE_DATA,
86 Input_SZ_A => SIZE_DATA,
86 Input_SZ_B => SIZE_PARAM)
87 Input_SZ_B => SIZE_PARAM)
87 PORT MAP (
88 PORT MAP (
88 clk => clk,
89 clk => clk,
89 reset => rstn,
90 reset => rstn,
90
91
91 mult => data_in_valid,
92 mult => data_in_valid,
92 OP1 => data_in,
93 OP1 => data_in,
93 OP2 => param_in,
94 OP2 => param_in,
94
95
95 RES => data_x_param);
96 RES => data_x_param);
96
97
97 data_out <= data_x_param(SIZE_DATA + SIZE_PARAM-1 DOWNTO SIZE_PARAM);
98 data_out <= data_x_param(SIZE_DATA + SIZE_PARAM-2 DOWNTO SIZE_PARAM-1) WHEN PARAM_ALL_POSITIVE = '1' ELSE
99 data_x_param(SIZE_DATA + SIZE_PARAM-1 DOWNTO SIZE_PARAM);
100
98
101
99 WINDOWS_REG: SYNC_FF
102 WINDOWS_REG: SYNC_FF
100 GENERIC MAP (
103 GENERIC MAP (
101 NB_FF_OF_SYNC => 1)
104 NB_FF_OF_SYNC => 1)
102 PORT MAP (
105 PORT MAP (
103 clk => clk,
106 clk => clk,
104 rstn => rstn,
107 rstn => rstn,
105 A => data_in_valid,
108 A => data_in_valid,
106 A_sync => data_out_valid);
109 A_sync => data_out_valid);
107
110
108 END beh;
111 END beh; No newline at end of file
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@@ -1,96 +1,99
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27
27
28 LIBRARY lpp;
28 LIBRARY lpp;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.window_function_pkg.ALL;
30 USE lpp.window_function_pkg.ALL;
31
31
32 ENTITY WF_rom IS
32 ENTITY WF_rom IS
33 GENERIC (
33 GENERIC (
34 SIZE_PARAM : INTEGER := 10;
34 SIZE_PARAM : INTEGER := 10;
35 NB_POINT_BY_WINDOW : INTEGER := 256
35 NB_POINT_BY_WINDOW : INTEGER := 256
36 );
36 );
37 PORT (
37 PORT (
38 data : OUT STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
38 data : OUT STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
39 index : IN INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1
39 index : IN INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1 ;
40 PARAM_ALL_POSITIVE : OUT STD_LOGIC
40 );
41 );
41 END WF_rom;
42 END WF_rom;
42
43
43 ARCHITECTURE beh OF WF_rom IS
44 ARCHITECTURE beh OF WF_rom IS
44
45
45 CONSTANT SIZE_ARRAY : INTEGER := 256; --
46 CONSTANT SIZE_ARRAY : INTEGER := 256; --
46 CONSTANT SIZE_ARRAY_PARAM : INTEGER := 16; -- bits
47 CONSTANT SIZE_ARRAY_PARAM : INTEGER := 16; -- bits
47 TYPE array_std_logic_vector IS ARRAY (SIZE_ARRAY-1 DOWNTO 0) OF STD_LOGIC_VECTOR(SIZE_ARRAY_PARAM-1 DOWNTO 0);
48 TYPE array_std_logic_vector IS ARRAY (SIZE_ARRAY-1 DOWNTO 0) OF STD_LOGIC_VECTOR(SIZE_ARRAY_PARAM-1 DOWNTO 0);
48 CONSTANT ROM_array : array_std_logic_vector := (
49 CONSTANT ROM_array : array_std_logic_vector := (
49 X"0000",X"0004",X"0013",X"002C",X"004F",X"007C",X"00B2",X"00F3",
50 X"0000",X"0004",X"0013",X"002C",X"004F",X"007C",X"00B2",X"00F3",
50 X"013D",X"0191",X"01EE",X"0256",X"02C6",X"0341",X"03C5",X"0452",
51 X"013D",X"0191",X"01EE",X"0256",X"02C6",X"0341",X"03C5",X"0452",
51 X"04E8",X"0588",X"0631",X"06E2",X"079D",X"0860",X"092C",X"0A01",
52 X"04E8",X"0588",X"0631",X"06E2",X"079D",X"0860",X"092C",X"0A01",
52 X"0ADE",X"0BC3",X"0CB0",X"0DA5",X"0EA3",X"0FA7",X"10B4",X"11C7",
53 X"0ADE",X"0BC3",X"0CB0",X"0DA5",X"0EA3",X"0FA7",X"10B4",X"11C7",
53 X"12E2",X"1404",X"152C",X"165C",X"1792",X"18CE",X"1A10",X"1B58",
54 X"12E2",X"1404",X"152C",X"165C",X"1792",X"18CE",X"1A10",X"1B58",
54 X"1CA6",X"1DF9",X"1F51",X"20AF",X"2211",X"2379",X"24E4",X"2654",
55 X"1CA6",X"1DF9",X"1F51",X"20AF",X"2211",X"2379",X"24E4",X"2654",
55 X"27C8",X"293F",X"2ABA",X"2C39",X"2DBA",X"2F3E",X"30C5",X"324E",
56 X"27C8",X"293F",X"2ABA",X"2C39",X"2DBA",X"2F3E",X"30C5",X"324E",
56 X"33DA",X"3567",X"36F6",X"3886",X"3A18",X"3BAA",X"3D3D",X"3ED1",
57 X"33DA",X"3567",X"36F6",X"3886",X"3A18",X"3BAA",X"3D3D",X"3ED1",
57 X"4064",X"41F8",X"438B",X"451E",X"46B0",X"4841",X"49D1",X"4B5F",
58 X"4064",X"41F8",X"438B",X"451E",X"46B0",X"4841",X"49D1",X"4B5F",
58 X"4CEB",X"4E75",X"4FFE",X"5183",X"5306",X"5486",X"5603",X"577C",
59 X"4CEB",X"4E75",X"4FFE",X"5183",X"5306",X"5486",X"5603",X"577C",
59 X"58F2",X"5A64",X"5BD1",X"5D3B",X"5E9F",X"5FFF",X"615B",X"62B1",
60 X"58F2",X"5A64",X"5BD1",X"5D3B",X"5E9F",X"5FFF",X"615B",X"62B1",
60 X"6401",X"654C",X"6691",X"67D0",X"6909",X"6A3C",X"6B68",X"6C8D",
61 X"6401",X"654C",X"6691",X"67D0",X"6909",X"6A3C",X"6B68",X"6C8D",
61 X"6DAB",X"6EC3",X"6FD2",X"70DB",X"71DC",X"72D5",X"73C6",X"74B0",
62 X"6DAB",X"6EC3",X"6FD2",X"70DB",X"71DC",X"72D5",X"73C6",X"74B0",
62 X"7591",X"7669",X"773A",X"7801",X"78C0",X"7977",X"7A24",X"7AC8",
63 X"7591",X"7669",X"773A",X"7801",X"78C0",X"7977",X"7A24",X"7AC8",
63 X"7B63",X"7BF5",X"7C7D",X"7CFD",X"7D72",X"7DDE",X"7E41",X"7E99",
64 X"7B63",X"7BF5",X"7C7D",X"7CFD",X"7D72",X"7DDE",X"7E41",X"7E99",
64 X"7EE9",X"7F2E",X"7F69",X"7F9B",X"7FC3",X"7FE0",X"7FF4",X"7FFE",
65 X"7EE9",X"7F2E",X"7F69",X"7F9B",X"7FC3",X"7FE0",X"7FF4",X"7FFE",
65 X"7FFE",X"7FF4",X"7FE0",X"7FC3",X"7F9B",X"7F69",X"7F2E",X"7EE9",
66 X"7FFE",X"7FF4",X"7FE0",X"7FC3",X"7F9B",X"7F69",X"7F2E",X"7EE9",
66 X"7E99",X"7E41",X"7DDE",X"7D72",X"7CFD",X"7C7D",X"7BF5",X"7B63",
67 X"7E99",X"7E41",X"7DDE",X"7D72",X"7CFD",X"7C7D",X"7BF5",X"7B63",
67 X"7AC8",X"7A24",X"7977",X"78C0",X"7801",X"773A",X"7669",X"7591",
68 X"7AC8",X"7A24",X"7977",X"78C0",X"7801",X"773A",X"7669",X"7591",
68 X"74B0",X"73C6",X"72D5",X"71DC",X"70DB",X"6FD2",X"6EC3",X"6DAB",
69 X"74B0",X"73C6",X"72D5",X"71DC",X"70DB",X"6FD2",X"6EC3",X"6DAB",
69 X"6C8D",X"6B68",X"6A3C",X"6909",X"67D0",X"6691",X"654C",X"6401",
70 X"6C8D",X"6B68",X"6A3C",X"6909",X"67D0",X"6691",X"654C",X"6401",
70 X"62B1",X"615B",X"6000",X"5E9F",X"5D3B",X"5BD1",X"5A64",X"58F2",
71 X"62B1",X"615B",X"6000",X"5E9F",X"5D3B",X"5BD1",X"5A64",X"58F2",
71 X"577C",X"5603",X"5486",X"5306",X"5183",X"4FFE",X"4E75",X"4CEB",
72 X"577C",X"5603",X"5486",X"5306",X"5183",X"4FFE",X"4E75",X"4CEB",
72 X"4B5F",X"49D1",X"4841",X"46B0",X"451E",X"438B",X"41F8",X"4064",
73 X"4B5F",X"49D1",X"4841",X"46B0",X"451E",X"438B",X"41F8",X"4064",
73 X"3ED1",X"3D3D",X"3BAA",X"3A18",X"3886",X"36F6",X"3567",X"33DA",
74 X"3ED1",X"3D3D",X"3BAA",X"3A18",X"3886",X"36F6",X"3567",X"33DA",
74 X"324E",X"30C5",X"2F3E",X"2DBA",X"2C39",X"2ABA",X"293F",X"27C8",
75 X"324E",X"30C5",X"2F3E",X"2DBA",X"2C39",X"2ABA",X"293F",X"27C8",
75 X"2654",X"24E4",X"2379",X"2211",X"20AF",X"1F51",X"1DF9",X"1CA6",
76 X"2654",X"24E4",X"2379",X"2211",X"20AF",X"1F51",X"1DF9",X"1CA6",
76 X"1B58",X"1A10",X"18CE",X"1792",X"165C",X"152C",X"1404",X"12E2",
77 X"1B58",X"1A10",X"18CE",X"1792",X"165C",X"152C",X"1404",X"12E2",
77 X"11C7",X"10B4",X"0FA7",X"0EA3",X"0DA5",X"0CB0",X"0BC3",X"0ADE",
78 X"11C7",X"10B4",X"0FA7",X"0EA3",X"0DA5",X"0CB0",X"0BC3",X"0ADE",
78 X"0A01",X"092C",X"0860",X"079D",X"06E2",X"0631",X"0588",X"04E8",
79 X"0A01",X"092C",X"0860",X"079D",X"06E2",X"0631",X"0588",X"04E8",
79 X"0452",X"03C5",X"0341",X"02C6",X"0256",X"01EE",X"0191",X"013D",
80 X"0452",X"03C5",X"0341",X"02C6",X"0256",X"01EE",X"0191",X"013D",
80 X"00F3",X"00B2",X"007C",X"004F",X"002C",X"0013",X"0004",X"0000");
81 X"00F3",X"00B2",X"007C",X"004F",X"002C",X"0013",X"0004",X"0000");
81
82
82 SIGNAL data_selected : STD_LOGIC_VECTOR(SIZE_ARRAY_PARAM-1 DOWNTO 0);
83 SIGNAL data_selected : STD_LOGIC_VECTOR(SIZE_ARRAY_PARAM-1 DOWNTO 0);
83 BEGIN
84 BEGIN
84
85
86 PARAM_ALL_POSITIVE <= '1';
87
85 ALL_PARAM_DEFINE: IF NB_POINT_BY_WINDOW < SIZE_ARRAY + 1 GENERATE
88 ALL_PARAM_DEFINE: IF NB_POINT_BY_WINDOW < SIZE_ARRAY + 1 GENERATE
86 data_selected <= ROM_array(index);
89 data_selected <= ROM_array(index);
87 END GENERATE ALL_PARAM_DEFINE;
90 END GENERATE ALL_PARAM_DEFINE;
88
91
89 HALF_PARAM_DEFINE: IF NB_POINT_BY_WINDOW > SIZE_ARRAY AND NB_POINT_BY_WINDOW < 2 * SIZE_ARRAY + 1 GENERATE
92 HALF_PARAM_DEFINE: IF NB_POINT_BY_WINDOW > SIZE_ARRAY AND NB_POINT_BY_WINDOW < 2 * SIZE_ARRAY + 1 GENERATE
90 data_selected <= ROM_array(index) WHEN index < SIZE_ARRAY ELSE
93 data_selected <= ROM_array(index) WHEN index < SIZE_ARRAY ELSE
91 ROM_array(2*SIZE_ARRAY-1-index);
94 ROM_array(2*SIZE_ARRAY-1-index);
92 END GENERATE HALF_PARAM_DEFINE;
95 END GENERATE HALF_PARAM_DEFINE;
93
96
94 data <= data_selected(SIZE_ARRAY_PARAM-1 DOWNTO SIZE_ARRAY_PARAM-SIZE_PARAM);
97 data <= data_selected(SIZE_ARRAY_PARAM-1 DOWNTO SIZE_ARRAY_PARAM-SIZE_PARAM);
95
98
96 END beh;
99 END beh; No newline at end of file
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@@ -1,84 +1,88
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27
27
28 LIBRARY lpp;
28 LIBRARY lpp;
29 USE lpp.window_function_pkg.ALL;
29 USE lpp.window_function_pkg.ALL;
30
30
31 ENTITY window_function IS
31 ENTITY window_function IS
32 GENERIC (
32 GENERIC (
33 SIZE_DATA : INTEGER := 16;
33 SIZE_DATA : INTEGER := 16;
34 SIZE_PARAM : INTEGER := 10;
34 SIZE_PARAM : INTEGER := 10;
35 NB_POINT_BY_WINDOW : INTEGER := 256
35 NB_POINT_BY_WINDOW : INTEGER := 256
36 );
36 );
37
37
38 PORT (
38 PORT (
39 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41 --ctrl
41 --ctrl
42 restart_window : IN STD_LOGIC;
42 restart_window : IN STD_LOGIC;
43 --data_in
43 --data_in
44 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
44 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
45 data_in_valid : IN STD_LOGIC;
45 data_in_valid : IN STD_LOGIC;
46 --data_out
46 --data_out
47 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
47 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
48 data_out_valid : OUT STD_LOGIC
48 data_out_valid : OUT STD_LOGIC
49 );
49 );
50
50
51 END window_function;
51 END window_function;
52
52
53 ARCHITECTURE beh OF window_function IS
53 ARCHITECTURE beh OF window_function IS
54
54
55 SIGNAL param_in : STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
55 SIGNAL param_in : STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
56 SIGNAL param_index : INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1;
56 SIGNAL param_index : INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1;
57
57
58 SIGNAL PARAM_ALL_POSITIVE : STD_LOGIC;
59
58 BEGIN
60 BEGIN
59
61
60 WF_rom_1: WF_rom
62 WF_rom_1: WF_rom
61 GENERIC MAP (
63 GENERIC MAP (
62 SIZE_PARAM => SIZE_PARAM,
64 SIZE_PARAM => SIZE_PARAM,
63 NB_POINT_BY_WINDOW => NB_POINT_BY_WINDOW)
65 NB_POINT_BY_WINDOW => NB_POINT_BY_WINDOW)
64 PORT MAP (
66 PORT MAP (
65 data => param_in,
67 data => param_in,
66 index => param_index);
68 index => param_index,
69 PARAM_ALL_POSITIVE => PARAM_ALL_POSITIVE );
67
70
68 WF_processing_1: WF_processing
71 WF_processing_1: WF_processing
69 GENERIC MAP (
72 GENERIC MAP (
70 SIZE_DATA => SIZE_DATA,
73 SIZE_DATA => SIZE_DATA,
71 SIZE_PARAM => SIZE_PARAM,
74 SIZE_PARAM => SIZE_PARAM,
72 NB_POINT_BY_WINDOW => NB_POINT_BY_WINDOW)
75 NB_POINT_BY_WINDOW => NB_POINT_BY_WINDOW)
73 PORT MAP (
76 PORT MAP (
74 clk => clk,
77 clk => clk,
75 rstn => rstn,
78 rstn => rstn,
76 restart_window => restart_window,
79 restart_window => restart_window,
77 data_in => data_in,
80 data_in => data_in,
78 data_in_valid => data_in_valid,
81 data_in_valid => data_in_valid,
79 data_out => data_out,
82 data_out => data_out,
80 data_out_valid => data_out_valid,
83 data_out_valid => data_out_valid,
81 param_in => param_in,
84 param_in => param_in,
82 param_index => param_index);
85 param_index => param_index,
86 PARAM_ALL_POSITIVE => PARAM_ALL_POSITIVE );
83
87
84 END beh;
88 END beh; No newline at end of file
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@@ -1,72 +1,74
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 PACKAGE window_function_pkg IS
27 PACKAGE window_function_pkg IS
28
28
29 COMPONENT window_function
29 COMPONENT window_function
30 GENERIC (
30 GENERIC (
31 SIZE_DATA : INTEGER;
31 SIZE_DATA : INTEGER;
32 SIZE_PARAM : INTEGER;
32 SIZE_PARAM : INTEGER;
33 NB_POINT_BY_WINDOW : INTEGER);
33 NB_POINT_BY_WINDOW : INTEGER);
34 PORT (
34 PORT (
35 clk : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 restart_window : IN STD_LOGIC;
37 restart_window : IN STD_LOGIC;
38 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
38 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
39 data_in_valid : IN STD_LOGIC;
39 data_in_valid : IN STD_LOGIC;
40 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
40 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
41 data_out_valid : OUT STD_LOGIC
41 data_out_valid : OUT STD_LOGIC
42 );
42 );
43 END COMPONENT;
43 END COMPONENT;
44
44
45 COMPONENT WF_processing
45 COMPONENT WF_processing
46 GENERIC (
46 GENERIC (
47 SIZE_DATA : INTEGER;
47 SIZE_DATA : INTEGER;
48 SIZE_PARAM : INTEGER;
48 SIZE_PARAM : INTEGER;
49 NB_POINT_BY_WINDOW : INTEGER);
49 NB_POINT_BY_WINDOW : INTEGER);
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 restart_window : IN STD_LOGIC;
53 restart_window : IN STD_LOGIC;
54 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
54 data_in : IN STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
55 data_in_valid : IN STD_LOGIC;
55 data_in_valid : IN STD_LOGIC;
56 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
56 data_out : OUT STD_LOGIC_VECTOR(SIZE_DATA-1 DOWNTO 0);
57 data_out_valid : OUT STD_LOGIC;
57 data_out_valid : OUT STD_LOGIC;
58 param_in : IN STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
58 param_in : IN STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
59 param_index : OUT INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1
59 param_index : OUT INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1;
60 PARAM_ALL_POSITIVE : IN STD_LOGIC
60 );
61 );
61 END COMPONENT;
62 END COMPONENT;
62
63
63 COMPONENT WF_rom
64 COMPONENT WF_rom
64 GENERIC (
65 GENERIC (
65 SIZE_PARAM : INTEGER;
66 SIZE_PARAM : INTEGER;
66 NB_POINT_BY_WINDOW : INTEGER);
67 NB_POINT_BY_WINDOW : INTEGER);
67 PORT (
68 PORT (
68 data : OUT STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
69 data : OUT STD_LOGIC_VECTOR(SIZE_PARAM-1 DOWNTO 0);
69 index : IN INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1);
70 index : IN INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1;
71 PARAM_ALL_POSITIVE : OUT STD_LOGIC);
70 END COMPONENT;
72 END COMPONENT;
71
73
72 END window_function_pkg;
74 END window_function_pkg;
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