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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34
35
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 --USE work.config.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_demux.all;
46 use lpp.lpp_dma_pkg.all;
47 use lpp.lpp_Header.all;
48 use lpp.lpp_fft.all;
49 use lpp.lpp_matrix.all;
50
51
52 ENTITY TestBench IS
53 END;
54
55 ARCHITECTURE Behavioral OF TestBench IS
56
57
58 component TestModule_ADS7886 IS
59 GENERIC (
60 freq : INTEGER ;
61 amplitude : INTEGER ;
62 impulsion : INTEGER
63 );
64 PORT (
65 -- CONV --
66 cnv_run : IN STD_LOGIC;
67 cnv : IN STD_LOGIC;
68
69 -- DATA --
70 sck : IN STD_LOGIC;
71 sdo : OUT STD_LOGIC
72 );
73 END component;
74
75 SIGNAL clk49_152MHz : STD_LOGIC := '0';
76 SIGNAL clkm : STD_LOGIC := '0';
77 SIGNAL rstn : STD_LOGIC := '0';
78 SIGNAL coarse_time_0 : STD_LOGIC := '0';
79
80 -- -- ADC interface
81 -- SIGNAL bias_fail_sw : STD_LOGIC; -- OUT
82 -- SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
83 -- SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
84 -- SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
85
86 --
87 SIGNAL apbi : apb_slv_in_type;
88 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
89 SIGNAL ahbmi : ahb_mst_in_type;
90 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
91
92 -- -- internal
93 -- SIGNAL sample : Samples14v(7 DOWNTO 0);
94 -- SIGNAL sample_val : STD_LOGIC;
95
96 -- ACQ
97 signal CNV_CH1 : STD_LOGIC;
98 signal SCK_CH1 : STD_LOGIC;
99 signal SDO_CH1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
100 signal Bias_Fails : std_logic;
101 signal sample_val : STD_LOGIC;
102 signal sample : Samples(8-1 DOWNTO 0);
103
104 signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
110 -- FIFOs
111 signal FifoF0_Empty : std_logic_vector(4 downto 0);
112 signal FifoF0_Data : std_logic_vector(79 downto 0);
113 signal FifoF1_Empty : std_logic_vector(4 downto 0);
114 signal FifoF1_Data : std_logic_vector(79 downto 0);
115 signal FifoF3_Empty : std_logic_vector(4 downto 0);
116 signal FifoF3_Data : std_logic_vector(79 downto 0);
117 signal FifoINT_Full : std_logic_vector(4 downto 0);
118 signal FifoINT_Data : std_logic_vector(79 downto 0);
119 signal FifoOUT_Full : std_logic_vector(1 downto 0);
120 signal FifoOUT_Empty : std_logic_vector(1 downto 0);
121 signal FifoOUT_Data : std_logic_vector(63 downto 0);
122 -- MATRICE SPECTRALE
123 signal SM_FlagError : std_logic;
124 signal SM_Pong : std_logic;
125 signal SM_Wen : std_logic;
126 signal SM_Read : std_logic_vector(4 downto 0);
127 signal SM_Write : std_logic_vector(1 downto 0);
128 signal SM_ReUse : std_logic_vector(4 downto 0);
129 signal SM_Param : std_logic_vector(3 downto 0);
130 signal SM_Data : std_logic_vector(63 downto 0);
131 -- FFT
132 signal FFT_Load : std_logic;
133 signal FFT_Read : std_logic_vector(4 downto 0);
134 signal FFT_Write : std_logic_vector(4 downto 0);
135 signal FFT_ReUse : std_logic_vector(4 downto 0);
136 signal FFT_Data : std_logic_vector(79 downto 0);
137 -- DEMUX
138 signal DMUX_Read : std_logic_vector(14 downto 0);
139 signal DMUX_Empty : std_logic_vector(4 downto 0);
140 signal DMUX_Data : std_logic_vector(79 downto 0);
141 signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
142 -- Header
143 signal Head_Read : std_logic_vector(1 downto 0);
144 signal Head_Data : std_logic_vector(31 downto 0);
145 signal Head_Empty : std_logic;
146 signal Head_Header : std_logic_vector(31 DOWNTO 0);
147 signal Head_Valid : std_logic;
148 signal Head_Val : std_logic;
149 --DMA
150 signal DMA_Read : std_logic;
151 signal DMA_ack : std_logic;
152 signal AHB_Master_In : AHB_Mst_In_Type;
153 signal AHB_Master_Out : AHB_Mst_Out_Type;
154
155
156 BEGIN
157
158 -----------------------------------------------------------------------------
159
160 -- MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE
161 -- TestModule_RHF1401_1: TestModule_RHF1401
162 -- GENERIC MAP (
163 -- freq => 24*(I+1),
164 -- amplitude => 8000/(I+1),
165 -- impulsion => 0)
166 -- PORT MAP (
167 -- ADC_smpclk => ADC_smpclk,
168 -- ADC_OEB_bar => ADC_OEB_bar_CH(I),
169 -- ADC_data => ADC_data);
170 -- END GENERATE MODULE_RHF1401;
171
172 MODULE_ADS7886: FOR I IN 0 TO 7 GENERATE
173 TestModule_ADS7886_0 : TestModule_ADS7886
174 GENERIC MAP (
175 freq => 24*(I+1),
176 amplitude => 8000/(I+1),
177 impulsion => 0)
178 PORT MAP(
179 -- CONV --
180 cnv_run => '1',
181 cnv => CNV_CH1,
182 -- DATA --
183 sck => SCK_CH1,
184 sdo => SDO_CH1(I));
185 END GENERATE MODULE_ADS7886;
186
187
188 -----------------------------------------------------------------------------
189
190 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
191 clkm <= NOT clkm AFTER 20 ns; -- 25 MHz
192 coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms;
193
194 -----------------------------------------------------------------------------
195 -- waveform generation
196 WaveGen_Proc : PROCESS
197 BEGIN
198 WAIT UNTIL clkm = '1';
199 apbi <= apb_slv_in_none;
200 rstn <= '0';
201 -- cnv_rstn <= '0';
202 -- run_cnv <= '0';
203 WAIT UNTIL clkm = '1';
204 WAIT UNTIL clkm = '1';
205 WAIT UNTIL clkm = '1';
206 rstn <= '1';
207 -- cnv_rstn <= '1';
208 WAIT UNTIL clkm = '1';
209 WAIT UNTIL clkm = '1';
210 WAIT UNTIL clkm = '1';
211
212 WAIT;
213
214 END PROCESS WaveGen_Proc;
215
216
217 ahbmi.HGRANT(2) <= '1';
218 ahbmi.HREADY <= '1';
219 ahbmi.HRESP <= HRESP_OKAY;
220
221
222
223 -------------------------------------------------------------------------------
224 -------------------------------------------------------------------------------
225 -- DUT ------------------------------------------------------------------------
226 -------------------------------------------------------------------------------
227 -------------------------------------------------------------------------------
228 ACQ0 : lpp_top_acq
229 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk49_152MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
230
231 Bias_Fails <= '0';
232 --- FIFO IN -------------------------------------------------------------
233
234 Memf0 : lppFIFOxN
235 generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
236 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
237
238 Memf1 : lppFIFOxN
239 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
240 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
241
242 Memf3 : lppFIFOxN
243 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
244 port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
245
246 --- DEMUX -------------------------------------------------------------
247
248 DMUX0 : DEMUX
249 generic map(Data_sz => 16)
250 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
251
252 --- FFT -------------------------------------------------------------
253
254 FFT0 : FFT
255 generic map(Data_sz => 16,NbData => 256)
256 port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
257
258 ----- LINK MEMORY -------------------------------------------------------
259
260 MemInt : lppFIFOxN
261 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
262 port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
263
264 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
265
266 SM0 : MatriceSpectrale
267 generic map(Input_SZ => 16,Result_SZ => 32)
268 port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
269
270 MemOut : lppFIFOxN
271 generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
272 port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
273
274 ----- Header -------------------------------------------------------
275
276 Head0 : HeaderBuilder
277 generic map(Data_sz => 32)
278 port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
279
280 ----- DMA -------------------------------------------------------
281
282 DMA0 : lpp_dma
283 generic map(
284 tech =>inferred,
285 hindex => 2,
286 pindex => 9,
287 paddr => 9,
288 pmask => 16#fff#,
289 pirq => 0)
290 port map(clkm,rstn,apbi,apbo(9),AHB_Master_In,AHB_Master_Out,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
291
292 -------------------------------------------------------------------------------
293 -------------------------------------------------------------------------------
294
295 END Behavioral; No newline at end of file
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1
2
3 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
4 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
5 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
6 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actar.vhd
7 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/actram.vhd
8 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftDp.vhd
9 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fftSm.vhd
10 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/fft_components.vhd
11 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
12 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/primitives.vhd
13 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/twiddle.vhd
14 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./dsp/lpp_fft/FFT.vhd
15
16 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ALU_Driver.vhd
17 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Dispatch.vhd
18 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/DriveInputs.vhd
19 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/GetResult.vhd
20 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Matrix.vhd
21 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd
22 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/Starter.vhd
23 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd
24 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd
25 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd
26 # vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_matrix/lpp_matrix.vhd
27
28 vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
29
30 vcom -quiet -93 -work lpp ../../lib/../../VHD_Lib/lib/lpp/./lpp_ad_Conv/TestModule_ADS7886.vhd
31 vcom -quiet -93 -work work TestBench.vhd
32
33 vsim work.testbench No newline at end of file
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@@ -1,19 +1,20
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
4 ./dsp/lpp_fft
5 ./general_purpose
5 ./general_purpose
6 ./general_purpose/lpp_AMR
6 ./general_purpose/lpp_AMR
7 ./general_purpose/lpp_balise
7 ./general_purpose/lpp_balise
8 ./general_purpose/lpp_delay
8 ./general_purpose/lpp_delay
9 ./lpp_ad_Conv
9 ./lpp_ad_Conv
10 ./lpp_amba
10 ./lpp_amba
11 ./lpp_bootloader
11 ./lpp_bootloader
12 ./lpp_cna
12 ./lpp_cna
13 ./lpp_demux
13 ./lpp_demux
14 ./lpp_dma
14 ./lpp_dma
15 ./lpp_Header
15 ./lpp_matrix
16 ./lpp_matrix
16 ./lpp_memory
17 ./lpp_memory
17 ./lpp_top_lfr
18 ./lpp_top_lfr
18 ./lpp_uart
19 ./lpp_uart
19 ./lpp_usb
20 ./lpp_usb
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@@ -1,94 +1,95
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.fft_components.all;
25 library lpp;
26 use lpp.lpp_fft.all;
26 use lpp.lpp_fft.all;
27 use lpp.fft_components.all;
27
28
28 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
29
30
30 entity FFT is
31 entity FFT is
31 generic(
32 generic(
32 Data_sz : integer := 16;
33 Data_sz : integer := 16;
33 NbData : integer := 256);
34 NbData : integer := 256);
34 port(
35 port(
35 clkm : in std_logic;
36 clkm : in std_logic;
36 rstn : in std_logic;
37 rstn : in std_logic;
37 FifoIN_Empty : in std_logic_vector(4 downto 0);
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
38 FifoIN_Data : in std_logic_vector(79 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
39 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 Load : out std_logic;
41 Load : out std_logic;
41 Read : out std_logic_vector(4 downto 0);
42 Read : out std_logic_vector(4 downto 0);
42 Write : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
43 ReUse : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
44 Data : out std_logic_vector(79 downto 0)
45 Data : out std_logic_vector(79 downto 0)
45 );
46 );
46 end entity;
47 end entity;
47
48
48
49
49 architecture ar_FFT of FFT is
50 architecture ar_FFT of FFT is
50
51
51 signal Drive_Write : std_logic;
52 signal Drive_Write : std_logic;
52 signal Drive_DataRE : std_logic_vector(15 downto 0);
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
53 signal Drive_DataIM : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
54
55
55 signal Start : std_logic;
56 signal Start : std_logic;
56 signal FFT_Load : std_logic;
57 signal FFT_Load : std_logic;
57 signal FFT_Ready : std_logic;
58 signal FFT_Ready : std_logic;
58 signal FFT_Valid : std_logic;
59 signal FFT_Valid : std_logic;
59 signal FFT_DataRE : std_logic_vector(15 downto 0);
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
60 signal FFT_DataIM : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
61
62
62 signal Link_Read : std_logic;
63 signal Link_Read : std_logic;
63
64
64 begin
65 begin
65
66
66 Start <= '0';
67 Start <= '0';
67 Load <= FFT_Load;
68 Load <= FFT_Load;
68
69
69 DRIVE : Driver_FFT
70 DRIVE : Driver_FFT
70 generic map(Data_sz,NbData)
71 generic map(Data_sz,NbData)
71 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
72
73
73 FFT0 : CoreFFT
74 FFT0 : CoreFFT
74 generic map(
75 generic map(
75 LOGPTS => gLOGPTS,
76 LOGPTS => gLOGPTS,
76 LOGLOGPTS => gLOGLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
77 WSIZE => gWSIZE,
78 WSIZE => gWSIZE,
78 TWIDTH => gTWIDTH,
79 TWIDTH => gTWIDTH,
79 DWIDTH => gDWIDTH,
80 DWIDTH => gDWIDTH,
80 TDWIDTH => gTDWIDTH,
81 TDWIDTH => gTDWIDTH,
81 RND_MODE => gRND_MODE,
82 RND_MODE => gRND_MODE,
82 SCALE_MODE => gSCALE_MODE,
83 SCALE_MODE => gSCALE_MODE,
83 PTS => gPTS,
84 PTS => gPTS,
84 HALFPTS => gHALFPTS,
85 HALFPTS => gHALFPTS,
85 inBuf_RWDLY => gInBuf_RWDLY)
86 inBuf_RWDLY => gInBuf_RWDLY)
86 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
87 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
87
88
88
89
89 LINK : Linker_FFT
90 LINK : Linker_FFT
90 generic map(Data_sz,NbData)
91 generic map(Data_sz,NbData)
91 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
92 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
92
93
93
94
94 end architecture; No newline at end of file
95 end architecture;
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@@ -1,72 +1,73
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
25 library lpp;
26 use lpp.FFT_config.all;
26
27
27 --! Programme qui va permettre de gοΏ½nοΏ½rer des flags utilisοΏ½s au niveau du driver C
28 --! Programme qui va permettre de gοΏ½nοΏ½rer des flags utilisοΏ½s au niveau du driver C
28
29
29 entity Flag_Extremum is
30 entity Flag_Extremum is
30 port(
31 port(
31 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
32 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
32 load : in std_logic; --! Signal en provenance de CoreFFT
33 load : in std_logic; --! Signal en provenance de CoreFFT
33 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
34 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
34 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
35 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
35 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
36 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
36 );
37 );
37 end Flag_Extremum;
38 end Flag_Extremum;
38
39
39 --! @details Flags gοΏ½nοΏ½rοΏ½s a partir de signaux fourni par l'IP FFT d'actel
40 --! @details Flags gοΏ½nοΏ½rοΏ½s a partir de signaux fourni par l'IP FFT d'actel
40
41
41 architecture ar_Flag_Extremum of Flag_Extremum is
42 architecture ar_Flag_Extremum of Flag_Extremum is
42
43
43 begin
44 begin
44 process (clk,raz)
45 process (clk,raz)
45 begin
46 begin
46 if(raz='0')then
47 if(raz='0')then
47 fill <= '0';
48 fill <= '0';
48 ready <= '0';
49 ready <= '0';
49
50
50 elsif(clk' event and clk='1')then
51 elsif(clk' event and clk='1')then
51
52
52 if(load='1' and y_rdy='0')then
53 if(load='1' and y_rdy='0')then
53 fill <= '1';
54 fill <= '1';
54 ready <= '0';
55 ready <= '0';
55
56
56 elsif(y_rdy='1')then
57 elsif(y_rdy='1')then
57 fill <= '0';
58 fill <= '0';
58 ready <= '1';
59 ready <= '1';
59
60
60 else
61 else
61 fill <= '0';
62 fill <= '0';
62 ready <= '0';
63 ready <= '0';
63
64
64 end if;
65 end if;
65 end if;
66 end if;
66 end process;
67 end process;
67
68
68 end ar_Flag_Extremum;
69 end ar_Flag_Extremum;
69
70
70
71
71
72
72
73
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@@ -1,110 +1,111
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity HeaderBuilder is
26 entity HeaderBuilder is
27 generic(
27 generic(
28 Data_sz : integer := 32);
28 Data_sz : integer := 32);
29 port(
29 port(
30 clkm : in std_logic;
30 clkm : in std_logic;
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 pong : in std_logic;
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
34 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
36 Matrix_Write : in std_logic;
37 Valid : out std_logic;
37 Valid : out std_logic;
38
38
39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
40 emptyIN : in std_logic_vector(1 downto 0);
40 emptyIN : in std_logic_vector(1 downto 0);
41 RenOUT : out std_logic_vector(1 downto 0);
41 RenOUT : out std_logic_vector(1 downto 0);
42
42
43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
44 emptyOUT : out std_logic;
44 emptyOUT : out std_logic;
45 RenIN : in std_logic;
45 RenIN : in std_logic;
46
46
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 header_val : out std_logic;
48 header_val : out std_logic;
49 header_ack : in std_logic
49 header_ack : in std_logic
50 );
50 );
51 end entity;
51 end entity;
52
52
53
53
54 architecture ar_HeaderBuilder of HeaderBuilder is
54 architecture ar_HeaderBuilder of HeaderBuilder is
55
55
56 signal Matrix_Param : std_logic_vector(3 downto 0);
56 signal Matrix_Param : std_logic_vector(3 downto 0);
57 signal Write_reg : std_logic;
57 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
58 signal Data_cpt : integer;
59 signal MAX : integer;
59 signal MAX : integer;
60
60
61
61
62 begin
62 begin
63
63
64 process (clkm,rstn)
64 process (clkm,rstn)
65 begin
65 begin
66 if(rstn='0')then
66 if(rstn='0')then
67 Valid <= '0';
67 Valid <= '0';
68 Write_reg <= '0';
68 Write_reg <= '0';
69 Data_cpt <= 0;
69 Data_cpt <= 0;
70 MAX <= 0;
70 MAX <= 0;
71
71
72
72
73 elsif(clkm' event and clkm='1')then
73 elsif(clkm' event and clkm='1')then
74 Write_reg <= Matrix_Write;
74 Write_reg <= Matrix_Write;
75
75
76 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
76 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 MAX <= 128;
77 MAX <= 128;
78 else
78 else
79 MAX <= 256;
79 MAX <= 256;
80 end if;
80 end if;
81
81
82 if(Write_reg = '0' and Matrix_Write = '1')then
82 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
83 if(Data_cpt = MAX)then
84 Data_cpt <= 0;
84 Data_cpt <= 0;
85 Valid <= '1';
85 Valid <= '1';
86 header_val <= '1';
86 header_val <= '1';
87 else
87 else
88 Data_cpt <= Data_cpt + 1;
88 Data_cpt <= Data_cpt + 1;
89 Valid <= '0';
89 Valid <= '0';
90 end if;
90 end if;
91 end if;
91 end if;
92
92
93 if(header_ack = '1')then
93 if(header_ack = '1')then
94 header_val <= '0';
94 header_val <= '0';
95 end if;
95 end if;
96
96
97 end if;
97 end if;
98 end process;
98 end process;
99
99
100 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
100 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101
101
102 header(1 downto 0) <= Matrix_Type;
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
103 header(5 downto 2) <= Matrix_Param;
104 header(31 downto 6) <= (others => '0');
104
105
105 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
106 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
107 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
107
108
108 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
109 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
109
110
110 end architecture; No newline at end of file
111 end architecture;
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@@ -1,352 +1,352
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_amba.ALL;
37 USE lpp.lpp_amba.ALL;
38 USE lpp.apb_devices_list.ALL;
38 USE lpp.apb_devices_list.ALL;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_ip IS
45 ENTITY lpp_dma_ip IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
48 hindex : INTEGER := 2
49 );
49 );
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- fifo interface
59 -- fifo interface
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 fifo_empty : IN STD_LOGIC;
61 fifo_empty : IN STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
63
63
64 -- header
64 -- header
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 header_val : IN STD_LOGIC;
66 header_val : IN STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
68
68
69 -- Reg out
69 -- Reg out
70 ready_matrix_f0_0 : OUT STD_LOGIC;
70 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77
77
78 -- Reg In
78 -- Reg In
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
85
85
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 );
92 );
93 END;
93 END;
94
94
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL DMAIn : DMA_In_Type;
97 SIGNAL DMAIn : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
101 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
102
102
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 TYPE state_DMAWriteBurst IS (IDLE,
105 TYPE state_DMAWriteBurst IS (IDLE,
106 TRASH_FIFO,
106 TRASH_FIFO,
107 WAIT_HEADER_ACK,
107 WAIT_HEADER_ACK,
108 SEND_DATA,
108 SEND_DATA,
109 WAIT_DATA_ACK,
109 WAIT_DATA_ACK,
110 CHECK_LENGTH
110 CHECK_LENGTH
111 );
111 );
112 SIGNAL state : state_DMAWriteBurst := IDLE;
112 SIGNAL state : state_DMAWriteBurst := IDLE;
113
113
114 SIGNAL nbSend : INTEGER;
114 SIGNAL nbSend : INTEGER;
115 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL header_check_ok : STD_LOGIC;
118 SIGNAL header_check_ok : STD_LOGIC;
119 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL send_matrix : STD_LOGIC;
120 SIGNAL send_matrix : STD_LOGIC;
121 SIGNAL request : STD_LOGIC;
121 SIGNAL request : STD_LOGIC;
122 SIGNAL remaining_data_request : INTEGER;
122 SIGNAL remaining_data_request : INTEGER;
123 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 SIGNAL header_select : STD_LOGIC;
126 SIGNAL header_select : STD_LOGIC;
127
127
128 SIGNAL header_send : STD_LOGIC;
128 SIGNAL header_send : STD_LOGIC;
129 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL header_send_ok : STD_LOGIC;
130 SIGNAL header_send_ok : STD_LOGIC;
131 SIGNAL header_send_ko : STD_LOGIC;
131 SIGNAL header_send_ko : STD_LOGIC;
132
132
133 SIGNAL component_send : STD_LOGIC;
133 SIGNAL component_send : STD_LOGIC;
134 SIGNAL component_send_ok : STD_LOGIC;
134 SIGNAL component_send_ok : STD_LOGIC;
135 SIGNAL component_send_ko : STD_LOGIC;
135 SIGNAL component_send_ko : STD_LOGIC;
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL fifo_ren_trash : STD_LOGIC;
137 SIGNAL fifo_ren_trash : STD_LOGIC;
138 SIGNAL component_fifo_ren : STD_LOGIC;
138 SIGNAL component_fifo_ren : STD_LOGIC;
139
139
140 -----------------------------------------------------------------------------
140 -----------------------------------------------------------------------------
141 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
142
142
143 BEGIN
143 BEGIN
144
144
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 -- DMA to AHB interface
146 -- DMA to AHB interface
147 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
148
148
149 DMA2AHB_1 : DMA2AHB
149 DMA2AHB_1 : DMA2AHB
150 GENERIC MAP (
150 GENERIC MAP (
151 hindex => hindex,
151 hindex => hindex,
152 vendorid => VENDOR_LPP,
152 vendorid => VENDOR_LPP,
153 deviceid => 0,
153 deviceid => 0,
154 version => 0,
154 version => 0,
155 syncrst => 1,
155 syncrst => 1,
156 boundary => 1) -- FIX 11/01/2013
156 boundary => 1) -- FIX 11/01/2013
157 PORT MAP (
157 PORT MAP (
158 HCLK => HCLK,
158 HCLK => HCLK,
159 HRESETn => HRESETn,
159 HRESETn => HRESETn,
160 DMAIn => DMAIn,
160 DMAIn => DMAIn,
161 DMAOut => DMAOut,
161 DMAOut => DMAOut,
162 AHBIn => AHB_Master_In,
162 AHBIn => AHB_Master_In,
163 AHBOut => AHB_Master_Out);
163 AHBOut => AHB_Master_Out);
164
164
165 debug_reg <= debug_reg_s;
165 debug_reg <= debug_reg_s;
166
166
167 debug_info: PROCESS (HCLK, HRESETn)
167 debug_info: PROCESS (HCLK, HRESETn)
168 BEGIN -- PROCESS debug_info
168 BEGIN -- PROCESS debug_info
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
169 IF HRESETn = '0' THEN -- asynchronous reset (active low)
170 debug_reg <= (OTHERS => '0');
170 debug_reg_s <= (OTHERS => '0');
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
171 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
172 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
173 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
174 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
174 IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF;
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
175 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
176 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
177 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
178 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
178 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
179
179
180 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
180 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
181 END IF;
181 END IF;
182 END PROCESS debug_info;
182 END PROCESS debug_info;
183
183
184
184
185 matrix_type <= header(1 DOWNTO 0);
185 matrix_type <= header(1 DOWNTO 0);
186 component_type <= header(5 DOWNTO 2);
186 component_type <= header(5 DOWNTO 2);
187
187
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 '0';
192 '0';
193
193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 '0';
197 '0';
198
198
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
203 (OTHERS => '0');
203 (OTHERS => '0');
204
204
205 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
206 -- DMA control
206 -- DMA control
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 BEGIN -- PROCESS DMAWriteBurst_p
209 BEGIN -- PROCESS DMAWriteBurst_p
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 state <= IDLE;
211 state <= IDLE;
212 header_ack <= '0';
212 header_ack <= '0';
213 ready_matrix_f0_0 <= '0';
213 ready_matrix_f0_0 <= '0';
214 ready_matrix_f0_1 <= '0';
214 ready_matrix_f0_1 <= '0';
215 ready_matrix_f1 <= '0';
215 ready_matrix_f1 <= '0';
216 ready_matrix_f2 <= '0';
216 ready_matrix_f2 <= '0';
217 error_anticipating_empty_fifo <= '0';
217 error_anticipating_empty_fifo <= '0';
218 error_bad_component_error <= '0';
218 error_bad_component_error <= '0';
219 component_type_pre <= "1110";
219 component_type_pre <= "1110";
220 fifo_ren_trash <= '1';
220 fifo_ren_trash <= '1';
221 component_send <= '0';
221 component_send <= '0';
222 address <= (OTHERS => '0');
222 address <= (OTHERS => '0');
223 header_select <= '0';
223 header_select <= '0';
224 header_send <= '0';
224 header_send <= '0';
225 header_data <= (OTHERS => '0');
225 header_data <= (OTHERS => '0');
226 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
226 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
227
227
228 CASE state IS
228 CASE state IS
229 WHEN IDLE =>
229 WHEN IDLE =>
230 ready_matrix_f0_0 <= '0';
230 ready_matrix_f0_0 <= '0';
231 ready_matrix_f0_1 <= '0';
231 ready_matrix_f0_1 <= '0';
232 ready_matrix_f1 <= '0';
232 ready_matrix_f1 <= '0';
233 ready_matrix_f2 <= '0';
233 ready_matrix_f2 <= '0';
234 error_bad_component_error <= '0';
234 error_bad_component_error <= '0';
235 header_select <= '1';
235 header_select <= '1';
236 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
236 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
237 IF header_check_ok = '1' THEN
237 IF header_check_ok = '1' THEN
238 header_data <= header;
238 header_data <= header;
239 component_type_pre <= header(5 DOWNTO 2);
239 component_type_pre <= header(5 DOWNTO 2);
240 header_ack <= '1';
240 header_ack <= '1';
241 --
241 --
242 header_send <= '1';
242 header_send <= '1';
243 IF component_type = "0000" THEN
243 IF component_type = "0000" THEN
244 address <= address_matrix;
244 address <= address_matrix;
245 END IF;
245 END IF;
246 header_data <= header;
246 header_data <= header;
247 --
247 --
248 state <= WAIT_HEADER_ACK;
248 state <= WAIT_HEADER_ACK;
249 ELSE
249 ELSE
250 error_bad_component_error <= '1';
250 error_bad_component_error <= '1';
251 component_type_pre <= "1110";
251 component_type_pre <= "1110";
252 header_ack <= '1';
252 header_ack <= '1';
253 state <= TRASH_FIFO;
253 state <= TRASH_FIFO;
254 END IF;
254 END IF;
255 END IF;
255 END IF;
256
256
257 WHEN TRASH_FIFO =>
257 WHEN TRASH_FIFO =>
258 error_bad_component_error <= '0';
258 error_bad_component_error <= '0';
259 error_anticipating_empty_fifo <= '0';
259 error_anticipating_empty_fifo <= '0';
260 IF fifo_empty = '1' THEN
260 IF fifo_empty = '1' THEN
261 state <= IDLE;
261 state <= IDLE;
262 fifo_ren_trash <= '1';
262 fifo_ren_trash <= '1';
263 ELSE
263 ELSE
264 fifo_ren_trash <= '0';
264 fifo_ren_trash <= '0';
265 END IF;
265 END IF;
266
266
267 WHEN WAIT_HEADER_ACK =>
267 WHEN WAIT_HEADER_ACK =>
268 header_send <= '0';
268 header_send <= '0';
269 IF header_send_ko = '1' THEN
269 IF header_send_ko = '1' THEN
270 state <= TRASH_FIFO;
270 state <= TRASH_FIFO;
271 error_anticipating_empty_fifo <= '1';
271 error_anticipating_empty_fifo <= '1';
272 -- TODO : error sending header
272 -- TODO : error sending header
273 ELSIF header_send_ok = '1' THEN
273 ELSIF header_send_ok = '1' THEN
274 header_select <= '0';
274 header_select <= '0';
275 state <= SEND_DATA;
275 state <= SEND_DATA;
276 address <= address + 4;
276 address <= address + 4;
277 END IF;
277 END IF;
278
278
279 WHEN SEND_DATA =>
279 WHEN SEND_DATA =>
280 IF fifo_empty = '1' THEN
280 IF fifo_empty = '1' THEN
281 state <= IDLE;
281 state <= IDLE;
282 IF component_type = "1110" THEN
282 IF component_type = "1110" THEN
283 CASE matrix_type IS
283 CASE matrix_type IS
284 WHEN "00" => ready_matrix_f0_0 <= '1';
284 WHEN "00" => ready_matrix_f0_0 <= '1';
285 WHEN "01" => ready_matrix_f0_1 <= '1';
285 WHEN "01" => ready_matrix_f0_1 <= '1';
286 WHEN "10" => ready_matrix_f1 <= '1';
286 WHEN "10" => ready_matrix_f1 <= '1';
287 WHEN "11" => ready_matrix_f2 <= '1';
287 WHEN "11" => ready_matrix_f2 <= '1';
288 WHEN OTHERS => NULL;
288 WHEN OTHERS => NULL;
289 END CASE;
289 END CASE;
290 END IF;
290 END IF;
291 ELSE
291 ELSE
292 component_send <= '1';
292 component_send <= '1';
293 address <= address;
293 address <= address;
294 state <= WAIT_DATA_ACK;
294 state <= WAIT_DATA_ACK;
295 END IF;
295 END IF;
296
296
297 WHEN WAIT_DATA_ACK =>
297 WHEN WAIT_DATA_ACK =>
298 component_send <= '0';
298 component_send <= '0';
299 IF component_send_ok = '1' THEN
299 IF component_send_ok = '1' THEN
300 address <= address + 64;
300 address <= address + 64;
301 state <= SEND_DATA;
301 state <= SEND_DATA;
302 ELSIF component_send_ko = '1' THEN
302 ELSIF component_send_ko = '1' THEN
303 error_anticipating_empty_fifo <= '0';
303 error_anticipating_empty_fifo <= '0';
304 state <= TRASH_FIFO;
304 state <= TRASH_FIFO;
305 END IF;
305 END IF;
306
306
307 WHEN CHECK_LENGTH =>
307 WHEN CHECK_LENGTH =>
308 state <= IDLE;
308 state <= IDLE;
309 WHEN OTHERS => NULL;
309 WHEN OTHERS => NULL;
310 END CASE;
310 END CASE;
311
311
312 END IF;
312 END IF;
313 END PROCESS DMAWriteFSM_p;
313 END PROCESS DMAWriteFSM_p;
314
314
315 -----------------------------------------------------------------------------
315 -----------------------------------------------------------------------------
316 -- SEND 1 word by DMA
316 -- SEND 1 word by DMA
317 -----------------------------------------------------------------------------
317 -----------------------------------------------------------------------------
318 lpp_dma_send_1word_1 : lpp_dma_send_1word
318 lpp_dma_send_1word_1 : lpp_dma_send_1word
319 PORT MAP (
319 PORT MAP (
320 HCLK => HCLK,
320 HCLK => HCLK,
321 HRESETn => HRESETn,
321 HRESETn => HRESETn,
322 DMAIn => header_dmai,
322 DMAIn => header_dmai,
323 DMAOut => DMAOut,
323 DMAOut => DMAOut,
324
324
325 send => header_send,
325 send => header_send,
326 address => address,
326 address => address,
327 data => header_data,
327 data => header_data,
328 send_ok => header_send_ok,
328 send_ok => header_send_ok,
329 send_ko => header_send_ko
329 send_ko => header_send_ko
330 );
330 );
331
331
332 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
333 -- SEND 16 word by DMA (in burst mode)
333 -- SEND 16 word by DMA (in burst mode)
334 -----------------------------------------------------------------------------
334 -----------------------------------------------------------------------------
335 lpp_dma_send_16word_1 : lpp_dma_send_16word
335 lpp_dma_send_16word_1 : lpp_dma_send_16word
336 PORT MAP (
336 PORT MAP (
337 HCLK => HCLK,
337 HCLK => HCLK,
338 HRESETn => HRESETn,
338 HRESETn => HRESETn,
339 DMAIn => component_dmai,
339 DMAIn => component_dmai,
340 DMAOut => DMAOut,
340 DMAOut => DMAOut,
341
341
342 send => component_send,
342 send => component_send,
343 address => address,
343 address => address,
344 data => fifo_data,
344 data => fifo_data,
345 ren => component_fifo_ren,
345 ren => component_fifo_ren,
346 send_ok => component_send_ok,
346 send_ok => component_send_ok,
347 send_ko => component_send_ko);
347 send_ko => component_send_ko);
348
348
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
349 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
350 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
351
351
352 END Behavioral;
352 END Behavioral; No newline at end of file
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@@ -1,216 +1,217
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 use lpp.general_purpose.all;
26 use lpp.general_purpose.all;
26
27
27 --! Driver de l'ALU
28 --! Driver de l'ALU
28
29
29 entity ALU_Driver is
30 entity ALU_Driver is
30 generic(
31 generic(
31 Input_SZ_1 : integer := 16;
32 Input_SZ_1 : integer := 16;
32 Input_SZ_2 : integer := 16);
33 Input_SZ_2 : integer := 16);
33 port(
34 port(
34 clk : in std_logic; --! Horloge du composant
35 clk : in std_logic; --! Horloge du composant
35 reset : in std_logic; --! Reset general du composant
36 reset : in std_logic; --! Reset general du composant
36 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
37 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
37 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
38 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
38 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
39 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
39 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
40 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
40 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½
41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½
41 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
42 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
42 Read : out std_logic; --! Flag, opοΏ½rande disponible
43 Read : out std_logic; --! Flag, opοΏ½rande disponible
43 CTRL : out std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
44 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes
45 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
46 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second OpοΏ½rande
47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second OpοΏ½rande
47 );
48 );
48 end ALU_Driver;
49 end ALU_Driver;
49
50
50 --! @details Les opοΏ½randes sont issue des donnοΏ½es d'entrοΏ½es et associοΏ½ aux bonnes valeurs sur CTRL, les diffοΏ½rentes opοΏ½rations sont effectuοΏ½es
51 --! @details Les opοΏ½randes sont issue des donnοΏ½es d'entrοΏ½es et associοΏ½ aux bonnes valeurs sur CTRL, les diffοΏ½rentes opοΏ½rations sont effectuοΏ½es
51
52
52 architecture ar_ALU_Driver of ALU_Driver is
53 architecture ar_ALU_Driver of ALU_Driver is
53
54
54 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
55 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
55 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
57 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
57 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
58 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
58
59
59 signal go_st : std_logic;
60 signal go_st : std_logic;
60 signal Take_reg : std_logic;
61 signal Take_reg : std_logic;
61 signal Received_reg : std_logic;
62 signal Received_reg : std_logic;
62
63
63 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
64 signal ect : etat;
65 signal ect : etat;
65 signal st : etat;
66 signal st : etat;
66
67
67 begin
68 begin
68 process(clk,reset)
69 process(clk,reset)
69 begin
70 begin
70
71
71 if(reset='0')then
72 if(reset='0')then
72 ect <= eX;
73 ect <= eX;
73 st <= e0;
74 st <= e0;
74 go_st <= '0';
75 go_st <= '0';
75 CTRL <= ctrl_CLRMAC;
76 CTRL <= ctrl_CLRMAC;
76 COMP <= "00"; -- pas de complement
77 COMP <= "00"; -- pas de complement
77 Read <= '0';
78 Read <= '0';
78 Valid <= '0';
79 Valid <= '0';
79 Take_reg <= '0';
80 Take_reg <= '0';
80 Received_reg <= '0';
81 Received_reg <= '0';
81
82
82 elsif(clk'event and clk='1')then
83 elsif(clk'event and clk='1')then
83 Take_reg <= Take;
84 Take_reg <= Take;
84 Received_reg <= Received;
85 Received_reg <= Received;
85
86
86 case ect is
87 case ect is
87 when eX =>
88 when eX =>
88 go_st <= '0';
89 go_st <= '0';
89 Read <= '1';
90 Read <= '1';
90 CTRL <= ctrl_CLRMAC;
91 CTRL <= ctrl_CLRMAC;
91 ect <= e0;
92 ect <= e0;
92
93
93 when e0 =>
94 when e0 =>
94 OP1re <= IN1;
95 OP1re <= IN1;
95 if(Conjugate='1')then --
96 if(Conjugate='1')then --
96 OP2re <= IN1; --
97 OP2re <= IN1; --
97 else --
98 else --
98 OP2re <= IN2; -- modif 23/06/11
99 OP2re <= IN2; -- modif 23/06/11
99 end if; --
100 end if; --
100 if(Take_reg='0' and Take='1')then
101 if(Take_reg='0' and Take='1')then
101 read <= '0';
102 read <= '0';
102 ect <= e1;
103 ect <= e1;
103 end if;
104 end if;
104
105
105 when e1 =>
106 when e1 =>
106 OP1 <= OP1re;
107 OP1 <= OP1re;
107 OP2 <= OP2re;
108 OP2 <= OP2re;
108 CTRL <= ctrl_MAC;
109 CTRL <= ctrl_MAC;
109 Read <= '1';
110 Read <= '1';
110 ect <= eY;
111 ect <= eY;
111
112
112 when eY =>
113 when eY =>
113 OP1im <= IN1;
114 OP1im <= IN1;
114 if(Conjugate='1')then --
115 if(Conjugate='1')then --
115 OP2im <= IN1; --
116 OP2im <= IN1; --
116 else --
117 else --
117 OP2im <= IN2; -- modif 23/06/11
118 OP2im <= IN2; -- modif 23/06/11
118 end if; --
119 end if; --
119 CTRL <= ctrl_IDLE;
120 CTRL <= ctrl_IDLE;
120 if(Take_reg='1' and Take='0')then
121 if(Take_reg='1' and Take='0')then
121 Read <= '0';
122 Read <= '0';
122 ect <= e2;
123 ect <= e2;
123 end if;
124 end if;
124
125
125 when e2 =>
126 when e2 =>
126 OP1 <= OP1im;
127 OP1 <= OP1im;
127 OP2 <= OP2im;
128 OP2 <= OP2im;
128 CTRL <= ctrl_MAC;
129 CTRL <= ctrl_MAC;
129 ect <= eZ;
130 ect <= eZ;
130
131
131 when eZ =>
132 when eZ =>
132 CTRL <= ctrl_IDLE;
133 CTRL <= ctrl_IDLE;
133 go_st <= '1';
134 go_st <= '1';
134 if(Received_reg='0' and Received='1')then
135 if(Received_reg='0' and Received='1')then
135 if(Conjugate='1')then
136 if(Conjugate='1')then
136 ect <= eX;
137 ect <= eX;
137 else
138 else
138 ect <= e3;
139 ect <= e3;
139 end if;
140 end if;
140 end if;
141 end if;
141
142
142 when e3 =>
143 when e3 =>
143 CTRL <= ctrl_CLRMAC;
144 CTRL <= ctrl_CLRMAC;
144 go_st <= '0';
145 go_st <= '0';
145 ect <= e4;
146 ect <= e4;
146
147
147 when e4 =>
148 when e4 =>
148 OP1 <= OP1im;
149 OP1 <= OP1im;
149 OP2 <= OP2re;
150 OP2 <= OP2re;
150 CTRL <= ctrl_MAC;
151 CTRL <= ctrl_MAC;
151 ect <= e5;
152 ect <= e5;
152
153
153 when e5 =>
154 when e5 =>
154 OP1 <= OP1re;
155 OP1 <= OP1re;
155 OP2 <= OP2im;
156 OP2 <= OP2im;
156 COMP <= "10";
157 COMP <= "10";
157 ect <= eW;
158 ect <= eW;
158
159
159 when eW =>
160 when eW =>
160 CTRL <= ctrl_IDLE;
161 CTRL <= ctrl_IDLE;
161 COMP <= "00";
162 COMP <= "00";
162 go_st <= '1';
163 go_st <= '1';
163 if(Received_reg='1' and Received='0')then
164 if(Received_reg='1' and Received='0')then
164 ect <= eX;
165 ect <= eX;
165 end if;
166 end if;
166 end case;
167 end case;
167 ---------------------------------------------------------------------------------
168 ---------------------------------------------------------------------------------
168 case st is
169 case st is
169 when e0 =>
170 when e0 =>
170 if(go_st='1')then
171 if(go_st='1')then
171 st <= e1;
172 st <= e1;
172 end if;
173 end if;
173
174
174 when e1 =>
175 when e1 =>
175 Valid <= '1';
176 Valid <= '1';
176 st <= e2;
177 st <= e2;
177
178
178 when e2 =>
179 when e2 =>
179 if(Received_reg='0' and Received='1')then
180 if(Received_reg='0' and Received='1')then
180 Valid <= '0';
181 Valid <= '0';
181 if(Conjugate='1')then
182 if(Conjugate='1')then
182 st <= eY;
183 st <= eY;
183 else
184 else
184 st <= eX;
185 st <= eX;
185 end if;
186 end if;
186 end if;
187 end if;
187
188
188 when eX =>
189 when eX =>
189 st <= e3;
190 st <= e3;
190
191
191 when e3 =>
192 when e3 =>
192 if(go_st='1')then
193 if(go_st='1')then
193 st <= e4;
194 st <= e4;
194 end if;
195 end if;
195
196
196 when e4 =>
197 when e4 =>
197 Valid <= '1';
198 Valid <= '1';
198 st <= e5;
199 st <= e5;
199
200
200 when e5 =>
201 when e5 =>
201 if(Received_reg='1' and Received='0')then
202 if(Received_reg='1' and Received='0')then
202 Valid <= '0';
203 Valid <= '0';
203 st <= eY;
204 st <= eY;
204 end if;
205 end if;
205
206
206 when eY =>
207 when eY =>
207 st <= e0;
208 st <= e0;
208
209
209 when others =>
210 when others =>
210 null;
211 null;
211 end case;
212 end case;
212
213
213 end if;
214 end if;
214 end process;
215 end process;
215
216
216 end ar_ALU_Driver; No newline at end of file
217 end ar_ALU_Driver;
Show file before | Show file after | Hide comments
@@ -1,87 +1,87
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 --library lpp;
25 library lpp;
26 --use lpp.lpp_matrix.all;
26 use lpp.lpp_matrix.all;
27
27
28 entity MatriceSpectrale is
28 entity MatriceSpectrale is
29 generic(
29 generic(
30 Input_SZ : integer := 16;
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
31 Result_SZ : integer := 32);
32 port(
32 port(
33 clkm : in std_logic;
33 clkm : in std_logic;
34 rstn : in std_logic;
34 rstn : in std_logic;
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
39 Valid : in std_logic;
39 Valid : in std_logic;
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
41 ACQ : in std_logic;
41 ACQ : in std_logic;
42 SM_Write : out std_logic;
42 SM_Write : out std_logic;
43 FlagError : out std_logic;
43 FlagError : out std_logic;
44 Pong : out std_logic;
44 Pong : out std_logic;
45 Statu : out std_logic_vector(3 downto 0);
45 Statu : out std_logic_vector(3 downto 0);
46 Write : out std_logic_vector(1 downto 0);
46 Write : out std_logic_vector(1 downto 0);
47 Read : out std_logic_vector(4 downto 0);
47 Read : out std_logic_vector(4 downto 0);
48 ReUse : out std_logic_vector(4 downto 0);
48 ReUse : out std_logic_vector(4 downto 0);
49 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
49 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
50 );
50 );
51 end entity;
51 end entity;
52
52
53
53
54 architecture ar_MatriceSpectrale of MatriceSpectrale is
54 architecture ar_MatriceSpectrale of MatriceSpectrale is
55
55
56 signal Matrix_Write : std_logic;
56 signal Matrix_Write : std_logic;
57 signal Matrix_Read : std_logic_vector(1 downto 0);
57 signal Matrix_Read : std_logic_vector(1 downto 0);
58 signal Matrix_Result : std_logic_vector(31 downto 0);
58 signal Matrix_Result : std_logic_vector(31 downto 0);
59
59
60 signal TopSM_Start : std_logic;
60 signal TopSM_Start : std_logic;
61 signal TopSM_Statu : std_logic_vector(3 downto 0);
61 signal TopSM_Statu : std_logic_vector(3 downto 0);
62 signal TopSM_Data1 : std_logic_vector(15 downto 0);
62 signal TopSM_Data1 : std_logic_vector(15 downto 0);
63 signal TopSM_Data2 : std_logic_vector(15 downto 0);
63 signal TopSM_Data2 : std_logic_vector(15 downto 0);
64
64
65 begin
65 begin
66
66
67 CTRL0 : entity work.ReUse_CTRLR
67 CTRL0 : ReUse_CTRLR
68 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
68 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
69
69
70
70
71 TopSM : entity work.TopSpecMatrix
71 TopSM : TopSpecMatrix
72 generic map (Input_SZ)
72 generic map (Input_SZ)
73 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
73 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
74
74
75 SM : entity work.SpectralMatrix
75 SM : SpectralMatrix
76 generic map (Input_SZ,Result_SZ)
76 generic map (Input_SZ,Result_SZ)
77 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
77 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
78
78
79 DISP : entity work.Dispatch
79 DISP : Dispatch
80 generic map(Result_SZ)
80 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
82
82
83 Statu <= TopSM_Statu;
83 Statu <= TopSM_Statu;
84 SM_Write <= Matrix_Write;
84 SM_Write <= Matrix_Write;
85
85
86 end architecture;
86 end architecture;
87
87
Show file before | Show file after | Hide comments
@@ -1,84 +1,85
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 use lpp.lpp_matrix.all;
26 use lpp.lpp_matrix.all;
26
27
27 entity SpectralMatrix is
28 entity SpectralMatrix is
28 generic(
29 generic(
29 Input_SZ : integer := 16;
30 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
31 Result_SZ : integer := 32);
31 port(
32 port(
32 clk : in std_logic;
33 clk : in std_logic;
33 reset : in std_logic;
34 reset : in std_logic;
34 Start : in std_logic;
35 Start : in std_logic;
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 Statu : in std_logic_vector(3 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
38 -- FullFIFO : in std_logic;
39 -- FullFIFO : in std_logic;
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
41 WriteFIFO : out std_logic;
41 Result : out std_logic_vector(Result_SZ-1 downto 0)
42 Result : out std_logic_vector(Result_SZ-1 downto 0)
42 );
43 );
43 end SpectralMatrix;
44 end SpectralMatrix;
44
45
45
46
46 architecture ar_SpectralMatrix of SpectralMatrix is
47 architecture ar_SpectralMatrix of SpectralMatrix is
47
48
48 signal RaZ : std_logic;
49 signal RaZ : std_logic;
49 signal Read_int : std_logic;
50 signal Read_int : std_logic;
50 signal Take_int : std_logic;
51 signal Take_int : std_logic;
51 signal Received_int : std_logic;
52 signal Received_int : std_logic;
52 signal Valid_int : std_logic;
53 signal Valid_int : std_logic;
53 signal Conjugate_int : std_logic;
54 signal Conjugate_int : std_logic;
54
55
55 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
56 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
56
57
57
58
58 begin
59 begin
59
60
60 RaZ <= reset and Start;
61 RaZ <= reset and Start;
61
62
62 IN1 : DriveInputs
63 IN1 : DriveInputs
63 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
64 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
64
65
65
66
66 CALC0 : Matrix
67 CALC0 : Matrix
67 generic map(Input_SZ)
68 generic map(Input_SZ)
68 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
69 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
69
70
70
71
71 RES0 : GetResult
72 RES0 : GetResult
72 generic map(Result_SZ)
73 generic map(Result_SZ)
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
74 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
74
75
75
76
76 With Statu select
77 With Statu select
77 Conjugate_int <= '1' when "0001",
78 Conjugate_int <= '1' when "0001",
78 '1' when "0011",
79 '1' when "0011",
79 '1' when "0110",
80 '1' when "0110",
80 '1' when "1010",
81 '1' when "1010",
81 '1' when "1111",
82 '1' when "1111",
82 '0' when others;
83 '0' when others;
83
84
84 end ar_SpectralMatrix; No newline at end of file
85 end ar_SpectralMatrix;
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