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LFR-EQM 2.1.83...
pellion -
r601:1b6a99d2ea09 (LFR-EQM) 2-1-83 simu_with_Leon3
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
49
49
50 --library proasic3l;
50 --library proasic3l;
51 --use proasic3l.all;
51 --use proasic3l.all;
52
52
53 ENTITY LFR_EQM IS
53 ENTITY LFR_EQM IS
54 GENERIC (
54 GENERIC (
55 Mem_use : INTEGER := use_RAM;
55 Mem_use : INTEGER := use_RAM;
56 USE_BOOTLOADER : INTEGER := 0;
56 USE_BOOTLOADER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 1;
57 USE_ADCDRIVER : INTEGER := 1;
58 tech : INTEGER := apa3e;
58 tech : INTEGER := apa3e;
59 tech_leon : INTEGER := apa3e;
59 tech_leon : INTEGER := apa3e;
60 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
60 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 USE_DEBUG_VECTOR : INTEGER := 0
61 USE_DEBUG_VECTOR : INTEGER := 0
62 );
62 );
63
63
64 PORT (
64 PORT (
65 clk50MHz : IN STD_ULOGIC;
65 clk50MHz : IN STD_ULOGIC;
66 clk49_152MHz : IN STD_ULOGIC;
66 clk49_152MHz : IN STD_ULOGIC;
67 reset : IN STD_ULOGIC;
67 reset : IN STD_ULOGIC;
68
68
69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70
70
71 -- TAG --------------------------------------------------------------------
71 -- TAG --------------------------------------------------------------------
72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 -- UART APB ---------------------------------------------------------------
74 -- UART APB ---------------------------------------------------------------
75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 -- RAM --------------------------------------------------------------------
77 -- RAM --------------------------------------------------------------------
78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80
80
81 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 nSRAM_E2 : OUT STD_LOGIC; -- new
83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_W : OUT STD_LOGIC; -- new
86 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_G : OUT STD_LOGIC; -- new
87 nSRAM_BUSY : IN STD_LOGIC; -- new
87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 -- SPW --------------------------------------------------------------------
88 -- SPW --------------------------------------------------------------------
89 spw1_en : OUT STD_LOGIC; -- new
89 spw1_en : OUT STD_LOGIC; -- new
90 spw1_din : IN STD_LOGIC;
90 spw1_din : IN STD_LOGIC;
91 spw1_sin : IN STD_LOGIC;
91 spw1_sin : IN STD_LOGIC;
92 spw1_dout : OUT STD_LOGIC;
92 spw1_dout : OUT STD_LOGIC;
93 spw1_sout : OUT STD_LOGIC;
93 spw1_sout : OUT STD_LOGIC;
94 spw2_en : OUT STD_LOGIC; -- new
94 spw2_en : OUT STD_LOGIC; -- new
95 spw2_din : IN STD_LOGIC;
95 spw2_din : IN STD_LOGIC;
96 spw2_sin : IN STD_LOGIC;
96 spw2_sin : IN STD_LOGIC;
97 spw2_dout : OUT STD_LOGIC;
97 spw2_dout : OUT STD_LOGIC;
98 spw2_sout : OUT STD_LOGIC;
98 spw2_sout : OUT STD_LOGIC;
99 -- ADC --------------------------------------------------------------------
99 -- ADC --------------------------------------------------------------------
100 bias_fail_sw : OUT STD_LOGIC;
100 bias_fail_sw : OUT STD_LOGIC;
101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 ADC_smpclk : OUT STD_LOGIC;
102 ADC_smpclk : OUT STD_LOGIC;
103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 -- DAC --------------------------------------------------------------------
104 -- DAC --------------------------------------------------------------------
105 DAC_SDO : OUT STD_LOGIC;
105 DAC_SDO : OUT STD_LOGIC;
106 DAC_SCK : OUT STD_LOGIC;
106 DAC_SCK : OUT STD_LOGIC;
107 DAC_SYNC : OUT STD_LOGIC;
107 DAC_SYNC : OUT STD_LOGIC;
108 DAC_CAL_EN : OUT STD_LOGIC;
108 DAC_CAL_EN : OUT STD_LOGIC;
109 -- HK ---------------------------------------------------------------------
109 -- HK ---------------------------------------------------------------------
110 HK_smpclk : OUT STD_LOGIC;
110 HK_smpclk : OUT STD_LOGIC;
111 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 ---------------------------------------------------------------------------
113 ---------------------------------------------------------------------------
114 -- TAG8 : OUT STD_LOGIC
114 -- TAG8 : OUT STD_LOGIC
115 );
115 );
116
116
117 END LFR_EQM;
117 END LFR_EQM;
118
118
119
119
120 ARCHITECTURE beh OF LFR_EQM IS
120 ARCHITECTURE beh OF LFR_EQM IS
121
121
122 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127
127
128 -- CONSTANTS
128 -- CONSTANTS
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133
133
134 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbi_ext : apb_slv_in_type;
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140
140
141 -- Spacewire signals
141 -- Spacewire signals
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 SIGNAL spw_rxtxclk : STD_ULOGIC;
145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 SIGNAL spw_rxclkn : STD_ULOGIC;
146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 SIGNAL spw_clk : STD_LOGIC;
147 SIGNAL spw_clk : STD_LOGIC;
148 SIGNAL swni : grspw_in_type;
148 SIGNAL swni : grspw_in_type;
149 SIGNAL swno : grspw_out_type;
149 SIGNAL swno : grspw_out_type;
150
150
151 --GPIO
151 --GPIO
152 SIGNAL gpioi : gpio_in_type;
152 SIGNAL gpioi : gpio_in_type;
153 SIGNAL gpioo : gpio_out_type;
153 SIGNAL gpioo : gpio_out_type;
154
154
155 -- AD Converter ADS7886
155 -- AD Converter ADS7886
156 SIGNAL sample : Samples14v(8 DOWNTO 0);
156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 SIGNAL sample_s : Samples(8 DOWNTO 0);
157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
158 SIGNAL sample_val : STD_LOGIC;
159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160
160
161 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163
163
164 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
165 SIGNAL rstn_25 : STD_LOGIC;
165 SIGNAL rstn_25 : STD_LOGIC;
166 SIGNAL rstn_24 : STD_LOGIC;
166 SIGNAL rstn_24 : STD_LOGIC;
167
167
168 SIGNAL LFR_soft_rstn : STD_LOGIC;
168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 SIGNAL LFR_rstn : STD_LOGIC;
169 SIGNAL LFR_rstn : STD_LOGIC;
170
170
171 SIGNAL ADC_smpclk_s : STD_LOGIC;
171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172
172
173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174
174
175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 SIGNAL clk_25_int : STD_LOGIC := '0';
176 SIGNAL clk_25_int : STD_LOGIC := '0';
177
177
178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179
179
180 SIGNAL rstn_50 : STD_LOGIC;
180 SIGNAL rstn_50 : STD_LOGIC;
181 SIGNAL clk_lock : STD_LOGIC;
181 SIGNAL clk_lock : STD_LOGIC;
182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184
184
185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL ahbrxd: STD_LOGIC;
186 SIGNAL ahbrxd: STD_LOGIC;
187 SIGNAL ahbtxd: STD_LOGIC;
187 SIGNAL ahbtxd: STD_LOGIC;
188 SIGNAL urxd1 : STD_LOGIC;
188 SIGNAL urxd1 : STD_LOGIC;
189 SIGNAL utxd1 : STD_LOGIC;
189 SIGNAL utxd1 : STD_LOGIC;
190 BEGIN -- beh
190 BEGIN -- beh
191
191
192 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
193 -- CLK_LOCK
193 -- CLK_LOCK
194 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196
196
197 PROCESS (clk50MHz_int, rstn_50)
197 PROCESS (clk50MHz_int, rstn_50)
198 BEGIN -- PROCESS
198 BEGIN -- PROCESS
199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 clk_lock <= '0';
200 clk_lock <= '0';
201 clk_busy_counter <= (OTHERS => '0');
201 clk_busy_counter <= (OTHERS => '0');
202 nSRAM_BUSY_reg <= '0';
202 nSRAM_BUSY_reg <= '0';
203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 nSRAM_BUSY_reg <= nSRAM_BUSY;
204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 IF clk_busy_counter = "1111" THEN
206 IF clk_busy_counter = "1111" THEN
207 clk_lock <= '1';
207 clk_lock <= '1';
208 ELSE
208 ELSE
209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 END IF;
210 END IF;
211 END IF;
211 END IF;
212 END IF;
212 END IF;
213 END PROCESS;
213 END PROCESS;
214
214
215 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
216 -- CLK
216 -- CLK
217 -----------------------------------------------------------------------------
217 -----------------------------------------------------------------------------
218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220
220
221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 clk50MHz_int <= clk50MHz;
222 clk50MHz_int <= clk50MHz;
223
223
224 PROCESS(clk50MHz_int)
224 PROCESS(clk50MHz_int)
225 BEGIN
225 BEGIN
226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 --clk_25_int <= NOT clk_25_int;
227 --clk_25_int <= NOT clk_25_int;
228 clk_25 <= NOT clk_25;
228 clk_25 <= NOT clk_25;
229 END IF;
229 END IF;
230 END PROCESS;
230 END PROCESS;
231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232
232
233 PROCESS(clk49_152MHz)
233 PROCESS(clk49_152MHz)
234 BEGIN
234 BEGIN
235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 clk_24 <= NOT clk_24;
236 clk_24 <= NOT clk_24;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239 -- clk_49 <= clk49_152MHz;
239 -- clk_49 <= clk49_152MHz;
240
240
241 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
242 --
242 --
243 leon3_soc_1 : leon3_soc
243 leon3_soc_1 : leon3_soc
244 GENERIC MAP (
244 GENERIC MAP (
245 fabtech => tech_leon,
245 fabtech => tech_leon,
246 memtech => tech_leon,
246 memtech => tech_leon,
247 padtech => inferred,
247 padtech => inferred,
248 clktech => inferred,
248 clktech => inferred,
249 disas => 0,
249 disas => 0,
250 dbguart => 0,
250 dbguart => 0,
251 pclow => 2,
251 pclow => 2,
252 clk_freq => 25000,
252 clk_freq => 25000,
253 IS_RADHARD => 0,
253 IS_RADHARD => 0,
254 NB_CPU => 1,
254 NB_CPU => 1,
255 ENABLE_FPU => 1,
255 ENABLE_FPU => 1,
256 FPU_NETLIST => 0,
256 FPU_NETLIST => 0,
257 ENABLE_DSU => 1,
257 ENABLE_DSU => 1,
258 ENABLE_AHB_UART => 1,
258 ENABLE_AHB_UART => 1,
259 ENABLE_APB_UART => 1,
259 ENABLE_APB_UART => 1,
260 ENABLE_IRQMP => 1,
260 ENABLE_IRQMP => 1,
261 ENABLE_GPT => 1,
261 ENABLE_GPT => 1,
262 NB_AHB_MASTER => NB_AHB_MASTER,
262 NB_AHB_MASTER => NB_AHB_MASTER,
263 NB_AHB_SLAVE => NB_AHB_SLAVE,
263 NB_AHB_SLAVE => NB_AHB_SLAVE,
264 NB_APB_SLAVE => NB_APB_SLAVE,
264 NB_APB_SLAVE => NB_APB_SLAVE,
265 ADDRESS_SIZE => 19,
265 ADDRESS_SIZE => 19,
266 USES_IAP_MEMCTRLR => 1,
266 USES_IAP_MEMCTRLR => 1,
267 BYPASS_EDAC_MEMCTRLR => '0',
267 BYPASS_EDAC_MEMCTRLR => '0',
268 SRBANKSZ => 8)
268 SRBANKSZ => 8)
269 PORT MAP (
269 PORT MAP (
270 clk => clk_25,
270 clk => clk_25,
271 reset => rstn_25,
271 reset => rstn_25,
272 errorn => OPEN,
272 errorn => OPEN,
273
273
274 ahbrxd => ahbrxd, -- INPUT
274 ahbrxd => ahbrxd, -- INPUT
275 ahbtxd => ahbtxd, -- OUTPUT
275 ahbtxd => ahbtxd, -- OUTPUT
276 urxd1 => urxd1, -- INPUT
276 urxd1 => urxd1, -- INPUT
277 utxd1 => utxd1, -- OUTPUT
277 utxd1 => utxd1, -- OUTPUT
278
278
279 address => address,
279 address => address,
280 data => data,
280 data => data,
281 nSRAM_BE0 => OPEN,
281 nSRAM_BE0 => OPEN,
282 nSRAM_BE1 => OPEN,
282 nSRAM_BE1 => OPEN,
283 nSRAM_BE2 => OPEN,
283 nSRAM_BE2 => OPEN,
284 nSRAM_BE3 => OPEN,
284 nSRAM_BE3 => OPEN,
285 nSRAM_WE => nSRAM_W,
285 nSRAM_WE => nSRAM_W,
286 nSRAM_CE => nSRAM_CE,
286 nSRAM_CE => nSRAM_CE,
287 nSRAM_OE => nSRAM_G,
287 nSRAM_OE => nSRAM_G,
288 nSRAM_READY => nSRAM_BUSY,
288 nSRAM_READY => nSRAM_BUSY,
289 SRAM_MBE => nSRAM_MBE,
289 SRAM_MBE => nSRAM_MBE,
290
290
291 apbi_ext => apbi_ext,
291 apbi_ext => apbi_ext,
292 apbo_ext => apbo_ext,
292 apbo_ext => apbo_ext,
293 ahbi_s_ext => ahbi_s_ext,
293 ahbi_s_ext => ahbi_s_ext,
294 ahbo_s_ext => ahbo_s_ext,
294 ahbo_s_ext => ahbo_s_ext,
295 ahbi_m_ext => ahbi_m_ext,
295 ahbi_m_ext => ahbi_m_ext,
296 ahbo_m_ext => ahbo_m_ext);
296 ahbo_m_ext => ahbo_m_ext);
297
297
298
298
299 nSRAM_E1 <= nSRAM_CE(0);
299 nSRAM_E1 <= nSRAM_CE(0);
300 nSRAM_E2 <= nSRAM_CE(1);
300 nSRAM_E2 <= nSRAM_CE(1);
301
301
302 -------------------------------------------------------------------------------
302 -------------------------------------------------------------------------------
303 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
303 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
304 -------------------------------------------------------------------------------
304 -------------------------------------------------------------------------------
305 apb_lfr_management_1 : apb_lfr_management
305 apb_lfr_management_1 : apb_lfr_management
306 GENERIC MAP (
306 GENERIC MAP (
307 tech => tech,
307 tech => tech,
308 pindex => 6,
308 pindex => 6,
309 paddr => 6,
309 paddr => 6,
310 pmask => 16#fff#,
310 pmask => 16#fff#,
311 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
311 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
312 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
312 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
313 PORT MAP (
313 PORT MAP (
314 clk25MHz => clk_25,
314 clk25MHz => clk_25,
315 resetn_25MHz => rstn_25, -- TODO
315 resetn_25MHz => rstn_25, -- TODO
316 --clk24_576MHz => clk_24, -- 49.152MHz/2
316 --clk24_576MHz => clk_24, -- 49.152MHz/2
317 --resetn_24_576MHz => rstn_24, -- TODO
317 --resetn_24_576MHz => rstn_24, -- TODO
318
318
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322
322
323 HK_sample => sample_s(8),
323 HK_sample => sample_s(8),
324 HK_val => sample_val,
324 HK_val => sample_val,
325 HK_sel => HK_SEL,
325 HK_sel => HK_SEL,
326
326
327 DAC_SDO => DAC_SDO,
327 DAC_SDO => DAC_SDO,
328 DAC_SCK => DAC_SCK,
328 DAC_SCK => DAC_SCK,
329 DAC_SYNC => DAC_SYNC,
329 DAC_SYNC => DAC_SYNC,
330 DAC_CAL_EN => DAC_CAL_EN,
330 DAC_CAL_EN => DAC_CAL_EN,
331
331
332 coarse_time => coarse_time,
332 coarse_time => coarse_time,
333 fine_time => fine_time,
333 fine_time => fine_time,
334 LFR_soft_rstn => LFR_soft_rstn
334 LFR_soft_rstn => LFR_soft_rstn
335 );
335 );
336
336
337 -----------------------------------------------------------------------
337 -----------------------------------------------------------------------
338 --- SpaceWire --------------------------------------------------------
338 --- SpaceWire --------------------------------------------------------
339 -----------------------------------------------------------------------
339 -----------------------------------------------------------------------
340
340
341 ------------------------------------------------------------------------------
341 ------------------------------------------------------------------------------
342 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
342 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
343 ------------------------------------------------------------------------------
343 ------------------------------------------------------------------------------
344 spw1_en <= '1';
344 spw1_en <= '1';
345 spw2_en <= '1';
345 spw2_en <= '1';
346 ------------------------------------------------------------------------------
346 ------------------------------------------------------------------------------
347 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
347 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
348 ------------------------------------------------------------------------------
348 ------------------------------------------------------------------------------
349
349
350 --spw_clk <= clk50MHz;
350 --spw_clk <= clk50MHz;
351 --spw_rxtxclk <= spw_clk;
351 --spw_rxtxclk <= spw_clk;
352 --spw_rxclkn <= NOT spw_rxtxclk;
352 --spw_rxclkn <= NOT spw_rxtxclk;
353
353
354 -- PADS for SPW1
354 -- PADS for SPW1
355 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
355 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
356 PORT MAP (spw1_din, dtmp(0));
356 PORT MAP (spw1_din, dtmp(0));
357 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
357 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
358 PORT MAP (spw1_sin, stmp(0));
358 PORT MAP (spw1_sin, stmp(0));
359 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
359 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
360 PORT MAP (spw1_dout, swno.d(0));
360 PORT MAP (spw1_dout, swno.d(0));
361 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
361 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
362 PORT MAP (spw1_sout, swno.s(0));
362 PORT MAP (spw1_sout, swno.s(0));
363 -- PADS FOR SPW2
363 -- PADS FOR SPW2
364 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
364 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
365 PORT MAP (spw2_din, dtmp(1));
365 PORT MAP (spw2_din, dtmp(1));
366 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
366 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
367 PORT MAP (spw2_sin, stmp(1));
367 PORT MAP (spw2_sin, stmp(1));
368 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
368 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
369 PORT MAP (spw2_dout, swno.d(1));
369 PORT MAP (spw2_dout, swno.d(1));
370 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
370 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
371 PORT MAP (spw2_sout, swno.s(1));
371 PORT MAP (spw2_sout, swno.s(1));
372
372
373 -- GRSPW PHY
373 -- GRSPW PHY
374 --spw1_input: if CFG_SPW_GRSPW = 1 generate
374 --spw1_input: if CFG_SPW_GRSPW = 1 generate
375 spw_inputloop : FOR j IN 0 TO 1 GENERATE
375 spw_inputloop : FOR j IN 0 TO 1 GENERATE
376 spw_phy0 : grspw_phy
376 spw_phy0 : grspw_phy
377 GENERIC MAP(
377 GENERIC MAP(
378 tech => tech_leon,
378 tech => tech_leon,
379 rxclkbuftype => 1,
379 rxclkbuftype => 1,
380 scantest => 0)
380 scantest => 0)
381 PORT MAP(
381 PORT MAP(
382 rxrst => swno.rxrst,
382 rxrst => swno.rxrst,
383 di => dtmp(j),
383 di => dtmp(j),
384 si => stmp(j),
384 si => stmp(j),
385 rxclko => spw_rxclk(j),
385 rxclko => spw_rxclk(j),
386 do => swni.d(j),
386 do => swni.d(j),
387 ndo => swni.nd(j*5+4 DOWNTO j*5),
387 ndo => swni.nd(j*5+4 DOWNTO j*5),
388 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
388 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
389 END GENERATE spw_inputloop;
389 END GENERATE spw_inputloop;
390
390
391 -- SPW core
391 -- SPW core
392 sw0 : grspwm GENERIC MAP(
392 sw0 : grspwm GENERIC MAP(
393 tech => tech_leon,
393 tech => tech_leon,
394 hindex => 1,
394 hindex => 1,
395 pindex => 5,
395 pindex => 5,
396 paddr => 5,
396 paddr => 5,
397 pirq => 11,
397 pirq => 11,
398 sysfreq => 25000, -- CPU_FREQ
398 sysfreq => 25000, -- CPU_FREQ
399 rmap => 1,
399 rmap => 1,
400 rmapcrc => 1,
400 rmapcrc => 1,
401 fifosize1 => 16,
401 fifosize1 => 16,
402 fifosize2 => 16,
402 fifosize2 => 16,
403 rxclkbuftype => 1,
403 rxclkbuftype => 1,
404 rxunaligned => 0,
404 rxunaligned => 0,
405 rmapbufs => 4,
405 rmapbufs => 4,
406 ft => 0,
406 ft => 0,
407 netlist => 0,
407 netlist => 0,
408 ports => 2,
408 ports => 2,
409 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
409 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
410 memtech => tech_leon,
410 memtech => tech_leon,
411 destkey => 2,
411 destkey => 2,
412 spwcore => 1
412 spwcore => 1
413 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
413 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
414 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
414 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
415 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
415 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
416 )
416 )
417 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
417 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
418 spw_rxclk(1),
418 spw_rxclk(1),
419 clk50MHz_int,
419 clk50MHz_int,
420 clk50MHz_int,
420 clk50MHz_int,
421 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
421 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
422 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
422 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
423 swni, swno);
423 swni, swno);
424
424
425 swni.tickin <= '0';
425 swni.tickin <= '0';
426 swni.rmapen <= '1';
426 swni.rmapen <= '1';
427 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
427 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
428 swni.tickinraw <= '0';
428 swni.tickinraw <= '0';
429 swni.timein <= (OTHERS => '0');
429 swni.timein <= (OTHERS => '0');
430 swni.dcrstval <= (OTHERS => '0');
430 swni.dcrstval <= (OTHERS => '0');
431 swni.timerrstval <= (OTHERS => '0');
431 swni.timerrstval <= (OTHERS => '0');
432
432
433 -------------------------------------------------------------------------------
433 -------------------------------------------------------------------------------
434 -- LFR ------------------------------------------------------------------------
434 -- LFR ------------------------------------------------------------------------
435 -------------------------------------------------------------------------------
435 -------------------------------------------------------------------------------
436 LFR_rstn <= LFR_soft_rstn AND rstn_25;
436 LFR_rstn <= LFR_soft_rstn AND rstn_25;
437
437
438 lpp_lfr_1 : lpp_lfr
438 lpp_lfr_1 : lpp_lfr
439 GENERIC MAP (
439 GENERIC MAP (
440 Mem_use => Mem_use,
440 Mem_use => Mem_use,
441 tech => tech,
441 tech => tech,
442 nb_data_by_buffer_size => 32,
442 nb_data_by_buffer_size => 32,
443 --nb_word_by_buffer_size => 30,
443 --nb_word_by_buffer_size => 30,
444 nb_snapshot_param_size => 32,
444 nb_snapshot_param_size => 32,
445 delta_vector_size => 32,
445 delta_vector_size => 32,
446 delta_vector_size_f0_2 => 7, -- log2(96)
446 delta_vector_size_f0_2 => 7, -- log2(96)
447 pindex => 15,
447 pindex => 15,
448 paddr => 15,
448 paddr => 15,
449 pmask => 16#fff#,
449 pmask => 16#fff#,
450 pirq_ms => 6,
450 pirq_ms => 6,
451 pirq_wfp => 14,
451 pirq_wfp => 14,
452 hindex => 2,
452 hindex => 2,
453 top_lfr_version => X"020152", -- aa.bb.cc version
453 top_lfr_version => X"020153", -- aa.bb.cc version
454 -- AA : BOARD NUMBER
454 -- AA : BOARD NUMBER
455 -- 0 => MINI_LFR
455 -- 0 => MINI_LFR
456 -- 1 => EM
456 -- 1 => EM
457 -- 2 => EQM (with A3PE3000)
457 -- 2 => EQM (with A3PE3000)
458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
459 PORT MAP (
459 PORT MAP (
460 clk => clk_25,
460 clk => clk_25,
461 rstn => LFR_rstn,
461 rstn => LFR_rstn,
462 sample_B => sample_s(2 DOWNTO 0),
462 sample_B => sample_s(2 DOWNTO 0),
463 sample_E => sample_s(7 DOWNTO 3),
463 sample_E => sample_s(7 DOWNTO 3),
464 sample_val => sample_val,
464 sample_val => sample_val,
465 apbi => apbi_ext,
465 apbi => apbi_ext,
466 apbo => apbo_ext(15),
466 apbo => apbo_ext(15),
467 ahbi => ahbi_m_ext,
467 ahbi => ahbi_m_ext,
468 ahbo => ahbo_m_ext(2),
468 ahbo => ahbo_m_ext(2),
469 coarse_time => coarse_time,
469 coarse_time => coarse_time,
470 fine_time => fine_time,
470 fine_time => fine_time,
471 data_shaping_BW => bias_fail_sw,
471 data_shaping_BW => bias_fail_sw,
472 debug_vector => debug_vector,
472 debug_vector => debug_vector,
473 debug_vector_ms => OPEN); --,
473 debug_vector_ms => OPEN); --,
474 --observation_vector_0 => OPEN,
474 --observation_vector_0 => OPEN,
475 --observation_vector_1 => OPEN,
475 --observation_vector_1 => OPEN,
476 --observation_reg => observation_reg);
476 --observation_reg => observation_reg);
477
477
478
478
479 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
479 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
480 sample_s(I) <= sample(I) & '0' & '0';
480 sample_s(I) <= sample(I) & '0' & '0';
481 END GENERATE all_sample;
481 END GENERATE all_sample;
482 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
482 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
483
483
484 -----------------------------------------------------------------------------
484 -----------------------------------------------------------------------------
485 --
485 --
486 -----------------------------------------------------------------------------
486 -----------------------------------------------------------------------------
487 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
487 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
488 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
488 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
489 GENERIC MAP (
489 GENERIC MAP (
490 ChanelCount => 9,
490 ChanelCount => 9,
491 ncycle_cnv_high => 12,
491 ncycle_cnv_high => 12,
492 ncycle_cnv => 25,
492 ncycle_cnv => 25,
493 FILTER_ENABLED => 16#FF#)
493 FILTER_ENABLED => 16#FF#)
494 PORT MAP (
494 PORT MAP (
495 cnv_clk => clk_24,
495 cnv_clk => clk_24,
496 cnv_rstn => rstn_24,
496 cnv_rstn => rstn_24,
497 cnv => ADC_smpclk_s,
497 cnv => ADC_smpclk_s,
498 clk => clk_25,
498 clk => clk_25,
499 rstn => rstn_25,
499 rstn => rstn_25,
500 ADC_data => ADC_data,
500 ADC_data => ADC_data,
501 ADC_nOE => ADC_OEB_bar_CH_s,
501 ADC_nOE => ADC_OEB_bar_CH_s,
502 sample => sample,
502 sample => sample,
503 sample_val => sample_val);
503 sample_val => sample_val);
504
504
505 END GENERATE USE_ADCDRIVER_true;
505 END GENERATE USE_ADCDRIVER_true;
506
506
507 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
507 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
508 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
508 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
509 GENERIC MAP (
509 GENERIC MAP (
510 ChanelCount => 9,
510 ChanelCount => 9,
511 ncycle_cnv_high => 25,
511 ncycle_cnv_high => 25,
512 ncycle_cnv => 50,
512 ncycle_cnv => 50,
513 FILTER_ENABLED => 16#FF#)
513 FILTER_ENABLED => 16#FF#)
514 PORT MAP (
514 PORT MAP (
515 cnv_clk => clk_24,
515 cnv_clk => clk_24,
516 cnv_rstn => rstn_24,
516 cnv_rstn => rstn_24,
517 cnv => ADC_smpclk_s,
517 cnv => ADC_smpclk_s,
518 clk => clk_25,
518 clk => clk_25,
519 rstn => rstn_25,
519 rstn => rstn_25,
520 ADC_data => ADC_data,
520 ADC_data => ADC_data,
521 ADC_nOE => OPEN,
521 ADC_nOE => OPEN,
522 sample => OPEN,
522 sample => OPEN,
523 sample_val => sample_val);
523 sample_val => sample_val);
524
524
525 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
525 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
526
526
527 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
527 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
528 ramp_generator_1: ramp_generator
528 ramp_generator_1: ramp_generator
529 GENERIC MAP (
529 GENERIC MAP (
530 DATA_SIZE => 14,
530 DATA_SIZE => 14,
531 VALUE_UNSIGNED_INIT => 2**I,
531 VALUE_UNSIGNED_INIT => 2**I,
532 VALUE_UNSIGNED_INCR => 0,
532 VALUE_UNSIGNED_INCR => 0,
533 VALUE_UNSIGNED_MASK => 16#3FFF#)
533 VALUE_UNSIGNED_MASK => 16#3FFF#)
534 PORT MAP (
534 PORT MAP (
535 clk => clk_25,
535 clk => clk_25,
536 rstn => rstn_25,
536 rstn => rstn_25,
537 new_data => sample_val,
537 new_data => sample_val,
538 output_data => sample(I) );
538 output_data => sample(I) );
539 END GENERATE all_sample;
539 END GENERATE all_sample;
540
540
541
541
542 END GENERATE USE_ADCDRIVER_false;
542 END GENERATE USE_ADCDRIVER_false;
543
543
544
544
545
545
546
546
547 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
547 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
548
548
549 ADC_smpclk <= ADC_smpclk_s;
549 ADC_smpclk <= ADC_smpclk_s;
550 HK_smpclk <= ADC_smpclk_s;
550 HK_smpclk <= ADC_smpclk_s;
551
551
552
552
553 -----------------------------------------------------------------------------
553 -----------------------------------------------------------------------------
554 -- HK
554 -- HK
555 -----------------------------------------------------------------------------
555 -----------------------------------------------------------------------------
556 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
556 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
557
557
558 -----------------------------------------------------------------------------
558 -----------------------------------------------------------------------------
559 --
559 --
560 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
561 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
561 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
562 lpp_bootloader_1: lpp_bootloader
562 lpp_bootloader_1: lpp_bootloader
563 GENERIC MAP (
563 GENERIC MAP (
564 pindex => 13,
564 pindex => 13,
565 paddr => 13,
565 paddr => 13,
566 pmask => 16#fff#,
566 pmask => 16#fff#,
567 hindex => 3,
567 hindex => 3,
568 haddr => 0,
568 haddr => 0,
569 hmask => 16#fff#)
569 hmask => 16#fff#)
570 PORT MAP (
570 PORT MAP (
571 HCLK => clk_25,
571 HCLK => clk_25,
572 HRESETn => rstn_25,
572 HRESETn => rstn_25,
573 apbi => apbi_ext,
573 apbi => apbi_ext,
574 apbo => apbo_ext(13),
574 apbo => apbo_ext(13),
575 ahbsi => ahbi_s_ext,
575 ahbsi => ahbi_s_ext,
576 ahbso => ahbo_s_ext(3));
576 ahbso => ahbo_s_ext(3));
577 END GENERATE inst_bootloader;
577 END GENERATE inst_bootloader;
578
578
579 -----------------------------------------------------------------------------
579 -----------------------------------------------------------------------------
580 --
580 --
581 -----------------------------------------------------------------------------
581 -----------------------------------------------------------------------------
582 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
582 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
583 PROCESS (clk_25, rstn_25)
583 PROCESS (clk_25, rstn_25)
584 BEGIN -- PROCESS
584 BEGIN -- PROCESS
585 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
585 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
586 TAG <= (OTHERS => '0');
586 TAG <= (OTHERS => '0');
587 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
587 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
588 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
588 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
589 END IF;
589 END IF;
590 END PROCESS;
590 END PROCESS;
591
591
592
592
593 END GENERATE USE_DEBUG_VECTOR_IF;
593 END GENERATE USE_DEBUG_VECTOR_IF;
594
594
595 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
595 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
596 ahbrxd <= TAG(1);
596 ahbrxd <= TAG(1);
597 TAG(3) <= ahbtxd;
597 TAG(3) <= ahbtxd;
598 urxd1 <= TAG(2);
598 urxd1 <= TAG(2);
599 TAG(4) <= utxd1;
599 TAG(4) <= utxd1;
600 TAG(8) <= nSRAM_BUSY;
600 TAG(8) <= nSRAM_BUSY;
601 END GENERATE USE_DEBUG_VECTOR_IF2;
601 END GENERATE USE_DEBUG_VECTOR_IF2;
602
602
603 END beh;
603 END beh;
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@@ -1,301 +1,228
1
1
2 LIBRARY IEEE;
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.numeric_std.ALL;
4 USE IEEE.numeric_std.ALL;
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
7 USE lpp.general_purpose.SYNC_FF;
8
8
9 ENTITY top_ad_conv_RHF1401_withFilter IS
9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
10 GENERIC(
11 ChanelCount : INTEGER := 8;
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 25;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 50;
13 ncycle_cnv : INTEGER := 25;
14 FILTER_ENABLED : INTEGER := 16#FF#
14 FILTER_ENABLED : INTEGER := 16#FF#
15 );
15 );
16 PORT (
16 PORT (
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 cnv_rstn : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
19
19
20 cnv : OUT STD_LOGIC;
20 cnv : OUT STD_LOGIC;
21
21
22 clk : IN STD_LOGIC; -- 25MHz
22 clk : IN STD_LOGIC; -- 25MHz
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 ADC_data : IN Samples14;
24 ADC_data : IN Samples14;
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 sample_val : OUT STD_LOGIC
27 sample_val : OUT STD_LOGIC
28 );
28 );
29 END top_ad_conv_RHF1401_withFilter;
29 END top_ad_conv_RHF1401_withFilter;
30
30
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32
32
33 SIGNAL cnv_cycle_counter : INTEGER;
33 SIGNAL cnv_cycle_counter : INTEGER;
34 SIGNAL cnv_s : STD_LOGIC;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_reg : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
38 SIGNAL cnv_sync_falling : STD_LOGIC;
39
38
40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
41 SIGNAL enable_ADC : STD_LOGIC;
40 SIGNAL enable_ADC : STD_LOGIC;
42
41
43
42
44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
45
44
46 SIGNAL channel_counter : INTEGER;
45 SIGNAL channel_counter : INTEGER;
47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
48
47
49 SIGNAL ADC_data_selected : Samples14;
48 SIGNAL ADC_data_selected : Samples14;
50 SIGNAL ADC_data_result : Samples15;
49 SIGNAL ADC_data_result : Samples15;
51
50
52 SIGNAL sample_counter : INTEGER;
51 SIGNAL sample_counter : INTEGER;
53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54
53
55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
56
57 -----------------------------------------------------------------------------
58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 1;
59 CONSTANT DATA_CYCLE_VALID : INTEGER := 2;
60
55
61 -- GEN OutPut Enable
62 TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
63 SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
64 SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1 ;
66 SIGNAL ADC_data_valid : STD_LOGIC;
67 SIGNAL ADC_data_valid_s : STD_LOGIC;
68 SIGNAL ADC_data_reg : Samples14;
69 -----------------------------------------------------------------------------
70 CONSTANT SAMPLE_DIVISION : INTEGER := 10;
71 SIGNAL sample_val_s : STD_LOGIC;
72 SIGNAL sample_val_s2 : STD_LOGIC;
73 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
74 BEGIN
56 BEGIN
75
57
76
58
77 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
78 -- CNV GEN
60 -- CNV GEN
79 -----------------------------------------------------------------------------
61 -----------------------------------------------------------------------------
80 PROCESS (cnv_clk, cnv_rstn)
62 PROCESS (cnv_clk, cnv_rstn)
81 BEGIN -- PROCESS
63 BEGIN -- PROCESS
82 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
64 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
83 cnv_cycle_counter <= 0;
65 cnv_cycle_counter <= 0;
84 cnv_s <= '0';
66 cnv_s <= '0';
85 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
86 IF cnv_cycle_counter < ncycle_cnv-1 THEN
68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
87 cnv_cycle_counter <= cnv_cycle_counter + 1;
69 cnv_cycle_counter <= cnv_cycle_counter + 1;
88 IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
70 IF cnv_cycle_counter < ncycle_cnv_high THEN
89 cnv_s <= '1';
71 cnv_s <= '1';
90 ELSE
72 ELSE
91 cnv_s <= '0';
73 cnv_s <= '0';
92 END IF;
74 END IF;
93 ELSE
75 ELSE
94 cnv_s <= '1';
76 cnv_s <= '1';
95 cnv_cycle_counter <= 0;
77 cnv_cycle_counter <= 0;
96 END IF;
78 END IF;
97 END IF;
79 END IF;
98 END PROCESS;
80 END PROCESS;
99
81
100 cnv <= cnv_s;
82 cnv <= cnv_s;
101
83
102 PROCESS (cnv_clk, cnv_rstn)
84 PROCESS (cnv_clk, cnv_rstn)
103 BEGIN -- PROCESS
85 BEGIN -- PROCESS
104 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
105 cnv_s_reg <= '0';
87 cnv_s_reg <= '0';
106 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
107 cnv_s_reg <= cnv_s;
89 cnv_s_reg <= cnv_s;
108 END IF;
90 END IF;
109 END PROCESS;
91 END PROCESS;
110
92
111
93
112 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
113 -- SYNC CNV
95 -- SYNC CNV
114 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
115
97
116 SYNC_FF_cnv : SYNC_FF
98 SYNC_FF_cnv : SYNC_FF
117 GENERIC MAP (
99 GENERIC MAP (
118 NB_FF_OF_SYNC => 2)
100 NB_FF_OF_SYNC => 2)
119 PORT MAP (
101 PORT MAP (
120 clk => clk,
102 clk => clk,
121 rstn => rstn,
103 rstn => rstn,
122 A => cnv_s_reg,
104 A => cnv_s_reg,
123 A_sync => cnv_sync);
105 A_sync => cnv_sync);
124
106
107
125 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
126 --
109 -- DATA GEN Output Enable
110 -----------------------------------------------------------------------------
111 PROCESS (clk, rstn)
112 BEGIN -- PROCESS
113 IF rstn = '0' THEN -- asynchronous reset (active low)
114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 cnv_sync_pre <= '0';
116 enable_ADC <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 cnv_sync_pre <= cnv_sync;
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
120 enable_ADC <= '1';
121 ADC_nOE_reg(0) <= '0';
122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
123 ELSE
124 enable_ADC <= NOT enable_ADC;
125 IF enable_ADC = '0' THEN
126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
127 END IF;
128 END IF;
129
130 END IF;
131 END PROCESS;
132
133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
134
135 -----------------------------------------------------------------------------
136 -- ADC READ DATA
127 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
128 PROCESS (clk, rstn)
138 PROCESS (clk, rstn)
129 BEGIN -- PROCESS
139 BEGIN -- PROCESS
130 IF rstn = '0' THEN -- asynchronous reset (active low)
140 IF rstn = '0' THEN -- asynchronous reset (active low)
131 cnv_sync_reg <= '0';
141 channel_counter <= MAX_COUNTER;
142
143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
144 sample_reg(I) <= (OTHERS => '0');
145 END LOOP all_sample_reg_init;
146
147 sample_val <= '0';
148 sample_counter <= 0;
132 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
133 cnv_sync_reg <= cnv_sync;
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
134 END IF;
151 channel_counter <= 0;
135 END PROCESS;
152 ELSE
136
153 IF channel_counter < MAX_COUNTER THEN
137 cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0';
154 channel_counter <= channel_counter + 1;
138
155 END IF;
139 -----------------------------------------------------------------------------
156 END IF;
140 -- GEN OutPut Enable
141 -----------------------------------------------------------------------------
142 PROCESS (clk, rstn)
143 BEGIN -- PROCESS
144 IF rstn = '0' THEN
145 -------------------------------------------------------------------------
146 ADC_nOE <= (OTHERS => '1');
147 ADC_current <= 0;
148 ADC_current_cycle_enabled <= 0;
149 state_GEN_OEn <= IDLE;
150 -------------------------------------------------------------------------
151 ADC_data_reg <= (OTHERS => '0');
152 all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
153 sample_reg(I) <= (OTHERS => '0');
154 sample(I) <= (OTHERS => '0');
155 END LOOP all_channel_sample_reg_init;
156 sample_val <= '0';
157 sample_val <= '0';
157 sample_val_s <= '0';
158
158 sample_val_counter <= 0;
159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
159 -------------------------------------------------------------------------
160 IF channel_counter = I*2 THEN
160 ELSIF clk'event AND clk = '1' THEN
161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
161 -------------------------------------------------------------------------
162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
162 sample_val_s <= '0';
163 ELSE
163 ADC_nOE <= (OTHERS => '1');
164 sample_reg(I) <= ADC_data;
164 CASE state_GEN_OEn IS
165 WHEN IDLE =>
166 IF cnv_sync_falling = '1' THEN
167 --ADC_nOE(0) <= '1';
168 state_GEN_OEn <= GEN_OE;
169 ADC_current <= 0;
170 ADC_current_cycle_enabled <= 1;
171 END IF;
165 END IF;
172
166 END IF;
173 WHEN GEN_OE =>
167 END LOOP all_sample_reg;
174 ADC_nOE(ADC_current) <= '0';
175
176 ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
177
178 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
179 state_GEN_OEn <= WAIT_CYCLE;
180 END IF;
181
182 WHEN WAIT_CYCLE =>
183 ADC_current_cycle_enabled <= 1;
184 IF ADC_current = ChanelCount-1 THEN
185 state_GEN_OEn <= IDLE;
186 sample_val_s <= '1';
187 ELSE
188 ADC_current <= ADC_current + 1;
189 state_GEN_OEn <= GEN_OE;
190 END IF;
191 WHEN OTHERS => NULL;
192 END CASE;
193 -------------------------------------------------------------------------
194 ADC_data_reg <= ADC_data;
195
168
196 all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
169 IF channel_counter = (ChanelCount-1)*2 THEN
197 IF ADC_data_valid = '1' AND ADC_current = I THEN
170
198 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
172 sample_counter <= 0 ;
173 sample_val <= '1';
199 ELSE
174 ELSE
200 sample_reg(I) <= sample_reg(I);
175 sample_counter <= sample_counter +1;
201 END IF;
176 END IF;
202 END LOOP all_channel_sample_reg;
177
203 -------------------------------------------------------------------------
178 END IF;
204 sample_val <= '0';
205 IF sample_val_s2 = '1' THEN
206 IF sample_val_counter = SAMPLE_DIVISION-1 THEN
207 sample_val_counter <= 0;
208 sample_val <= '1'; -- TODO
209 sample <= sample_reg;
210 ELSE
211 sample_val_counter <= sample_val_counter + 1;
212 sample_val <= '0';
213 END IF;
214 END IF;
215
216 END IF;
179 END IF;
217 END PROCESS;
180 END PROCESS;
218
181
182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
183 -- BEGIN -- PROCESS mux_adc
184 -- CASE channel_counter IS
185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
186 -- END CASE;
187 -- END PROCESS mux_adc;
219
188
220
189
221 REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE
190 -----------------------------------------------------------------------------
222 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
223
192 -----------------------------------------------------------------------------
224 PROCESS (clk, rstn)
225 BEGIN -- PROCESS
226 IF rstn = '0' THEN -- asynchronous reset (active low)
227 ADC_data_valid <= '0';
228 sample_val_s2 <= '0';
229 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
230 ADC_data_valid <= ADC_data_valid_s;
231 sample_val_s2 <= sample_val_s;
232 END IF;
233 END PROCESS;
234
235 END GENERATE REG_ADC_DATA_valid;
236
193
237 noREG_ADC_DATA_valid: IF DATA_CYCLE_VALID < OE_NB_CYCLE_ENABLED GENERATE
194 WITH channel_counter SELECT
238 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
239
196 sample_reg(1) WHEN 1*2,
240 ADC_data_valid <= ADC_data_valid_s;
197 sample_reg(2) WHEN 2*2,
241 sample_val_s2 <= sample_val_s;
198 sample_reg(3) WHEN 3*2,
242 END GENERATE noREG_ADC_DATA_valid;
199 sample_reg(4) WHEN 4*2,
243
200 sample_reg(5) WHEN 5*2,
244 REGm_ADC_DATA_valid: IF DATA_CYCLE_VALID > OE_NB_CYCLE_ENABLED GENERATE
201 sample_reg(6) WHEN 6*2,
245
202 sample_reg(7) WHEN 7*2,
246 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED + 1 ELSE '0';
247
248 REG_1: SYNC_FF
249 GENERIC MAP (
250 NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1)
251 PORT MAP (
252 clk => clk,
253 rstn => rstn,
254 A => ADC_data_valid_s,
255 A_sync => ADC_data_valid);
256
257 REG_2: SYNC_FF
258 GENERIC MAP (
259 NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1)
260 PORT MAP (
261 clk => clk,
262 rstn => rstn,
263 A => sample_val_s,
264 A_sync => sample_val_s2);
265 END GENERATE REGm_ADC_DATA_valid;
266
267
268
269 WITH ADC_current SELECT
270 ADC_data_selected <= sample_reg(0) WHEN 0,
271 sample_reg(1) WHEN 1,
272 sample_reg(2) WHEN 2,
273 sample_reg(3) WHEN 3,
274 sample_reg(4) WHEN 4,
275 sample_reg(5) WHEN 5,
276 sample_reg(6) WHEN 6,
277 sample_reg(7) WHEN 7,
278 sample_reg(8) WHEN OTHERS ;
203 sample_reg(8) WHEN OTHERS ;
279
204
280 ADC_data_result <= std_logic_vector((
205 -----------------------------------------------------------------------------
281 signed( ADC_data_selected(13) & ADC_data_selected) +
206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
282 signed( ADC_data_reg(13) & ADC_data_reg)
207 -----------------------------------------------------------------------------
283 ));
284
208
285 -- sample <= sample_reg;
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
210
211 sample <= sample_reg;
286
212
287 END ar_top_ad_conv_RHF1401;
213 END ar_top_ad_conv_RHF1401;
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