HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r193:16c5d6a814b5

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r193:16c5d6a814b5

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boards/em-LeonLPP-A3PE3kL-v2/Makefile.inc created 644 +19 0

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		1	PACKAGE=\"\"
		2	SPEED=Std
		3	SYNFREQ=50
		4
		5	TECHNOLOGY=ProASIC3E
		6	LIBERO_DIE=IT14X14M4
		7	PART=A3PE3000
		8
		9	DESIGNER_VOLTAGE=COM
		10	DESIGNER_TEMP=COM
		11	DESIGNER_PACKAGE=FBGA
		12	DESIGNER_PINS=324
		13
		14	MANUFACTURER=Actel
		15	MGCTECHNOLOGY=Proasic3
		16	MGCPART=$(PART)
		17	MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		18	LIBERO_PACKAGE=fg$(DESIGNER_PINS)
		19

boards/em-LeonLPP-A3PE3kL-v2/default.sdc created 644 +59 0

			@@ -0,0 +1,59
		1	# Synplicity, Inc. constraint file
		2	# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
		3	# Written on Wed Aug 1 19:29:24 2007
		4	# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
		5
		6	#
		7	# Collections
		8	#
		9
		10	#
		11	# Clocks
		12	#
		13	define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5
		14
		15	#
		16	# Clock to Clock
		17	#
		18
		19	#
		20	# Inputs/Outputs
		21	#
		22	define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
		23	define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
		24
		25
		26	#
		27	# Registers
		28	#
		29
		30	#
		31	# Multicycle Path
		32	#
		33
		34	#
		35	# False Path
		36	#
		37
		38	#
		39	# Path Delay
		40	#
		41
		42	#
		43	# Attributes
		44	#
		45	define_global_attribute syn_useioff {1}
		46	define_global_attribute -disable syn_netlist_hierarchy {0}
		47	define_attribute {etx_clk} syn_noclockbuf {1}
		48
		49	#
		50	# I/O standards
		51	#
		52
		53	#
		54	# Compile Points
		55	#
		56
		57	#
		58	# Other Constraints
		59	#

boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc created 644 +112 0

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		1	set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
		2	set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
		3	set_io reset -pinname N18 -fixed yes -DIRECTION Inout
		4
		5	set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
		6	set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
		7	set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
		8	set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
		9	set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
		10	set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
		11	set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
		12	set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
		13	set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
		14	set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
		15	set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
		16	set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
		17	set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
		18	set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
		19	set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
		20	set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
		21	set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
		22	set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
		23	set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
		24	set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
		25
		26	set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
		27	set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
		28	set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
		29	set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
		30	set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
		31	set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
		32	set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
		33	set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
		34	set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
		35	set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
		36	set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
		37	set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
		38	set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
		39	set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
		40	set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
		41	set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
		42	set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
		43	set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
		44	set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
		45	set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
		46	set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
		47	set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
		48	set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
		49	set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
		50	set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
		51	set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
		52	set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
		53	set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
		54	set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
		55	set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
		56	set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
		57	set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
		58
		59	set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
		60	set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
		61	set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
		62	set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
		63	set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
		64	set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
		65	set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
		66
		67	set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
		68	set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
		69	set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
		70	set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
		71
		72	set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
		73	set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
		74	set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
		75
		76	set_io ahbtxd -pinname J12 -fixed yes -DIRECTION Inout
		77	#set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
		78	set_io ahbrxd -pinname L16 -fixed yes -DIRECTION Inout
		79	#set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
		80	set_io urxd1 -pinname M16 -fixed yes -DIRECTION Inout
		81	set_io utxd1 -pinname L13 -fixed yes -DIRECTION Inout
		82	set_io errorn -pinname P6 -fixed yes -DIRECTION Inout
		83	#set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
		84	#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
		85
		86	set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
		87
		88	set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
		89	set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
		90	set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
		91	set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
		92	set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
		93	set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
		94	set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
		95	set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
		96
		97	set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
		98
		99	set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
		100	set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
		101	set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
		102	set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
		103	set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
		104	set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
		105	set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
		106	set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
		107	set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
		108	set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
		109	set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
		110	set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
		111	set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
		112	set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout

boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL_testData29.pdc created 644 +8 0

			@@ -0,0 +1,8
		1	set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout
		2	set_io data_29 -pinname J18 -fixed yes -DIRECTION Inout
		3
		4	set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
		5	set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
		6	set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
		7
		8	set_io Reset -pinname N18 -fixed yes -DIRECTION Inout

boards/em-LeonLPP-A3PE3kL-v2/lpp-dm-sheldon-a3pe3000.pdc created 644 +611 0

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	1	# Actel Physical design constraints file
	2	# Generated file
	3
	4	# Version: 9.1 SP3 9.1.3.4
	5	# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
	6	# Date generated: Tue Oct 18 08:21:45 2011
	7
	8	#
	9	# IO banks setting
	10	#
	11
	12
	13	#
	14	# I/O constraints
	15	#
	16
	17	#set_io {scm_adc[0]} -pinname D1 -fixed yes -DIRECTION Inout
	18	#set_io {scm_adc[1]} -pinname E1 -fixed yes -DIRECTION Inout
	19	#set_io {scm_adc[2]} -pinname F1 -fixed yes -DIRECTION Inout
	20	#set_io {bias_adc[0]} -pinname H1 -fixed yes -DIRECTION Inout
	21	#set_io {bias_adc[1]} -pinname J1 -fixed yes -DIRECTION Inout
	22	#set_io {bias_adc[2]} -pinname N1 -fixed yes -DIRECTION Inout
	23	#set_io {bias_adc[3]} -pinname P1 -fixed yes -DIRECTION Inout
	24	#set_io {bias_adc[4]} -pinname R1 -fixed yes -DIRECTION Inout
	25
	26	#set_io {sdo_adc[0]} -pinname D1 -fixed yes -DIRECTION Inout
	27	#set_io {sdo_adc[1]} -pinname E1 -fixed yes -DIRECTION Inout
	28	#set_io {sdo_adc[2]} -pinname F1 -fixed yes -DIRECTION Inout
	29	#set_io {sdo_adc[3]} -pinname H1 -fixed yes -DIRECTION Inout
	30	#set_io {sdo_adc[4]} -pinname J1 -fixed yes -DIRECTION Inout
	31	#set_io {sdo_adc[5]} -pinname N1 -fixed yes -DIRECTION Inout
	32	#set_io {sdo_adc[6]} -pinname P1 -fixed yes -DIRECTION Inout
	33	#set_io {sdo_adc[7]} -pinname R1 -fixed yes -DIRECTION Inout
	34
	35	#set_io CNV_CH1 -pinname K1 -fixed yes -DIRECTION Inout
	36	#set_io SCK_CH1 -pinname L1 -fixed yes -DIRECTION Inout
	37	#set_io Bias_Fails -pinname G2 -fixed yes -DIRECTION Inout
	38
	39	set_io CE2 \
	40	-pinname K14 \
	41	-fixed yes \
	42	-DIRECTION Inout
	43
	44
	45	set_io MODE \
	46	-pinname C15 \
	47	-fixed yes \
	48	-DIRECTION Inout
	49
	50
	51	set_io SSRAM_CLK \
	52	-pinname D15 \
	53	-fixed yes \
	54	-DIRECTION Inout
	55
	56
	57	set_io ZZ \
	58	-pinname E18 \
	59	-fixed yes \
	60	-DIRECTION Inout
	61
	62
	63	set_io {address[0]} \
	64	-pinname D18 \
	65	-fixed yes \
	66	-DIRECTION Inout
	67
	68
	69	set_io {address[1]} \
	70	-pinname B17 \
	71	-fixed yes \
	72	-DIRECTION Inout
	73
	74
	75	set_io {address[2]} \
	76	-pinname A17 \
	77	-fixed yes \
	78	-DIRECTION Inout
	79
	80
	81	set_io {address[3]} \
	82	-pinname B16 \
	83	-fixed yes \
	84	-DIRECTION Inout
	85
	86
	87	set_io {address[4]} \
	88	-pinname A16 \
	89	-fixed yes \
	90	-DIRECTION Inout
	91
	92
	93	set_io {address[5]} \
	94	-pinname A15 \
	95	-fixed yes \
	96	-DIRECTION Inout
	97
	98
	99	set_io {address[6]} \
	100	-pinname A14 \
	101	-fixed yes \
	102	-DIRECTION Inout
	103
	104
	105	set_io {address[7]} \
	106	-pinname B13 \
	107	-fixed yes \
	108	-DIRECTION Inout
	109
	110
	111	set_io {address[8]} \
	112	-pinname B9 \
	113	-fixed yes \
	114	-DIRECTION Inout
	115
	116
	117	set_io {address[9]} \
	118	-pinname A8 \
	119	-fixed yes \
	120	-DIRECTION Inout
	121
	122
	123	set_io {address[10]} \
	124	-pinname B7 \
	125	-fixed yes \
	126	-DIRECTION Inout
	127
	128
	129	set_io {address[11]} \
	130	-pinname A6 \
	131	-fixed yes \
	132	-DIRECTION Inout
	133
	134
	135	set_io {address[12]} \
	136	-pinname B6 \
	137	-fixed yes \
	138	-DIRECTION Inout
	139
	140
	141	set_io {address[13]} \
	142	-pinname A5 \
	143	-fixed yes \
	144	-DIRECTION Inout
	145
	146
	147	set_io {address[14]} \
	148	-pinname A4 \
	149	-fixed yes \
	150	-DIRECTION Inout
	151
	152
	153	set_io {address[15]} \
	154	-pinname B3 \
	155	-fixed yes \
	156	-DIRECTION Inout
	157
	158
	159	set_io {address[16]} \
	160	-pinname B18 \
	161	-fixed yes \
	162	-DIRECTION Inout
	163
	164
	165	set_io {address[17]} \
	166	-pinname A13 \
	167	-fixed yes \
	168	-DIRECTION Inout
	169
	170
	171	set_io {address[18]} \
	172	-pinname B12 \
	173	-fixed yes \
	174	-DIRECTION Inout
	175
	176
	177	set_io ahbrxd \
	178	-pinname V4 \
	179	-fixed yes \
	180	-DIRECTION Inout
	181
	182
	183	set_io ahbtxd \
	184	-pinname V3 \
	185	-fixed yes \
	186	-DIRECTION Inout
	187
	188	#set_io urxd1 \
	189	# -pinname V9 \
	190	# -fixed yes \
	191	# -DIRECTION Inout
	192
	193	set_io utxd1 \
	194	-pinname V8 \
	195	-fixed yes \
	196	-DIRECTION Inout
	197
	198	set_io clk49_152MHz \
	199	-pinname D13 \
	200	-fixed yes \
	201	-DIRECTION Inout
	202
	203	set_io clk100MHz \
	204	-pinname D14 \
	205	-fixed yes \
	206	-DIRECTION Inout
	207
	208	set_io {data[0]} \
	209	-pinname F10 \
	210	-fixed yes \
	211	-DIRECTION Inout
	212
	213
	214	set_io {data[1]} \
	215	-pinname F9 \
	216	-fixed yes \
	217	-DIRECTION Inout
	218
	219
	220	set_io {data[2]} \
	221	-pinname F8 \
	222	-fixed yes \
	223	-DIRECTION Inout
	224
	225
	226	set_io {data[3]} \
	227	-pinname F7 \
	228	-fixed yes \
	229	-DIRECTION Inout
	230
	231
	232	set_io {data[4]} \
	233	-pinname E6 \
	234	-fixed yes \
	235	-DIRECTION Inout
	236
	237
	238	set_io {data[5]} \
	239	-pinname D5 \
	240	-fixed yes \
	241	-DIRECTION Inout
	242
	243
	244	set_io {data[6]} \
	245	-pinname C4 \
	246	-fixed yes \
	247	-DIRECTION Inout
	248
	249
	250	set_io {data[7]} \
	251	-pinname D3 \
	252	-fixed yes \
	253	-DIRECTION Inout
	254
	255
	256	set_io {data[8]} \
	257	-pinname F18 \
	258	-fixed yes \
	259	-DIRECTION Inout
	260
	261
	262	set_io {data[9]} \
	263	-pinname H18 \
	264	-fixed yes \
	265	-DIRECTION Inout
	266
	267
	268	set_io {data[10]} \
	269	-pinname J18 \
	270	-fixed yes \
	271	-DIRECTION Inout
	272
	273
	274	set_io {data[11]} \
	275	-pinname K18 \
	276	-fixed yes \
	277	-DIRECTION Inout
	278
	279
	280	set_io {data[12]} \
	281	-pinname L18 \
	282	-fixed yes \
	283	-DIRECTION Inout
	284
	285
	286	set_io {data[13]} \
	287	-pinname N18 \
	288	-fixed yes \
	289	-DIRECTION Inout
	290
	291
	292	set_io {data[14]} \
	293	-pinname P18 \
	294	-fixed yes \
	295	-DIRECTION Inout
	296
	297
	298	set_io {data[15]} \
	299	-pinname R18 \
	300	-fixed yes \
	301	-DIRECTION Inout
	302
	303
	304	set_io {data[16]} \
	305	-pinname M16 \
	306	-fixed yes \
	307	-DIRECTION Inout
	308
	309
	310	set_io {data[17]} \
	311	-pinname N17 \
	312	-fixed yes \
	313	-DIRECTION Inout
	314
	315
	316	set_io {data[18]} \
	317	-pinname P16 \
	318	-fixed yes \
	319	-DIRECTION Inout
	320
	321
	322	set_io {data[19]} \
	323	-pinname R13 \
	324	-fixed yes \
	325	-DIRECTION Inout
	326
	327
	328	set_io {data[20]} \
	329	-pinname T13 \
	330	-fixed yes \
	331	-DIRECTION Inout
	332
	333
	334	set_io {data[21]} \
	335	-pinname U13 \
	336	-fixed yes \
	337	-DIRECTION Inout
	338
	339
	340	set_io {data[22]} \
	341	-pinname U12 \
	342	-fixed yes \
	343	-DIRECTION Inout
	344
	345
	346	set_io {data[23]} \
	347	-pinname U10 \
	348	-fixed yes \
	349	-DIRECTION Inout
	350
	351
	352	set_io {data[24]} \
	353	-pinname C16 \
	354	-fixed yes \
	355	-DIRECTION Inout
	356
	357
	358	set_io {data[25]} \
	359	-pinname D16 \
	360	-fixed yes \
	361	-DIRECTION Inout
	362
	363
	364	set_io {data[26]} \
	365	-pinname E15 \
	366	-fixed yes \
	367	-DIRECTION Inout
	368
	369
	370	set_io {data[27]} \
	371	-pinname F16 \
	372	-fixed yes \
	373	-DIRECTION Inout
	374
	375
	376	set_io {data[28]} \
	377	-pinname G16 \
	378	-fixed yes \
	379	-DIRECTION Inout
	380
	381
	382	set_io {data[29]} \
	383	-pinname H16 \
	384	-fixed yes \
	385	-DIRECTION Inout
	386
	387
	388	set_io {data[30]} \
	389	-pinname J15 \
	390	-fixed yes \
	391	-DIRECTION Inout
	392
	393
	394	set_io {data[31]} \
	395	-pinname K15 \
	396	-fixed yes \
	397	-DIRECTION Inout
	398
	399
	400	set_io dsuact \
	401	-pinname N7 \
	402	-fixed yes \
	403	-DIRECTION Inout
	404
	405
	406	set_io dsubre \
	407	-pinname N6 \
	408	-fixed yes \
	409	-DIRECTION Inout
	410
	411
	412	set_io errorn \
	413	-pinname U6 \
	414	-fixed yes \
	415	-DIRECTION Inout
	416
	417
	418	set_io {led[0]} \
	419	-pinname T11 \
	420	-fixed no \
	421	-DIRECTION Inout
	422
	423
	424	set_io {led[1]} \
	425	-pinname R11 \
	426	-fixed no \
	427	-DIRECTION Inout
	428
	429
	430	set_io nADSC \
	431	-pinname D10 \
	432	-fixed yes \
	433	-DIRECTION Inout
	434
	435
	436	set_io nADSP \
	437	-pinname C10 \
	438	-fixed yes \
	439	-DIRECTION Inout
	440
	441
	442	set_io nADV \
	443	-pinname B10 \
	444	-fixed yes \
	445	-DIRECTION Inout
	446
	447
	448	set_io nBWE \
	449	-pinname F11 \
	450	-fixed yes \
	451	-DIRECTION Inout
	452
	453
	454	set_io nBWa \
	455	-pinname F15 \
	456	-fixed yes \
	457	-DIRECTION Inout
	458
	459
	460	set_io nBWb \
	461	-pinname G15 \
	462	-fixed yes \
	463	-DIRECTION Inout
	464
	465
	466	set_io nBWc \
	467	-pinname H15 \
	468	-fixed yes \
	469	-DIRECTION Inout
	470
	471
	472	set_io nBWd \
	473	-pinname J14 \
	474	-fixed yes \
	475	-DIRECTION Inout
	476
	477
	478	set_io nCE1 \
	479	-pinname L15 \
	480	-fixed yes \
	481	-DIRECTION Inout
	482
	483
	484	set_io nCE3 \
	485	-pinname E13 \
	486	-fixed yes \
	487	-DIRECTION Inout
	488
	489
	490	set_io nGW \
	491	-pinname C11 \
	492	-fixed yes \
	493	-DIRECTION Inout
	494
	495
	496	set_io nOE \
	497	-pinname E10 \
	498	-fixed yes \
	499	-DIRECTION Inout
	500
	501
	502	set_io reset \
	503	-pinname P13 \
	504	-fixed yes \
	505	-DIRECTION Inout
	506
	507
	508
	509	set_io {gpio[0]} -pinname J7 -fixed yes
	510	set_io {gpio[1]} -pinname C2 -fixed yes
	511	set_io {gpio[2]} -pinname C3 -fixed yes
	512	set_io {gpio[3]} -pinname D4 -fixed yes
	513	set_io {gpio[4]} -pinname E4 -fixed yes
	514	set_io {gpio[5]} -pinname F2 -fixed yes
	515	set_io {gpio[6]} -pinname G3 -fixed yes
	516
	517	set_io spw1_din -pinname V11 -fixed yes
	518	set_io spw1_sin -pinname V13 -fixed yes
	519	set_io spw1_dout -pinname V15 -fixed yes
	520	set_io spw1_sout -pinname V14 -fixed yes
	521	set_io spw1_en_bar -pinname V16 -fixed yes
	522	set_io spw2_en_bar -pinname T18 -fixed yes
	523
	524
	525	#
	526	# Non IO constraints
	527	#
	528
	529
	530	#
	531	# Old IO constraints, commented out for reference
	532	#
	533
	534	# set_io clk50MHz -pinname D13 -fixed yes
	535	# set_io reset -pinname P13 -fixed yes
	536	# set_io errorn -pinname U6 -fixed yes
	537	# set_io dsubre -pinname N6 -fixed yes
	538	# set_io dsuact -pinname N7 -fixed yes
	539	# set_io {led[0]} -pinname T11 -fixed yes
	540	# set_io {led[1]} -pinname R11 -fixed yes
	541	# set_io ahbrxd -pinname V4 -fixed yes
	542	# set_io ahbtxd -pinname V3 -fixed yes
	543	# set_io urxd1 -pinname V9 -fixed yes
	544	# set_io utxd1 -pinname V8 -fixed yes
	545	# set_io {data[0]} -pinname F10 -fixed yes
	546	# set_io {data[1]} -pinname F9 -fixed yes
	547	# set_io {data[2]} -pinname F8 -fixed yes
	548	# set_io {data[3]} -pinname F7 -fixed yes
	549	# set_io {data[4]} -pinname E6 -fixed yes
	550	# set_io {data[5]} -pinname D5 -fixed yes
	551	# set_io {data[6]} -pinname C4 -fixed yes
	552	# set_io {data[7]} -pinname D3 -fixed yes
	553	# set_io {data[8]} -pinname F18 -fixed yes
	554	# set_io {data[9]} -pinname H18 -fixed yes
	555	# set_io {data[10]} -pinname J18 -fixed yes
	556	# set_io {data[11]} -pinname K18 -fixed yes
	557	# set_io {data[12]} -pinname L18 -fixed yes
	558	# set_io {data[13]} -pinname N18 -fixed yes
	559	# set_io {data[14]} -pinname P18 -fixed yes
	560	# set_io {data[15]} -pinname R18 -fixed yes
	561	# set_io {data[16]} -pinname M16 -fixed yes
	562	# set_io {data[17]} -pinname N17 -fixed yes
	563	# set_io {data[18]} -pinname P16 -fixed yes
	564	# set_io {data[19]} -pinname R13 -fixed yes
	565	# set_io {data[20]} -pinname T13 -fixed yes
	566	# set_io {data[21]} -pinname U13 -fixed yes
	567	# set_io {data[22]} -pinname U12 -fixed yes
	568	# set_io {data[23]} -pinname U10 -fixed yes
	569	# set_io {data[24]} -pinname C16 -fixed yes
	570	# set_io {data[25]} -pinname D16 -fixed yes
	571	# set_io {data[26]} -pinname E15 -fixed yes
	572	# set_io {data[27]} -pinname F16 -fixed yes
	573	# set_io {data[28]} -pinname G16 -fixed yes
	574	# set_io {data[29]} -pinname H16 -fixed yes
	575	# set_io {data[30]} -pinname J15 -fixed yes
	576	# set_io {data[31]} -pinname K15 -fixed yes
	577	# set_io {address[0]} -pinname D18 -fixed yes
	578	# set_io {address[1]} -pinname B17 -fixed yes
	579	# set_io {address[2]} -pinname A17 -fixed yes
	580	# set_io {address[3]} -pinname B16 -fixed yes
	581	# set_io {address[4]} -pinname A16 -fixed yes
	582	# set_io {address[5]} -pinname A15 -fixed yes
	583	# set_io {address[6]} -pinname A14 -fixed yes
	584	# set_io {address[7]} -pinname B13 -fixed yes
	585	# set_io {address[8]} -pinname B9 -fixed yes
	586	# set_io {address[9]} -pinname A8 -fixed yes
	587	# set_io {address[10]} -pinname B7 -fixed yes
	588	# set_io {address[11]} -pinname A6 -fixed yes
	589	# set_io {address[12]} -pinname B6 -fixed yes
	590	# set_io {address[13]} -pinname A5 -fixed yes
	591	# set_io {address[14]} -pinname A4 -fixed yes
	592	# set_io {address[15]} -pinname B3 -fixed yes
	593	# set_io {address[16]} -pinname B18 -fixed yes
	594	# set_io {address[17]} -pinname A13 -fixed yes
	595	# set_io {address[18]} -pinname B12 -fixed yes
	596	# set_io nBWa -pinname F15 -fixed yes
	597	# set_io nBWb -pinname G15 -fixed yes
	598	# set_io nBWc -pinname H15 -fixed yes
	599	# set_io nBWd -pinname J14 -fixed yes
	600	# set_io nBWE -pinname F11 -fixed yes
	601	# set_io nADSC -pinname D10 -fixed yes
	602	# set_io nADSP -pinname C10 -fixed yes
	603	# set_io nADV -pinname B10 -fixed yes
	604	# set_io nGW -pinname C11 -fixed yes
	605	# set_io nCE1 -pinname L15 -fixed yes
	606	# set_io CE2 -pinname K14 -fixed yes
	607	# set_io nCE3 -pinname E13 -fixed yes
	608	# set_io nOE -pinname E10 -fixed yes
	609	# set_io MODE -pinname C15 -fixed yes
	610	# set_io SSRAM_CLK -pinname D15 -fixed yes
	611	# set_io ZZ -pinname E18 -fixed yes

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/.config created 644 +288 0

			@@ -0,0 +1,288
		1	#
		2	# Automatically generated make config: don't edit
		3	#
		4
		5	#
		6	# Synthesis
		7	#
		8	# CONFIG_SYN_INFERRED is not set
		9	# CONFIG_SYN_STRATIX is not set
		10	# CONFIG_SYN_STRATIXII is not set
		11	# CONFIG_SYN_STRATIXIII is not set
		12	# CONFIG_SYN_CYCLONEIII is not set
		13	# CONFIG_SYN_ALTERA is not set
		14	# CONFIG_SYN_AXCEL is not set
		15	# CONFIG_SYN_PROASIC is not set
		16	# CONFIG_SYN_PROASICPLUS is not set
		17	CONFIG_SYN_PROASIC3=y
		18	# CONFIG_SYN_UT025CRH is not set
		19	# CONFIG_SYN_ATC18 is not set
		20	# CONFIG_SYN_ATC18RHA is not set
		21	# CONFIG_SYN_CUSTOM1 is not set
		22	# CONFIG_SYN_EASIC90 is not set
		23	# CONFIG_SYN_IHP25 is not set
		24	# CONFIG_SYN_IHP25RH is not set
		25	# CONFIG_SYN_LATTICE is not set
		26	# CONFIG_SYN_ECLIPSE is not set
		27	# CONFIG_SYN_PEREGRINE is not set
		28	# CONFIG_SYN_RH_LIB18T is not set
		29	# CONFIG_SYN_RHUMC is not set
		30	# CONFIG_SYN_SMIC13 is not set
		31	# CONFIG_SYN_SPARTAN2 is not set
		32	# CONFIG_SYN_SPARTAN3 is not set
		33	# CONFIG_SYN_SPARTAN3E is not set
		34	# CONFIG_SYN_VIRTEX is not set
		35	# CONFIG_SYN_VIRTEXE is not set
		36	# CONFIG_SYN_VIRTEX2 is not set
		37	# CONFIG_SYN_VIRTEX4 is not set
		38	# CONFIG_SYN_VIRTEX5 is not set
		39	# CONFIG_SYN_UMC is not set
		40	# CONFIG_SYN_TSMC90 is not set
		41	# CONFIG_SYN_INFER_RAM is not set
		42	# CONFIG_SYN_INFER_PADS is not set
		43	# CONFIG_SYN_NO_ASYNC is not set
		44	# CONFIG_SYN_SCAN is not set
		45
		46	#
		47	# Clock generation
		48	#
		49	# CONFIG_CLK_INFERRED is not set
		50	# CONFIG_CLK_HCLKBUF is not set
		51	# CONFIG_CLK_ALTDLL is not set
		52	# CONFIG_CLK_LATDLL is not set
		53	CONFIG_CLK_PRO3PLL=y
		54	# CONFIG_CLK_LIB18T is not set
		55	# CONFIG_CLK_RHUMC is not set
		56	# CONFIG_CLK_CLKDLL is not set
		57	# CONFIG_CLK_DCM is not set
		58	CONFIG_CLK_MUL=2
		59	CONFIG_CLK_DIV=8
		60	CONFIG_OCLK_DIV=2
		61	# CONFIG_PCI_SYSCLK is not set
		62	CONFIG_LEON3=y
		63	CONFIG_PROC_NUM=1
		64
		65	#
		66	# Processor
		67	#
		68
		69	#
		70	# Integer unit
		71	#
		72	CONFIG_IU_NWINDOWS=8
		73	# CONFIG_IU_V8MULDIV is not set
		74	# CONFIG_IU_SVT is not set
		75	CONFIG_IU_LDELAY=1
		76	CONFIG_IU_WATCHPOINTS=0
		77	# CONFIG_PWD is not set
		78	CONFIG_IU_RSTADDR=00000
		79
		80	#
		81	# Floating-point unit
		82	#
		83	# CONFIG_FPU_ENABLE is not set
		84
		85	#
		86	# Cache system
		87	#
		88	CONFIG_ICACHE_ENABLE=y
		89	CONFIG_ICACHE_ASSO1=y
		90	# CONFIG_ICACHE_ASSO2 is not set
		91	# CONFIG_ICACHE_ASSO3 is not set
		92	# CONFIG_ICACHE_ASSO4 is not set
		93	# CONFIG_ICACHE_SZ1 is not set
		94	# CONFIG_ICACHE_SZ2 is not set
		95	CONFIG_ICACHE_SZ4=y
		96	# CONFIG_ICACHE_SZ8 is not set
		97	# CONFIG_ICACHE_SZ16 is not set
		98	# CONFIG_ICACHE_SZ32 is not set
		99	# CONFIG_ICACHE_SZ64 is not set
		100	# CONFIG_ICACHE_SZ128 is not set
		101	# CONFIG_ICACHE_SZ256 is not set
		102	# CONFIG_ICACHE_LZ16 is not set
		103	CONFIG_ICACHE_LZ32=y
		104	CONFIG_DCACHE_ENABLE=y
		105	CONFIG_DCACHE_ASSO1=y
		106	# CONFIG_DCACHE_ASSO2 is not set
		107	# CONFIG_DCACHE_ASSO3 is not set
		108	# CONFIG_DCACHE_ASSO4 is not set
		109	# CONFIG_DCACHE_SZ1 is not set
		110	# CONFIG_DCACHE_SZ2 is not set
		111	CONFIG_DCACHE_SZ4=y
		112	# CONFIG_DCACHE_SZ8 is not set
		113	# CONFIG_DCACHE_SZ16 is not set
		114	# CONFIG_DCACHE_SZ32 is not set
		115	# CONFIG_DCACHE_SZ64 is not set
		116	# CONFIG_DCACHE_SZ128 is not set
		117	# CONFIG_DCACHE_SZ256 is not set
		118	# CONFIG_DCACHE_LZ16 is not set
		119	CONFIG_DCACHE_LZ32=y
		120	# CONFIG_DCACHE_SNOOP is not set
		121	CONFIG_CACHE_FIXED=0
		122
		123	#
		124	# MMU
		125	#
		126	CONFIG_MMU_ENABLE=y
		127	# CONFIG_MMU_COMBINED is not set
		128	CONFIG_MMU_SPLIT=y
		129	# CONFIG_MMU_REPARRAY is not set
		130	CONFIG_MMU_REPINCREMENT=y
		131	# CONFIG_MMU_I2 is not set
		132	# CONFIG_MMU_I4 is not set
		133	CONFIG_MMU_I8=y
		134	# CONFIG_MMU_I16 is not set
		135	# CONFIG_MMU_I32 is not set
		136	# CONFIG_MMU_D2 is not set
		137	# CONFIG_MMU_D4 is not set
		138	CONFIG_MMU_D8=y
		139	# CONFIG_MMU_D16 is not set
		140	# CONFIG_MMU_D32 is not set
		141	CONFIG_MMU_FASTWB=y
		142	CONFIG_MMU_PAGE_4K=y
		143	# CONFIG_MMU_PAGE_8K is not set
		144	# CONFIG_MMU_PAGE_16K is not set
		145	# CONFIG_MMU_PAGE_32K is not set
		146	# CONFIG_MMU_PAGE_PROG is not set
		147
		148	#
		149	# Debug Support Unit
		150	#
		151	# CONFIG_DSU_ENABLE is not set
		152
		153	#
		154	# Fault-tolerance
		155	#
		156
		157	#
		158	# VHDL debug settings
		159	#
		160	# CONFIG_IU_DISAS is not set
		161	# CONFIG_DEBUG_PC32 is not set
		162
		163	#
		164	# AMBA configuration
		165	#
		166	CONFIG_AHB_DEFMST=0
		167	CONFIG_AHB_RROBIN=y
		168	# CONFIG_AHB_SPLIT is not set
		169	CONFIG_AHB_IOADDR=FFF
		170	CONFIG_APB_HADDR=800
		171	# CONFIG_AHB_MON is not set
		172
		173	#
		174	# Debug Link
		175	#
		176	CONFIG_DSU_UART=y
		177	# CONFIG_DSU_JTAG is not set
		178
		179	#
		180	# Peripherals
		181	#
		182
		183	#
		184	# Memory controllers
		185	#
		186
		187	#
		188	# 8/32-bit PROM/SRAM controller
		189	#
		190	CONFIG_SRCTRL=y
		191	# CONFIG_SRCTRL_8BIT is not set
		192	CONFIG_SRCTRL_PROMWS=3
		193	CONFIG_SRCTRL_RAMWS=0
		194	CONFIG_SRCTRL_IOWS=0
		195	# CONFIG_SRCTRL_RMW is not set
		196	CONFIG_SRCTRL_SRBANKS1=y
		197	# CONFIG_SRCTRL_SRBANKS2 is not set
		198	# CONFIG_SRCTRL_SRBANKS3 is not set
		199	# CONFIG_SRCTRL_SRBANKS4 is not set
		200	# CONFIG_SRCTRL_SRBANKS5 is not set
		201	# CONFIG_SRCTRL_BANKSZ0 is not set
		202	# CONFIG_SRCTRL_BANKSZ1 is not set
		203	# CONFIG_SRCTRL_BANKSZ2 is not set
		204	# CONFIG_SRCTRL_BANKSZ3 is not set
		205	# CONFIG_SRCTRL_BANKSZ4 is not set
		206	# CONFIG_SRCTRL_BANKSZ5 is not set
		207	# CONFIG_SRCTRL_BANKSZ6 is not set
		208	# CONFIG_SRCTRL_BANKSZ7 is not set
		209	# CONFIG_SRCTRL_BANKSZ8 is not set
		210	# CONFIG_SRCTRL_BANKSZ9 is not set
		211	# CONFIG_SRCTRL_BANKSZ10 is not set
		212	# CONFIG_SRCTRL_BANKSZ11 is not set
		213	# CONFIG_SRCTRL_BANKSZ12 is not set
		214	# CONFIG_SRCTRL_BANKSZ13 is not set
		215	CONFIG_SRCTRL_ROMASEL=19
		216
		217	#
		218	# Leon2 memory controller
		219	#
		220	CONFIG_MCTRL_LEON2=y
		221	# CONFIG_MCTRL_8BIT is not set
		222	# CONFIG_MCTRL_16BIT is not set
		223	# CONFIG_MCTRL_5CS is not set
		224	# CONFIG_MCTRL_SDRAM is not set
		225
		226	#
		227	# PC133 SDRAM controller
		228	#
		229	# CONFIG_SDCTRL is not set
		230
		231	#
		232	# On-chip RAM/ROM
		233	#
		234	# CONFIG_AHBROM_ENABLE is not set
		235	# CONFIG_AHBRAM_ENABLE is not set
		236
		237	#
		238	# Ethernet
		239	#
		240	# CONFIG_GRETH_ENABLE is not set
		241
		242	#
		243	# CAN
		244	#
		245	# CONFIG_CAN_ENABLE is not set
		246
		247	#
		248	# PCI
		249	#
		250	# CONFIG_PCI_SIMPLE_TARGET is not set
		251	# CONFIG_PCI_MASTER_TARGET is not set
		252	# CONFIG_PCI_ARBITER is not set
		253	# CONFIG_PCI_TRACE is not set
		254
		255	#
		256	# Spacewire
		257	#
		258	# CONFIG_SPW_ENABLE is not set
		259
		260	#
		261	# UARTs, timers and irq control
		262	#
		263	CONFIG_UART1_ENABLE=y
		264	# CONFIG_UA1_FIFO1 is not set
		265	# CONFIG_UA1_FIFO2 is not set
		266	CONFIG_UA1_FIFO4=y
		267	# CONFIG_UA1_FIFO8 is not set
		268	# CONFIG_UA1_FIFO16 is not set
		269	# CONFIG_UA1_FIFO32 is not set
		270	# CONFIG_UART2_ENABLE is not set
		271	CONFIG_IRQ3_ENABLE=y
		272	# CONFIG_IRQ3_SEC is not set
		273	CONFIG_GPT_ENABLE=y
		274	CONFIG_GPT_NTIM=2
		275	CONFIG_GPT_SW=8
		276	CONFIG_GPT_TW=32
		277	CONFIG_GPT_IRQ=8
		278	CONFIG_GPT_SEPIRQ=y
		279	CONFIG_GPT_WDOGEN=y
		280	CONFIG_GPT_WDOG=FFFF
		281	CONFIG_GRGPIO_ENABLE=y
		282	CONFIG_GRGPIO_WIDTH=8
		283	CONFIG_GRGPIO_IMASK=0000
		284
		285	#
		286	# VHDL Debugging
		287	#
		288	# CONFIG_DEBUG_UART is not set

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/Makefile created 644 +49 0

			@@ -0,0 +1,49
		1	GRLIB=../..
		2	TOP=leon3mp
		3	BOARD=em-LeonLPP-A3PE3kL-v2
		4	include $(GRLIB)/boards/$(BOARD)/Makefile.inc
		5	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		6	UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
		7	QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
		8	EFFORT=high
		9	XSTOPT=
		10	SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
		11	#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
		12	VHDLSYNFILES=config.vhd leon3mp.vhd
		13	#VHDLSIMFILES=testbench.vhd
		14	#SIMTOP=testbench
		15	#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
		16	#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
		17	PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
		18	BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
		19	CLEAN=soft-clean
		20
		21	TECHLIBS = proasic3e
		22
		23	LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		24	tmtc openchip hynix ihp gleichmann micron usbhc
		25
		26	DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
		27	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
		28	./amba_lcd_16x2_ctrlr \
		29	./general_purpose/lpp_AMR \
		30	./general_purpose/lpp_balise \
		31	./general_purpose/lpp_delay \
		32	./dsp/lpp_fft \
		33	./lpp_bootloader \
		34	./lpp_cna \
		35	./lpp_demux \
		36	./lpp_matrix \
		37	./lpp_uart \
		38	./lpp_usb \
		39	./lpp_Header \
		40
		41	FILESKIP = i2cmst.vhd \
		42	APB_MULTI_DIODE.vhd \
		43	APB_SIMPLE_DIODE.vhd
		44
		45	include $(GRLIB)/bin/Makefile
		46	include $(GRLIB)/software/leon3/Makefile
		47
		48	################## project specific targets ##########################
		49

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/config.vhd created 644 +182 0

			@@ -0,0 +1,182
		1	-----------------------------------------------------------------------------
		2	-- LEON3 Demonstration design test bench configuration
		3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 2 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	------------------------------------------------------------------------------
		15
		16
		17	library techmap;
		18	use techmap.gencomp.all;
		19
		20	package config is
		21
		22
		23	-- Technology and synthesis options
		24	constant CFG_FABTECH : integer := apa3e;
		25	constant CFG_MEMTECH : integer := apa3e;
		26	constant CFG_PADTECH : integer := inferred;
		27	constant CFG_NOASYNC : integer := 0;
		28	constant CFG_SCAN : integer := 0;
		29
		30	-- Clock generator
		31	constant CFG_CLKTECH : integer := inferred;
		32	constant CFG_CLKMUL : integer := (1);
		33	constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
		34	constant CFG_OCLKDIV : integer := (1);
		35	constant CFG_PCIDLL : integer := 0;
		36	constant CFG_PCISYSCLK: integer := 0;
		37	constant CFG_CLK_NOFB : integer := 0;
		38
		39	-- LEON3 processor core
		40	constant CFG_LEON3 : integer := 1;
		41	constant CFG_NCPU : integer := (1);
		42	--constant CFG_NWIN : integer := (7); -- PLE
		43	constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
		44	constant CFG_V8 : integer := 0;
		45	constant CFG_MAC : integer := 0;
		46	constant CFG_SVT : integer := 0;
		47	constant CFG_RSTADDR : integer := 16#00000#;
		48	constant CFG_LDDEL : integer := (1);
		49	constant CFG_NWP : integer := (0);
		50	constant CFG_PWD : integer := 1*2;
		51	constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
		52	--constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
		53	constant CFG_GRFPUSH : integer := 0;
		54	constant CFG_ICEN : integer := 1;
		55	constant CFG_ISETS : integer := 1;
		56	constant CFG_ISETSZ : integer := 4;
		57	constant CFG_ILINE : integer := 4;
		58	constant CFG_IREPL : integer := 0;
		59	constant CFG_ILOCK : integer := 0;
		60	constant CFG_ILRAMEN : integer := 0;
		61	constant CFG_ILRAMADDR: integer := 16#8E#;
		62	constant CFG_ILRAMSZ : integer := 1;
		63	constant CFG_DCEN : integer := 1;
		64	constant CFG_DSETS : integer := 1;
		65	constant CFG_DSETSZ : integer := 4;
		66	constant CFG_DLINE : integer := 4;
		67	constant CFG_DREPL : integer := 0;
		68	constant CFG_DLOCK : integer := 0;
		69	constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
		70	constant CFG_DFIXED : integer := 16#00F3#;
		71	constant CFG_DLRAMEN : integer := 0;
		72	constant CFG_DLRAMADDR: integer := 16#8F#;
		73	constant CFG_DLRAMSZ : integer := 1;
		74	constant CFG_MMUEN : integer := 0;
		75	constant CFG_ITLBNUM : integer := 2;
		76	constant CFG_DTLBNUM : integer := 2;
		77	constant CFG_TLB_TYPE : integer := 1 + 0*2;
		78	constant CFG_TLB_REP : integer := 1;
		79	constant CFG_DSU : integer := 1;
		80	constant CFG_ITBSZ : integer := 0;
		81	constant CFG_ATBSZ : integer := 0;
		82	constant CFG_LEON3FT_EN : integer := 0;
		83	constant CFG_IUFT_EN : integer := 0;
		84	constant CFG_FPUFT_EN : integer := 0;
		85	constant CFG_RF_ERRINJ : integer := 0;
		86	constant CFG_CACHE_FT_EN : integer := 0;
		87	constant CFG_CACHE_ERRINJ : integer := 0;
		88	constant CFG_LEON3_NETLIST: integer := 0;
		89	constant CFG_DISAS : integer := 0 + 0;
		90	constant CFG_PCLOW : integer := 2;
		91
		92	-- AMBA settings
		93	constant CFG_DEFMST : integer := (0);
		94	constant CFG_RROBIN : integer := 1;
		95	constant CFG_SPLIT : integer := 0;
		96	constant CFG_AHBIO : integer := 16#FFF#;
		97	constant CFG_APBADDR : integer := 16#800#;
		98	constant CFG_AHB_MON : integer := 0;
		99	constant CFG_AHB_MONERR : integer := 0;
		100	constant CFG_AHB_MONWAR : integer := 0;
		101
		102	-- DSU UART
		103	constant CFG_AHB_UART : integer := 1;
		104
		105	-- JTAG based DSU interface
		106	constant CFG_AHB_JTAG : integer := 0;
		107
		108	-- Ethernet DSU
		109	constant CFG_DSU_ETH : integer := 0 + 0;
		110	constant CFG_ETH_BUF : integer := 1;
		111	constant CFG_ETH_IPM : integer := 16#C0A8#;
		112	constant CFG_ETH_IPL : integer := 16#0033#;
		113	constant CFG_ETH_ENM : integer := 16#00007A#;
		114	constant CFG_ETH_ENL : integer := 16#CC0001#;
		115
		116	-- LEON2 memory controller
		117	constant CFG_MCTRL_LEON2 : integer := 1;
		118	constant CFG_MCTRL_RAM8BIT : integer := 0;
		119	constant CFG_MCTRL_RAM16BIT : integer := 0;
		120	constant CFG_MCTRL_5CS : integer := 0;
		121	constant CFG_MCTRL_SDEN : integer := 0;
		122	constant CFG_MCTRL_SEPBUS : integer := 0;
		123	constant CFG_MCTRL_INVCLK : integer := 0;
		124	constant CFG_MCTRL_SD64 : integer := 0;
		125	constant CFG_MCTRL_PAGE : integer := 0 + 0;
		126
		127	-- SSRAM controller
		128	constant CFG_SSCTRL : integer := 0;
		129	constant CFG_SSCTRLP16 : integer := 0;
		130
		131	-- AHB ROM
		132	constant CFG_AHBROMEN : integer := 0;
		133	constant CFG_AHBROPIP : integer := 0;
		134	constant CFG_AHBRODDR : integer := 16#000#;
		135	constant CFG_ROMADDR : integer := 16#000#;
		136	constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
		137
		138	-- AHB RAM
		139	constant CFG_AHBRAMEN : integer := 0;
		140	constant CFG_AHBRSZ : integer := 1;
		141	constant CFG_AHBRADDR : integer := 16#A00#;
		142
		143	-- Gaisler Ethernet core
		144	constant CFG_GRETH : integer := 0;
		145	constant CFG_GRETH1G : integer := 0;
		146	constant CFG_ETH_FIFO : integer := 8;
		147
		148	-- CAN 2.0 interface
		149	constant CFG_CAN : integer := 0;
		150	constant CFG_CANIO : integer := 16#0#;
		151	constant CFG_CANIRQ : integer := 0;
		152	constant CFG_CANLOOP : integer := 0;
		153	constant CFG_CAN_SYNCRST : integer := 0;
		154	constant CFG_CANFT : integer := 0;
		155
		156	-- UART 1
		157	constant CFG_UART1_ENABLE : integer := 1;
		158	constant CFG_UART1_FIFO : integer := 1;
		159
		160	-- LEON3 interrupt controller
		161	constant CFG_IRQ3_ENABLE : integer := 1;
		162
		163	-- Modular timer
		164	constant CFG_GPT_ENABLE : integer := 1;
		165	constant CFG_GPT_NTIM : integer := (2);
		166	constant CFG_GPT_SW : integer := (8);
		167	constant CFG_GPT_TW : integer := (32);
		168	constant CFG_GPT_IRQ : integer := (8);
		169	constant CFG_GPT_SEPIRQ : integer := 1;
		170	constant CFG_GPT_WDOGEN : integer := 0;
		171	constant CFG_GPT_WDOG : integer := 16#0#;
		172
		173	-- GPIO port
		174	constant CFG_GRGPIO_ENABLE : integer := 1;
		175	constant CFG_GRGPIO_IMASK : integer := 16#0000#;
		176	constant CFG_GRGPIO_WIDTH : integer := (7);
		177
		178	-- GRLIB debugging
		179	constant CFG_DUART : integer := 0;
		180
		181
		182	end;

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/history.txt created 644 +21 0

			@@ -0,0 +1,21
		1	leon3mp_em_JCPE_02-07-2013.pdb
		2	+ UART ok
		3	+ SPW ok
		4	+ Leon3 ok
		5
		6	leon3mp_em_JCPE_05-07-2013.pdb
		7	+ UART ok
		8	+ SPW ok
		9	+ Leon3 ok
		10	+ Waveform ok
		11	-> No filter
		12	-> Inverted ADC Input Channel
		13
		14	leon3mp_em_JCPE_08-07-2013.pdb
		15	+ UART ??
		16	+ SPW ??
		17	+ Leon3 ??
		18	+ Waveform ??
		19	-> No filter
		20
		21

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/leon3mp_em_JCPE_02-07-2013.pdb created 644 binary 0 0

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designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/leon3mp_em_JCPE_05-07-2013.pdb created 644 binary 0 0

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designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/leon3mp_em_JCPE_08-07-2013.pdb created 644 binary 0 0

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designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/leon3mp.vhd created 644 +516 0

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	1	-----------------------------------------------------------------------------
	2	-- LEON3 Demonstration design
	3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	------------------------------------------------------------------------------
	19
	20
	21	LIBRARY ieee;
	22	USE ieee.std_logic_1164.ALL;
	23	LIBRARY grlib;
	24	USE grlib.amba.ALL;
	25	USE grlib.stdlib.ALL;
	26	LIBRARY techmap;
	27	USE techmap.gencomp.ALL;
	28	LIBRARY gaisler;
	29	USE gaisler.memctrl.ALL;
	30	USE gaisler.leon3.ALL;
	31	USE gaisler.uart.ALL;
	32	USE gaisler.misc.ALL;
	33	USE gaisler.spacewire.ALL; -- PLE
	34	LIBRARY esa;
	35	USE esa.memoryctrl.ALL;
	36	USE work.config.ALL;
	37	LIBRARY lpp;
	38	--use lpp.lpp_amba.all;
	39	USE lpp.lpp_memory.ALL;
	40	USE lpp.lpp_ad_conv.ALL;
	41	USE lpp.lpp_top_lfr_pkg.ALL;
	42	--use lpp.lpp_uart.all;
	43	--use lpp.lpp_matrix.all;
	44	--use lpp.lpp_delay.all;
	45	--use lpp.lpp_fft.all;
	46	--use lpp.fft_components.all;
	47	use lpp.iir_filter.all;
	48	USE lpp.general_purpose.ALL;
	49	--use lpp.Filtercfg.all;
	50	USE lpp.lpp_lfr_time_management.ALL; -- PLE
	51	--use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE
	52
	53	ENTITY leon3mp IS
	54	GENERIC (
	55	fabtech : INTEGER := CFG_FABTECH;
	56	memtech : INTEGER := CFG_MEMTECH;
	57	padtech : INTEGER := CFG_PADTECH;
	58	clktech : INTEGER := CFG_CLKTECH;
	59	disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
	60	dbguart : INTEGER := CFG_DUART; -- Print UART on console
	61	pclow : INTEGER := CFG_PCLOW
	62	);
	63	PORT (
	64	clk50MHz : IN STD_ULOGIC;
	65	clk49_152MHz : IN STD_ULOGIC;
	66	reset : IN STD_ULOGIC;
	67
	68	errorn : OUT STD_ULOGIC;
	69
	70	-- UART AHB ---------------------------------------------------------------
	71	ahbrxd : IN STD_ULOGIC; -- DSU rx data
	72	ahbtxd : OUT STD_ULOGIC; -- DSU tx data
	73
	74	-- UART APB ---------------------------------------------------------------
	75	urxd1 : IN STD_ULOGIC; -- UART1 rx data
	76	utxd1 : OUT STD_ULOGIC; -- UART1 tx data
	77
	78	-- RAM --------------------------------------------------------------------
	79	address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
	80	data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	81	nSRAM_BE0 : OUT STD_LOGIC;
	82	nSRAM_BE1 : OUT STD_LOGIC;
	83	nSRAM_BE2 : OUT STD_LOGIC;
	84	nSRAM_BE3 : OUT STD_LOGIC;
	85	nSRAM_WE : OUT STD_LOGIC;
	86	nSRAM_CE : OUT STD_LOGIC;
	87	nSRAM_OE : OUT STD_LOGIC;
	88
	89	-- SPW --------------------------------------------------------------------
	90	spw1_din : IN STD_LOGIC; -- PLE
	91	spw1_sin : IN STD_LOGIC; -- PLE
	92	spw1_dout : OUT STD_LOGIC; -- PLE
	93	spw1_sout : OUT STD_LOGIC; -- PLE
	94
	95	-- ADC --------------------------------------------------------------------
	96	bias_fail_sw : OUT STD_LOGIC;
	97	ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	98	ADC_smpclk : OUT STD_LOGIC;
	99	ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
	100
	101	---------------------------------------------------------------------------
	102	led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
	103	);
	104	END;
	105
	106	ARCHITECTURE Behavioral OF leon3mp IS
	107
	108	--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
	109	-- CFG_GRETH+CFG_AHB_JTAG;
	110	CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
	111	CFG_AHB_UART+
	112	CFG_GRETH+
	113	CFG_AHB_JTAG
	114	+2; -- 1 is for the SpaceWire module grspw2, which is a master
	115	CONSTANT maxahbm : INTEGER := maxahbmsp;
	116
	117	--Clk & Rst g�n�
	118	SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
	119	SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
	120	SIGNAL resetnl : STD_ULOGIC;
	121	SIGNAL clk2x : STD_ULOGIC;
	122	SIGNAL lclk2x : STD_ULOGIC;
	123	SIGNAL lclk25MHz : STD_ULOGIC;
	124	SIGNAL lclk50MHz : STD_ULOGIC;
	125	SIGNAL lclk100MHz : STD_ULOGIC;
	126	SIGNAL clkm : STD_ULOGIC;
	127	SIGNAL rstn : STD_ULOGIC;
	128	SIGNAL rstraw : STD_ULOGIC;
	129	SIGNAL pciclk : STD_ULOGIC;
	130	SIGNAL sdclkl : STD_ULOGIC;
	131	SIGNAL cgi : clkgen_in_type;
	132	SIGNAL cgo : clkgen_out_type;
	133	--- AHB / APB
	134	SIGNAL apbi : apb_slv_in_type;
	135	SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
	136	SIGNAL ahbsi : ahb_slv_in_type;
	137	SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
	138	SIGNAL ahbmi : ahb_mst_in_type;
	139	SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
	140	--UART
	141	SIGNAL ahbuarti : uart_in_type;
	142	SIGNAL ahbuarto : uart_out_type;
	143	SIGNAL apbuarti : uart_in_type;
	144	SIGNAL apbuarto : uart_out_type;
	145	--MEM CTRLR
	146	SIGNAL memi : memory_in_type;
	147	SIGNAL memo : memory_out_type;
	148	SIGNAL wpo : wprot_out_type;
	149	SIGNAL sdo : sdram_out_type;
	150	SIGNAL ramcs : STD_ULOGIC;
	151	--IRQ
	152	SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
	153	SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
	154	--Timer
	155	SIGNAL gpti : gptimer_in_type;
	156	SIGNAL gpto : gptimer_out_type;
	157	--GPIO
	158	SIGNAL gpioi : gpio_in_type;
	159	SIGNAL gpioo : gpio_out_type;
	160	--DSU
	161	SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
	162	SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
	163	SIGNAL dsui : dsu_in_type;
	164	SIGNAL dsuo : dsu_out_type;
	165
	166	---------------------------------------------------------------------
	167	--- AJOUT TEST ------------------------Signaux----------------------
	168	---------------------------------------------------------------------
	169
	170	---------------------------------------------------------------------
	171	CONSTANT IOAEN : INTEGER := CFG_CAN;
	172	CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
	173
	174	-- time management signal
	175	SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
	176	SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
	177
	178	-- Spacewire signals
	179	SIGNAL dtmp : STD_ULOGIC; -- PLE
	180	SIGNAL stmp : STD_ULOGIC; -- PLE
	181	SIGNAL rxclko : STD_ULOGIC; -- PLE
	182	SIGNAL swni : grspw_in_type; -- PLE
	183	SIGNAL swno : grspw_out_type; -- PLE
	184	SIGNAL clkmn : STD_ULOGIC; -- PLE
	185	SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
	186
	187	-- AD Converter RHF1401
	188	SIGNAL sample : Samples14v(7 DOWNTO 0);
	189	SIGNAL sample_val : STD_LOGIC;
	190	-----------------------------------------------------------------------------
	191	SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
	192
	193	BEGIN
	194
	195
	196	----------------------------------------------------------------------
	197	--- Reset and Clock generation -------------------------------------
	198	----------------------------------------------------------------------
	199
	200	vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
	201	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
	202
	203	rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
	204
	205
	206	clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz);
	207
	208	clkgen0 : clkgen -- clock generator
	209	GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
	210	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
	211	PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
	212
	213	PROCESS(lclk100MHz)
	214	BEGIN
	215	IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
	216	lclk50MHz <= NOT lclk50MHz;
	217	END IF;
	218	END PROCESS;
	219
	220	PROCESS(lclk50MHz)
	221	BEGIN
	222	IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
	223	lclk25MHz <= NOT lclk25MHz;
	224	END IF;
	225	END PROCESS;
	226
	227	lclk2x <= lclk50MHz;
	228
	229	----------------------------------------------------------------------
	230	--- LEON3 processor / DSU / IRQ ------------------------------------
	231	----------------------------------------------------------------------
	232
	233	l3 : IF CFG_LEON3 = 1 GENERATE
	234	cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
	235	u0 : leon3s -- LEON3 processor
	236	GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
	237	0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
	238	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
	239	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
	240	CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
	241	CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
	242	PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
	243	irqi(i), irqo(i), dbgi(i), dbgo(i));
	244	END GENERATE;
	245	errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
	246
	247	dsugen : IF CFG_DSU = 1 GENERATE
	248	dsu0 : dsu3 -- LEON3 Debug Support Unit
	249	GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
	250	ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
	251	PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
	252	dsui.enable <= '1';
	253	dsui.break <= '0';
	254	led(2) <= dsuo.active;
	255	END GENERATE;
	256	END GENERATE;
	257
	258	nodsu : IF CFG_DSU = 0 GENERATE
	259	ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
	260	END GENERATE;
	261
	262	irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
	263	irqctrl0 : irqmp -- interrupt controller
	264	GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
	265	PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
	266	END GENERATE;
	267	irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
	268	x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
	269	irqi(i).irl <= "0000";
	270	END GENERATE;
	271	apbo(2) <= apb_none;
	272	END GENERATE;
	273
	274	----------------------------------------------------------------------
	275	--- Memory controllers ---------------------------------------------
	276	----------------------------------------------------------------------
	277	memctrlr : mctrl GENERIC MAP (
	278	hindex => 0,
	279	pindex => 0,
	280	paddr => 0,
	281	srbanks => 1
	282	)
	283	PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
	284
	285	memi.brdyn <= '1';
	286	memi.bexcn <= '1';
	287	memi.writen <= '1';
	288	memi.wrn <= "1111";
	289	memi.bwidth <= "10";
	290
	291	bdr : FOR i IN 0 TO 3 GENERATE
	292	data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
	293	PORT MAP (
	294	data(31-i8 DOWNTO 24-i8),
	295	memo.data(31-i8 DOWNTO 24-i8),
	296	memo.bdrive(i),
	297	memi.data(31-i8 DOWNTO 24-i8));
	298	END GENERATE;
	299
	300	addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
	301	PORT MAP (address, memo.address(21 DOWNTO 2));
	302
	303	rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
	304	oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
	305	nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
	306	nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
	307	nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
	308	nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
	309	nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
	310
	311	----------------------------------------------------------------------
	312	--- AHB CONTROLLER -------------------------------------------------
	313	----------------------------------------------------------------------
	314	ahb0 : ahbctrl -- AHB arbiter/multiplexer
	315	GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
	316	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
	317	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
	318	PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
	319
	320	----------------------------------------------------------------------
	321	--- AHB UART -------------------------------------------------------
	322	----------------------------------------------------------------------
	323	dcomgen : IF CFG_AHB_UART = 1 GENERATE
	324	dcom0 : ahbuart
	325	GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4)
	326	PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
	327	dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
	328	dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
	329	led(0) <= NOT ahbuarti.rxd;
	330	led(1) <= NOT ahbuarto.txd;
	331	END GENERATE;
	332	nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
	333
	334	----------------------------------------------------------------------
	335	--- APB Bridge -----------------------------------------------------
	336	----------------------------------------------------------------------
	337	apb0 : apbctrl -- AHB/APB bridge
	338	GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
	339	PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
	340
	341	----------------------------------------------------------------------
	342	--- GPT Timer ------------------------------------------------------
	343	----------------------------------------------------------------------
	344	gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
	345	timer0 : gptimer -- timer unit
	346	GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
	347	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
	348	nbits => CFG_GPT_TW)
	349	PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
	350	gpti.dhalt <= dsuo.tstop;
	351	gpti.extclk <= '0';
	352	END GENERATE;
	353	notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
	354
	355
	356	----------------------------------------------------------------------
	357	--- APB UART -------------------------------------------------------
	358	----------------------------------------------------------------------
	359	ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
	360	uart1 : apbuart -- UART 1
	361	GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
	362	fifosize => CFG_UART1_FIFO)
	363	PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
	364	apbuarti.rxd <= urxd1;
	365	apbuarti.extclk <= '0';
	366	utxd1 <= apbuarto.txd;
	367	apbuarti.ctsn <= '0';
	368	END GENERATE;
	369	noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
	370
	371	-------------------------------------------------------------------------------
	372	-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
	373	-------------------------------------------------------------------------------
	374	lfrtimemanagement0 : apb_lfr_time_management
	375	GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#,
	376	masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536,
	377	pirq => 12)
	378	PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6),
	379	coarse_time, fine_time);
	380
	381	-----------------------------------------------------------------------
	382	--- SpaceWire --------------------------------------------------------
	383	-----------------------------------------------------------------------
	384	spw_phy0 : grspw2_phy
	385	GENERIC MAP(
	386	scantest => 0,
	387	tech => memtech,
	388	input_type => 0) -- self_clocking mode
	389	PORT MAP(
	390	rstn => rstn,
	391	rxclki => clkm,
	392	rxclkin => clkmn,
	393	nrxclki => clkm, -- not used in self-clocking
	394	di => dtmp,
	395	si => stmp,
	396	do => swni.d(1 DOWNTO 0),
	397	dov => swni.dv(1 DOWNTO 0),
	398	dconnect => swni.dconnect(1 DOWNTO 0),
	399	rxclko => rxclko);
	400
	401	sw0 : grspwm
	402	GENERIC MAP(
	403	tech => apa3e,
	404	hindex => 1,
	405	pindex => 5,
	406	paddr => 5,
	407	pirq => 11,
	408	sysfreq => 25000,
	409	usegen => 1, -- sysfreq not used by the core version 2? usegen?
	410	nsync => 1, -- nsync not used by the core version 2?
	411	rmap => 1,
	412	rmapcrc => 1,
	413	fifosize1 => 16,
	414	fifosize2 => 16,
	415	rxclkbuftype => 2,
	416	rxunaligned => 0,
	417	spwcore => 2,
	418	memtech => apa3e,
	419	nodeaddr => 254,
	420	destkey => 2, -- added nodeaddr and destkey parameters
	421	rmapbufs => 4,
	422	netlist => 0,
	423	ft => 0,
	424	ports => 2)
	425	PORT MAP(
	426	rstn, clkm,
	427	rxclko, rxclko,
	428	txclk, txclk,
	429	ahbmi, ahbmo(1),
	430	apbi, apbo(5),
	431	swni, swno);
	432
	433	swni.tickin <= '0';
	434	swni.rmapen <= '1';
	435	swni.clkdiv10 <= "00001001";
	436
	437	spw1_dout <= swno.d(0);
	438	spw1_sout <= swno.s(0);
	439	dtmp <= spw1_din;
	440	stmp <= spw1_sin;
	441
	442	txclk <= lclk100MHz;
	443
	444
	445	-------------------------------------------------------------------------------
	446	-- WAVEFORM PICKER
	447	-------------------------------------------------------------------------------
	448	-- sdo_adc(4 DOWNTO 0) <= bias_adc(4 DOWNTO 0);
	449	-- sdo_adc(7 DOWNTO 5) <= scm_adc(2 DOWNTO 0);
	450
	451	waveform_picker0 : top_wf_picker
	452	GENERIC MAP(
	453	hindex => 2,
	454	pindex => 15,
	455	paddr => 15,
	456	pmask => 16#fff#,
	457	pirq => 14,
	458	tech => CFG_FABTECH,
	459	nb_burst_available_size => 12, -- size of the register holding the nb of burst
	460	nb_snapshot_param_size => 12, -- size of the register holding the snapshots size
	461	delta_snapshot_size => 16, -- snapshots period
	462	delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts
	463	delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot
	464	ENABLE_FILTER => '0'
	465	)
	466	PORT MAP(
	467	sample => sample,
	468	sample_val => sample_val,
	469	--
	470	cnv_clk => clk49_152MHz,
	471	cnv_rstn => rstn,
	472	-- AMBA AHB system signals
	473	HCLK => clkm,
	474	HRESETn => rstn,
	475	-- AMBA APB Slave Interface
	476	apbi => apbi,
	477	apbo => apbo(15),
	478	-- AMBA AHB Master Interface
	479	AHB_Master_In => ahbmi,
	480	AHB_Master_Out => ahbmo(2),
	481	--
	482	coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time
	483	--
	484	data_shaping_BW => bias_fail_sw
	485	);
	486
	487	top_ad_conv_RHF1401_1: top_ad_conv_RHF1401
	488	GENERIC MAP (
	489	ChanelCount => 8,
	490	ncycle_cnv_high => 79,
	491	ncycle_cnv => 500)
	492	PORT MAP (
	493	cnv_clk => clk49_152MHz,
	494	cnv_rstn => rstn,
	495
	496	cnv => ADC_smpclk,
	497
	498	clk => clkm,
	499	rstn => rstn,
	500	ADC_data => ADC_data,
	501	--ADC_smpclk => ,
	502	ADC_nOE => ADC_OEB_bar_CH_s,
	503	sample => sample,
	504	sample_val => sample_val);
	505
	506	ADC_OEB_bar_CH(0) <= ADC_OEB_bar_CH_s(5); -- B1
	507	ADC_OEB_bar_CH(1) <= ADC_OEB_bar_CH_s(6); -- B2
	508	ADC_OEB_bar_CH(2) <= ADC_OEB_bar_CH_s(7); -- B3
	509
	510	ADC_OEB_bar_CH(3) <= ADC_OEB_bar_CH_s(0); -- V1
	511	ADC_OEB_bar_CH(4) <= ADC_OEB_bar_CH_s(1); -- V2
	512	ADC_OEB_bar_CH(5) <= ADC_OEB_bar_CH_s(2); -- V3
	513	ADC_OEB_bar_CH(6) <= ADC_OEB_bar_CH_s(3); -- V4
	514	ADC_OEB_bar_CH(7) <= ADC_OEB_bar_CH_s(4); -- V5
	515
	516	END Behavioral; No newline at end of file

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/tb_wf_picker.vhd created 644 +253 0

			@@ -0,0 +1,253
		1	-----------------------------------------------------------------------------
		2	-- LEON3 Demonstration design
		3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 2 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	--
		15	-- You should have received a copy of the GNU General Public License
		16	-- along with this program; if not, write to the Free Software
		17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		18	------------------------------------------------------------------------------
		19
		20
		21	LIBRARY ieee;
		22	USE ieee.std_logic_1164.ALL;
		23	LIBRARY grlib;
		24	USE grlib.amba.ALL;
		25	USE grlib.stdlib.ALL;
		26	LIBRARY techmap;
		27	USE techmap.gencomp.ALL;
		28	LIBRARY gaisler;
		29	USE gaisler.memctrl.ALL;
		30	USE gaisler.leon3.ALL;
		31	USE gaisler.uart.ALL;
		32	USE gaisler.misc.ALL;
		33	USE gaisler.spacewire.ALL; -- PLE
		34
		35	LIBRARY esa;
		36	USE esa.memoryctrl.ALL;
		37	--USE work.config.ALL;
		38	LIBRARY lpp;
		39	USE lpp.lpp_memory.ALL;
		40	USE lpp.lpp_ad_conv.ALL;
		41	USE lpp.lpp_top_lfr_pkg.ALL;
		42	USE lpp.iir_filter.ALL;
		43	USE lpp.general_purpose.ALL;
		44	USE lpp.lpp_lfr_time_management.ALL;
		45
		46	ENTITY tb_wf_picker IS
		47	END;
		48
		49	ARCHITECTURE Behavioral OF tb_wf_picker IS
		50
		51	SIGNAL clk49_152MHz : STD_LOGIC := '0';
		52	SIGNAL clkm : STD_LOGIC := '0';
		53	SIGNAL rstn : STD_LOGIC := '0';
		54	SIGNAL coarse_time_0 : STD_LOGIC := '0';
		55
		56	-- ADC interface
		57	SIGNAL bias_fail_sw : STD_LOGIC; -- OUT
		58	SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
		59	SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
		60	SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
		61
		62	--
		63	SIGNAL apbi : apb_slv_in_type;
		64	SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
		65	SIGNAL ahbmi : ahb_mst_in_type;
		66	SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
		67
		68	-- internal
		69	SIGNAL sample : Samples14v(7 DOWNTO 0);
		70	SIGNAL sample_val : STD_LOGIC;
		71
		72	BEGIN
		73
		74	-----------------------------------------------------------------------------
		75
		76	MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE
		77	TestModule_RHF1401_1: TestModule_RHF1401
		78	GENERIC MAP (
		79	freq => 24*(I+1),
		80	amplitude => 8000/(I+1),
		81	impulsion => 0)
		82	PORT MAP (
		83	ADC_smpclk => ADC_smpclk,
		84	ADC_OEB_bar => ADC_OEB_bar_CH(I),
		85	ADC_data => ADC_data);
		86	END GENERATE MODULE_RHF1401;
		87
		88	-----------------------------------------------------------------------------
		89
		90	clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
		91	clkm <= NOT clkm AFTER 20 ns; -- 25 MHz
		92	coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms;
		93
		94	-----------------------------------------------------------------------------
		95	-- waveform generation
		96	WaveGen_Proc : PROCESS
		97	BEGIN
		98	-- insert signal assignments here
		99	WAIT UNTIL clkm = '1';
		100	apbi <= apb_slv_in_none;
		101	rstn <= '0';
		102	-- cnv_rstn <= '0';
		103	-- run_cnv <= '0';
		104	WAIT UNTIL clkm = '1';
		105	WAIT UNTIL clkm = '1';
		106	WAIT UNTIL clkm = '1';
		107	rstn <= '1';
		108	-- cnv_rstn <= '1';
		109	WAIT UNTIL clkm = '1';
		110	WAIT UNTIL clkm = '1';
		111	WAIT UNTIL clkm = '1';
		112	WAIT UNTIL clkm = '1';
		113	WAIT UNTIL clkm = '1';
		114	WAIT UNTIL clkm = '1';
		115	-- run_cnv <= '1';
		116	WAIT UNTIL clkm = '1';
		117	WAIT UNTIL clkm = '1';
		118	WAIT UNTIL clkm = '1';
		119	WAIT UNTIL clkm = '1';
		120	WAIT UNTIL clkm = '1';
		121	WAIT UNTIL clkm = '1';
		122	WAIT UNTIL clkm = '1';
		123	WAIT UNTIL clkm = '1';
		124	WAIT UNTIL clkm = '1';
		125	WAIT UNTIL clkm = '1';
		126	WAIT UNTIL clkm = '1';
		127	WAIT UNTIL clkm = '1';
		128	apbi.psel(15) <= '1';
		129	apbi.penable <= '1';
		130	apbi.pwrite <= '1';
		131	-- 765432
		132	apbi.paddr(7 DOWNTO 2) <= "001000";
		133	apbi.pwdata(4 DOWNTO 0) <= "00000";
		134	WAIT UNTIL clkm = '1';
		135	apbi.paddr(7 DOWNTO 2) <= "001001";
		136	apbi.pwdata(6 DOWNTO 0) <= "0000000";
		137	WAIT UNTIL clkm = '1';
		138	apbi.paddr(7 DOWNTO 2) <= "001010";
		139	apbi.pwdata <= "10000000000000000000000000000000";
		140	WAIT UNTIL clkm = '1';
		141	apbi.paddr(7 DOWNTO 2) <= "001011";
		142	apbi.pwdata <= "10010000000000000000000000000000";
		143	WAIT UNTIL clkm = '1';
		144	apbi.paddr(7 DOWNTO 2) <= "001100";
		145	apbi.pwdata <= "10100000000000000000000000000000";
		146	WAIT UNTIL clkm = '1';
		147	apbi.paddr(7 DOWNTO 2) <= "001101";
		148	apbi.pwdata <= "10110000000000000000000000000000";
		149	WAIT UNTIL clkm = '1';
		150	apbi.paddr(7 DOWNTO 2) <= "001110";
		151	apbi.pwdata(11 DOWNTO 0) <= "000000000000";
		152	WAIT UNTIL clkm = '1';
		153	apbi.paddr(7 DOWNTO 2) <= "001111";
		154	apbi.pwdata(15 DOWNTO 0) <= "0000000000000001"; -- A => 1 * 100 ms
		155	WAIT UNTIL clkm = '1';
		156	apbi.paddr(7 DOWNTO 2) <= "010000"; -- delta_f2_f1
		157	apbi.pwdata(15 DOWNTO 0) <= "0000000001111000"; -- 0x78 = 120
		158	WAIT UNTIL clkm = '1';
		159	apbi.paddr(7 DOWNTO 2) <= "010001"; -- delta_f2_f0
		160	apbi.pwdata(19 DOWNTO 0) <= "00000000001011111000"; -- 0x2f8 = 760
		161	WAIT UNTIL clkm = '1';
		162	apbi.paddr(7 DOWNTO 2) <= "010010"; -- nb_burst_available
		163	apbi.pwdata(11 DOWNTO 0) <= "000000001100"; -- 12 = 0xC
		164	WAIT UNTIL clkm = '1';
		165	apbi.paddr(7 DOWNTO 2) <= "010011"; -- nb_snapshot_param
		166	apbi.pwdata(11 DOWNTO 0) <= "000000001111"; -- 15 (+ 1)
		167	WAIT UNTIL clkm = '1';
		168	WAIT UNTIL clkm = '1';
		169	WAIT UNTIL clkm = '1';
		170	WAIT UNTIL clkm = '1';
		171	WAIT UNTIL clkm = '1';
		172	apbi.paddr(7 DOWNTO 2) <= "001001";
		173	apbi.pwdata(6 DOWNTO 0) <= "0000111";
		174	WAIT UNTIL clkm = '1';
		175	apbi.psel(15) <= '1';
		176	apbi.penable <= '0';
		177	apbi.pwrite <= '0';
		178	WAIT UNTIL clkm = '1';
		179
		180	WAIT;
		181
		182	END PROCESS WaveGen_Proc;
		183
		184
		185	ahbmi.HGRANT(2) <= '1';
		186	ahbmi.HREADY <= '1';
		187	ahbmi.HRESP <= HRESP_OKAY;
		188
		189
		190
		191	-------------------------------------------------------------------------------
		192	-------------------------------------------------------------------------------
		193	-- DUT ------------------------------------------------------------------------
		194	-------------------------------------------------------------------------------
		195	-------------------------------------------------------------------------------
		196
		197	top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
		198	GENERIC MAP (
		199	ChanelCount => 8,
		200	ncycle_cnv_high => 79,
		201	ncycle_cnv => 500)
		202	PORT MAP (
		203	cnv_clk => clk49_152MHz,
		204	cnv_rstn => rstn,
		205
		206	cnv => ADC_smpclk,
		207
		208	clk => clkm,
		209	rstn => rstn,
		210	ADC_data => ADC_data,
		211	ADC_nOE => ADC_OEB_bar_CH,
		212	sample => sample,
		213	sample_val => sample_val);
		214
		215	waveform_picker0 : top_wf_picker
		216	GENERIC MAP(
		217	hindex => 2,
		218	pindex => 15,
		219	paddr => 15,
		220	pmask => 16#fff#,
		221	pirq => 14,
		222	tech => inferred,
		223	nb_burst_available_size => 12, -- size of the register holding the nb of burst
		224	nb_snapshot_param_size => 12, -- size of the register holding the snapshots size
		225	delta_snapshot_size => 16, -- snapshots period
		226	delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts
		227	delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot
		228	ENABLE_FILTER => '0'
		229	)
		230	PORT MAP(
		231	sample => sample,
		232	sample_val => sample_val,
		233	--
		234	cnv_clk => clk49_152MHz,
		235	cnv_rstn => rstn,
		236	-- AMBA AHB system signals
		237	HCLK => clkm,
		238	HRESETn => rstn,
		239	-- AMBA APB Slave Interface
		240	apbi => apbi,
		241	apbo => apbo(15),
		242	-- AMBA AHB Master Interface
		243	AHB_Master_In => ahbmi,
		244	AHB_Master_Out => ahbmo(2),
		245	--
		246	coarse_time_0 => coarse_time_0, -- bit 0 of the coarse time
		247	--
		248	data_shaping_BW => bias_fail_sw
		249	);
		250	-------------------------------------------------------------------------------
		251	-------------------------------------------------------------------------------
		252
		253	END Behavioral;

designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/wave_tb.do created 644 +65 0

			@@ -0,0 +1,65
		1	onerror {resume}
		2	quietly WaveActivateNextPane {} 0
		3	add wave -noupdate /tb_wf_picker/clk49_152mhz
		4	add wave -noupdate /tb_wf_picker/clkm
		5	add wave -noupdate /tb_wf_picker/rstn
		6	add wave -noupdate /tb_wf_picker/coarse_time_0
		7	add wave -noupdate /tb_wf_picker/bias_fail_sw
		8	add wave -noupdate /tb_wf_picker/adc_oeb_bar_ch
		9	add wave -noupdate /tb_wf_picker/adc_smpclk
		10	add wave -noupdate /tb_wf_picker/adc_data
		11	add wave -noupdate /tb_wf_picker/apbi
		12	add wave -noupdate /tb_wf_picker/apbo
		13	add wave -noupdate /tb_wf_picker/ahbmi
		14	add wave -noupdate /tb_wf_picker/sample
		15	add wave -noupdate /tb_wf_picker/sample_val
		16	add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/cnv_clk
		17	add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/clk
		18	add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/rstn
		19	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_data
		20	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/chanelcount
		21	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_noe_reg_shift
		22	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_noe_reg
		23	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/sample_reg
		24	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/cnv_clk_reg
		25	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/start_readout
		26	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/state
		27	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_index
		28	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_noe
		29	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/sample_val
		30	add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/sample
		31	add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/cnv_clk
		32	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f3
		33	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f3_val
		34	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f2
		35	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f2_val
		36	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f1
		37	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f1_val
		38	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f0
		39	add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f0_val
		40	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren
		41	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren
		42	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/ren
		43	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/ready
		44	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata
		45	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen
		46	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen
		47	add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata
		48	add wave -noupdate /tb_wf_picker/ahbmo(2)
		49	TreeUpdate [SetDefaultTree]
		50	WaveRestoreCursors {{Cursor 1} {27385336150 ps} 0}
		51	configure wave -namecolwidth 644
		52	configure wave -valuecolwidth 534
		53	configure wave -justifyvalue left
		54	configure wave -signalnamewidth 0
		55	configure wave -snapdistance 10
		56	configure wave -datasetprefix 0
		57	configure wave -rowmargin 4
		58	configure wave -childrowmargin 2
		59	configure wave -gridoffset 0
		60	configure wave -gridperiod 1
		61	configure wave -griddelta 40
		62	configure wave -timeline 0
		63	configure wave -timelineunits ns
		64	update
		65	WaveRestoreZoom {2342005961 ps} {4381125074 ps}

lib/lpp/dsp/lpp_fft/lpp_fft.vhd +259 -259

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			@@ -1,260 +1,260
	1		------------------------------------------------------------------------------
	2		-- This file is a part of the LPP VHDL IP LIBRARY
	3		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4		--
	5		-- This program is free software; you can redistribute it and/or modify
	6		-- it under the terms of the GNU General Public License as published by
	7		-- the Free Software Foundation; either version 3 of the License, or
	8		-- (at your option) any later version.
	9		--
	10		-- This program is distributed in the hope that it will be useful,
	11		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13		-- GNU General Public License for more details.
	14		--
	15		-- You should have received a copy of the GNU General Public License
	16		-- along with this program; if not, write to the Free Software
	17		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18		------------------------------------------------------------------------------
	19		-- Author : Martin Morlot
	20		-- Mail : martin.morlot@lpp.polytechnique.fr
	21		------------------------------------------------------------------------------
	22		library ieee;
	23		use ieee.std_logic_1164.all;
	24		library grlib;
	25		use grlib.amba.all;
	26		use std.textio.all;
	27		library lpp;
	28		use lpp.lpp_amba.all;
	29		use ~~work~~.fft_components.all;
	30
	31		--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
	32
	33		package lpp_fft is
	34
	35		component APB_FFT is
	36		generic (
	37		pindex : integer := 0;
	38		paddr : integer := 0;
	39		pmask : integer := 16#fff#;
	40		pirq : integer := 0;
	41		abits : integer := 8;
	42		Data_sz : integer := 16
	43		);
	44		port (
	45		clk : in std_logic;
	46		rst : in std_logic; --! Reset general du composant
	47		apbi : in apb_slv_in_type;
	48		apbo : out apb_slv_out_type
	49		);
	50		end component;
	51
	52
	53		component APB_FFT_half is
	54		generic (
	55		pindex : integer := 0;
	56		paddr : integer := 0;
	57		pmask : integer := 16#fff#;
	58		pirq : integer := 0;
	59		abits : integer := 8;
	60		Data_sz : integer := 16
	61		);
	62		port (
	63		clk : in std_logic; --! Horloge du composant
	64		rst : in std_logic; --! Reset general du composant
	65		Ren : in std_logic;
	66		ready : out std_logic;
	67		valid : out std_logic;
	68		DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
	69		DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
	70		OUTfill : out std_logic;
	71		OUTwrite : out std_logic;
	72		apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
	73		apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
	74		);
	75		end component;
	76
	77		component FFT is
	78		generic(
	79		Data_sz : integer := 16;
	80		NbData : integer := 256);
	81		port(
	82		clkm : in std_logic;
	83		rstn : in std_logic;
	84		FifoIN_Empty : in std_logic_vector(4 downto 0);
	85		FifoIN_Data : in std_logic_vector(79 downto 0);
	86		FifoOUT_Full : in std_logic_vector(4 downto 0);
	87		Load : out std_logic;
	88		Read : out std_logic_vector(4 downto 0);
	89		Write : out std_logic_vector(4 downto 0);
	90		ReUse : out std_logic_vector(4 downto 0);
	91		Data : out std_logic_vector(79 downto 0)
	92		);
	93		end component;
	94
	95		component Flag_Extremum is
	96		port(
	97		clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
	98		load : in std_logic; --! Signal en provenance de CoreFFT
	99		y_rdy : in std_logic; --! Signal en provenance de CoreFFT
	100		fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
	101		ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
	102		);
	103		end component;
	104
	105
	106		component Linker_FFT is
	107		generic(
	108		Data_sz : integer range 1 to 32 := 16;
	109		NbData : integer range 1 to 512 := 256
	110		);
	111		port(
	112		clk : in std_logic;
	113		rstn : in std_logic;
	114		Ready : in std_logic;
	115		Valid : in std_logic;
	116		Full : in std_logic_vector(4 downto 0);
	117		Data_re : in std_logic_vector(Data_sz-1 downto 0);
	118		Data_im : in std_logic_vector(Data_sz-1 downto 0);
	119		Read : out std_logic;
	120		Write : out std_logic_vector(4 downto 0);
	121		ReUse : out std_logic_vector(4 downto 0);
	122		DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
	123		);
	124		end component;
	125
	126
	127		component Driver_FFT is
	128		generic(
	129		Data_sz : integer range 1 to 32 := 16;
	130		NbData : integer range 1 to 512 := 256
	131		);
	132		port(
	133		clk : in std_logic;
	134		rstn : in std_logic;
	135		Load : in std_logic;
	136		Empty : in std_logic_vector(4 downto 0);
	137		DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
	138		Valid : out std_logic;
	139		Read : out std_logic_vector(4 downto 0);
	140		Data_re : out std_logic_vector(Data_sz-1 downto 0);
	141		Data_im : out std_logic_vector(Data_sz-1 downto 0)
	142		);
	143		end component;
	144
	145		component FFTamont is
	146		generic(
	147		Data_sz : integer range 1 to 32 := 16;
	148		NbData : integer range 1 to 512 := 256
	149		);
	150		port(
	151		clk : in std_logic;
	152		rstn : in std_logic;
	153		Load : in std_logic;
	154		Empty : in std_logic;
	155		DATA : in std_logic_vector(Data_sz-1 downto 0);
	156		Valid : out std_logic;
	157		Read : out std_logic;
	158		Data_re : out std_logic_vector(Data_sz-1 downto 0);
	159		Data_im : out std_logic_vector(Data_sz-1 downto 0)
	160		);
	161		end component;
	162
	163		component FFTaval is
	164		generic(
	165		Data_sz : integer range 1 to 32 := 8;
	166		NbData : integer range 1 to 512 := 256
	167		);
	168		port(
	169		clk : in std_logic;
	170		rstn : in std_logic;
	171		Ready : in std_logic;
	172		Valid : in std_logic;
	173		Full : in std_logic;
	174		Data_re : in std_logic_vector(Data_sz-1 downto 0);
	175		Data_im : in std_logic_vector(Data_sz-1 downto 0);
	176		Read : out std_logic;
	177		Write : out std_logic;
	178		ReUse : out std_logic;
	179		DATA : out std_logic_vector(Data_sz-1 downto 0)
	180		);
	181		end component;
	182		--==============================================================\|
	183		--================== IP VHDL de la FFT actel ===================\|
	184		--================ non partag� dans la VHD_Lib =================\|
	185		--==============================================================\|
	186
	187		component CoreFFT IS
	188		GENERIC (
	189		LOGPTS : integer := gLOGPTS;
	190		LOGLOGPTS : integer := gLOGLOGPTS;
	191		WSIZE : integer := gWSIZE;
	192		TWIDTH : integer := gTWIDTH;
	193		DWIDTH : integer := gDWIDTH;
	194		TDWIDTH : integer := gTDWIDTH;
	195		RND_MODE : integer := gRND_MODE;
	196		SCALE_MODE : integer := gSCALE_MODE;
	197		PTS : integer := gPTS;
	198		HALFPTS : integer := gHALFPTS;
	199		inBuf_RWDLY : integer := gInBuf_RWDLY );
	200		PORT (
	201		clk,ifiStart,ifiNreset : IN std_logic;
	202		ifiD_valid, ifiRead_y : IN std_logic;
	203		ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
	204		ifoLoad, ifoPong : OUT std_logic;
	205		ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
	206		ifoY_valid, ifoY_rdy : OUT std_logic);
	207		END component;
	208
	209
	210		component actar is
	211		port( DataA : in std_logic_vector(15 downto 0); DataB : in
	212		std_logic_vector(15 downto 0); Mult : out
	213		std_logic_vector(31 downto 0);Clock : in std_logic) ;
	214		end component;
	215
	216		component actram is
	217		port( DI : in std_logic_vector(31 downto 0); DO : out
	218		std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
	219		WADDR : in std_logic_vector(6 downto 0); RADDR : in
	220		std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
	221		std_logic) ;
	222		end component;
	223
	224		component switch IS
	225		GENERIC ( DWIDTH : integer := 32 );
	226		PORT (
	227		clk, sel, validIn : IN std_logic;
	228		inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
	229		outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
	230		validOut : OUT std_logic);
	231		END component;
	232
	233		component twid_rA IS
	234		GENERIC (LOGPTS : integer := 8;
	235		LOGLOGPTS : integer := 3 );
	236		PORT (clk : IN std_logic;
	237		timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
	238		stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
	239		tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
	240		END component;
	241
	242		component counter IS
	243		GENERIC (
	244		WIDTH : integer := 7;
	245		TERMCOUNT : integer := 127 );
	246		PORT (
	247		clk, nGrst, rst, cntEn : IN std_logic;
	248		tc : OUT std_logic;
	249		Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
	250		END component;
	251
	252
	253		component twiddle IS
	254		PORT (
	255		A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
	256		T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
	257		END component;
	258
	259
		1	------------------------------------------------------------------------------
		2	-- This file is a part of the LPP VHDL IP LIBRARY
		3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 3 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	--
		15	-- You should have received a copy of the GNU General Public License
		16	-- along with this program; if not, write to the Free Software
		17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		18	------------------------------------------------------------------------------
		19	-- Author : Martin Morlot
		20	-- Mail : martin.morlot@lpp.polytechnique.fr
		21	------------------------------------------------------------------------------
		22	library ieee;
		23	use ieee.std_logic_1164.all;
		24	library grlib;
		25	use grlib.amba.all;
		26	use std.textio.all;
		27	library lpp;
		28	use lpp.lpp_amba.all;
		29	use lpp.fft_components.all;
		30
		31	--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
		32
		33	package lpp_fft is
		34
		35	component APB_FFT is
		36	generic (
		37	pindex : integer := 0;
		38	paddr : integer := 0;
		39	pmask : integer := 16#fff#;
		40	pirq : integer := 0;
		41	abits : integer := 8;
		42	Data_sz : integer := 16
		43	);
		44	port (
		45	clk : in std_logic;
		46	rst : in std_logic; --! Reset general du composant
		47	apbi : in apb_slv_in_type;
		48	apbo : out apb_slv_out_type
		49	);
		50	end component;
		51
		52
		53	component APB_FFT_half is
		54	generic (
		55	pindex : integer := 0;
		56	paddr : integer := 0;
		57	pmask : integer := 16#fff#;
		58	pirq : integer := 0;
		59	abits : integer := 8;
		60	Data_sz : integer := 16
		61	);
		62	port (
		63	clk : in std_logic; --! Horloge du composant
		64	rst : in std_logic; --! Reset general du composant
		65	Ren : in std_logic;
		66	ready : out std_logic;
		67	valid : out std_logic;
		68	DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
		69	DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
		70	OUTfill : out std_logic;
		71	OUTwrite : out std_logic;
		72	apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
		73	apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
		74	);
		75	end component;
		76
		77	component FFT is
		78	generic(
		79	Data_sz : integer := 16;
		80	NbData : integer := 256);
		81	port(
		82	clkm : in std_logic;
		83	rstn : in std_logic;
		84	FifoIN_Empty : in std_logic_vector(4 downto 0);
		85	FifoIN_Data : in std_logic_vector(79 downto 0);
		86	FifoOUT_Full : in std_logic_vector(4 downto 0);
		87	Load : out std_logic;
		88	Read : out std_logic_vector(4 downto 0);
		89	Write : out std_logic_vector(4 downto 0);
		90	ReUse : out std_logic_vector(4 downto 0);
		91	Data : out std_logic_vector(79 downto 0)
		92	);
		93	end component;
		94
		95	component Flag_Extremum is
		96	port(
		97	clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
		98	load : in std_logic; --! Signal en provenance de CoreFFT
		99	y_rdy : in std_logic; --! Signal en provenance de CoreFFT
		100	fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
		101	ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
		102	);
		103	end component;
		104
		105
		106	component Linker_FFT is
		107	generic(
		108	Data_sz : integer range 1 to 32 := 16;
		109	NbData : integer range 1 to 512 := 256
		110	);
		111	port(
		112	clk : in std_logic;
		113	rstn : in std_logic;
		114	Ready : in std_logic;
		115	Valid : in std_logic;
		116	Full : in std_logic_vector(4 downto 0);
		117	Data_re : in std_logic_vector(Data_sz-1 downto 0);
		118	Data_im : in std_logic_vector(Data_sz-1 downto 0);
		119	Read : out std_logic;
		120	Write : out std_logic_vector(4 downto 0);
		121	ReUse : out std_logic_vector(4 downto 0);
		122	DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
		123	);
		124	end component;
		125
		126
		127	component Driver_FFT is
		128	generic(
		129	Data_sz : integer range 1 to 32 := 16;
		130	NbData : integer range 1 to 512 := 256
		131	);
		132	port(
		133	clk : in std_logic;
		134	rstn : in std_logic;
		135	Load : in std_logic;
		136	Empty : in std_logic_vector(4 downto 0);
		137	DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
		138	Valid : out std_logic;
		139	Read : out std_logic_vector(4 downto 0);
		140	Data_re : out std_logic_vector(Data_sz-1 downto 0);
		141	Data_im : out std_logic_vector(Data_sz-1 downto 0)
		142	);
		143	end component;
		144
		145	component FFTamont is
		146	generic(
		147	Data_sz : integer range 1 to 32 := 16;
		148	NbData : integer range 1 to 512 := 256
		149	);
		150	port(
		151	clk : in std_logic;
		152	rstn : in std_logic;
		153	Load : in std_logic;
		154	Empty : in std_logic;
		155	DATA : in std_logic_vector(Data_sz-1 downto 0);
		156	Valid : out std_logic;
		157	Read : out std_logic;
		158	Data_re : out std_logic_vector(Data_sz-1 downto 0);
		159	Data_im : out std_logic_vector(Data_sz-1 downto 0)
		160	);
		161	end component;
		162
		163	component FFTaval is
		164	generic(
		165	Data_sz : integer range 1 to 32 := 8;
		166	NbData : integer range 1 to 512 := 256
		167	);
		168	port(
		169	clk : in std_logic;
		170	rstn : in std_logic;
		171	Ready : in std_logic;
		172	Valid : in std_logic;
		173	Full : in std_logic;
		174	Data_re : in std_logic_vector(Data_sz-1 downto 0);
		175	Data_im : in std_logic_vector(Data_sz-1 downto 0);
		176	Read : out std_logic;
		177	Write : out std_logic;
		178	ReUse : out std_logic;
		179	DATA : out std_logic_vector(Data_sz-1 downto 0)
		180	);
		181	end component;
		182	--==============================================================\|
		183	--================== IP VHDL de la FFT actel ===================\|
		184	--================ non partag� dans la VHD_Lib =================\|
		185	--==============================================================\|
		186
		187	component CoreFFT IS
		188	GENERIC (
		189	LOGPTS : integer := gLOGPTS;
		190	LOGLOGPTS : integer := gLOGLOGPTS;
		191	WSIZE : integer := gWSIZE;
		192	TWIDTH : integer := gTWIDTH;
		193	DWIDTH : integer := gDWIDTH;
		194	TDWIDTH : integer := gTDWIDTH;
		195	RND_MODE : integer := gRND_MODE;
		196	SCALE_MODE : integer := gSCALE_MODE;
		197	PTS : integer := gPTS;
		198	HALFPTS : integer := gHALFPTS;
		199	inBuf_RWDLY : integer := gInBuf_RWDLY );
		200	PORT (
		201	clk,ifiStart,ifiNreset : IN std_logic;
		202	ifiD_valid, ifiRead_y : IN std_logic;
		203	ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
		204	ifoLoad, ifoPong : OUT std_logic;
		205	ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
		206	ifoY_valid, ifoY_rdy : OUT std_logic);
		207	END component;
		208
		209
		210	component actar is
		211	port( DataA : in std_logic_vector(15 downto 0); DataB : in
		212	std_logic_vector(15 downto 0); Mult : out
		213	std_logic_vector(31 downto 0);Clock : in std_logic) ;
		214	end component;
		215
		216	component actram is
		217	port( DI : in std_logic_vector(31 downto 0); DO : out
		218	std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
		219	WADDR : in std_logic_vector(6 downto 0); RADDR : in
		220	std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
		221	std_logic) ;
		222	end component;
		223
		224	component switch IS
		225	GENERIC ( DWIDTH : integer := 32 );
		226	PORT (
		227	clk, sel, validIn : IN std_logic;
		228	inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
		229	outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
		230	validOut : OUT std_logic);
		231	END component;
		232
		233	component twid_rA IS
		234	GENERIC (LOGPTS : integer := 8;
		235	LOGLOGPTS : integer := 3 );
		236	PORT (clk : IN std_logic;
		237	timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
		238	stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
		239	tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
		240	END component;
		241
		242	component counter IS
		243	GENERIC (
		244	WIDTH : integer := 7;
		245	TERMCOUNT : integer := 127 );
		246	PORT (
		247	clk, nGrst, rst, cntEn : IN std_logic;
		248	tc : OUT std_logic;
		249	Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
		250	END component;
		251
		252
		253	component twiddle IS
		254	PORT (
		255	A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
		256	T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
		257	END component;
		258
		259
	260	260	end; No newline at end of file

lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +1 -1

              LIBRARY ieee;
              USE ieee.std_logic_1164.ALL;
              LIBRARY lpp;
              USE lpp.lpp_ad_conv.ALL;
              USE lpp.iir_filter.ALL;
              USE lpp.FILTERcfg.ALL;
              USE lpp.lpp_memory.ALL;
              USE lpp.lpp_top_lfr_pkg.ALL;
              LIBRARY techmap;
              USE techmap.gencomp.ALL;
              ENTITY lpp_top_acq IS
                GENERIC(
                  tech : INTEGER := 0
                  );
                PORT (
                  -- ADS7886
                  cnv_run         : IN  STD_LOGIC;
                  cnv             : OUT STD_LOGIC;
                  sck             : OUT STD_LOGIC;
                  sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                  --
                  cnv_clk         : IN  STD_LOGIC;    -- 49 MHz
                  cnv_rstn        : IN  STD_LOGIC;
                  --
                  clk             : IN  STD_LOGIC;    -- 25 MHz
                  rstn            : IN  STD_LOGIC;
                  --
                  sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                  sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                  --
                  sample_f1_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                  sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                  --
                  sample_f2_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                  sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                  --
                  sample_f3_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                  sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
                  );
              END lpp_top_acq;
              ARCHITECTURE tb OF lpp_top_acq IS
                COMPONENT Downsampling
                  GENERIC (
                    ChanelCount : INTEGER;
                    SampleSize  : INTEGER;
                    DivideParam : INTEGER);
                  PORT (
                    clk            : IN  STD_LOGIC;
                    rstn           : IN  STD_LOGIC;
                    sample_in_val  : IN  STD_LOGIC;
                    sample_in      : IN  samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
                    sample_out_val : OUT STD_LOGIC;
                    sample_out     : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
                END COMPONENT;
                -----------------------------------------------------------------------------
                CONSTANT ChanelCount     : INTEGER := 8;
                CONSTANT ncycle_cnv_high : INTEGER := 79;
                CONSTANT ncycle_cnv      : INTEGER := 500;
                -----------------------------------------------------------------------------
                SIGNAL   sample           : Samples(ChanelCount-1 DOWNTO 0);
                SIGNAL   sample_val       : STD_LOGIC;
                SIGNAL   sample_val_delay : STD_LOGIC;
                -----------------------------------------------------------------------------
                CONSTANT Coef_SZ          : INTEGER := 9;
                CONSTANT CoefCntPerCel    : INTEGER := 6;
                CONSTANT CoefPerCel       : INTEGER := 5;
                CONSTANT Cels_count       : INTEGER := 5;
                SIGNAL coefs_v2                    : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
                SIGNAL sample_filter_in            : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                --
                SIGNAL sample_filter_v2_out_val    : STD_LOGIC;
                SIGNAL sample_filter_v2_out        : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                --
                SIGNAL sample_filter_v2_out_r_val  : STD_LOGIC;
                SIGNAL sample_filter_v2_out_r      : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                -----------------------------------------------------------------------------
                SIGNAL downsampling_cnt            : STD_LOGIC_VECTOR(1 DOWNTO 0);
                SIGNAL sample_downsampling_out_val : STD_LOGIC;
                SIGNAL sample_downsampling_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                --
                SIGNAL sample_f0_val               : STD_LOGIC;
                SIGNAL sample_f0                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                -----------------------------------------------------------------------------
                SIGNAL sample_f1_val               : STD_LOGIC;
                SIGNAL sample_f1                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                --
                SIGNAL sample_f2_val               : STD_LOGIC;
                SIGNAL sample_f2                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                --
                SIGNAL sample_f3_val               : STD_LOGIC;
                SIGNAL sample_f3                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
              BEGIN
                -- component instantiation
                -----------------------------------------------------------------------------
                DIGITAL_acquisition : AD7688_drvr
                  GENERIC MAP (
                    ChanelCount     => ChanelCount,
                    ncycle_cnv_high => ncycle_cnv_high,
                    ncycle_cnv      => ncycle_cnv)
                  PORT MAP (
                    cnv_clk    => cnv_clk,                      --
                    cnv_rstn   => cnv_rstn,                     --
                    cnv_run    => cnv_run,                      --
                    cnv        => cnv,                          --
                    clk        => clk,                          --
                    rstn       => rstn,                         --
                    sck        => sck,                          --
                    sdo        => sdo(ChanelCount-1 DOWNTO 0),  --
                    sample     => sample,
                    sample_val => sample_val);
                -----------------------------------------------------------------------------
                PROCESS (clk, rstn)
                BEGIN  -- PROCESS
                  IF rstn = '0' THEN                  -- asynchronous reset (active low)
                    sample_val_delay <= '0';
                  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                    sample_val_delay <= sample_val;
                  END IF;
                END PROCESS;
                -----------------------------------------------------------------------------
                ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
                  SampleLoop : FOR j IN 0 TO 15 GENERATE
                    sample_filter_in(i, j) <= sample(i)(j);
                  END GENERATE;
                  sample_filter_in(i, 16) <= sample(i)(15);
                  sample_filter_in(i, 17) <= sample(i)(15);
                END GENERATE;
                coefs_v2 <= CoefsInitValCst_v2;
                IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                  GENERIC MAP (
                    tech         => 0,
-                   Mem_use      => use_RAM,
+                   Mem_use      => use_CEL, -- use_RAM
                    Sample_SZ    => 18,
                    Coef_SZ      => Coef_SZ,
                    Coef_Nb      => 25,               -- TODO
                    Coef_sel_SZ  => 5,                -- TODO
                    Cels_count   => Cels_count,
                    ChanelsCount => ChanelCount)
                  PORT MAP (
                    rstn           => rstn,
                    clk            => clk,
                    virg_pos       => 7,
                    coefs          => coefs_v2,
                    sample_in_val  => sample_val_delay,
                    sample_in      => sample_filter_in,
                    sample_out_val => sample_filter_v2_out_val,
                    sample_out     => sample_filter_v2_out);
                -----------------------------------------------------------------------------
                PROCESS (clk, rstn)
                BEGIN  -- PROCESS
                  IF rstn = '0' THEN                  -- asynchronous reset (active low)
                    sample_filter_v2_out_r_val <= '0';
                    rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
                      rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
                        sample_filter_v2_out_r(I, J) <= '0';
                      END LOOP rst_all_bits;
                    END LOOP rst_all_chanel;
                  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                    sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
                    IF sample_filter_v2_out_val = '1' THEN
                      sample_filter_v2_out_r <= sample_filter_v2_out;
                    END IF;
                  END IF;
                END PROCESS;
                -----------------------------------------------------------------------------
                -- F0 -- @24.576 kHz
                -----------------------------------------------------------------------------
                Downsampling_f0 : Downsampling
                  GENERIC MAP (
                    ChanelCount => ChanelCount,
                    SampleSize  => 18,
                    DivideParam => 4)
                  PORT MAP (
                    clk            => clk,
                    rstn           => rstn,
                    sample_in_val  => sample_filter_v2_out_val ,
                    sample_in      => sample_filter_v2_out,
                    sample_out_val => sample_f0_val,
                    sample_out     => sample_f0);
                all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
                  sample_f0_wdata(I)      <= sample_f0(0, I);
                  sample_f0_wdata(16*1+I) <= sample_f0(1, I);
                  sample_f0_wdata(16*2+I) <= sample_f0(2, I);
                  sample_f0_wdata(16*3+I) <= sample_f0(6, I);
                  sample_f0_wdata(16*4+I) <= sample_f0(7, I);
                END GENERATE all_bit_sample_f0;
                  sample_f0_wen <= NOT(sample_f0_val) &
                                   NOT(sample_f0_val) &
                                   NOT(sample_f0_val) &
                                   NOT(sample_f0_val) &
                                   NOT(sample_f0_val);
                -----------------------------------------------------------------------------
                -- F1 -- @4096 Hz
                -----------------------------------------------------------------------------
                Downsampling_f1 : Downsampling
                  GENERIC MAP (
                    ChanelCount => ChanelCount,
                    SampleSize  => 18,
                    DivideParam => 6)
                  PORT MAP (
                    clk            => clk,
                    rstn           => rstn,
                    sample_in_val  => sample_f0_val ,
                    sample_in      => sample_f0,
                    sample_out_val => sample_f1_val,
                    sample_out     => sample_f1);
                sample_f1_wen <= NOT(sample_f1_val) &
                                   NOT(sample_f1_val) &
                                   NOT(sample_f1_val) &
                                   NOT(sample_f1_val) &
                                   NOT(sample_f1_val);
                all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
                  sample_f1_wdata(I)      <= sample_f1(0, I);
                  sample_f1_wdata(16*1+I) <= sample_f1(1, I);
                  sample_f1_wdata(16*2+I) <= sample_f1(2, I);
                  sample_f1_wdata(16*3+I) <= sample_f1(6, I);
                  sample_f1_wdata(16*4+I) <= sample_f1(7, I);
                END GENERATE all_bit_sample_f1;
                -----------------------------------------------------------------------------
                -- F2 -- @16 Hz
                -----------------------------------------------------------------------------
                Downsampling_f2 : Downsampling
                  GENERIC MAP (
                    ChanelCount => ChanelCount,
                    SampleSize  => 18,
                    DivideParam => 96)
                  PORT MAP (
                    clk            => clk,
                    rstn           => rstn,
                    sample_in_val  => sample_f1_val ,
                    sample_in      => sample_f1,
                    sample_out_val => sample_f2_val,
                    sample_out     => sample_f2);
                sample_f2_wen <= NOT(sample_f2_val) &
                                   NOT(sample_f2_val) &
                                   NOT(sample_f2_val) &
                                   NOT(sample_f2_val) &
                                   NOT(sample_f2_val);
                all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
                  sample_f2_wdata(I)      <= sample_f2(0, I);
                  sample_f2_wdata(16*1+I) <= sample_f2(1, I);
                  sample_f2_wdata(16*2+I) <= sample_f2(2, I);
                  sample_f2_wdata(16*3+I) <= sample_f2(6, I);
                  sample_f2_wdata(16*4+I) <= sample_f2(7, I);
                END GENERATE all_bit_sample_f2;
                -----------------------------------------------------------------------------
                -- F3 -- @256 Hz
                -----------------------------------------------------------------------------
                Downsampling_f3 : Downsampling
                  GENERIC MAP (
                    ChanelCount => ChanelCount,
                    SampleSize  => 18,
                    DivideParam => 256)
                  PORT MAP (
                    clk            => clk,
                    rstn           => rstn,
                    sample_in_val  => sample_f0_val ,
                    sample_in      => sample_f0,
                    sample_out_val => sample_f3_val,
                    sample_out     => sample_f3);
                sample_f3_wen <= (NOT sample_f3_val) &
                                   (NOT sample_f3_val) &
                                   (NOT sample_f3_val) &
                                   (NOT sample_f3_val) &
                                   (NOT sample_f3_val);
                all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
                  sample_f3_wdata(I)      <= sample_f3(0, I);
                  sample_f3_wdata(16*1+I) <= sample_f3(1, I);
                  sample_f3_wdata(16*2+I) <= sample_f3(2, I);
                  sample_f3_wdata(16*3+I) <= sample_f3(6, I);
                  sample_f3_wdata(16*4+I) <= sample_f3(7, I);
                END GENERATE all_bit_sample_f3;
              END tb;

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