HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r575:125577122712

add custom AHB DMA

pellion -

r575:125577122712 simu_double_DMA

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r575:125577122712

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lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd created 644 +178 0

@@ -0,0 +1,178
	1
	2	------------------------------------------------------------------------------
	3	-- This file is a part of the LPP VHDL IP LIBRARY
	4	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	5	--
	6	-- This program is free software; you can redistribute it and/or modify
	7	-- it under the terms of the GNU General Public License as published by
	8	-- the Free Software Foundation; either version 3 of the License, or
	9	-- (at your option) any later version.
	10	--
	11	-- This program is distributed in the hope that it will be useful,
	12	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	-- GNU General Public License for more details.
	15	--
	16	-- You should have received a copy of the GNU General Public License
	17	-- along with this program; if not, write to the Free Software
	18	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	-------------------------------------------------------------------------------
	20	-- Author : Jean-christophe Pellion
	21	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	22	-- jean-christophe.pellion@easii-ic.com
	23	-------------------------------------------------------------------------------
	24	-- 1.0 - initial version
	25	-------------------------------------------------------------------------------
	26	LIBRARY ieee;
	27	USE ieee.std_logic_1164.ALL;
	28	USE ieee.numeric_std.ALL;
	29	LIBRARY grlib;
	30	USE grlib.amba.ALL;
	31	USE grlib.stdlib.ALL;
	32	USE grlib.devices.ALL;
	33
	34	LIBRARY lpp;
	35	USE lpp.lpp_amba.ALL;
	36	USE lpp.apb_devices_list.ALL;
	37	USE lpp.lpp_memory.ALL;
	38	USE lpp.lpp_dma_pkg.ALL;
	39	USE lpp.general_purpose.ALL;
	40	--USE lpp.lpp_waveform_pkg.ALL;
	41	LIBRARY techmap;
	42	USE techmap.gencomp.ALL;
	43
	44
	45	ENTITY lpp_dma_SEND16B_FIFO2DMA IS
	46	GENERIC (
	47	hindex : INTEGER := 2;
	48	vendorid : IN INTEGER := 0;
	49	deviceid : IN INTEGER := 0;
	50	version : IN INTEGER := 0
	51	);
	52	PORT (
	53	clk : IN STD_LOGIC;
	54	rstn : IN STD_LOGIC;
	55
	56	-- AMBA AHB Master Interface
	57	AHB_Master_In : IN AHB_Mst_In_Type;
	58	AHB_Master_Out : OUT AHB_Mst_Out_Type;
	59
	60	-- FIFO Interface
	61	ren : OUT STD_LOGIC;
	62	data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	63
	64	-- Controls
	65	send : IN STD_LOGIC;
	66	valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
	67	done : OUT STD_LOGIC;
	68	address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
	69	);
	70	END;
	71
	72	ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
	73
	74	CONSTANT HConfig : AHB_Config_Type := (
	75	0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
	76	OTHERS => (OTHERS => '0'));
	77
	78	SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
	79	SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
	80
	81	SIGNAL address_counter_reset : STD_LOGIC;
	82	SIGNAL address_counter_add1 : STD_LOGIC;
	83
	84	SIGNAL REQ_ON_GOING : STD_LOGIC;
	85	SIGNAL DATA_ON_GOING : STD_LOGIC;
	86	SIGNAL DATA_ON_GOING_s : STD_LOGIC;
	87	SIGNAL TRANSACTION_ON_GOING : STD_LOGIC;
	88	SIGNAL internal_send : STD_LOGIC;
	89
	90	BEGIN
	91
	92	-----------------------------------------------------------------------------
	93	AHB_Master_Out.HCONFIG <= HConfig;
	94	AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
	95	AHB_Master_Out.HINDEX <= hindex;
	96	AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
	97	AHB_Master_Out.HIRQ <= (OTHERS => '0');
	98	AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16
	99	AHB_Master_Out.HWRITE <= '1';
	100	AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
	101
	102	AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
	103	AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
	104	-----------------------------------------------------------------------------
	105
	106	AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
	107	AHB_Master_Out.HWDATA <= ahbdrivedata(data);
	108
	109
	110	-----------------------------------------------------------------------------
	111	-- REN GEN
	112	-----------------------------------------------------------------------------
	113	ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING);
	114
	115	-----------------------------------------------------------------------------
	116	-- ADDR GEN
	117	-----------------------------------------------------------------------------
	118	PROCESS (clk, rstn)
	119	BEGIN -- PROCESS
	120	IF rstn = '0' THEN -- asynchronous reset (active low)
	121	address_counter_reg <= (OTHERS => '0');
	122	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	123	IF DATA_ON_GOING = '0' THEN
	124	address_counter_reg <= (OTHERS => '0');
	125	ELSE
	126	address_counter_reg <= address_counter;
	127	END IF;
	128	END IF;
	129	END PROCESS;
	130
	131	--address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
	132	-- address_counter_reg;
	133	address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
	134	address_counter_reg;
	135
	136	-----------------------------------------------------------------------------
	137	--
	138	-----------------------------------------------------------------------------
	139	PROCESS (clk, rstn)
	140	BEGIN -- PROCESS
	141	IF rstn = '0' THEN -- asynchronous reset (active low)
	142	REQ_ON_GOING <= '0';
	143	done <= '0';
	144	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	145	done <= '0';
	146	IF send = '1' THEN --send = '1' THEN
	147	REQ_ON_GOING <= '1';
	148	ELSE
	149	IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN
	150	REQ_ON_GOING <= '0';
	151	done <= '1';
	152	END IF;
	153	END IF;
	154	END IF;
	155	END PROCESS;
	156
	157	-----------------------------------------------------------------------------
	158	--
	159	-----------------------------------------------------------------------------
	160	PROCESS (clk, rstn)
	161	BEGIN -- PROCESS
	162	IF rstn = '0' THEN -- asynchronous reset (active low)
	163	DATA_ON_GOING <= '0';
	164	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	165	IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	166	DATA_ON_GOING <= '1';
	167	ELSE
	168	IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
	169	DATA_ON_GOING <= '0';
	170	END IF;
	171	-- DATA_ON_GOING_s <= REQ_ON_GOING ;
	172	END IF;
	173	END IF;
	174	END PROCESS;
	175	--DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING;
	176
	177
	178	END Behavioral;

designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +3 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             --library proasic3l;
             --use proasic3l.all;
             ENTITY LFR_EQM IS
               --GENERIC (
               --  Mem_use                : INTEGER := use_RAM);
               PORT (
                 clk50MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
-                address        : OUT   STD_LOGIC_VECTOR(18 DOWNTO 0);
+                address        : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_MBE      : INOUT   STD_LOGIC;   -- new
                 nSRAM_E1       : OUT   STD_LOGIC;   -- new
                 nSRAM_E2       : OUT   STD_LOGIC;   -- new
             --    nSRAM_SCRUB    : OUT   STD_LOGIC;   -- new
                 nSRAM_W        : OUT   STD_LOGIC;   -- new
                 nSRAM_G        : OUT   STD_LOGIC;   -- new
                 nSRAM_BUSY     : IN   STD_LOGIC;   -- new
                 -- SPW --------------------------------------------------------------------
                 spw1_en        : OUT   STD_LOGIC;   -- new
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_en        : OUT   STD_LOGIC;   -- new
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- DAC --------------------------------------------------------------------
                 DAC_SDO    : OUT STD_LOGIC;
                 DAC_SCK    : OUT STD_LOGIC;
                 DAC_SYNC   : OUT STD_LOGIC;
                 DAC_CAL_EN : OUT STD_LOGIC;
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8           : OUT   STD_LOGIC
                 );
             END LFR_EQM;
             ARCHITECTURE beh OF LFR_EQM IS
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 3;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn_25 : STD_LOGIC;
               SIGNAL rstn_24 : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL clk50MHz_int : STD_LOGIC := '0';
               SIGNAL clk_25_int      : STD_LOGIC := '0';
               component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
               rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
               --clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int );
               clk50MHz_int <= clk50MHz;
               PROCESS(clk50MHz_int)
               BEGIN
                 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
                   --clk_25_int <= NOT clk_25_int;
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               --clk_pad_25 : clkint  port map (A => clk_25_int, Y => clk_25 );
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3l,
                   memtech         => apa3l,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
-                  ADDRESS_SIZE    => 19,
+                  ADDRESS_SIZE    => 20,
-                  USES_IAP_MEMCTRLR => 1,
+                  USES_IAP_MEMCTRLR => 0,
                   BYPASS_EDAC_MEMCTRLR => '0',
                   SRBANKSZ          => 8)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn_25,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   ahbtxd => TAG3,
                   urxd1  => TAG2,
                   utxd1  => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => OPEN,
                   nSRAM_BE1 => OPEN,
                   nSRAM_BE2 => OPEN,
                   nSRAM_BE3 => OPEN,
                   nSRAM_WE  => nSRAM_W,
                   nSRAM_CE  => nSRAM_CE,
                   nSRAM_OE  => nSRAM_G,
                   nSRAM_READY => nSRAM_BUSY,
                   SRAM_MBE    => nSRAM_MBE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               nSRAM_E1 <= nSRAM_CE(0);
               nSRAM_E2 <= nSRAM_CE(1);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   tech             => apa3l,
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   --FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz          => clk_25,
                   resetn_25MHz      => rstn_25,      --      TODO
                   --clk24_576MHz      => clk_24,          -- 49.152MHz/2
                   --resetn_24_576MHz  => rstn_24,      --      TODO
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_s(8),
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   DAC_SDO           => DAC_SDO,
                   DAC_SCK            => DAC_SCK,
                   DAC_SYNC          => DAC_SYNC,
                   DAC_CAL_EN        => DAC_CAL_EN,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               ------------------------------------------------------------------------------
               -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
               ------------------------------------------------------------------------------
               spw1_en   <= '1';
               spw2_en   <= '1';
               ------------------------------------------------------------------------------
               -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
               ------------------------------------------------------------------------------
               --spw_clk     <= clk50MHz;
               --spw_rxtxclk <= spw_clk;
               --spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3l,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3l,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3l,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1),
                          clk50MHz_int,
                          clk50MHz_int,
             --             spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 50 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
                   top_lfr_version        => X"020145")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                                                         --      2 => EQM (with A3PE3000)
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               lpp_lfr_2 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 14,
                   paddr                  => 14,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 3,
                   top_lfr_version        => X"020145")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                                                         --      2 => EQM (with A3PE3000)
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(14),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(3),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => OPEN,--bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 9,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25,
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_24,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn_25,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,
                   sample_val => sample_val);
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               TAG8 <= nSRAM_BUSY;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
             END beh;

lib/lpp/lpp_dma/DMA_SubSystem.vhd +26 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
+            USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             --USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             --USE lpp.lpp_top_lfr_pkg.ALL;
             --USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY DMA_SubSystem IS
               GENERIC (
-                hindex : INTEGER := 2);
+                hindex     : INTEGER := 2;
+                CUSTOM_DMA : INTEGER := 1);
               PORT (
                 clk              : IN  STD_LOGIC;
                 rstn             : IN  STD_LOGIC;
                 run              : IN  STD_LOGIC;
                 -- AHB
                 ahbi             : IN  AHB_Mst_In_Type;
                 ahbo             : OUT AHB_Mst_Out_Type;
                 ---------------------------------------------------------------------------
                 fifo_burst_valid : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 fifo_data        : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                 fifo_ren         : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 buffer_new       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 buffer_addr      : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                 buffer_length    : IN  STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
                 buffer_full      : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 buffer_full_err  : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 grant_error      : OUT STD_LOGIC    --
                 );
             END DMA_SubSystem;
             ARCHITECTURE beh OF DMA_SubSystem IS
               COMPONENT DMA_SubSystem_GestionBuffer
                 GENERIC (
                   BUFFER_ADDR_SIZE   : INTEGER;
                   BUFFER_LENGTH_SIZE : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   buffer_new      : IN  STD_LOGIC;
                   buffer_addr     : IN  STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
                   buffer_length   : IN  STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
                   buffer_full     : OUT STD_LOGIC;
                   buffer_full_err : OUT STD_LOGIC;
                   burst_send      : IN  STD_LOGIC;
                   burst_addr      : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_Arbiter
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   data_burst_valid       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_MUX
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   fifo_grant      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data       : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_address    : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren        : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   dma_send        : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_address     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_ren         : IN  STD_LOGIC;
                   dma_done        : IN  STD_LOGIC;
                   grant_error     : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               SIGNAL dma_send        : STD_LOGIC;
               SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_done        : STD_LOGIC;
               SIGNAL dma_ren         : STD_LOGIC;
               SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL burst_send      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_grant      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_address    : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);  --
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
+              GR_DMA : IF CUSTOM_DMA = 0 GENERATE
                 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
                   GENERIC MAP (
                     tech   => inferred,
                     hindex => hindex)
                   PORT MAP (
                     HCLK           => clk,
                     HRESETn        => rstn,
                     run            => run,
                     AHB_Master_In  => ahbi,
                     AHB_Master_Out => ahbo,
                     send        => dma_send,
                     valid_burst => dma_valid_burst,
                     done        => dma_done,
                     ren         => dma_ren,
                     address     => dma_address,
                     data        => dma_data);
+              END GENERATE GR_DMA;
+              LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
+                lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
+                  GENERIC MAP (
+                    hindex   => hindex,
+                    vendorid => VENDOR_LPP,
+                    deviceid => 10,
+                    version  => 0)
+                  PORT MAP (
+                    clk            => clk,
+                    rstn           => rstn,
+                    AHB_Master_In  => ahbi,
+                    AHB_Master_Out => ahbo,
+                    ren         => dma_ren,
+                    data        => dma_data,
+                    send        => dma_send,
+                    valid_burst => dma_valid_burst,
+                    done        => dma_done,
+                    address     => dma_address);
+              END GENERATE LPP_DMA_IP;
               -----------------------------------------------------------------------------
               -- RoundRobin Selection Channel For DMA
               -----------------------------------------------------------------------------
               DMA_SubSystem_Arbiter_1 : DMA_SubSystem_Arbiter
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   data_burst_valid       => fifo_burst_valid,
                   data_burst_valid_grant => fifo_grant);
               -----------------------------------------------------------------------------
               -- Mux between the channel from Waveform Picker and Spectral Matrix
               -----------------------------------------------------------------------------
               DMA_SubSystem_MUX_1 : DMA_SubSystem_MUX
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => run,
                   fifo_grant      => fifo_grant,
                   fifo_data       => fifo_data,
                   fifo_address    => fifo_address,
                   fifo_ren        => fifo_ren,
                   fifo_burst_done => burst_send,
                   dma_send        => dma_send,
                   dma_valid_burst => dma_valid_burst,
                   dma_address     => dma_address,
                   dma_data        => dma_data,
                   dma_ren         => dma_ren,
                   dma_done        => dma_done,
                   grant_error => grant_error);
               -----------------------------------------------------------------------------
               -- GEN ADDR
               -----------------------------------------------------------------------------
               all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
                 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
                   GENERIC MAP (
                     BUFFER_ADDR_SIZE   => 32,
                     BUFFER_LENGTH_SIZE => 26)
                   PORT MAP (
                     clk  => clk,
                     rstn => rstn,
                     run  => run,
                     buffer_new      => buffer_new(I),
                     buffer_addr     => buffer_addr(32*(I+1)-1 DOWNTO I*32),
                     buffer_length   => buffer_length(26*(I+1)-1 DOWNTO I*26),
                     buffer_full     => buffer_full(I),
                     buffer_full_err => buffer_full_err(I),
                     burst_send => burst_send(I),
                     burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
                     );
               END GENERATE all_buffer;
             END beh;

lib/lpp/lpp_dma/lpp_dma_pkg.vhd +21 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE std.textio.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             --LIBRARY lpp;
             --USE lpp.lpp_amba.ALL;
             --USE lpp.apb_devices_list.ALL;
             --USE lpp.lpp_memory.ALL;
             PACKAGE lpp_dma_pkg IS
               COMPONENT lpp_dma
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER;
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER;
                   pirq   : INTEGER);
                 PORT (
                   HCLK           : IN  STD_ULOGIC;
                   HRESETn        : IN  STD_ULOGIC;
                   apbi           : IN  apb_slv_in_type;
                   apbo           : OUT apb_slv_out_type;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   -- fifo interface
                   fifo_data      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty     : IN  STD_LOGIC;
                   fifo_ren       : OUT STD_LOGIC;
                   -- header
                   header         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val     : IN  STD_LOGIC;
                   header_ack     : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fifo_test_dma
                 GENERIC (
                   tech   : INTEGER;
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER);
                 PORT (
                   HCLK       : IN  STD_ULOGIC;
                   HRESETn    : IN  STD_ULOGIC;
                   apbi       : IN  apb_slv_in_type;
                   apbo       : OUT apb_slv_out_type;
                   -- fifo interface
                   fifo_data  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : OUT STD_LOGIC;
                   fifo_ren   : IN  STD_LOGIC;
                   -- header
                   header     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val : OUT STD_LOGIC;
                   header_ack : IN  STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT lpp_dma_apbreg
                 GENERIC (
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER;
                   pirq   : INTEGER);
                 PORT (
                   HCLK                          : IN  STD_ULOGIC;
                   HRESETn                       : IN  STD_ULOGIC;
                   apbi                          : IN  apb_slv_in_type;
                   apbo                          : OUT apb_slv_out_type;
                   -- IN
                   ready_matrix_f0_0             : IN  STD_LOGIC;
                   ready_matrix_f0_1             : IN  STD_LOGIC;
                   ready_matrix_f1               : IN  STD_LOGIC;
                   ready_matrix_f2               : IN  STD_LOGIC;
                   error_anticipating_empty_fifo : IN  STD_LOGIC;
                   error_bad_component_error     : IN  STD_LOGIC;
                   debug_reg                     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                   -- OUT
                   status_ready_matrix_f0_0             : OUT STD_LOGIC;
                   status_ready_matrix_f0_1             : OUT STD_LOGIC;
                   status_ready_matrix_f1               : OUT STD_LOGIC;
                   status_ready_matrix_f2               : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo : OUT STD_LOGIC;
                   status_error_bad_component_error     : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_dma_send_1word
                 PORT (
                   HCLK    : IN  STD_ULOGIC;
                   HRESETn : IN  STD_ULOGIC;
                   DMAIn   : OUT DMA_In_Type;
                   DMAOut  : IN  DMA_OUt_Type;
                   send    : IN  STD_LOGIC;
                   address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data    : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   ren     : OUT STD_LOGIC;
                   send_ok : OUT STD_LOGIC;
                   send_ko : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_send_16word
                 PORT (
                   HCLK    : IN  STD_ULOGIC;
                   HRESETn : IN  STD_ULOGIC;
                   DMAIn   : OUT DMA_In_Type;
                   DMAOut  : IN  DMA_OUt_Type;
                   send    : IN  STD_LOGIC;
                   address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data    : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   ren     : OUT STD_LOGIC;
                   send_ok : OUT STD_LOGIC;
                   send_ko : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fifo_latency_correction
                 PORT (
                   HCLK       : IN  STD_ULOGIC;
                   HRESETn    : IN  STD_ULOGIC;
                   fifo_data  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : IN  STD_LOGIC;
                   fifo_ren   : OUT STD_LOGIC;
                   dma_data   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_empty  : OUT STD_LOGIC;
                   dma_ren    : IN  STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_ip
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER);
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   AHB_Master_In                          : IN  AHB_Mst_In_Type;
                   AHB_Master_Out                         : OUT AHB_Mst_Out_Type;
                   fifo_data                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty                             : IN  STD_LOGIC;
                   fifo_ren                               : OUT STD_LOGIC;
                   header                                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val                             : IN  STD_LOGIC;
                   header_ack                             : OUT STD_LOGIC;
                   ready_matrix_f0_0                      : OUT STD_LOGIC;
                   ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
                   error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : IN  STD_LOGIC;
                   status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
                   status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
                   status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0_0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_dma_singleOrBurst
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER);
                 PORT (
                   HCLK           : IN  STD_ULOGIC;
                   HRESETn        : IN  STD_ULOGIC;
                   run            : IN  STD_LOGIC;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   send           : IN  STD_LOGIC;
                   valid_burst    : IN  STD_LOGIC;
                   done           : OUT STD_LOGIC;
                   ren            : OUT STD_LOGIC;
                   address        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data           : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_dmaout_okay : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- DMA_SubSystem
               -----------------------------------------------------------------------------
               COMPONENT DMA_SubSystem
                 GENERIC (
-                  hindex : INTEGER);
+                  hindex : INTEGER;
+                  CUSTOM_DMA : INTEGER := 1);
                 PORT (
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   run              : IN  STD_LOGIC;
                   ahbi             : IN  AHB_Mst_In_Type;
                   ahbo             : OUT AHB_Mst_Out_Type;
                   fifo_burst_valid : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data        : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren         : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   buffer_new       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   buffer_addr      : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   buffer_length    : IN  STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
                   buffer_full      : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   buffer_full_err  : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   grant_error      : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT DMA_SubSystem_GestionBuffer
                 GENERIC (
                   BUFFER_ADDR_SIZE   : INTEGER;
                   BUFFER_LENGTH_SIZE : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   buffer_new      : IN  STD_LOGIC;
                   buffer_addr     : IN  STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
                   buffer_length   : IN  STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
                   buffer_full     : OUT STD_LOGIC;
                   buffer_full_err : OUT STD_LOGIC;
                   burst_send      : IN  STD_LOGIC;
                   burst_addr      : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_Arbiter
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   data_burst_valid       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_MUX
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   fifo_grant      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data       : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_address    : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren        : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   dma_send        : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_address     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_ren         : IN  STD_LOGIC;
                   dma_done        : IN  STD_LOGIC;
                   grant_error     : OUT STD_LOGIC);
               END COMPONENT;
+              COMPONENT lpp_dma_SEND16B_FIFO2DMA
+                GENERIC (
+                  hindex   :    INTEGER;
+                  vendorid : in Integer;
+                  deviceid : in Integer;
+                  version  : in Integer);
+                PORT (
+                  clk            : IN  STD_LOGIC;
+                  rstn           : IN  STD_LOGIC;
+                  AHB_Master_In  : IN  AHB_Mst_In_Type;
+                  AHB_Master_Out : OUT AHB_Mst_Out_Type;
+                  ren            : OUT STD_LOGIC;
+                  data           : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  send           : IN  STD_LOGIC;
+                  valid_burst    : IN  STD_LOGIC;
+                  done           : OUT STD_LOGIC;
+                  address        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
+              END COMPONENT;
             END;

lib/lpp/lpp_dma/vhdlsyn.txt +1 0

             lpp_dma_pkg.vhd
             fifo_latency_correction.vhd
             lpp_dma.vhd
             lpp_dma_ip.vhd
             lpp_dma_send_16word.vhd
             lpp_dma_send_1word.vhd
             lpp_dma_singleOrBurst.vhd
             DMA_SubSystem.vhd
             DMA_SubSystem_GestionBuffer.vhd
             DMA_SubSystem_Arbiter.vhd
             DMA_SubSystem_MUX.vhd
+            lpp_dma_SEND16B_FIFO2DMA.vhd

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +5 -3

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             LIBRARY iap;
             USE iap.memctrl.ALL;
             ENTITY leon3_soc IS
               GENERIC (
                 fabtech           : INTEGER := apa3e;
                 memtech           : INTEGER := apa3e;
                 padtech           : INTEGER := inferred;
                 clktech           : INTEGER := inferred;
                 disas             : INTEGER := 0;      -- Enable disassembly to console
                 dbguart           : INTEGER := 0;      -- Print UART on console
                 pclow             : INTEGER := 2;
                 --
                 clk_freq          : INTEGER := 25000;  --kHz
                 --
                 IS_RADHARD        : INTEGER := 0;
                 --
                 NB_CPU            : INTEGER := 1;
                 ENABLE_FPU        : INTEGER := 1;
                 FPU_NETLIST       : INTEGER := 1;
                 ENABLE_DSU        : INTEGER := 1;
                 ENABLE_AHB_UART   : INTEGER := 1;
                 ENABLE_APB_UART   : INTEGER := 1;
                 ENABLE_IRQMP      : INTEGER := 1;
                 ENABLE_GPT        : INTEGER := 1;
                 --
                 NB_AHB_MASTER     : INTEGER := 1;
                 NB_AHB_SLAVE      : INTEGER := 1;
                 NB_APB_SLAVE      : INTEGER := 1;
                 --
                 ADDRESS_SIZE      : INTEGER := 20;
                 USES_IAP_MEMCTRLR : INTEGER := 0;
                 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
                 SRBANKSZ          : INTEGER := 8
                 );
               PORT (
                 clk   : IN STD_ULOGIC;
                 reset : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
                 nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext    : OUT   apb_slv_in_type;
                 apbo_ext    : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext  : OUT   ahb_slv_in_type;
                 ahbo_s_ext  : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext  : OUT   AHB_Mst_In_Type;
                 ahbo_m_ext  : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
                 );
             END;
             ARCHITECTURE Behavioral OF leon3_soc IS
               -----------------------------------------------------------------------------
               -- CONFIG -------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- Clock generator
               CONSTANT CFG_CLKMUL    : INTEGER := (1);
               CONSTANT CFG_CLKDIV    : INTEGER := (1);  -- divide 50MHz by 2 to get 25MHz
               CONSTANT CFG_OCLKDIV   : INTEGER := (1);
               CONSTANT CFG_CLK_NOFB  : INTEGER := 0;
               -- LEON3 processor core
               CONSTANT CFG_LEON3     : INTEGER := 1;
               CONSTANT CFG_NCPU      : INTEGER := NB_CPU;
               CONSTANT CFG_NWIN      : INTEGER := (8);  -- to be compatible with BCC and RCC
               CONSTANT CFG_V8        : INTEGER := 0;
               CONSTANT CFG_MAC       : INTEGER := 0;
               CONSTANT CFG_SVT       : INTEGER := 0;
               CONSTANT CFG_RSTADDR   : INTEGER := 16#00000#;
               CONSTANT CFG_LDDEL     : INTEGER := (1);
               CONSTANT CFG_NWP       : INTEGER := (0);
               CONSTANT CFG_PWD       : INTEGER := 1*2;
               CONSTANT CFG_FPU       : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
               -- 1*(8 + 16 * 0) => grfpu-light
               -- 1*(8 + 16 * 1) => netlist
               -- 0*(8 + 16 * 0) => No FPU
               -- 0*(8 + 16 * 1) => No FPU;
               CONSTANT CFG_ICEN      : INTEGER := 1;
               CONSTANT CFG_ISETS     : INTEGER := 1;
               CONSTANT CFG_ISETSZ    : INTEGER := 4;
               CONSTANT CFG_ILINE     : INTEGER := 4;
               CONSTANT CFG_IREPL     : INTEGER := 0;
               CONSTANT CFG_ILOCK     : INTEGER := 0;
               CONSTANT CFG_ILRAMEN   : INTEGER := 0;
               CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
               CONSTANT CFG_ILRAMSZ   : INTEGER := 1;
               CONSTANT CFG_DCEN      : INTEGER := 1;
               CONSTANT CFG_DSETS     : INTEGER := 1;
               CONSTANT CFG_DSETSZ    : INTEGER := 4;
               CONSTANT CFG_DLINE     : INTEGER := 4;
               CONSTANT CFG_DREPL     : INTEGER := 0;
               CONSTANT CFG_DLOCK     : INTEGER := 0;
               CONSTANT CFG_DSNOOP    : INTEGER := 0 + 0 + 4*0;
               CONSTANT CFG_DLRAMEN   : INTEGER := 0;
               CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
               CONSTANT CFG_DLRAMSZ   : INTEGER := 1;
               CONSTANT CFG_MMUEN     : INTEGER := 0;
               CONSTANT CFG_ITLBNUM   : INTEGER := 2;
               CONSTANT CFG_DTLBNUM   : INTEGER := 2;
               CONSTANT CFG_TLB_TYPE  : INTEGER := 1 + 0*2;
               CONSTANT CFG_TLB_REP   : INTEGER := 1;
               CONSTANT CFG_DSU   : INTEGER := ENABLE_DSU;
               CONSTANT CFG_ITBSZ : INTEGER := 0;
               CONSTANT CFG_ATBSZ : INTEGER := 0;
               -- AMBA settings
               CONSTANT CFG_DEFMST  : INTEGER := (0);
               CONSTANT CFG_RROBIN  : INTEGER := 1;
               CONSTANT CFG_SPLIT   : INTEGER := 0;
               CONSTANT CFG_AHBIO   : INTEGER := 16#FFF#;
               CONSTANT CFG_APBADDR : INTEGER := 16#800#;
               -- DSU UART
               CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
               -- LEON2 memory controller
               CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
               -- UART 1
               CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
               CONSTANT CFG_UART1_FIFO   : INTEGER := 1;
               -- LEON3 interrupt controller
               CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
               -- Modular timer
               CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
               CONSTANT CFG_GPT_NTIM   : INTEGER := (2);
               CONSTANT CFG_GPT_SW     : INTEGER := (8);
               CONSTANT CFG_GPT_TW     : INTEGER := (32);
               CONSTANT CFG_GPT_IRQ    : INTEGER := (8);
               CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
               CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
               CONSTANT CFG_GPT_WDOG   : INTEGER := 16#0#;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SIGNALs
               -----------------------------------------------------------------------------
               CONSTANT maxahbmsp  : INTEGER            := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
               -- CLK & RST --
               SIGNAL   clk2x      : STD_ULOGIC;
               SIGNAL   clkmn      : STD_ULOGIC;
               SIGNAL   clkm       : STD_ULOGIC;
               SIGNAL   rstn       : STD_ULOGIC;
               SIGNAL   rstraw     : STD_ULOGIC;
               SIGNAL   pciclk     : STD_ULOGIC;
               SIGNAL   sdclkl     : STD_ULOGIC;
               SIGNAL   cgi        : clkgen_in_type;
               SIGNAL   cgo        : clkgen_out_type;
               --- AHB / APB
               SIGNAL   apbi       : apb_slv_in_type;
               SIGNAL   apbo       : apb_slv_out_vector := (OTHERS => apb_none);
               SIGNAL   ahbsi      : ahb_slv_in_type;
               SIGNAL   ahbso      : ahb_slv_out_vector := (OTHERS => ahbs_none);
               SIGNAL   ahbmi      : ahb_mst_in_type;
               SIGNAL   ahbmo      : ahb_mst_out_vector := (OTHERS => ahbm_none);
               --UART
               SIGNAL   ahbuarti   : uart_in_type;
               SIGNAL   ahbuarto   : uart_out_type;
               SIGNAL   apbuarti   : uart_in_type;
               SIGNAL   apbuarto   : uart_out_type;
               --MEM CTRLR
               SIGNAL   memi       : memory_in_type;
               SIGNAL   memo       : memory_out_type;
               SIGNAL   wpo        : wprot_out_type;
               SIGNAL   sdo        : sdram_out_type;
               SIGNAL   mbe        : STD_LOGIC;      -- enable memory programming
               SIGNAL   mbe_drive  : STD_LOGIC;      -- drive the MBE memory signal
               SIGNAL   nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL   nSRAM_OE_s : STD_LOGIC;
               --IRQ
               SIGNAL   irqi       : irq_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   irqo       : irq_out_vector(0 TO CFG_NCPU-1);
               --Timer
               SIGNAL   gpti       : gptimer_in_type;
               SIGNAL   gpto       : gptimer_out_type;
               --DSU
               SIGNAL   dbgi       : l3_debug_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   dbgo       : l3_debug_out_vector(0 TO CFG_NCPU-1);
               SIGNAL   dsui       : dsu_in_type;
               SIGNAL   dsuo       : dsu_out_type;
               -----------------------------------------------------------------------------
             BEGIN
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               cgi.pllctrl <= "00";
               cgi.pllrst  <= rstraw;
               rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
               clkgen0 : clkgen                      -- clock generator
                 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
                              CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
                 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : IF CFG_LEON3 = 1 GENERATE
                 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
                     u0 : ENTITY gaisler.leon3s                       -- LEON3 processor
                       GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
 , CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
                                    CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
                                    CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
                                    CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
                                    CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
                       PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                                 irqi(i), irqo(i), dbgi(i), dbgo(i));
                   END GENERATE leon3_non_radhard;
                   leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
                     cpu : ENTITY gaisler.leon3ft
                       GENERIC MAP (
                         HINDEX     => i,  --: integer;             --CPU_HINDEX,
                         FABTECH    => fabtech,        --CFG_TECH,
                         MEMTECH    => memtech,        --CFG_TECH,
                         NWINDOWS   => CFG_NWIN,       --CFG_NWIN,
                         DSU        => CFG_DSU,        --condSel (HAS_DEBUG, 1, 0),
                         FPU        => CFG_FPU,        --CFG_FPU,
                         V8         => CFG_V8,         --CFG_V8,
                         CP         => 0,              --CFG_CP,
                         MAC        => CFG_MAC,        --CFG_MAC,
                         PCLOW      => pclow,          --CFG_PCLOW,
                         NOTAG      => 0,              --CFG_NOTAG,
                         NWP        => CFG_NWP,        --CFG_NWP,
                         ICEN       => CFG_ICEN,       --CFG_ICEN,
                         IREPL      => CFG_IREPL,      --CFG_IREPL,
                         ISETS      => CFG_ISETS,      --CFG_ISETS,
                         ILINESIZE  => CFG_ILINE,      --CFG_ILINE,
                         ISETSIZE   => CFG_ISETSZ,     --CFG_ISETSZ,
                         ISETLOCK   => CFG_ILOCK,      --CFG_ILOCK,
                         DCEN       => CFG_DCEN,       --CFG_DCEN,
                         DREPL      => CFG_DREPL,      --CFG_DREPL,
                         DSETS      => CFG_DSETS,      --CFG_DSETS,
                         DLINESIZE  => CFG_DLINE,      --CFG_DLINE,
                         DSETSIZE   => CFG_DSETSZ,     --CFG_DSETSZ,
                         DSETLOCK   => CFG_DLOCK,      --CFG_DLOCK,
                         DSNOOP     => CFG_DSNOOP,     --CFG_DSNOOP,
                         ILRAM      => CFG_ILRAMEN,    --CFG_ILRAMEN,
                         ILRAMSIZE  => CFG_ILRAMSZ,    --CFG_ILRAMSZ,
                         ILRAMSTART => CFG_ILRAMADDR,  --CFG_ILRAMADDR,
                         DLRAM      => CFG_DLRAMEN,    --CFG_DLRAMEN,
                         DLRAMSIZE  => CFG_DLRAMSZ,    --CFG_DLRAMSZ,
                         DLRAMSTART => CFG_DLRAMADDR,  --CFG_DLRAMADDR,
                         MMUEN      => CFG_MMUEN,      --CFG_MMUEN,
                         ITLBNUM    => CFG_ITLBNUM,    --CFG_ITLBNUM,
                         DTLBNUM    => CFG_DTLBNUM,    --CFG_DTLBNUM,
                         TLB_TYPE   => CFG_TLB_TYPE,   --CFG_TLB_TYPE,
                         TLB_REP    => CFG_TLB_REP,    --CFG_TLB_REP,
                         LDDEL      => CFG_LDDEL,      --CFG_LDDEL,
                         DISAS      => disas,          --condSel (SIM_ENABLED, 1, 0),
                         TBUF       => CFG_ITBSZ,      --CFG_ITBSZ,
                         PWD        => CFG_PWD,        --CFG_PWD,
                         SVT        => CFG_SVT,        --CFG_SVT,
                         RSTADDR    => CFG_RSTADDR,    --CFG_RSTADDR,
                         SMP        => CFG_NCPU-1,     --CFG_NCPU-1,
                         IUFT       => 2,  --: integer range 0 to 4;--CFG_IUFT_EN,
                         FPFT       => 1,  --: integer range 0 to 4;--CFG_FPUFT_EN,
                         CMFT       => 1,  --: integer range 0 to 1;--CFG_CACHE_FT_EN,
                         IUINJ      => 0,  --: integer;             --CFG_RF_ERRINJ,
                         CEINJ      => 0,  --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
                         CACHED     => 0,  --: integer;             --CFG_DFIXED,
                         NETLIST    => 0,  --: integer;             --CFG_LEON3_NETLIST,
                         SCANTEST   => 0,  --: integer;             --CFG_SCANTEST,
                         MMUPGSZ    => 0,  --: integer range 0 to 5;--CFG_MMU_PAGE,
                         BP         => 1)              --CFG_BP
                       PORT MAP (                      --
                         rstn  => rstn,                --rst_n,
                         clk   => clkm,                --clk,
                         ahbi  => ahbmi,               --ahbmi,
                         ahbo  => ahbmo(i),             --ahbmo(CPU_HINDEX),
                         ahbsi => ahbsi,               --ahbsi,
                         ahbso => ahbso,               --ahbso,
                         irqi  => irqi(i),             --irqi(CPU_HINDEX),
                         irqo  => irqo(i),             --irqo(CPU_HINDEX),
                         dbgi  => dbgi(i),             --dbgi(CPU_HINDEX),
                         dbgo  => dbgo(i),             --dbgo(CPU_HINDEX),
                         gclk  => clkm                 --clk
                         );
                   END GENERATE leon3_radhard_i;
                 END GENERATE;
                 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
                 dsugen : IF CFG_DSU = 1 GENERATE
                   dsu0 : dsu3                       -- LEON3 Debug Support Unit
-                    GENERIC MAP (hindex => 0,       --      TODO : hindex => 2
+                    GENERIC MAP (hindex => 2,       --      TODO : hindex => 2
                                  haddr => 16#900#, hmask => 16#F00#,
                                  ncpu   => CFG_NCPU, tbits => 30, tech => memtech,
                                  irq => 0, kbytes => CFG_ATBSZ)
-                    PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),--      TODO :ahbso(2)
+                    PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),--      TODO :ahbso(2)
                               dbgo, dbgi, dsui, dsuo);
                   dsui.enable <= '1';
                   dsui.break  <= '0';
                 END GENERATE;
               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
                 ahbso(2)    <= ahbs_none;
                 dsuo.tstop  <= '0';
                 dsuo.active <= '0';
               END GENERATE;
               irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
                 irqctrl0 : irqmp                    -- interrupt controller
                   GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                   PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
               END GENERATE;
               irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
                 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   irqi(i).irl <= "0000";
                 END GENERATE;
                 apbo(2) <= apb_none;
               END GENERATE;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
               ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
                 memctrlr : mctrl GENERIC MAP (
                   hindex  => 0,
                   pindex  => 0,
                   paddr   => 0,
                   srbanks => 1
                   )
                   PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
                 memi.bexcn <= '1';
                 memi.brdyn <= '1';
                 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
                 nSRAM_OE_s <= memo.ramoen(0);
               END GENERATE;
               IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
                 memctrlr : srctrle_0ws
                   GENERIC MAP(
                     hindex   => 2,                  -- TODO : hindex   => 0
                     pindex   => 0,
                     paddr    => 0,
                     srbanks  => 2,
                     banksz   => SRBANKSZ,                  --512k * 32
                     rmw      => 1,
                     --Aeroflex memory generics:
-                    mbpbusy  => BYPASS_EDAC_MEMCTRLR,
+                    mbpedac  => BYPASS_EDAC_MEMCTRLR,
                     mprog    => 1,          -- program memory by default values after reset
                     mpsrate  => 15,                 -- default scrub rate period
                     mpb2s    => 14,                  -- default busy to scrub delay
                     mpapb    => 1,                  -- instantiate apb register
                     mchipcnt => 2,
                     mpenall  => 1  -- when 0 program only E1 chip, else program all dies
                     )
                   PORT MAP (
                     rst       => rstn,
                     clk       => clkm,
                     ahbsi     => ahbsi,
                     ahbso     => ahbso(2),          -- TODO :ahbso(0),
                     apbi      => apbi,
                     apbo      => apbo(0),
                     sri       => memi,
                     sro       => memo,
                     --Aeroflex memory signals:
                     ucerr     => OPEN,              -- uncorrectable error signal
                     mbe       => mbe,               -- enable memory programming
                     mbe_drive => mbe_drive          -- drive the MBE memory signal
                     );
                 memi.brdyn <= nSRAM_READY;
                 mbe_pad : iopad
                   GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP(pad => SRAM_MBE,
                            i   => mbe,
                            en  => mbe_drive,
                            o   => memi.bexcn);
                 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
                 nSRAM_OE_s <= memo.oen;
               END GENERATE;
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
                     memo.data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
                     memi.data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
               rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
               oen_pad  : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
               nBWE_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
               nBWc_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                              ioen    => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : IF CFG_AHB_UART = 1 GENERATE
                 dcom0 : ahbuart
                   GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
                   PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
                 dsurx_pad : inpad GENERIC MAP (tech  => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
               END GENERATE;
               nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl                        -- AHB/APB bridge
                 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
                 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
                 timer0 : gptimer                    -- timer unit
                   GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                                sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                                nbits  => CFG_GPT_TW)
                   PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt  <= dsuo.tstop;
                 gpti.extclk <= '0';
               END GENERATE;
               notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
                 uart1 : apbuart                     -- UART 1
                   GENERIC MAP (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                                fifosize => CFG_UART1_FIFO)
                   PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd    <= urxd1;
                 apbuarti.extclk <= '0';
                 utxd1           <= apbuarto.txd;
                 apbuarti.ctsn   <= '0';
               END GENERATE;
               noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
             -------------------------------------------------------------------------------
             -- AMBA BUS -------------------------------------------------------------------
             -------------------------------------------------------------------------------
               -- APB --------------------------------------------------------------------
               apbi_ext <= apbi;
               all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
                 max_16_apb : IF I + 5 < 16 GENERATE
                   apbo(I+5) <= apbo_ext(I+5);
                 END GENERATE max_16_apb;
               END GENERATE all_apb;
               -- AHB_Slave --------------------------------------------------------------
               ahbi_s_ext <= ahbsi;
               all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
                 max_16_ahbs : IF I + 3 < 16 GENERATE
                   ahbso(I+3) <= ahbo_s_ext(I+3);
                 END GENERATE max_16_ahbs;
               END GENERATE all_ahbs;
               -- AHB_Master -------------------------------------------------------------
               ahbi_m_ext <= ahbmi;
               all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
                 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
                   ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
                 END GENERATE max_16_ahbm;
               END GENERATE all_ahbm;
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +1 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
                 sample_B        : IN  Samples(2 DOWNTO 0);
                 sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 debug_vector    : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               SIGNAL data_shaping_R2  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0          : STD_LOGIC;
             --  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
               SIGNAL ready_matrix_f1          : STD_LOGIC;
               SIGNAL ready_matrix_f2          : STD_LOGIC;
               SIGNAL status_ready_matrix_f0   : STD_LOGIC;
             --  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
               SIGNAL status_ready_matrix_f1   : STD_LOGIC;
               SIGNAL status_ready_matrix_f2   : STD_LOGIC;
               SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL length_matrix_f0         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f1         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f2         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               -- WFP
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               --SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
             --  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
             --  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
             --  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
             --  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
             --  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL wfp_error_buffer_full   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
             --  SIGNAL dma_sel_valid   : STD_LOGIC;
             --  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
             --  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
             --  SIGNAL ongoing_reg         : STD_LOGIC;
             --  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL dma_send_reg        : STD_LOGIC;
             --  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
             --  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
             --  SIGNAL dma_send        : STD_LOGIC;
             --  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
             --  SIGNAL dma_done        : STD_LOGIC;
             --  SIGNAL dma_ren         : STD_LOGIC;
             --  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
             --  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL data_ms_valid       : STD_LOGIC;
             --  SIGNAL data_ms_valid_burst : STD_LOGIC;
             --  SIGNAL data_ms_ren         : STD_LOGIC;
             --  SIGNAL data_ms_done        : STD_LOGIC;
             --  SIGNAL dma_ms_ongoing      : STD_LOGIC;
             --  SIGNAL run_ms              : STD_LOGIC;
             --  SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_buffer_full      : STD_LOGIC;
               SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
             --  SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_fifo_data        : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_fifo_ren         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_new       : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_addr      : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_buffer_length    : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
               SIGNAL dma_buffer_full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_full_err  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_grant_error      : STD_LOGIC;
               SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_time        :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f0_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f1_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f2_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f3_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               debug_vector <= apb_reg_debug_vector;
               -----------------------------------------------------------------------------
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
               sample_time <= coarse_time & fine_time;
               --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
               --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
               --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   sample_time      => sample_time,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   data_shaping_R2  => data_shaping_R2,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data,
                   sample_f0_time   => sample_f0_time,
                   sample_f1_time   => sample_f1_time,
                   sample_f2_time   => sample_f2_time,
                   sample_f3_time   => sample_f3_time
                   );
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
             --      nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => OPEN,--run_ms,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,       -- TODO
                   error_input_fifo_write => error_input_fifo_write,  -- TODO
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   addr_matrix_f0 => addr_matrix_f0,
                   addr_matrix_f1 => addr_matrix_f1,
                   addr_matrix_f2 => addr_matrix_f2,
                   length_matrix_f0  => length_matrix_f0,
                   length_matrix_f1  => length_matrix_f1,
                   length_matrix_f2  => length_matrix_f2,
                   -------------------------------------------------------------------------
                   --status_full       => status_full,       --      TODo
                   --status_full_ack   => status_full_ack,   --      TODo
                   --status_full_err   => status_full_err,   --      TODo
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   data_shaping_R2   => data_shaping_R2,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
             --      nb_word_by_buffer => nb_word_by_buffer, -- TODO
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => OPEN, --run,
                   start_date        => start_date,
             --      debug_signal      => debug_signal,
                   wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
                   wfp_addr_buffer         => wfp_addr_buffer,-- TODO
                   wfp_length_buffer       => wfp_length_buffer,-- TODO
                   wfp_ready_buffer        => wfp_ready_buffer,-- TODO
                   wfp_buffer_time         => wfp_buffer_time,-- TODO
                   wfp_error_buffer_full   => wfp_error_buffer_full, -- TODO
                   -------------------------------------------------------------------------
                   sample_f3_v     => sample_f3_data(1*16-1 DOWNTO 0*16),
                   sample_f3_e1    => sample_f3_data(2*16-1 DOWNTO 1*16),
                   sample_f3_e2    => sample_f3_data(3*16-1 DOWNTO 2*16),
                   sample_f3_valid => sample_f3_val,
                   debug_vector => apb_reg_debug_vector
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => inferred,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => '1',--run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_new_err    => status_new_err,
                   status_buffer_ready => wfp_status_buffer_ready,
                   addr_buffer         => wfp_addr_buffer,
                   length_buffer       => wfp_length_buffer,
                   ready_buffer        => wfp_ready_buffer,
                   buffer_time         => wfp_buffer_time,
                   error_buffer_full   => wfp_error_buffer_full,
                   coarse_time => coarse_time,
             --      fine_time   => fine_time,
                   --f0
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
                   data_f0_time                 => sample_f0_time,
                   --f1
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
                   data_f1_time                 => sample_f1_time,
                   --f2
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
                   data_f2_time                 => sample_f2_time,
                   --f3
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
                   data_f3_time                 => sample_f3_time,
                   -- OUTPUT -- DMA interface
                   dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
                   dma_fifo_data        => dma_fifo_data(32*4-1 DOWNTO 0),
                   dma_fifo_ren         => dma_fifo_ren(3 DOWNTO 0),
                   dma_buffer_new       => dma_buffer_new(3 DOWNTO 0),
                   dma_buffer_addr      => dma_buffer_addr(32*4-1 DOWNTO 0),
                   dma_buffer_length    => dma_buffer_length(26*4-1 DOWNTO 0),
                   dma_buffer_full      => dma_buffer_full(3 DOWNTO 0),
                   dma_buffer_full_err  => dma_buffer_full_err(3 DOWNTO 0)
                   );
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
                                NOT(sample_f2_val) & NOT(sample_f2_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
               -------------------------------------------------------------------------------
               --ms_softandhard_rstn <= rstn AND run_ms AND run;
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   clk  => clk,
                   --rstn => ms_softandhard_rstn,      --rstn,
                   rstn => rstn,
                   run  => '1',--run_ms,
                   start_date => start_date,
                   coarse_time => coarse_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f0_time  => sample_f0_time,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f1_time  => sample_f1_time,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
                   sample_f2_time  => sample_f2_time,
                   --DMA
                   dma_fifo_burst_valid => dma_fifo_burst_valid(4),                  -- OUT
                   dma_fifo_data        => dma_fifo_data((4+1)*32-1 DOWNTO 4*32),    -- OUT
                   dma_fifo_ren         => dma_fifo_ren(4),                          -- IN
                   dma_buffer_new       => dma_buffer_new(4),                        -- OUT
                   dma_buffer_addr      => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32),  -- OUT
                   dma_buffer_length    => dma_buffer_length((4+1)*26-1 DOWNTO 4*26),  -- OUT
                   dma_buffer_full      => dma_buffer_full(4),                       -- IN
                   dma_buffer_full_err  => dma_buffer_full_err(4),                   -- IN
                   --REG
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,
                   error_input_fifo_write => error_input_fifo_write,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0 => length_matrix_f0,
                   length_matrix_f1 => length_matrix_f1,
                   length_matrix_f2 => length_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   debug_vector   => debug_vector_ms);
               -----------------------------------------------------------------------------
               --run_dma <= run_ms OR run;
               DMA_SubSystem_1 : DMA_SubSystem
                 GENERIC MAP (
                   hindex => hindex)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => '1',--run_dma,
                   ahbi => ahbi,
                   ahbo => ahbo,
                   fifo_burst_valid => dma_fifo_burst_valid,  --fifo_burst_valid,
                   fifo_data        => dma_fifo_data,         --fifo_data,
                   fifo_ren         => dma_fifo_ren,          --fifo_ren,
                   buffer_new      => dma_buffer_new,       --buffer_new,
                   buffer_addr     => dma_buffer_addr,      --buffer_addr,
                   buffer_length   => dma_buffer_length,    --buffer_length,
                   buffer_full     => dma_buffer_full,      --buffer_full,
                   buffer_full_err => dma_buffer_full_err,  --buffer_full_err,
                   grant_error     => dma_grant_error);     --grant_error);
-            END beh;
  No newline at end of file
+            END beh;

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