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Added file init for RAM_CEL IP.[Need tests]...
Jeandet Alexis -
r641:0dc1942211a7 default draft
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1 1 #GRLIB=../..
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=testbench
6 6 BOARD=LFR-EQM
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 16 VHDLSIMFILES= tb.vhd
17 17 SIMTOP=testbench
18 18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 22 CLEAN=soft-clean
23 23
24 24 TECHLIBS = axcelerator
25 25
26 26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28 28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
30 30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./dsp/lpp_fft_rtax \
31 32 ./amba_lcd_16x2_ctrlr \
32 33 ./general_purpose/lpp_AMR \
33 34 ./general_purpose/lpp_balise \
34 35 ./general_purpose/lpp_delay \
35 36 ./lpp_bootloader \
36 37 ./lfr_management \
37 38 ./lpp_sim \
38 39 ./lpp_sim/CY7C1061DV33 \
39 40 ./lpp_cna \
40 41 ./lpp_uart \
41 42 ./lpp_usb \
42 43 ./dsp/lpp_fft \
44 ./lpp_leon3_soc \
45 ./lpp_debug_lfr
43 46
44 47 FILESKIP = i2cmst.vhd \
45 48 APB_MULTI_DIODE.vhd \
46 49 APB_MULTI_DIODE.vhd \
47 50 Top_MatrixSpec.vhd \
48 51 APB_FFT.vhd \
52 lpp_lfr_ms_FFT.vhd \
49 53 lpp_lfr_apbreg.vhd \
50 CoreFFT.vhd
54 CoreFFT.vhd \
55 lpp_lfr_ms.vhd
51 56
52 57 include $(GRLIB)/bin/Makefile
53 58 include $(GRLIB)/software/leon3/Makefile
54 59
55 60 ################## project specific targets ##########################
56 61
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1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 USE ieee.numeric_std.ALL;
5 5 USE IEEE.std_logic_signed.ALL;
6 6 USE IEEE.MATH_real.ALL;
7 7
8 8 LIBRARY techmap;
9 9 USE techmap.gencomp.ALL;
10 10
11 11 LIBRARY std;
12 12 USE std.textio.ALL;
13 13
14 14 LIBRARY lpp;
15 15 USE lpp.iir_filter.ALL;
16 16 USE lpp.lpp_ad_conv.ALL;
17 17 USE lpp.FILTERcfg.ALL;
18 18 USE lpp.lpp_lfr_filter_coeff.ALL;
19 19 USE lpp.general_purpose.ALL;
20 20 USE lpp.data_type_pkg.ALL;
21 21 USE lpp.lpp_lfr_pkg.ALL;
22 22 USE lpp.general_purpose.ALL;
23 23
24 24 ENTITY testbench IS
25 GENERIC(
26 tech : INTEGER := 0; --axcel,
27 Mem_use : INTEGER := use_CEL --use_RAM
28 );
25 29 END;
26 30
27 31 ARCHITECTURE behav OF testbench IS
28 32 CONSTANT ChanelCount : INTEGER := 8;
29 33 CONSTANT Coef_SZ : INTEGER := 9;
30 34 CONSTANT CoefCntPerCel : INTEGER := 6;
31 35 CONSTANT CoefPerCel : INTEGER := 5;
32 36 CONSTANT Cels_count : INTEGER := 5;
33 37
34 38 SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
35 39 SIGNAL sample_val : STD_LOGIC;
36 40
37 41 SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
38 42 SIGNAL sample_fx_val : STD_LOGIC;
39 43
40 44
41 45
42 46
43 47
44 48
45 49 SIGNAL TSTAMP : INTEGER := 0;
46 50 SIGNAL clk : STD_LOGIC := '0';
47 51 SIGNAL clk_24k : STD_LOGIC := '0';
48 52 SIGNAL clk_24k_r : STD_LOGIC := '0';
49 53 SIGNAL rstn : STD_LOGIC;
50 54
51 55 SIGNAL signal_gen : Samples(7 DOWNTO 0);
52 56 SIGNAL offset_gen : Samples(7 DOWNTO 0);
53 57
54 58 --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55 59
56 60 SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
57 61
58 62
59 63 COMPONENT generator IS
60 64 GENERIC (
61 65 AMPLITUDE : INTEGER := 100;
62 66 NB_BITS : INTEGER := 16);
63 67
64 68 PORT (
65 69 clk : IN STD_LOGIC;
66 70 rstn : IN STD_LOGIC;
67 71 run : IN STD_LOGIC;
68 72
69 73 data_ack : IN STD_LOGIC;
70 74 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
71 75 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
72 76 );
73 77 END COMPONENT;
74 78
75 79
76 80 FILE log_input : TEXT OPEN write_mode IS "log_input.txt";
77 81 FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
78 82
79 83 SIGNAL end_of_simu : STD_LOGIC := '0';
80 84
81 85 BEGIN
82 86
83 87 -----------------------------------------------------------------------------
84 88 -- CLOCK and RESET
85 89 -----------------------------------------------------------------------------
86 90 clk <= NOT clk AFTER 5 ns;
87 91 PROCESS
88 92 BEGIN -- PROCESS
89 93 end_of_simu <= '0';
90 94 WAIT UNTIL clk = '1';
91 95 rstn <= '0';
92 96 WAIT UNTIL clk = '1';
93 97 WAIT UNTIL clk = '1';
94 98 WAIT UNTIL clk = '1';
95 99 rstn <= '1';
96 100 WAIT FOR 2000 ms;
97 101 end_of_simu <= '1';
98 102 WAIT UNTIL clk = '1';
99 103 REPORT "*** END simulation ***" SEVERITY failure;
100 104 WAIT;
101 105 END PROCESS;
102 106 -----------------------------------------------------------------------------
103 107
104 108
105 109 -----------------------------------------------------------------------------
106 110 -- COMMON TIMESTAMPS
107 111 -----------------------------------------------------------------------------
108 112
109 113 PROCESS(clk)
110 114 BEGIN
111 115 IF clk'EVENT AND clk = '1' THEN
112 116 TSTAMP <= TSTAMP+1;
113 117 END IF;
114 118 END PROCESS;
115 119 -----------------------------------------------------------------------------
116 120
117 121
118 122 -----------------------------------------------------------------------------
119 123 -- LPP_LFR_FILTER f0
120 124 -----------------------------------------------------------------------------
121 125
122 126 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
123 127 GENERIC MAP (
124 tech => axcel,
128 tech => tech,
125 129 Mem_use => use_RAM,
126 130 Sample_SZ => 18,
127 131 Coef_SZ => Coef_SZ,
128 132 Coef_Nb => 25,
129 133 Coef_sel_SZ => 5,
130 134 Cels_count => Cels_count,
131 ChanelsCount => ChanelCount)
135 ChanelsCount => ChanelCount,
136 FILENAME => "RAM.txt")
132 137 PORT MAP (
133 138 rstn => rstn,
134 139 clk => clk,
135 140 virg_pos => 7,
136 141 coefs => CoefsInitValCst_v2,
137 142
138 143 sample_in_val => sample_val,
139 144 sample_in => sample,
140 145 sample_out_val => sample_fx_val,
141 146 sample_out => sample_fx);
142 147 -----------------------------------------------------------------------------
143 148
144 149
145 150 -----------------------------------------------------------------------------
146 151 -- SAMPLE GENERATION
147 152 -----------------------------------------------------------------------------
148 153 clk_24k <= NOT clk_24k AFTER 20345 ns;
149 154
150 155 PROCESS (clk, rstn)
151 156 BEGIN -- PROCESS
152 157 IF rstn = '0' THEN -- asynchronous reset (active low)
153 158 sample_val <= '0';
154 159 clk_24k_r <= '0';
155 160 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
156 161 clk_24k_r <= clk_24k;
157 162 IF clk_24k = '1' AND clk_24k_r = '0' THEN
158 163 sample_val <= '1';
159 164 ELSE
160 165 sample_val <= '0';
161 166 END IF;
162 167 END IF;
163 168 END PROCESS;
164 169 -----------------------------------------------------------------------------
165 170 generators : FOR I IN 0 TO 7 GENERATE
166 171 gen1 : generator
167 172 GENERIC MAP (
168 173 AMPLITUDE => 100,
169 174 NB_BITS => 16)
170 175 PORT MAP (
171 176 clk => clk,
172 177 rstn => rstn,
173 178 run => '1',
174 179 data_ack => sample_val,
175 180 offset => offset_gen(I),
176 181 data => signal_gen(I)
177 182 );
178 183 offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
179 184 END GENERATE generators;
180 185
181 186 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
182 187 SampleLoop : FOR j IN 0 TO 15 GENERATE
183 188 sample(i,j) <= signal_gen(i)(j);
184 189 sample_fx_wdata(i)(j) <= sample_fx(i,j);
185 190 END GENERATE;
186 191
187 192 sample(i, 16) <= signal_gen(i)(15);
188 193 sample(i, 17) <= signal_gen(i)(15);
189 194 END GENERATE;
190 195
191 196
192 197
193 198 -----------------------------------------------------------------------------
194 199 -- RECORD SIGNALS
195 200 -----------------------------------------------------------------------------
196 201
197 202 -- PROCESS(sample_val)
198 203 -- VARIABLE line_var : LINE;
199 204 -- BEGIN
200 205 -- IF sample_val'EVENT AND sample_val = '1' THEN
201 206 -- write(line_var, INTEGER'IMAGE(TSTAMP));
202 207 -- FOR I IN 0 TO 7 LOOP
203 208 -- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
204 209 -- END LOOP;
205 210 -- writeline(log_input, line_var);
206 211 -- END IF;
207 212 -- END PROCESS;
208 213
209 214 PROCESS(sample_fx_val,end_of_simu)
210 215 VARIABLE line_var : LINE;
211 216 BEGIN
212 217 IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
213 218 write(line_var, INTEGER'IMAGE(TSTAMP));
214 219 FOR I IN 0 TO 5 LOOP
215 220 write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
216 221 END LOOP;
217 222 writeline(log_output_fx, line_var);
218 223 END IF;
219 224 IF end_of_simu = '1' THEN
220 225 file_close(log_output_fx);
221 226 END IF;
222 227 END PROCESS;
223 228
224 229
225 230
226 231
227 232 END;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.iir_filter.ALL;
32 32 USE lpp.general_purpose.ALL;
33 33
34 34 ENTITY IIR_CEL_CTRLR_v2 IS
35 35 GENERIC (
36 36 tech : INTEGER := 0;
37 37 Mem_use : INTEGER := use_RAM;
38 38 Sample_SZ : INTEGER := 18;
39 39 Coef_SZ : INTEGER := 9;
40 40 Coef_Nb : INTEGER := 25;
41 41 Coef_sel_SZ : INTEGER := 5;
42 42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
43 ChanelsCount : INTEGER := 8;
44 FILENAME : STRING := "");
44 45 PORT (
45 46 rstn : IN STD_LOGIC;
46 47 clk : IN STD_LOGIC;
47 48
48 49 virg_pos : IN INTEGER;
49 50 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50 51
51 52 sample_in_val : IN STD_LOGIC;
52 53 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 54
54 55 sample_out_val : OUT STD_LOGIC;
55 56 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 57 END IIR_CEL_CTRLR_v2;
57 58
58 59 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59 60
60 61 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 62 GENERIC (
62 63 tech : INTEGER;
63 64 Mem_use : INTEGER;
64 65 Sample_SZ : INTEGER;
65 66 Coef_SZ : INTEGER;
66 67 Coef_Nb : INTEGER;
67 Coef_sel_SZ : INTEGER);
68 Coef_sel_SZ : INTEGER;
69 FILENAME : STRING);
68 70 PORT (
69 71 rstn : IN STD_LOGIC;
70 72 clk : IN STD_LOGIC;
71 73 virg_pos : IN INTEGER;
72 74 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 75 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 76 init_mem_done : out STD_LOGIC;
75 77 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
76 78 ram_write : IN STD_LOGIC;
77 79 ram_read : IN STD_LOGIC;
78 80 raddr_rst : IN STD_LOGIC;
79 81 raddr_add1 : IN STD_LOGIC;
80 82 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
81 83 alu_sel_input : IN STD_LOGIC;
82 84 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
83 85 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
84 86 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
85 87 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
86 88 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
87 89 END COMPONENT;
88 90
89 91 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
90 92 GENERIC (
91 93 Coef_sel_SZ : INTEGER;
92 94 Cels_count : INTEGER;
93 95 ChanelsCount : INTEGER);
94 96 PORT (
95 97 rstn : IN STD_LOGIC;
96 98 clk : IN STD_LOGIC;
97 99 sample_in_val : IN STD_LOGIC;
98 100 sample_in_rot : OUT STD_LOGIC;
99 101 sample_out_val : OUT STD_LOGIC;
100 102 sample_out_rot : OUT STD_LOGIC;
101 103 init_mem_done : in STD_LOGIC; --TODO
102 104 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 105 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
104 106 ram_write : OUT STD_LOGIC;
105 107 ram_read : OUT STD_LOGIC;
106 108 raddr_rst : OUT STD_LOGIC;
107 109 raddr_add1 : OUT STD_LOGIC;
108 110 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
109 111 alu_sel_input : OUT STD_LOGIC;
110 112 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
111 113 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
112 114 END COMPONENT;
113 115
114 116 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 117 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 118 SIGNAL ram_write : STD_LOGIC;
117 119 SIGNAL ram_read : STD_LOGIC;
118 120 SIGNAL raddr_rst : STD_LOGIC;
119 121 SIGNAL raddr_add1 : STD_LOGIC;
120 122 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 123 SIGNAL alu_sel_input : STD_LOGIC;
122 124 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
123 125 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
124 126
125 127 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
126 128 SIGNAL sample_in_rotate : STD_LOGIC;
127 129 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
128 130 SIGNAL sample_out_val_s : STD_LOGIC;
129 131 SIGNAL sample_out_val_s2 : STD_LOGIC;
130 132 SIGNAL sample_out_rot_s : STD_LOGIC;
131 133 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
132 134
133 135 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
134 136
135 137 signal init_mem_done : std_logic;
136 138
137 139 BEGIN
138 140
139 141 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
140 142 GENERIC MAP (
141 143 tech => tech,
142 144 Mem_use => Mem_use,
143 145 Sample_SZ => Sample_SZ,
144 146 Coef_SZ => Coef_SZ,
145 147 Coef_Nb => Coef_Nb,
146 Coef_sel_SZ => Coef_sel_SZ)
148 Coef_sel_SZ => Coef_sel_SZ,
149 FILENAME => FILENAME)
147 150 PORT MAP (
148 151 rstn => rstn,
149 152 clk => clk,
150 153 virg_pos => virg_pos,
151 154 coefs => coefs,
152 155 --CTRL
153 156 in_sel_src => in_sel_src,
154 157 init_mem_done => init_mem_done, --TODO
155 158 ram_sel_Wdata => ram_sel_Wdata,
156 159 ram_write => ram_write,
157 160 ram_read => ram_read,
158 161 raddr_rst => raddr_rst,
159 162 raddr_add1 => raddr_add1,
160 163 waddr_previous => waddr_previous,
161 164 alu_sel_input => alu_sel_input,
162 165 alu_sel_coeff => alu_sel_coeff,
163 166 alu_ctrl => alu_ctrl,
164 167 alu_comp => "00",
165 168 --DATA
166 169 sample_in => sample_in_s,
167 170 sample_out => sample_out_s);
168 171
169 172
170 173 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
171 174 GENERIC MAP (
172 175 Coef_sel_SZ => Coef_sel_SZ,
173 176 Cels_count => Cels_count,
174 177 ChanelsCount => ChanelsCount)
175 178 PORT MAP (
176 179 rstn => rstn,
177 180 clk => clk,
178 181 sample_in_val => sample_in_val,
179 182 sample_in_rot => sample_in_rotate,
180 183 sample_out_val => sample_out_val_s,
181 184 sample_out_rot => sample_out_rot_s,
182 185
183 186 init_mem_done => init_mem_done, --TODO
184 187
185 188 in_sel_src => in_sel_src,
186 189 ram_sel_Wdata => ram_sel_Wdata,
187 190 ram_write => ram_write,
188 191 ram_read => ram_read,
189 192 raddr_rst => raddr_rst,
190 193 raddr_add1 => raddr_add1,
191 194 waddr_previous => waddr_previous,
192 195 alu_sel_input => alu_sel_input,
193 196 alu_sel_coeff => alu_sel_coeff,
194 197 alu_ctrl => alu_ctrl);
195 198
196 199 -----------------------------------------------------------------------------
197 200 -- SAMPLE IN
198 201 -----------------------------------------------------------------------------
199 202 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
200 203
201 204 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
202 205 PROCESS (clk, rstn)
203 206 BEGIN -- PROCESS
204 207 IF rstn = '0' THEN -- asynchronous reset (active low)
205 208 sample_in_buf(I, J) <= '0';
206 209 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
207 210 IF sample_in_val = '1' THEN
208 211 sample_in_buf(I, J) <= sample_in(I, J);
209 212 ELSIF sample_in_rotate = '1' THEN
210 213 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
211 214 END IF;
212 215 END IF;
213 216 END PROCESS;
214 217 END GENERATE loop_all_chanel;
215 218
216 219 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
217 220
218 221 END GENERATE loop_all_sample;
219 222
220 223 -----------------------------------------------------------------------------
221 224 -- SAMPLE OUT
222 225 -----------------------------------------------------------------------------
223 226 PROCESS (clk, rstn)
224 227 BEGIN -- PROCESS
225 228 IF rstn = '0' THEN -- asynchronous reset (active low)
226 229 sample_out_val <= '0';
227 230 sample_out_val_s2 <= '0';
228 231 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
229 232 sample_out_val <= sample_out_val_s2;
230 233 sample_out_val_s2 <= sample_out_val_s;
231 234 END IF;
232 235 END PROCESS;
233 236
234 237 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
235 238 PROCESS (clk, rstn)
236 239 BEGIN -- PROCESS
237 240 IF rstn = '0' THEN -- asynchronous reset (active low)
238 241 sample_out_s2(ChanelsCount-1, I) <= '0';
239 242 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
240 243 IF sample_out_rot_s = '1' THEN
241 244 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
242 245 END IF;
243 246 END IF;
244 247 END PROCESS;
245 248 END GENERATE chanel_HIGH;
246 249
247 250 chanel_more : IF ChanelsCount > 1 GENERATE
248 251 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
249 252 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
250 253 PROCESS (clk, rstn)
251 254 BEGIN -- PROCESS
252 255 IF rstn = '0' THEN -- asynchronous reset (active low)
253 256 sample_out_s2(J-1, I) <= '0';
254 257 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
255 258 IF sample_out_rot_s = '1' THEN
256 259 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
257 260 END IF;
258 261 END IF;
259 262 END PROCESS;
260 263 END GENERATE all_bit;
261 264 END GENERATE all_chanel;
262 265 END GENERATE chanel_more;
263 266
264 267 sample_out <= sample_out_s2;
265 268 END ar_IIR_CEL_CTRLR_v2;
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@@ -1,254 +1,257
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.iir_filter.ALL;
27 27 USE lpp.general_purpose.ALL;
28 28
29 29
30 30
31 31 ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS
32 32 GENERIC(
33 33 tech : INTEGER := 0;
34 34 Mem_use : INTEGER := use_RAM;
35 35 Sample_SZ : INTEGER := 16;
36 36 Coef_SZ : INTEGER := 9;
37 37 Coef_Nb : INTEGER := 30;
38 Coef_sel_SZ : INTEGER := 5
38 Coef_sel_SZ : INTEGER := 5;
39 FILENAME : STRING:= ""
39 40 );
40 41 PORT(
41 42 rstn : IN STD_LOGIC;
42 43 clk : IN STD_LOGIC;
43 44 -- PARAMETER
44 45 virg_pos : IN INTEGER;
45 46 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
46 47 -- CONTROL
47 48 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 49 --
49 50 init_mem_done : out STD_LOGIC;
50 51 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
51 52 ram_write : IN STD_LOGIC;
52 53 ram_read : IN STD_LOGIC;
53 54 raddr_rst : IN STD_LOGIC;
54 55 raddr_add1 : IN STD_LOGIC;
55 56 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
56 57 --
57 58 alu_sel_input : IN STD_LOGIC;
58 59 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
59 60 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
60 61 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
61 62 -- DATA
62 63 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
63 64 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
64 65 );
65 66 END IIR_CEL_CTRLR_v2_DATAFLOW;
66 67
67 68 ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS
68 69
69 70 COMPONENT RAM_CTRLR_v2
70 71 GENERIC (
71 72 tech : INTEGER;
72 73 Input_SZ_1 : INTEGER;
73 Mem_use : INTEGER);
74 Mem_use : INTEGER;
75 FILENAME : STRING);
74 76 PORT (
75 77 rstn : IN STD_LOGIC;
76 78 clk : IN STD_LOGIC;
77 79 init_mem_done : out STD_LOGIC;
78 80 ram_write : IN STD_LOGIC;
79 81 ram_read : IN STD_LOGIC;
80 82 raddr_rst : IN STD_LOGIC;
81 83 raddr_add1 : IN STD_LOGIC;
82 84 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
83 85 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
84 86 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
85 87 END COMPONENT;
86 88
87 89 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
88 90 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
89 91 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
90 92 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
91 93 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
92 94 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
93 95
94 96 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
95 97 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
96 98
97 99 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
98 100
99 101 BEGIN
100 102
101 103 -----------------------------------------------------------------------------
102 104 -- INPUT
103 105 -----------------------------------------------------------------------------
104 106 PROCESS (clk, rstn)
105 107 BEGIN -- PROCESS
106 108 IF rstn = '0' THEN -- asynchronous reset (active low)
107 109 reg_sample_in <= (OTHERS => '0');
108 110 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
109 111 CASE in_sel_src IS
110 112 WHEN "00" => reg_sample_in <= reg_sample_in;
111 113 WHEN "01" => reg_sample_in <= sample_in;
112 114 WHEN "10" => reg_sample_in <= ram_output;
113 115 WHEN "11" => reg_sample_in <= alu_output;
114 116 WHEN OTHERS => NULL;
115 117 END CASE;
116 118 END IF;
117 119 END PROCESS;
118 120
119 121
120 122 -----------------------------------------------------------------------------
121 123 -- RAM + CTRL
122 124 -----------------------------------------------------------------------------
123 125
124 126 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
125 127 alu_output WHEN ram_sel_Wdata = "01" ELSE
126 128 ram_output;
127 129
128 130 RAM_CTRLR_v2_1: RAM_CTRLR_v2
129 131 GENERIC MAP (
130 132 tech => tech,
131 133 Input_SZ_1 => Sample_SZ,
132 Mem_use => Mem_use)
134 Mem_use => Mem_use,
135 FILENAME => FILENAME)
133 136 PORT MAP (
134 137 clk => clk,
135 138 rstn => rstn,
136 139 init_mem_done => init_mem_done,
137 140 ram_write => ram_write,
138 141 ram_read => ram_read,
139 142 raddr_rst => raddr_rst,
140 143 raddr_add1 => raddr_add1,
141 144 waddr_previous => waddr_previous,
142 145 sample_in => ram_input,
143 146 sample_out => ram_output);
144 147
145 148 -----------------------------------------------------------------------------
146 149 -- MAC_ACC
147 150 -----------------------------------------------------------------------------
148 151 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
149 152 -- Data In : mac_sample, mac_coef
150 153 -- Data Out: mac_output
151 154
152 155 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
153 156
154 157 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
155 158 coeff_in: IF I < Coef_Nb GENERATE
156 159 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
157 160 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
158 161 END GENERATE all_bit;
159 162 END GENERATE coeff_in;
160 163 coeff_null: IF I > (Coef_Nb -1) GENERATE
161 164 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
162 165 arrayCoeff(I,J) <= '0';
163 166 END GENERATE all_bit;
164 167 END GENERATE coeff_null;
165 168 END GENERATE coefftable;
166 169
167 170 Coeff_Mux : MUXN
168 171 GENERIC MAP (
169 172 Input_SZ => Coef_SZ,
170 173 NbStage => Coef_sel_SZ)
171 174 PORT MAP (
172 175 sel => alu_sel_coeff,
173 176 INPUT => arrayCoeff,
174 177 RES => alu_coef_s);
175 178
176 179
177 180 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
178 181 alu_coef(J) <= alu_coef_s(J);
179 182 END GENERATE all_bit;
180 183
181 184 -----------------------------------------------------------------------------
182 185 -- TODO : just for Synthesis test
183 186
184 187 --PROCESS (clk, rstn)
185 188 --BEGIN
186 189 -- IF rstn = '0' THEN
187 190 -- alu_coef <= (OTHERS => '0');
188 191 -- ELSIF clk'event AND clk = '1' THEN
189 192 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
190 193 -- alu_coef(J) <= alu_coef_s(J);
191 194 -- END LOOP all_bit;
192 195 -- END IF;
193 196 --END PROCESS;
194 197
195 198 -----------------------------------------------------------------------------
196 199
197 200
198 201 ALU_1: ALU
199 202 GENERIC MAP (
200 203 Arith_en => 1,
201 204 Input_SZ_1 => Sample_SZ,
202 205 Input_SZ_2 => Coef_SZ,
203 206 COMP_EN => 1)
204 207 PORT MAP (
205 208 clk => clk,
206 209 reset => rstn,
207 210 ctrl => alu_ctrl,
208 211 comp => alu_comp,
209 212 OP1 => alu_sample,
210 213 OP2 => alu_coef,
211 214 RES => alu_output_s);
212 215
213 216 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
214 217
215 218 sample_out <= alu_output;
216 219
217 220 END ar_IIR_CEL_CTRLR_v2_DATAFLOW;
218 221
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@@ -1,109 +1,140
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY ieee;
23 23 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_textio.ALL;
24 25 USE IEEE.numeric_std.ALL;
26 LIBRARY std;
27 USE std.textio.ALL;
28
25 29
26 30 ENTITY RAM_CEL IS
27 31 GENERIC(
28 32 DataSz : INTEGER RANGE 1 TO 32 := 8;
29 abits : INTEGER RANGE 2 TO 12 := 8);
33 abits : INTEGER RANGE 2 TO 12 := 8;
34 FILENAME : string:= ""
35 );
30 36 PORT(
31 37 WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
32 38 RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
33 39 WEN, REN : IN STD_LOGIC;
34 40 WADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
35 41 RADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
36 42 RWCLK, RESET : IN STD_LOGIC
37 43 ) ;
38 44 END RAM_CEL;
39 45
40 46
41 47
42 48 ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
43 49
44 50 CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0');
45 51 CONSTANT MAX : INTEGER := 2**(abits);
46 52
47 53 TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
48 54
49 SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit);
50 55 SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51 56
52 57 SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
58
59
60 -- Read a *.hex file
61 impure function ReadMemFile(FileName : STRING) return RAMarrayT is
62 file FileHandle : TEXT open READ_MODE is FileName;
63 variable CurrentLine : LINE;
64 variable TempWord : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
65 variable Result : RAMarrayT := (others => (others => '0'));
53 66
67 begin
68 for i in 0 to MAX - 1 loop
69 exit when endfile(FileHandle);
70 readline(FileHandle, CurrentLine);
71 hread(CurrentLine, TempWord);
72 Result(i) := TempWord;
73 end loop;
74
75 return Result;
76 end function;
77
78 impure function InitMem(FileName : STRING) return RAMarrayT is
79 variable Result : RAMarrayT := (others => (others => '0'));
80 begin
81 if FileName'length /= 0 then
82 Result := ReadMemFile(FileName);
83 end if;
84 return Result;
85 end function;
86
87 SIGNAL RAMarray : RAMarrayT := InitMem(FILENAME);
54 88 BEGIN
55 89
56 90 RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
57 91
58
59 92 PROCESS(RWclk, reset)
60 93 BEGIN
61 94 IF reset = '0' THEN
62 95 RD <= VectInit;
63 rst : FOR i IN 0 TO MAX-1 LOOP
64 RAMarray(i) <= (OTHERS => '0');
65 END LOOP;
96 -- rst : FOR i IN 0 TO MAX-1 LOOP
97 -- RAMarray(i) <= (OTHERS => '0');
98 -- END LOOP;
66 99
67 100 ELSIF RWclk'EVENT AND RWclk = '1' THEN
68 -- IF REN = '0' THEN
69 101 RD <= RD_int;
70 -- END IF;
71 102 IF REN = '0' THEN
72 103 RADDR_reg <= RADDR;
73 104 END IF;
74 105
75 106 IF WEN = '0' THEN
76 107 RAMarray(to_integer(UNSIGNED(WADDR))) <= WD;
77 108 END IF;
78 109
79 110 END IF;
80 111 END PROCESS;
81 112 END ar_RAM_CEL;
82 113
83 114
84 115
85 116
86 117
87 118
88 119
89 120
90 121
91 122
92 123
93 124
94 125
95 126
96 127
97 128
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101 132
102 133
103 134
104 135
105 136
106 137
107 138
108 139
109 140
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@@ -1,138 +1,139
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.iir_filter.ALL;
27 27 USE lpp.FILTERcfg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29 LIBRARY techmap;
30 30 USE techmap.gencomp.ALL;
31 31
32 32 ENTITY RAM_CTRLR_v2 IS
33 33 GENERIC(
34 34 tech : INTEGER := 0;
35 35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM;
37 FILENAME : STRING:= ""
37 38 );
38 39 PORT(
39 40 rstn : IN STD_LOGIC;
40 41 clk : IN STD_LOGIC;
41 42 -- ram init done
42 43 init_mem_done: out STD_LOGIC;
43 44 -- R/W Ctrl
44 45 ram_write : IN STD_LOGIC;
45 46 ram_read : IN STD_LOGIC;
46 47 -- ADDR Ctrl
47 48 raddr_rst : IN STD_LOGIC;
48 49 raddr_add1 : IN STD_LOGIC;
49 50 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 51 -- Data
51 52 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
52 53 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
53 54 );
54 55 END RAM_CTRLR_v2;
55 56
56 57
57 58 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
58 59
59 60 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
60 61 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
61 62 SIGNAL WEN, REN : STD_LOGIC;
62 63 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
63 64 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
64 65 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
65 66
66 67 signal rst_mem_done_s : std_logic;
67 68 signal ram_write_s : std_logic;
68 69
69 70 BEGIN
70 71
71 72 init_mem_done <= rst_mem_done_s;
72 73
73 74 sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
74 75 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0');
75 76 ram_write_s <= ram_write when rst_mem_done_s = '1' else '1';
76 77 -----------------------------------------------------------------------------
77 78 -- RAM
78 79 -----------------------------------------------------------------------------
79 80
80 81 memCEL : IF Mem_use = use_CEL GENERATE
81 82 WEN <= NOT ram_write_s;
82 83 REN <= NOT ram_read;
83 84 RAMblk : RAM_CEL
84 GENERIC MAP(Input_SZ_1, 8)
85 GENERIC MAP(Input_SZ_1, 8,FILENAME)
85 86 PORT MAP(
86 87 WD => WD,
87 88 RD => RD,
88 89 WEN => WEN,
89 90 REN => REN,
90 91 WADDR => WADDR,
91 92 RADDR => RADDR,
92 93 RWCLK => clk,
93 94 RESET => rstn
94 95 ) ;
95 96 END GENERATE;
96 97
97 98 memRAM : IF Mem_use = use_RAM GENERATE
98 99 SRAM : syncram_2p
99 100 GENERIC MAP(tech, 8, Input_SZ_1)
100 101 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
101 102 END GENERATE;
102 103
103 104 -----------------------------------------------------------------------------
104 105 -- RADDR
105 106 -----------------------------------------------------------------------------
106 107 PROCESS (clk, rstn)
107 108 BEGIN -- PROCESS
108 109 IF rstn = '0' THEN -- asynchronous reset (active low)
109 110 counter <= (OTHERS => '0');
110 111 rst_mem_done_s <= '0';
111 112 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
112 113 if rst_mem_done_s = '0' then
113 114 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
114 115 else
115 116 IF raddr_rst = '1' THEN
116 117 counter <= (OTHERS => '0');
117 118 ELSIF raddr_add1 = '1' THEN
118 119 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
119 120 END IF;
120 121 end if;
121 122 if counter = x"FF" then
122 123 rst_mem_done_s <= '1';
123 124 end if;
124 125
125 126 END IF;
126 127 END PROCESS;
127 128 RADDR <= counter;
128 129
129 130 -----------------------------------------------------------------------------
130 131 -- WADDR
131 132 -----------------------------------------------------------------------------
132 133 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else
133 134 STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
134 135 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
135 136 STD_LOGIC_VECTOR(UNSIGNED(counter));
136 137
137 138
138 139 END ar_RAM_CTRLR_v2;
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@@ -1,326 +1,328
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY ieee;
23 23 USE ieee.std_logic_1164.ALL;
24 24 LIBRARY grlib;
25 25 USE grlib.amba.ALL;
26 26 USE grlib.stdlib.ALL;
27 27 USE grlib.devices.ALL;
28 28
29 29
30 30
31 31
32 32 PACKAGE iir_filter IS
33 33
34 34
35 35 --===========================================================|
36 36 --================A L U C O N T R O L======================|
37 37 --===========================================================|
38 38 CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
39 39 CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
40 40 CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
41 41 CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
42 42 CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
43 43 CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
44 44
45 45 --____
46 46 --RAM |
47 47 --____|
48 48 CONSTANT use_RAM : INTEGER := 1;
49 49 CONSTANT use_CEL : INTEGER := 0;
50 50
51 51
52 52 --===========================================================|
53 53 --=============C O E F S ====================================|
54 54 --===========================================================|
55 55 -- create a specific type of data for coefs to avoid errors |
56 56 --===========================================================|
57 57
58 58 TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
59 59
60 60 TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
61 61
62 62 TYPE in_IIR_CEL_reg IS RECORD
63 63 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 65 END RECORD;
66 66
67 67 TYPE out_IIR_CEL_reg IS RECORD
68 68 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 END RECORD;
71 71
72 72
73 73 COMPONENT APB_IIR_CEL IS
74 74 GENERIC (
75 75 tech : INTEGER := 0;
76 76 pindex : INTEGER := 0;
77 77 paddr : INTEGER := 0;
78 78 pmask : INTEGER := 16#fff#;
79 79 pirq : INTEGER := 0;
80 80 abits : INTEGER := 8;
81 81 Sample_SZ : INTEGER := 16;
82 82 ChanelsCount : INTEGER := 6;
83 83 Coef_SZ : INTEGER := 9;
84 84 CoefCntPerCel : INTEGER := 6;
85 85 Cels_count : INTEGER := 5;
86 86 virgPos : INTEGER := 7;
87 87 Mem_use : INTEGER := use_RAM
88 88 );
89 89 PORT (
90 90 rst : IN STD_LOGIC;
91 91 clk : IN STD_LOGIC;
92 92 apbi : IN apb_slv_in_type;
93 93 apbo : OUT apb_slv_out_type;
94 94 sample_clk : IN STD_LOGIC;
95 95 sample_clk_out : OUT STD_LOGIC;
96 96 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
97 97 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
98 98 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
99 99 );
100 100 END COMPONENT;
101 101
102 102
103 103 COMPONENT Top_IIR IS
104 104 GENERIC(
105 105 Sample_SZ : INTEGER := 18;
106 106 ChanelsCount : INTEGER := 1;
107 107 Coef_SZ : INTEGER := 9;
108 108 CoefCntPerCel : INTEGER := 6;
109 109 Cels_count : INTEGER := 5);
110 110 PORT(
111 111 reset : IN STD_LOGIC;
112 112 clk : IN STD_LOGIC;
113 113 sample_clk : IN STD_LOGIC;
114 114 -- BP : in std_logic;
115 115 -- BPinput : in std_logic_vector(3 downto 0);
116 116 LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
117 117 INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
118 118 OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
119 119 );
120 120 END COMPONENT;
121 121
122 122 COMPONENT IIR_CEL_CTRLR_v2
123 123 GENERIC (
124 124 tech : INTEGER;
125 125 Mem_use : INTEGER;
126 126 Sample_SZ : INTEGER;
127 127 Coef_SZ : INTEGER;
128 128 Coef_Nb : INTEGER;
129 129 Coef_sel_SZ : INTEGER;
130 130 Cels_count : INTEGER;
131 ChanelsCount : INTEGER);
131 ChanelsCount : INTEGER;
132 FILENAME : STRING);
132 133 PORT (
133 134 rstn : IN STD_LOGIC;
134 135 clk : IN STD_LOGIC;
135 136 virg_pos : IN INTEGER;
136 137 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
137 138 sample_in_val : IN STD_LOGIC;
138 139 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
139 140 sample_out_val : OUT STD_LOGIC;
140 141 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
141 142 END COMPONENT;
142 143
143 144 COMPONENT IIR_CEL_CTRLR_v3
144 145 GENERIC (
145 146 tech : INTEGER;
146 147 Mem_use : INTEGER;
147 148 Sample_SZ : INTEGER;
148 149 Coef_SZ : INTEGER;
149 150 Coef_Nb : INTEGER;
150 151 Coef_sel_SZ : INTEGER;
151 152 Cels_count : INTEGER;
152 153 ChanelsCount : INTEGER);
153 154 PORT (
154 155 rstn : IN STD_LOGIC;
155 156 clk : IN STD_LOGIC;
156 157 virg_pos : IN INTEGER;
157 158 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
158 159 sample_in1_val : IN STD_LOGIC;
159 160 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
160 161 sample_in2_val : IN STD_LOGIC;
161 162 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
162 163 sample_out1_val : OUT STD_LOGIC;
163 164 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
164 165 sample_out2_val : OUT STD_LOGIC;
165 166 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
166 167 END COMPONENT;
167 168
168 169
169 170
170 171
171 172 --component FilterCTRLR is
172 173 --port(
173 174 -- reset : in std_logic;
174 175 -- clk : in std_logic;
175 176 -- sample_clk : in std_logic;
176 177 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
177 178 -- sample_in : in samplT;
178 179 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
179 180 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
180 181 --);
181 182 --end component;
182 183
183 184
184 185 --component FILTER_RAM_CTRLR is
185 186 --port(
186 187 -- reset : in std_logic;
187 188 -- clk : in std_logic;
188 189 -- run : in std_logic;
189 190 -- GO_0 : in std_logic;
190 191 -- B_A : in std_logic;
191 192 -- writeForce : in std_logic;
192 193 -- next_blk : in std_logic;
193 194 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
194 195 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
195 196 --);
196 197 --end component;
197 198
198 199
199 200 COMPONENT IIR_CEL_CTRLR IS
200 201 GENERIC(
201 202 tech : INTEGER := 0;
202 203 Sample_SZ : INTEGER := 16;
203 204 ChanelsCount : INTEGER := 1;
204 205 Coef_SZ : INTEGER := 9;
205 206 CoefCntPerCel : INTEGER := 3;
206 207 Cels_count : INTEGER := 5;
207 208 Mem_use : INTEGER := use_RAM
208 209 );
209 210 PORT(
210 211 reset : IN STD_LOGIC;
211 212 clk : IN STD_LOGIC;
212 213 sample_clk : IN STD_LOGIC;
213 214 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
214 215 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
215 216 virg_pos : IN INTEGER;
216 217 GOtest : OUT STD_LOGIC;
217 218 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
218 219 );
219 220 END COMPONENT;
220 221
221 222
222 223 COMPONENT RAM IS
223 224 GENERIC(
224 225 Input_SZ_1 : INTEGER := 8
225 226 );
226 227 PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
227 228 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
228 229 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
229 230 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC
230 231 ) ;
231 232 END COMPONENT;
232 233
233 234 COMPONENT RAM_CEL is
234 235 generic(DataSz : integer range 1 to 32 := 8;
235 abits : integer range 2 to 12 := 8);
236 abits : integer range 2 to 12 := 8;
237 FILENAME : STRING:="");
236 238 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
237 239 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
238 240 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
239 241 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
240 242 ) ;
241 243 end COMPONENT;
242 244
243 245 COMPONENT RAM_CEL_N
244 246 GENERIC (
245 247 size : INTEGER);
246 248 PORT (
247 249 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
248 250 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
249 251 WEN, REN : IN STD_LOGIC;
250 252 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
251 253 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
252 254 RWCLK, RESET : IN STD_LOGIC);
253 255 END COMPONENT;
254 256
255 257 COMPONENT IIR_CEL_FILTER IS
256 258 GENERIC(
257 259 tech : INTEGER := 0;
258 260 Sample_SZ : INTEGER := 16;
259 261 ChanelsCount : INTEGER := 1;
260 262 Coef_SZ : INTEGER := 9;
261 263 CoefCntPerCel : INTEGER := 3;
262 264 Cels_count : INTEGER := 5;
263 265 Mem_use : INTEGER := use_RAM);
264 266 PORT(
265 267 reset : IN STD_LOGIC;
266 268 clk : IN STD_LOGIC;
267 269 sample_clk : IN STD_LOGIC;
268 270 regs_in : IN in_IIR_CEL_reg;
269 271 regs_out : IN out_IIR_CEL_reg;
270 272 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
271 273 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
272 274 GOtest : OUT STD_LOGIC;
273 275 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
274 276
275 277 );
276 278 END COMPONENT;
277 279
278 280
279 281 COMPONENT RAM_CTRLR2 IS
280 282 GENERIC(
281 283 tech : INTEGER := 0;
282 284 Input_SZ_1 : INTEGER := 16;
283 285 Mem_use : INTEGER := use_RAM
284 286 );
285 287 PORT(
286 288 reset : IN STD_LOGIC;
287 289 clk : IN STD_LOGIC;
288 290 WD_sel : IN STD_LOGIC;
289 291 Read : IN STD_LOGIC;
290 292 WADDR_sel : IN STD_LOGIC;
291 293 count : IN STD_LOGIC;
292 294 SVG_ADDR : IN STD_LOGIC;
293 295 Write : IN STD_LOGIC;
294 296 GO_0 : IN STD_LOGIC;
295 297 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
296 298 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
297 299 );
298 300 END COMPONENT;
299 301
300 302 COMPONENT APB_IIR_Filter IS
301 303 GENERIC (
302 304 tech : INTEGER := 0;
303 305 pindex : INTEGER := 0;
304 306 paddr : INTEGER := 0;
305 307 pmask : INTEGER := 16#fff#;
306 308 pirq : INTEGER := 0;
307 309 abits : INTEGER := 8;
308 310 Sample_SZ : INTEGER := 16;
309 311 ChanelsCount : INTEGER := 1;
310 312 Coef_SZ : INTEGER := 9;
311 313 CoefCntPerCel : INTEGER := 6;
312 314 Cels_count : INTEGER := 5;
313 315 virgPos : INTEGER := 3;
314 316 Mem_use : INTEGER := use_RAM
315 317 );
316 318 PORT (
317 319 rst : IN STD_LOGIC;
318 320 clk : IN STD_LOGIC;
319 321 apbi : IN apb_slv_in_type;
320 322 apbo : OUT apb_slv_out_type;
321 323 sample_clk_out : OUT STD_LOGIC;
322 324 GOtest : OUT STD_LOGIC;
323 325 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
324 326 );
325 327 END COMPONENT;
326 328 END;
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