##// END OF EJS Templates
Update MINI LFR
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r637:0d81a266b983 simu_with_Leon3
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@@ -38,8 +38,8 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
@@ -131,13 +131,6 ARCHITECTURE beh OF MINI_LFR_top IS
131 131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 132 --
133 133 SIGNAL errorn : STD_LOGIC;
134 -- UART AHB ---------------------------------------------------------------
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
137
138 -- UART APB ---------------------------------------------------------------
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
141 134 --
142 135 SIGNAL I00_s : STD_LOGIC;
143 136
@@ -164,8 +157,6 ARCHITECTURE beh OF MINI_LFR_top IS
164 157 SIGNAL spw_clk : STD_LOGIC;
165 158 SIGNAL swni : grspw_in_type;
166 159 SIGNAL swno : grspw_out_type;
167 -- SIGNAL clkmn : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
169 160
170 161 --GPIO
171 162 SIGNAL gpioi : gpio_in_type;
@@ -220,15 +211,12 ARCHITECTURE beh OF MINI_LFR_top IS
220 211 BEGIN -- beh
221 212
222 213 -----------------------------------------------------------------------------
223 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
224 -- clk_50 frequency is 100 Mhz !
225 214 PROCESS (clk100MHz, reset)
226 215 BEGIN -- PROCESS
227 216 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
228 217 clk_50_s <= NOT clk_50_s;
229 218 END IF;
230 219 END PROCESS;
231 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
232 220 -----------------------------------------------------------------------------
233 221
234 222 PROCESS (clk_50_s, reset)
@@ -380,13 +368,10 BEGIN -- beh
380 368 pindex => 6,
381 369 paddr => 6,
382 370 pmask => 16#fff#,
383 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
384 371 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
385 372 PORT MAP (
386 373 clk25MHz => clk_25,
387 resetn_25MHz => rstn_25, -- TODO
388 -- clk24_576MHz => clk_24, -- 49.152MHz/2
389 -- resetn_24_576MHz => rstn_24, -- TODO
374 resetn_25MHz => rstn_25,
390 375 grspw_tick => swno.tickout,
391 376 apbi => apbi_ext,
392 377 apbo => apbo_ext(6),
@@ -432,7 +417,6 BEGIN -- beh
432 417 PORT MAP (SPW_RED_SOUT, swno.s(1));
433 418
434 419 -- GRSPW PHY
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 421 spw_phy0 : grspw_phy
438 422 GENERIC MAP(
@@ -496,8 +480,7 BEGIN -- beh
496 480
497 481
498 482 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 --LFR_rstn <= rstn_25;
500
483
501 484 lpp_lfr_1 : lpp_lfr
502 485 GENERIC MAP (
503 486 Mem_use => use_RAM,
@@ -533,7 +516,7 BEGIN -- beh
533 516 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 517 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 518 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 -- IO0 <= rstn_25;
519
537 520 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 521 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 522 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
@@ -566,10 +549,6 BEGIN -- beh
566 549 sample => sample,
567 550 sample_val => sample_val);
568 551
569 --IO10 <= ADC_SDO_sig(5);
570 --IO9 <= ADC_SDO_sig(4);
571 --IO8 <= ADC_SDO_sig(3);
572
573 552 ADC_nCS <= ADC_nCS_sig;
574 553 ADC_CLK <= ADC_CLK_sig;
575 554 ADC_SDO_sig <= ADC_SDO;
@@ -22,7 +22,7 CLEAN=soft-clean
22 22 TECHLIBS = proasic3e
23 23
24 24 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
25 tmtc openchip hynix ihp gleichmann micron usbhc
25 tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
26 26
27 27 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
28 28 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
@@ -42,7 +42,8 FILESKIP =i2cmst.vhd \
42 42 Top_MatrixSpec.vhd \
43 43 APB_FFT.vhd \
44 44 CoreFFT_simu.vhd \
45 lpp_lfr_apbreg_simu.vhd
45 lpp_lfr_apbreg_simu.vhd \
46 sgmii.vhd
46 47
47 48 include $(GRLIB)/bin/Makefile
48 49 include $(GRLIB)/software/leon3/Makefile
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