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1 | #GRLIB=../.. | |
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2 | VHDLIB=../.. | |
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3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
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4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
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5 | TOP=testbench | |
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6 | BOARD=LFR-EQM | |
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7 | include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc | |
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8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |
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9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |
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10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |
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11 | EFFORT=high | |
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12 | XSTOPT= | |
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13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
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14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
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15 | VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd | |
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16 | VHDLSIMFILES= tb.vhd | |
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17 | SIMTOP=testbench | |
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18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
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19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc | |
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20 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc | |
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21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |
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22 | CLEAN=soft-clean | |
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23 | ||
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24 | TECHLIBS = axcelerator | |
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25 | ||
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26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |
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27 | tmtc openchip hynix ihp gleichmann micron usbhc opencores | |
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28 | ||
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29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |
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30 | pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \ | |
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31 | ./amba_lcd_16x2_ctrlr \ | |
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32 | ./general_purpose/lpp_AMR \ | |
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33 | ./general_purpose/lpp_balise \ | |
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34 | ./general_purpose/lpp_delay \ | |
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35 | ./lpp_bootloader \ | |
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36 | ./lfr_management \ | |
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37 | ./lpp_sim \ | |
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38 | ./lpp_sim/CY7C1061DV33 \ | |
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39 | ./lpp_cna \ | |
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40 | ./lpp_uart \ | |
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41 | ./lpp_usb \ | |
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42 | ./dsp/lpp_fft \ | |
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43 | ||
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44 | FILESKIP = i2cmst.vhd \ | |
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45 | APB_MULTI_DIODE.vhd \ | |
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46 | APB_MULTI_DIODE.vhd \ | |
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47 | Top_MatrixSpec.vhd \ | |
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48 | APB_FFT.vhd \ | |
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49 | lpp_lfr_apbreg.vhd \ | |
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50 | CoreFFT.vhd | |
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51 | ||
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52 | include $(GRLIB)/bin/Makefile | |
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53 | include $(GRLIB)/software/leon3/Makefile | |
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54 | ||
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55 | ################## project specific targets ########################## | |
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56 |
@@ -0,0 +1,74 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
|
22 | ---------------------------------------------------------------------------- | |
|
23 | ||
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24 | LIBRARY ieee; | |
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25 | USE ieee.std_logic_1164.ALL; | |
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26 | use ieee.numeric_std.all; | |
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27 | USE IEEE.std_logic_signed.ALL; | |
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28 | USE IEEE.MATH_real.ALL; | |
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29 | ||
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30 | ENTITY generator IS | |
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31 | ||
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32 | GENERIC ( | |
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33 | AMPLITUDE : INTEGER := 100; | |
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34 | NB_BITS : INTEGER := 16); | |
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35 | ||
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36 | PORT ( | |
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37 | clk : IN STD_LOGIC; | |
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38 | rstn : IN STD_LOGIC; | |
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39 | run : IN STD_LOGIC; | |
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40 | ||
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41 | data_ack : IN STD_LOGIC; | |
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42 | offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); | |
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43 | data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) | |
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44 | ); | |
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45 | ||
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46 | END generator; | |
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47 | ||
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48 | ARCHITECTURE beh OF generator IS | |
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49 | ||
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50 | SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); | |
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51 | BEGIN -- beh | |
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52 | ||
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53 | ||
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54 | PROCESS (clk, rstn) | |
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55 | variable seed1, seed2: positive; -- seed values for random generator | |
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56 | variable rand: real; -- random real-number value in range 0 to 1.0 | |
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57 | BEGIN -- PROCESS | |
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58 | uniform(seed1, seed2, rand);--more entropy by skipping values | |
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59 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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60 | reg <= (OTHERS => '0'); | |
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61 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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62 | IF run = '0' THEN | |
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63 | reg <= (OTHERS => '0'); | |
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64 | ELSE | |
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65 | IF data_ack = '1' THEN | |
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66 | reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS)); | |
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67 | END IF; | |
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68 | END IF; | |
|
69 | END IF; | |
|
70 | END PROCESS; | |
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71 | ||
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72 | data <= reg; | |
|
73 | ||
|
74 | END beh; |
@@ -0,0 +1,227 | |||
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1 | ||
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2 | LIBRARY ieee; | |
|
3 | USE ieee.std_logic_1164.ALL; | |
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4 | USE ieee.numeric_std.ALL; | |
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5 | USE IEEE.std_logic_signed.ALL; | |
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6 | USE IEEE.MATH_real.ALL; | |
|
7 | ||
|
8 | LIBRARY techmap; | |
|
9 | USE techmap.gencomp.ALL; | |
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10 | ||
|
11 | LIBRARY std; | |
|
12 | USE std.textio.ALL; | |
|
13 | ||
|
14 | LIBRARY lpp; | |
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15 | USE lpp.iir_filter.ALL; | |
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16 | USE lpp.lpp_ad_conv.ALL; | |
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17 | USE lpp.FILTERcfg.ALL; | |
|
18 | USE lpp.lpp_lfr_filter_coeff.ALL; | |
|
19 | USE lpp.general_purpose.ALL; | |
|
20 | USE lpp.data_type_pkg.ALL; | |
|
21 | USE lpp.lpp_lfr_pkg.ALL; | |
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22 | USE lpp.general_purpose.ALL; | |
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23 | ||
|
24 | ENTITY testbench IS | |
|
25 | END; | |
|
26 | ||
|
27 | ARCHITECTURE behav OF testbench IS | |
|
28 | CONSTANT ChanelCount : INTEGER := 8; | |
|
29 | CONSTANT Coef_SZ : INTEGER := 9; | |
|
30 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
|
31 | CONSTANT CoefPerCel : INTEGER := 5; | |
|
32 | CONSTANT Cels_count : INTEGER := 5; | |
|
33 | ||
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34 | SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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35 | SIGNAL sample_val : STD_LOGIC; | |
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36 | ||
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37 | SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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38 | SIGNAL sample_fx_val : STD_LOGIC; | |
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39 | ||
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40 | ||
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41 | ||
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42 | ||
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43 | ||
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44 | ||
|
45 | SIGNAL TSTAMP : INTEGER := 0; | |
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46 | SIGNAL clk : STD_LOGIC := '0'; | |
|
47 | SIGNAL clk_24k : STD_LOGIC := '0'; | |
|
48 | SIGNAL clk_24k_r : STD_LOGIC := '0'; | |
|
49 | SIGNAL rstn : STD_LOGIC; | |
|
50 | ||
|
51 | SIGNAL signal_gen : Samples(7 DOWNTO 0); | |
|
52 | SIGNAL offset_gen : Samples(7 DOWNTO 0); | |
|
53 | ||
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54 | --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
55 | ||
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56 | SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0); | |
|
57 | ||
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58 | ||
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59 | COMPONENT generator IS | |
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60 | GENERIC ( | |
|
61 | AMPLITUDE : INTEGER := 100; | |
|
62 | NB_BITS : INTEGER := 16); | |
|
63 | ||
|
64 | PORT ( | |
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65 | clk : IN STD_LOGIC; | |
|
66 | rstn : IN STD_LOGIC; | |
|
67 | run : IN STD_LOGIC; | |
|
68 | ||
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69 | data_ack : IN STD_LOGIC; | |
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70 | offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); | |
|
71 | data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) | |
|
72 | ); | |
|
73 | END COMPONENT; | |
|
74 | ||
|
75 | ||
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76 | FILE log_input : TEXT OPEN write_mode IS "log_input.txt"; | |
|
77 | FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt"; | |
|
78 | ||
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79 | SIGNAL end_of_simu : STD_LOGIC := '0'; | |
|
80 | ||
|
81 | BEGIN | |
|
82 | ||
|
83 | ----------------------------------------------------------------------------- | |
|
84 | -- CLOCK and RESET | |
|
85 | ----------------------------------------------------------------------------- | |
|
86 | clk <= NOT clk AFTER 5 ns; | |
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87 | PROCESS | |
|
88 | BEGIN -- PROCESS | |
|
89 | end_of_simu <= '0'; | |
|
90 | WAIT UNTIL clk = '1'; | |
|
91 | rstn <= '0'; | |
|
92 | WAIT UNTIL clk = '1'; | |
|
93 | WAIT UNTIL clk = '1'; | |
|
94 | WAIT UNTIL clk = '1'; | |
|
95 | rstn <= '1'; | |
|
96 | WAIT FOR 2000 ms; | |
|
97 | end_of_simu <= '1'; | |
|
98 | WAIT UNTIL clk = '1'; | |
|
99 | REPORT "*** END simulation ***" SEVERITY failure; | |
|
100 | WAIT; | |
|
101 | END PROCESS; | |
|
102 | ----------------------------------------------------------------------------- | |
|
103 | ||
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104 | ||
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105 | ----------------------------------------------------------------------------- | |
|
106 | -- COMMON TIMESTAMPS | |
|
107 | ----------------------------------------------------------------------------- | |
|
108 | ||
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109 | PROCESS(clk) | |
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110 | BEGIN | |
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111 | IF clk'EVENT AND clk = '1' THEN | |
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112 | TSTAMP <= TSTAMP+1; | |
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113 | END IF; | |
|
114 | END PROCESS; | |
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115 | ----------------------------------------------------------------------------- | |
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116 | ||
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117 | ||
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118 | ----------------------------------------------------------------------------- | |
|
119 | -- LPP_LFR_FILTER f0 | |
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120 | ----------------------------------------------------------------------------- | |
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121 | ||
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122 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
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123 | GENERIC MAP ( | |
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124 | tech => axcel, | |
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125 | Mem_use => use_RAM, | |
|
126 | Sample_SZ => 18, | |
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127 | Coef_SZ => Coef_SZ, | |
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128 | Coef_Nb => 25, | |
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129 | Coef_sel_SZ => 5, | |
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130 | Cels_count => Cels_count, | |
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131 | ChanelsCount => ChanelCount) | |
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132 | PORT MAP ( | |
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133 | rstn => rstn, | |
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134 | clk => clk, | |
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135 | virg_pos => 7, | |
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136 | coefs => CoefsInitValCst_v2, | |
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137 | ||
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138 | sample_in_val => sample_val, | |
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139 | sample_in => sample, | |
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140 | sample_out_val => sample_fx_val, | |
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141 | sample_out => sample_fx); | |
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142 | ----------------------------------------------------------------------------- | |
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143 | ||
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144 | ||
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145 | ----------------------------------------------------------------------------- | |
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146 | -- SAMPLE GENERATION | |
|
147 | ----------------------------------------------------------------------------- | |
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148 | clk_24k <= NOT clk_24k AFTER 20345 ns; | |
|
149 | ||
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150 | PROCESS (clk, rstn) | |
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151 | BEGIN -- PROCESS | |
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152 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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153 | sample_val <= '0'; | |
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154 | clk_24k_r <= '0'; | |
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155 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
156 | clk_24k_r <= clk_24k; | |
|
157 | IF clk_24k = '1' AND clk_24k_r = '0' THEN | |
|
158 | sample_val <= '1'; | |
|
159 | ELSE | |
|
160 | sample_val <= '0'; | |
|
161 | END IF; | |
|
162 | END IF; | |
|
163 | END PROCESS; | |
|
164 | ----------------------------------------------------------------------------- | |
|
165 | generators : FOR I IN 0 TO 7 GENERATE | |
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166 | gen1 : generator | |
|
167 | GENERIC MAP ( | |
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168 | AMPLITUDE => 100, | |
|
169 | NB_BITS => 16) | |
|
170 | PORT MAP ( | |
|
171 | clk => clk, | |
|
172 | rstn => rstn, | |
|
173 | run => '1', | |
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174 | data_ack => sample_val, | |
|
175 | offset => offset_gen(I), | |
|
176 | data => signal_gen(I) | |
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177 | ); | |
|
178 | offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16)); | |
|
179 | END GENERATE generators; | |
|
180 | ||
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181 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
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182 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
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183 | sample(i,j) <= signal_gen(i)(j); | |
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184 | sample_fx_wdata(i)(j) <= sample_fx(i,j); | |
|
185 | END GENERATE; | |
|
186 | ||
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187 | sample(i, 16) <= signal_gen(i)(15); | |
|
188 | sample(i, 17) <= signal_gen(i)(15); | |
|
189 | END GENERATE; | |
|
190 | ||
|
191 | ||
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192 | ||
|
193 | ----------------------------------------------------------------------------- | |
|
194 | -- RECORD SIGNALS | |
|
195 | ----------------------------------------------------------------------------- | |
|
196 | ||
|
197 | -- PROCESS(sample_val) | |
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198 | -- VARIABLE line_var : LINE; | |
|
199 | -- BEGIN | |
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200 | -- IF sample_val'EVENT AND sample_val = '1' THEN | |
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201 | -- write(line_var, INTEGER'IMAGE(TSTAMP)); | |
|
202 | -- FOR I IN 0 TO 7 LOOP | |
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203 | -- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I))))); | |
|
204 | -- END LOOP; | |
|
205 | -- writeline(log_input, line_var); | |
|
206 | -- END IF; | |
|
207 | -- END PROCESS; | |
|
208 | ||
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209 | PROCESS(sample_fx_val,end_of_simu) | |
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210 | VARIABLE line_var : LINE; | |
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211 | BEGIN | |
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212 | IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN | |
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213 | write(line_var, INTEGER'IMAGE(TSTAMP)); | |
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214 | FOR I IN 0 TO 5 LOOP | |
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215 | write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I))))); | |
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216 | END LOOP; | |
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217 | writeline(log_output_fx, line_var); | |
|
218 | END IF; | |
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219 | IF end_of_simu = '1' THEN | |
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220 | file_close(log_output_fx); | |
|
221 | END IF; | |
|
222 | END PROCESS; | |
|
223 | ||
|
224 | ||
|
225 | ||
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226 | ||
|
227 | END; |
@@ -1,518 +1,519 | |||
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1 | 1 | LIBRARY ieee; |
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2 | 2 | USE ieee.std_logic_1164.ALL; |
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3 | 3 | USE ieee.numeric_std.ALL; |
|
4 | 4 | |
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5 | 5 | LIBRARY lpp; |
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6 | 6 | USE lpp.lpp_ad_conv.ALL; |
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7 | 7 | USE lpp.iir_filter.ALL; |
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8 | 8 | USE lpp.FILTERcfg.ALL; |
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9 | 9 | USE lpp.lpp_memory.ALL; |
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10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
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11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
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12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
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13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
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14 | 14 | USE lpp.general_purpose.ALL; |
|
15 | 15 | |
|
16 | 16 | LIBRARY techmap; |
|
17 | 17 | USE techmap.gencomp.ALL; |
|
18 | 18 | |
|
19 | 19 | LIBRARY grlib; |
|
20 | 20 | USE grlib.amba.ALL; |
|
21 | 21 | USE grlib.stdlib.ALL; |
|
22 | 22 | USE grlib.devices.ALL; |
|
23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
24 | 24 | |
|
25 | 25 | ENTITY lpp_lfr IS |
|
26 | 26 | GENERIC ( |
|
27 | 27 | Mem_use : INTEGER := use_RAM; |
|
28 | 28 | tech : INTEGER := inferred; |
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29 | 29 | nb_data_by_buffer_size : INTEGER := 32; |
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30 | 30 | nb_snapshot_param_size : INTEGER := 32; |
|
31 | 31 | delta_vector_size : INTEGER := 32; |
|
32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
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33 | 33 | |
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34 | 34 | pindex : INTEGER := 15; |
|
35 | 35 | paddr : INTEGER := 15; |
|
36 | 36 | pmask : INTEGER := 16#fff#; |
|
37 | 37 | pirq_ms : INTEGER := 6; |
|
38 | 38 | pirq_wfp : INTEGER := 14; |
|
39 | 39 | |
|
40 | 40 | hindex : INTEGER := 2; |
|
41 | 41 | |
|
42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153"; |
|
43 | 43 | |
|
44 | 44 | DEBUG_FORCE_DATA_DMA : INTEGER := 0; |
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45 | 45 | RTL_DESIGN_LIGHT : INTEGER := 0; |
|
46 | 46 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15 |
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47 | 47 | ); |
|
48 | 48 | PORT ( |
|
49 | 49 | clk : IN STD_LOGIC; |
|
50 | 50 | rstn : IN STD_LOGIC; |
|
51 | 51 | -- SAMPLE |
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52 | 52 | sample_B : IN Samples(2 DOWNTO 0); |
|
53 | 53 | sample_E : IN Samples(4 DOWNTO 0); |
|
54 | 54 | sample_val : IN STD_LOGIC; |
|
55 | 55 | -- APB |
|
56 | 56 | apbi : IN apb_slv_in_type; |
|
57 | 57 | apbo : OUT apb_slv_out_type; |
|
58 | 58 | -- AHB |
|
59 | 59 | ahbi : IN AHB_Mst_In_Type; |
|
60 | 60 | ahbo : OUT AHB_Mst_Out_Type; |
|
61 | 61 | -- TIME |
|
62 | 62 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
63 | 63 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
64 | 64 | -- |
|
65 | 65 | data_shaping_BW : OUT STD_LOGIC; |
|
66 | 66 | -- |
|
67 | 67 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
68 | 68 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
69 | 69 | ); |
|
70 | 70 | END lpp_lfr; |
|
71 | 71 | |
|
72 | 72 | ARCHITECTURE beh OF lpp_lfr IS |
|
73 | 73 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
74 | 74 | -- |
|
75 | 75 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
76 | 76 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
77 | 77 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
78 | 78 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
79 | 79 | SIGNAL data_shaping_R2 : STD_LOGIC; |
|
80 | 80 | -- |
|
81 | 81 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
82 | 82 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
83 | 83 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | 84 | -- |
|
85 | 85 | SIGNAL sample_f0_val : STD_LOGIC; |
|
86 | 86 | SIGNAL sample_f1_val : STD_LOGIC; |
|
87 | 87 | SIGNAL sample_f2_val : STD_LOGIC; |
|
88 | 88 | SIGNAL sample_f3_val : STD_LOGIC; |
|
89 | 89 | -- |
|
90 | 90 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
91 | 91 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
92 | 92 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
93 | 93 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
94 | 94 | -- |
|
95 | 95 | SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0); |
|
96 | 96 | SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0); |
|
97 | 97 | SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0); |
|
98 | 98 | SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0); |
|
99 | 99 | -- |
|
100 | 100 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
101 | 101 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
102 | 102 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
103 | 103 | |
|
104 | 104 | -- SM |
|
105 | 105 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
|
106 | 106 | -- SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
107 | 107 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
108 | 108 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
109 | 109 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; |
|
110 | 110 | -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
111 | 111 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
112 | 112 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
113 | 113 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | 114 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | 115 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | 116 | SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
117 | 117 | SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
118 | 118 | SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
119 | 119 | |
|
120 | 120 | -- WFP |
|
121 | 121 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
122 | 122 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
123 | 123 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
124 | 124 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
125 | 125 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
126 | 126 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
127 | 127 | |
|
128 | 128 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
129 | 129 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
130 | 130 | SIGNAL enable_f0 : STD_LOGIC; |
|
131 | 131 | SIGNAL enable_f1 : STD_LOGIC; |
|
132 | 132 | SIGNAL enable_f2 : STD_LOGIC; |
|
133 | 133 | SIGNAL enable_f3 : STD_LOGIC; |
|
134 | 134 | SIGNAL burst_f0 : STD_LOGIC; |
|
135 | 135 | SIGNAL burst_f1 : STD_LOGIC; |
|
136 | 136 | SIGNAL burst_f2 : STD_LOGIC; |
|
137 | 137 | |
|
138 | 138 | --SIGNAL run : STD_LOGIC; |
|
139 | 139 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
140 | 140 | |
|
141 | 141 | ----------------------------------------------------------------------------- |
|
142 | 142 | -- |
|
143 | 143 | ----------------------------------------------------------------------------- |
|
144 | 144 | |
|
145 | 145 | SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
146 | 146 | SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
147 | 147 | SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
148 | 148 | SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
149 | 149 | SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
150 | 150 | SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
151 | 151 | |
|
152 | 152 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
153 | 153 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
154 | 154 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
155 | 155 | |
|
156 | 156 | |
|
157 | 157 | SIGNAL error_buffer_full : STD_LOGIC; |
|
158 | 158 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
159 | 159 | |
|
160 | 160 | ----------------------------------------------------------------------------- |
|
161 | 161 | SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
162 | 162 | SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
163 | 163 | SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015 |
|
164 | 164 | SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015 |
|
165 | 165 | SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015 |
|
166 | 166 | SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
167 | 167 | SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
168 | 168 | SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); |
|
169 | 169 | SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); |
|
170 | 170 | SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | 171 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
172 | 172 | SIGNAL dma_grant_error : STD_LOGIC; |
|
173 | 173 | |
|
174 | 174 | SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
175 | 175 | ----------------------------------------------------------------------------- |
|
176 | 176 | SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
177 | 177 | SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
178 | 178 | SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
179 | 179 | SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
180 | 180 | SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
181 | 181 | |
|
182 | 182 | BEGIN |
|
183 | 183 | |
|
184 | 184 | ----------------------------------------------------------------------------- |
|
185 | 185 | |
|
186 | 186 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
187 | 187 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
188 | 188 | sample_time <= coarse_time & fine_time; |
|
189 | 189 | |
|
190 | 190 | ----------------------------------------------------------------------------- |
|
191 | 191 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
192 | 192 | GENERIC MAP ( |
|
193 | tech => tech, | |
|
193 | 194 | Mem_use => Mem_use, |
|
194 | 195 | RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT) |
|
195 | 196 | PORT MAP ( |
|
196 | 197 | sample => sample_s, |
|
197 | 198 | sample_val => sample_val, |
|
198 | 199 | sample_time => sample_time, |
|
199 | 200 | clk => clk, |
|
200 | 201 | rstn => rstn, |
|
201 | 202 | data_shaping_SP0 => data_shaping_SP0, |
|
202 | 203 | data_shaping_SP1 => data_shaping_SP1, |
|
203 | 204 | data_shaping_R0 => data_shaping_R0, |
|
204 | 205 | data_shaping_R1 => data_shaping_R1, |
|
205 | 206 | data_shaping_R2 => data_shaping_R2, |
|
206 | 207 | sample_f0_val => sample_f0_val, |
|
207 | 208 | sample_f1_val => sample_f1_val, |
|
208 | 209 | sample_f2_val => sample_f2_val, |
|
209 | 210 | sample_f3_val => sample_f3_val, |
|
210 | 211 | sample_f0_wdata => sample_f0_data, |
|
211 | 212 | sample_f1_wdata => sample_f1_data, |
|
212 | 213 | sample_f2_wdata => sample_f2_data, |
|
213 | 214 | sample_f3_wdata => sample_f3_data, |
|
214 | 215 | sample_f0_time => sample_f0_time, |
|
215 | 216 | sample_f1_time => sample_f1_time, |
|
216 | 217 | sample_f2_time => sample_f2_time, |
|
217 | 218 | sample_f3_time => sample_f3_time |
|
218 | 219 | ); |
|
219 | 220 | |
|
220 | 221 | ----------------------------------------------------------------------------- |
|
221 | 222 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
222 | 223 | GENERIC MAP ( |
|
223 | 224 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
224 | 225 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
225 | 226 | delta_vector_size => delta_vector_size, |
|
226 | 227 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
227 | 228 | pindex => pindex, |
|
228 | 229 | paddr => paddr, |
|
229 | 230 | pmask => pmask, |
|
230 | 231 | pirq_ms => pirq_ms, |
|
231 | 232 | pirq_wfp => pirq_wfp, |
|
232 | 233 | top_lfr_version => top_lfr_version) |
|
233 | 234 | PORT MAP ( |
|
234 | 235 | HCLK => clk, |
|
235 | 236 | HRESETn => rstn, |
|
236 | 237 | apbi => apbi, |
|
237 | 238 | apbo => apbo, |
|
238 | 239 | |
|
239 | 240 | -- run_ms => OPEN,--run_ms, |
|
240 | 241 | |
|
241 | 242 | ready_matrix_f0 => ready_matrix_f0, |
|
242 | 243 | ready_matrix_f1 => ready_matrix_f1, |
|
243 | 244 | ready_matrix_f2 => ready_matrix_f2, |
|
244 | 245 | error_buffer_full => error_buffer_full, |
|
245 | 246 | error_input_fifo_write => error_input_fifo_write, |
|
246 | 247 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
247 | 248 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
248 | 249 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
249 | 250 | |
|
250 | 251 | matrix_time_f0 => matrix_time_f0, |
|
251 | 252 | matrix_time_f1 => matrix_time_f1, |
|
252 | 253 | matrix_time_f2 => matrix_time_f2, |
|
253 | 254 | |
|
254 | 255 | addr_matrix_f0 => addr_matrix_f0, |
|
255 | 256 | addr_matrix_f1 => addr_matrix_f1, |
|
256 | 257 | addr_matrix_f2 => addr_matrix_f2, |
|
257 | 258 | |
|
258 | 259 | length_matrix_f0 => length_matrix_f0, |
|
259 | 260 | length_matrix_f1 => length_matrix_f1, |
|
260 | 261 | length_matrix_f2 => length_matrix_f2, |
|
261 | 262 | status_new_err => status_new_err, |
|
262 | 263 | data_shaping_BW => data_shaping_BW, |
|
263 | 264 | data_shaping_SP0 => data_shaping_SP0, |
|
264 | 265 | data_shaping_SP1 => data_shaping_SP1, |
|
265 | 266 | data_shaping_R0 => data_shaping_R0, |
|
266 | 267 | data_shaping_R1 => data_shaping_R1, |
|
267 | 268 | data_shaping_R2 => data_shaping_R2, |
|
268 | 269 | delta_snapshot => delta_snapshot, |
|
269 | 270 | delta_f0 => delta_f0, |
|
270 | 271 | delta_f0_2 => delta_f0_2, |
|
271 | 272 | delta_f1 => delta_f1, |
|
272 | 273 | delta_f2 => delta_f2, |
|
273 | 274 | nb_data_by_buffer => nb_data_by_buffer, |
|
274 | 275 | nb_snapshot_param => nb_snapshot_param, |
|
275 | 276 | enable_f0 => enable_f0, |
|
276 | 277 | enable_f1 => enable_f1, |
|
277 | 278 | enable_f2 => enable_f2, |
|
278 | 279 | enable_f3 => enable_f3, |
|
279 | 280 | burst_f0 => burst_f0, |
|
280 | 281 | burst_f1 => burst_f1, |
|
281 | 282 | burst_f2 => burst_f2, |
|
282 | 283 | run => OPEN, |
|
283 | 284 | start_date => start_date, |
|
284 | 285 | wfp_status_buffer_ready => wfp_status_buffer_ready, |
|
285 | 286 | wfp_addr_buffer => wfp_addr_buffer, |
|
286 | 287 | wfp_length_buffer => wfp_length_buffer, |
|
287 | 288 | |
|
288 | 289 | wfp_ready_buffer => wfp_ready_buffer, |
|
289 | 290 | wfp_buffer_time => wfp_buffer_time, |
|
290 | 291 | wfp_error_buffer_full => wfp_error_buffer_full, |
|
291 | 292 | ------------------------------------------------------------------------- |
|
292 | 293 | sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16), |
|
293 | 294 | sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16), |
|
294 | 295 | sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16), |
|
295 | 296 | sample_f3_valid => sample_f3_val, |
|
296 | 297 | debug_vector => apb_reg_debug_vector |
|
297 | 298 | ); |
|
298 | 299 | |
|
299 | 300 | ----------------------------------------------------------------------------- |
|
300 | 301 | ----------------------------------------------------------------------------- |
|
301 | 302 | lpp_waveform_1 : lpp_waveform |
|
302 | 303 | GENERIC MAP ( |
|
303 | 304 | tech => tech, |
|
304 | 305 | data_size => 6*16, |
|
305 | 306 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
306 | 307 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
307 | 308 | delta_vector_size => delta_vector_size, |
|
308 | 309 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
309 | 310 | ) |
|
310 | 311 | PORT MAP ( |
|
311 | 312 | clk => clk, |
|
312 | 313 | rstn => rstn, |
|
313 | 314 | |
|
314 | 315 | reg_run => '1',--run, |
|
315 | 316 | reg_start_date => start_date, |
|
316 | 317 | reg_delta_snapshot => delta_snapshot, |
|
317 | 318 | reg_delta_f0 => delta_f0, |
|
318 | 319 | reg_delta_f0_2 => delta_f0_2, |
|
319 | 320 | reg_delta_f1 => delta_f1, |
|
320 | 321 | reg_delta_f2 => delta_f2, |
|
321 | 322 | |
|
322 | 323 | enable_f0 => enable_f0, |
|
323 | 324 | enable_f1 => enable_f1, |
|
324 | 325 | enable_f2 => enable_f2, |
|
325 | 326 | enable_f3 => enable_f3, |
|
326 | 327 | burst_f0 => burst_f0, |
|
327 | 328 | burst_f1 => burst_f1, |
|
328 | 329 | burst_f2 => burst_f2, |
|
329 | 330 | |
|
330 | 331 | nb_data_by_buffer => nb_data_by_buffer, |
|
331 | 332 | nb_snapshot_param => nb_snapshot_param, |
|
332 | 333 | status_new_err => status_new_err, |
|
333 | 334 | |
|
334 | 335 | status_buffer_ready => wfp_status_buffer_ready, |
|
335 | 336 | addr_buffer => wfp_addr_buffer, |
|
336 | 337 | length_buffer => wfp_length_buffer, |
|
337 | 338 | ready_buffer => wfp_ready_buffer, |
|
338 | 339 | buffer_time => wfp_buffer_time, |
|
339 | 340 | error_buffer_full => wfp_error_buffer_full, |
|
340 | 341 | |
|
341 | 342 | coarse_time => coarse_time, |
|
342 | 343 | -- fine_time => fine_time, |
|
343 | 344 | |
|
344 | 345 | --f0 |
|
345 | 346 | data_f0_in_valid => sample_f0_val, |
|
346 | 347 | data_f0_in => sample_f0_data, |
|
347 | 348 | data_f0_time => sample_f0_time, |
|
348 | 349 | --f1 |
|
349 | 350 | data_f1_in_valid => sample_f1_val, |
|
350 | 351 | data_f1_in => sample_f1_data, |
|
351 | 352 | data_f1_time => sample_f1_time, |
|
352 | 353 | --f2 |
|
353 | 354 | data_f2_in_valid => sample_f2_val, |
|
354 | 355 | data_f2_in => sample_f2_data, |
|
355 | 356 | data_f2_time => sample_f2_time, |
|
356 | 357 | --f3 |
|
357 | 358 | data_f3_in_valid => sample_f3_val, |
|
358 | 359 | data_f3_in => sample_f3_data, |
|
359 | 360 | data_f3_time => sample_f3_time, |
|
360 | 361 | -- OUTPUT -- DMA interface |
|
361 | 362 | |
|
362 | 363 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), |
|
363 | 364 | dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0), |
|
364 | 365 | dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0), |
|
365 | 366 | dma_buffer_new => dma_buffer_new(3 DOWNTO 0), |
|
366 | 367 | dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0), |
|
367 | 368 | dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0), |
|
368 | 369 | dma_buffer_full => dma_buffer_full(3 DOWNTO 0), |
|
369 | 370 | dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0) |
|
370 | 371 | |
|
371 | 372 | ); |
|
372 | 373 | |
|
373 | 374 | ----------------------------------------------------------------------------- |
|
374 | 375 | -- Matrix Spectral |
|
375 | 376 | ----------------------------------------------------------------------------- |
|
376 | 377 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
377 | 378 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
378 | 379 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
379 | 380 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
380 | 381 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & |
|
381 | 382 | NOT(sample_f2_val) & NOT(sample_f2_val); |
|
382 | 383 | |
|
383 | 384 | |
|
384 | 385 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
385 | 386 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
386 | 387 | sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); |
|
387 | 388 | |
|
388 | 389 | ----------------------------------------------------------------------------- |
|
389 | 390 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
390 | 391 | GENERIC MAP ( |
|
391 | 392 | Mem_use => Mem_use, |
|
392 | 393 | WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE) |
|
393 | 394 | PORT MAP ( |
|
394 | 395 | clk => clk, |
|
395 | 396 | rstn => rstn, |
|
396 | 397 | |
|
397 | 398 | run => '1',--run_ms, |
|
398 | 399 | |
|
399 | 400 | start_date => start_date, |
|
400 | 401 | |
|
401 | 402 | coarse_time => coarse_time, |
|
402 | 403 | |
|
403 | 404 | sample_f0_wen => sample_f0_wen, |
|
404 | 405 | sample_f0_wdata => sample_f0_wdata, |
|
405 | 406 | sample_f0_time => sample_f0_time, |
|
406 | 407 | sample_f1_wen => sample_f1_wen, |
|
407 | 408 | sample_f1_wdata => sample_f1_wdata, |
|
408 | 409 | sample_f1_time => sample_f1_time, |
|
409 | 410 | sample_f2_wen => sample_f2_wen, |
|
410 | 411 | sample_f2_wdata => sample_f2_wdata, |
|
411 | 412 | sample_f2_time => sample_f2_time, |
|
412 | 413 | |
|
413 | 414 | --DMA |
|
414 | 415 | dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT |
|
415 | 416 | dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT |
|
416 | 417 | dma_fifo_ren => dma_fifo_ren(4), -- IN |
|
417 | 418 | dma_buffer_new => dma_buffer_new(4), -- OUT |
|
418 | 419 | dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT |
|
419 | 420 | dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT |
|
420 | 421 | dma_buffer_full => dma_buffer_full(4), -- IN |
|
421 | 422 | dma_buffer_full_err => dma_buffer_full_err(4), -- IN |
|
422 | 423 | |
|
423 | 424 | |
|
424 | 425 | |
|
425 | 426 | --REG |
|
426 | 427 | ready_matrix_f0 => ready_matrix_f0, |
|
427 | 428 | ready_matrix_f1 => ready_matrix_f1, |
|
428 | 429 | ready_matrix_f2 => ready_matrix_f2, |
|
429 | 430 | error_buffer_full => error_buffer_full, |
|
430 | 431 | error_input_fifo_write => error_input_fifo_write, |
|
431 | 432 | |
|
432 | 433 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
433 | 434 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
434 | 435 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
435 | 436 | addr_matrix_f0 => addr_matrix_f0, |
|
436 | 437 | addr_matrix_f1 => addr_matrix_f1, |
|
437 | 438 | addr_matrix_f2 => addr_matrix_f2, |
|
438 | 439 | |
|
439 | 440 | length_matrix_f0 => length_matrix_f0, |
|
440 | 441 | length_matrix_f1 => length_matrix_f1, |
|
441 | 442 | length_matrix_f2 => length_matrix_f2, |
|
442 | 443 | |
|
443 | 444 | matrix_time_f0 => matrix_time_f0, |
|
444 | 445 | matrix_time_f1 => matrix_time_f1, |
|
445 | 446 | matrix_time_f2 => matrix_time_f2, |
|
446 | 447 | |
|
447 | 448 | debug_vector => debug_vector_ms); |
|
448 | 449 | |
|
449 | 450 | ----------------------------------------------------------------------------- |
|
450 | 451 | PROCESS (clk, rstn) |
|
451 | 452 | BEGIN |
|
452 | 453 | IF rstn = '0' THEN |
|
453 | 454 | dma_fifo_data_forced_gen <= X"00040003"; |
|
454 | 455 | ELSIF clk'event AND clk = '1' THEN |
|
455 | 456 | IF dma_fifo_ren(0) = '0' THEN |
|
456 | 457 | CASE dma_fifo_data_forced_gen IS |
|
457 | 458 | WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002"; |
|
458 | 459 | WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001"; |
|
459 | 460 | WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003"; |
|
460 | 461 | WHEN OTHERS => NULL; |
|
461 | 462 | END CASE; |
|
462 | 463 | END IF; |
|
463 | 464 | END IF; |
|
464 | 465 | END PROCESS; |
|
465 | 466 | |
|
466 | 467 | dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen; |
|
467 | 468 | dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100"; |
|
468 | 469 | dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000"; |
|
469 | 470 | dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000"; |
|
470 | 471 | dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00"; |
|
471 | 472 | |
|
472 | 473 | dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced; |
|
473 | 474 | |
|
474 | 475 | DMA_SubSystem_1 : DMA_SubSystem |
|
475 | 476 | GENERIC MAP ( |
|
476 | 477 | hindex => hindex, |
|
477 | 478 | CUSTOM_DMA => 1) |
|
478 | 479 | PORT MAP ( |
|
479 | 480 | clk => clk, |
|
480 | 481 | rstn => rstn, |
|
481 | 482 | run => '1',--run_dma, |
|
482 | 483 | ahbi => ahbi, |
|
483 | 484 | ahbo => ahbo, |
|
484 | 485 | |
|
485 | 486 | fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid, |
|
486 | 487 | fifo_data => dma_fifo_data_debug, --fifo_data, |
|
487 | 488 | fifo_ren => dma_fifo_ren, --fifo_ren, |
|
488 | 489 | |
|
489 | 490 | buffer_new => dma_buffer_new, --buffer_new, |
|
490 | 491 | buffer_addr => dma_buffer_addr, --buffer_addr, |
|
491 | 492 | buffer_length => dma_buffer_length, --buffer_length, |
|
492 | 493 | buffer_full => dma_buffer_full, --buffer_full, |
|
493 | 494 | buffer_full_err => dma_buffer_full_err, --buffer_full_err, |
|
494 | 495 | grant_error => dma_grant_error, |
|
495 | 496 | debug_vector => debug_vector(8 DOWNTO 0) |
|
496 | 497 | ); --grant_error); |
|
497 | 498 | |
|
498 | 499 | ----------------------------------------------------------------------------- |
|
499 | 500 | -- OBSERVATION for SIMULATION |
|
500 | 501 | all_channel_sim: FOR I IN 0 TO 5 GENERATE |
|
501 | 502 | PROCESS (clk, rstn) |
|
502 | 503 | BEGIN -- PROCESS |
|
503 | 504 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
504 | 505 | sample_f0_data_sim(I) <= (OTHERS => '0'); |
|
505 | 506 | sample_f1_data_sim(I) <= (OTHERS => '0'); |
|
506 | 507 | sample_f2_data_sim(I) <= (OTHERS => '0'); |
|
507 | 508 | sample_f3_data_sim(I) <= (OTHERS => '0'); |
|
508 | 509 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
509 | 510 | IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF; |
|
510 | 511 | IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF; |
|
511 | 512 | IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF; |
|
512 | 513 | IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF; |
|
513 | 514 | END IF; |
|
514 | 515 | END PROCESS; |
|
515 | 516 | END GENERATE all_channel_sim; |
|
516 | 517 | ----------------------------------------------------------------------------- |
|
517 | 518 | |
|
518 | 519 | END beh; |
@@ -1,666 +1,667 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE ieee.numeric_std.ALL; |
|
26 | 26 | |
|
27 | 27 | LIBRARY lpp; |
|
28 | 28 | USE lpp.lpp_ad_conv.ALL; |
|
29 | 29 | USE lpp.iir_filter.ALL; |
|
30 | 30 | USE lpp.FILTERcfg.ALL; |
|
31 | 31 | USE lpp.lpp_memory.ALL; |
|
32 | 32 | USE lpp.lpp_waveform_pkg.ALL; |
|
33 | 33 | USE lpp.cic_pkg.ALL; |
|
34 | 34 | USE lpp.data_type_pkg.ALL; |
|
35 | 35 | USE lpp.lpp_lfr_filter_coeff.ALL; |
|
36 | 36 | |
|
37 | 37 | LIBRARY techmap; |
|
38 | 38 | USE techmap.gencomp.ALL; |
|
39 | 39 | |
|
40 | 40 | LIBRARY grlib; |
|
41 | 41 | USE grlib.amba.ALL; |
|
42 | 42 | USE grlib.stdlib.ALL; |
|
43 | 43 | USE grlib.devices.ALL; |
|
44 | 44 | USE GRLIB.DMA2AHB_Package.ALL; |
|
45 | 45 | |
|
46 | 46 | ENTITY lpp_lfr_filter IS |
|
47 | 47 | GENERIC( |
|
48 | tech : INTEGER := 0; | |
|
48 | 49 | Mem_use : INTEGER := use_RAM; |
|
49 | 50 | RTL_DESIGN_LIGHT : INTEGER := 0 |
|
50 | 51 | ); |
|
51 | 52 | PORT ( |
|
52 | 53 | sample : IN Samples(7 DOWNTO 0); |
|
53 | 54 | sample_val : IN STD_LOGIC; |
|
54 | 55 | sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
55 | 56 | -- |
|
56 | 57 | clk : IN STD_LOGIC; |
|
57 | 58 | rstn : IN STD_LOGIC; |
|
58 | 59 | -- |
|
59 | 60 | data_shaping_SP0 : IN STD_LOGIC; |
|
60 | 61 | data_shaping_SP1 : IN STD_LOGIC; |
|
61 | 62 | data_shaping_R0 : IN STD_LOGIC; |
|
62 | 63 | data_shaping_R1 : IN STD_LOGIC; |
|
63 | 64 | data_shaping_R2 : IN STD_LOGIC; |
|
64 | 65 | -- |
|
65 | 66 | sample_f0_val : OUT STD_LOGIC; |
|
66 | 67 | sample_f1_val : OUT STD_LOGIC; |
|
67 | 68 | sample_f2_val : OUT STD_LOGIC; |
|
68 | 69 | sample_f3_val : OUT STD_LOGIC; |
|
69 | 70 | -- |
|
70 | 71 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
71 | 72 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
72 | 73 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
73 | 74 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
74 | 75 | -- |
|
75 | 76 | sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
76 | 77 | sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
77 | 78 | sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
78 | 79 | sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
79 | 80 | ); |
|
80 | 81 | END lpp_lfr_filter; |
|
81 | 82 | |
|
82 | 83 | ARCHITECTURE tb OF lpp_lfr_filter IS |
|
83 | 84 | |
|
84 | 85 | COMPONENT Downsampling |
|
85 | 86 | GENERIC ( |
|
86 | 87 | ChanelCount : INTEGER; |
|
87 | 88 | SampleSize : INTEGER; |
|
88 | 89 | DivideParam : INTEGER); |
|
89 | 90 | PORT ( |
|
90 | 91 | clk : IN STD_LOGIC; |
|
91 | 92 | rstn : IN STD_LOGIC; |
|
92 | 93 | sample_in_val : IN STD_LOGIC; |
|
93 | 94 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
94 | 95 | sample_out_val : OUT STD_LOGIC; |
|
95 | 96 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
96 | 97 | END COMPONENT; |
|
97 | 98 | |
|
98 | 99 | ----------------------------------------------------------------------------- |
|
99 | 100 | CONSTANT ChanelCount : INTEGER := 8; |
|
100 | 101 | |
|
101 | 102 | ----------------------------------------------------------------------------- |
|
102 | 103 | SIGNAL sample_val_delay : STD_LOGIC; |
|
103 | 104 | ----------------------------------------------------------------------------- |
|
104 | 105 | CONSTANT Coef_SZ : INTEGER := 9; |
|
105 | 106 | CONSTANT CoefCntPerCel : INTEGER := 6; |
|
106 | 107 | CONSTANT CoefPerCel : INTEGER := 5; |
|
107 | 108 | CONSTANT Cels_count : INTEGER := 5; |
|
108 | 109 | |
|
109 | 110 | --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); |
|
110 | 111 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
111 | 112 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
112 | 113 | --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
113 | 114 | -- |
|
114 | 115 | SIGNAL sample_filter_v2_out_sim : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
115 | 116 | |
|
116 | 117 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
117 | 118 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
118 | 119 | ----------------------------------------------------------------------------- |
|
119 | 120 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; |
|
120 | 121 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
121 | 122 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
122 | 123 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
123 | 124 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
124 | 125 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
125 | 126 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
126 | 127 | ----------------------------------------------------------------------------- |
|
127 | 128 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; |
|
128 | 129 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
129 | 130 | ----------------------------------------------------------------------------- |
|
130 | 131 | -- SIGNAL sample_f0_val : STD_LOGIC; |
|
131 | 132 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
132 | 133 | SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0); |
|
133 | 134 | -- |
|
134 | 135 | -- SIGNAL sample_f1_val : STD_LOGIC; |
|
135 | 136 | |
|
136 | 137 | SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
137 | 138 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
138 | 139 | SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
139 | 140 | -- |
|
140 | 141 | -- SIGNAL sample_f2_val : STD_LOGIC; |
|
141 | 142 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
142 | 143 | SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
143 | 144 | SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
144 | 145 | SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
145 | 146 | SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
146 | 147 | SIGNAL sample_f2_cic_val : STD_LOGIC; |
|
147 | 148 | SIGNAL sample_f2_filter_val : STD_LOGIC; |
|
148 | 149 | |
|
149 | 150 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
150 | 151 | SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
151 | 152 | SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
152 | 153 | SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0); |
|
153 | 154 | SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0); |
|
154 | 155 | SIGNAL sample_f3_cic_val : STD_LOGIC; |
|
155 | 156 | SIGNAL sample_f3_filter_val : STD_LOGIC; |
|
156 | 157 | |
|
157 | 158 | ----------------------------------------------------------------------------- |
|
158 | 159 | --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
159 | 160 | --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
160 | 161 | --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
161 | 162 | --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
162 | 163 | ----------------------------------------------------------------------------- |
|
163 | 164 | |
|
164 | 165 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
165 | 166 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
166 | 167 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
167 | 168 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
168 | 169 | |
|
169 | 170 | SIGNAL sample_f0_val_s : STD_LOGIC; |
|
170 | 171 | SIGNAL sample_f1_val_s : STD_LOGIC; |
|
171 | 172 | SIGNAL sample_f1_val_ss : STD_LOGIC; |
|
172 | 173 | SIGNAL sample_f2_val_s : STD_LOGIC; |
|
173 | 174 | SIGNAL sample_f3_val_s : STD_LOGIC; |
|
174 | 175 | |
|
175 | 176 | ----------------------------------------------------------------------------- |
|
176 | 177 | -- CONFIG FILTER IIR f0 to f1 |
|
177 | 178 | ----------------------------------------------------------------------------- |
|
178 | 179 | CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5; |
|
179 | 180 | CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10; |
|
180 | 181 | CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8; |
|
181 | 182 | |
|
182 | 183 | CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := |
|
183 | 184 | ( |
|
184 | 185 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), |
|
185 | 186 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), |
|
186 | 187 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), |
|
187 | 188 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), |
|
188 | 189 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) |
|
189 | 190 | ); |
|
190 | 191 | CONSTANT f0_to_f1_gain : COEFF_CEL_REAL := |
|
191 | 192 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); |
|
192 | 193 | |
|
193 | 194 | CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0) |
|
194 | 195 | := get_IIR_CEL_FILTER_CONFIG( |
|
195 | 196 | f0_to_f1_COEFFICIENT_SIZE, |
|
196 | 197 | f0_to_f1_POINT_POSITION, |
|
197 | 198 | f0_to_f1_CEL_NUMBER, |
|
198 | 199 | f0_to_f1_sos, |
|
199 | 200 | f0_to_f1_gain); |
|
200 | 201 | ----------------------------------------------------------------------------- |
|
201 | 202 | |
|
202 | 203 | ----------------------------------------------------------------------------- |
|
203 | 204 | -- CONFIG FILTER IIR f2 and f3 |
|
204 | 205 | ----------------------------------------------------------------------------- |
|
205 | 206 | CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5; |
|
206 | 207 | CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10; |
|
207 | 208 | CONSTANT f2_f3_POINT_POSITION : INTEGER := 8; |
|
208 | 209 | |
|
209 | 210 | CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := |
|
210 | 211 | ( |
|
211 | 212 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), |
|
212 | 213 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), |
|
213 | 214 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), |
|
214 | 215 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), |
|
215 | 216 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) |
|
216 | 217 | ); |
|
217 | 218 | CONSTANT f2_f3_gain : COEFF_CEL_REAL := |
|
218 | 219 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); |
|
219 | 220 | |
|
220 | 221 | CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0) |
|
221 | 222 | := get_IIR_CEL_FILTER_CONFIG( |
|
222 | 223 | f2_f3_COEFFICIENT_SIZE, |
|
223 | 224 | f2_f3_POINT_POSITION, |
|
224 | 225 | f2_f3_CEL_NUMBER, |
|
225 | 226 | f2_f3_sos, |
|
226 | 227 | f2_f3_gain); |
|
227 | 228 | ----------------------------------------------------------------------------- |
|
228 | 229 | |
|
229 | 230 | SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
230 | 231 | SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
231 | 232 | SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
232 | 233 | SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
233 | 234 | SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
234 | 235 | SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
235 | 236 | SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
236 | 237 | -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
237 | 238 | -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
238 | 239 | SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
239 | 240 | |
|
240 | 241 | BEGIN |
|
241 | 242 | |
|
242 | 243 | ----------------------------------------------------------------------------- |
|
243 | 244 | PROCESS (clk, rstn) |
|
244 | 245 | BEGIN -- PROCESS |
|
245 | 246 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
246 | 247 | sample_val_delay <= '0'; |
|
247 | 248 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
248 | 249 | sample_val_delay <= sample_val; |
|
249 | 250 | END IF; |
|
250 | 251 | END PROCESS; |
|
251 | 252 | |
|
252 | 253 | ----------------------------------------------------------------------------- |
|
253 | 254 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
254 | 255 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
255 | 256 | sample_filter_in(i, j) <= sample(i)(j); |
|
256 | 257 | END GENERATE; |
|
257 | 258 | |
|
258 | 259 | sample_filter_in(i, 16) <= sample(i)(15); |
|
259 | 260 | sample_filter_in(i, 17) <= sample(i)(15); |
|
260 | 261 | END GENERATE; |
|
261 | 262 | |
|
262 | 263 | coefs_v2 <= CoefsInitValCst_v2; |
|
263 | 264 | |
|
264 | 265 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
265 | 266 | GENERIC MAP ( |
|
266 |
tech => |
|
|
267 | tech => tech, | |
|
267 | 268 | Mem_use => Mem_use, -- use_RAM |
|
268 | 269 | Sample_SZ => 18, |
|
269 | 270 | Coef_SZ => Coef_SZ, |
|
270 | 271 | Coef_Nb => 25, |
|
271 | 272 | Coef_sel_SZ => 5, |
|
272 | 273 | Cels_count => Cels_count, |
|
273 | 274 | ChanelsCount => ChanelCount) |
|
274 | 275 | PORT MAP ( |
|
275 | 276 | rstn => rstn, |
|
276 | 277 | clk => clk, |
|
277 | 278 | virg_pos => 7, |
|
278 | 279 | coefs => coefs_v2, |
|
279 | 280 | sample_in_val => sample_val_delay, |
|
280 | 281 | sample_in => sample_filter_in, |
|
281 | 282 | sample_out_val => sample_filter_v2_out_val, |
|
282 | 283 | sample_out => sample_filter_v2_out); |
|
283 | 284 | |
|
284 | 285 | -- TIME -- |
|
285 | 286 | PROCESS (clk, rstn) |
|
286 | 287 | BEGIN -- PROCESS |
|
287 | 288 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
288 | 289 | sample_time_reg <= (OTHERS => '0'); |
|
289 | 290 | sample_filter_v2_out_time <= (OTHERS => '0'); |
|
290 | 291 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
291 | 292 | IF sample_val = '1' THEN |
|
292 | 293 | sample_time_reg <= sample_time; |
|
293 | 294 | END IF; |
|
294 | 295 | IF sample_filter_v2_out_val = '1' THEN |
|
295 | 296 | sample_filter_v2_out_time <= sample_time_reg; |
|
296 | 297 | END IF; |
|
297 | 298 | END IF; |
|
298 | 299 | END PROCESS; |
|
299 | 300 | ---------- |
|
300 | 301 | |
|
301 | 302 | --for simulation/observation------------------------------------------------- |
|
302 | 303 | ALL_channel_f0_sim: FOR I IN 0 TO ChanelCount-1 GENERATE |
|
303 | 304 | all_bit: FOR J IN 0 TO 17 GENERATE |
|
304 | 305 | PROCESS (clk, rstn) |
|
305 | 306 | BEGIN -- PROCESS |
|
306 | 307 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
307 | 308 | sample_filter_v2_out_sim(I,J) <= '0'; |
|
308 | 309 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
309 | 310 | IF sample_filter_v2_out_val = '1' THEN |
|
310 | 311 | sample_filter_v2_out_sim(I,J) <= sample_filter_v2_out(I,J); |
|
311 | 312 | END IF; |
|
312 | 313 | END IF; |
|
313 | 314 | END PROCESS; |
|
314 | 315 | END GENERATE all_bit; |
|
315 | 316 | END GENERATE ALL_channel_f0_sim; |
|
316 | 317 | ----------------------------------------------------------------------------- |
|
317 | 318 | |
|
318 | 319 | |
|
319 | 320 | ----------------------------------------------------------------------------- |
|
320 | 321 | -- DATA_SHAPING |
|
321 | 322 | ----------------------------------------------------------------------------- |
|
322 | 323 | all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE |
|
323 | 324 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I); |
|
324 | 325 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I); |
|
325 | 326 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I); |
|
326 | 327 | END GENERATE all_data_shaping_in_loop; |
|
327 | 328 | |
|
328 | 329 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; |
|
329 | 330 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; |
|
330 | 331 | |
|
331 | 332 | PROCESS (clk, rstn) |
|
332 | 333 | BEGIN -- PROCESS |
|
333 | 334 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
334 | 335 | sample_data_shaping_out_val <= '0'; |
|
335 | 336 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
336 | 337 | sample_data_shaping_out_val <= sample_filter_v2_out_val; |
|
337 | 338 | END IF; |
|
338 | 339 | END PROCESS; |
|
339 | 340 | |
|
340 | 341 | SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE |
|
341 | 342 | PROCESS (clk, rstn) |
|
342 | 343 | BEGIN |
|
343 | 344 | IF rstn = '0' THEN |
|
344 | 345 | sample_data_shaping_out(0, j) <= '0'; |
|
345 | 346 | sample_data_shaping_out(1, j) <= '0'; |
|
346 | 347 | sample_data_shaping_out(2, j) <= '0'; |
|
347 | 348 | sample_data_shaping_out(3, j) <= '0'; |
|
348 | 349 | sample_data_shaping_out(4, j) <= '0'; |
|
349 | 350 | sample_data_shaping_out(5, j) <= '0'; |
|
350 | 351 | sample_data_shaping_out(6, j) <= '0'; |
|
351 | 352 | sample_data_shaping_out(7, j) <= '0'; |
|
352 | 353 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
353 | 354 | sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j); |
|
354 | 355 | IF data_shaping_SP0 = '1' THEN |
|
355 | 356 | sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j); |
|
356 | 357 | ELSE |
|
357 | 358 | sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j); |
|
358 | 359 | END IF; |
|
359 | 360 | IF data_shaping_SP1 = '1' THEN |
|
360 | 361 | sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j); |
|
361 | 362 | ELSE |
|
362 | 363 | sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j); |
|
363 | 364 | END IF; |
|
364 | 365 | sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j); |
|
365 | 366 | sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j); |
|
366 | 367 | sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j); |
|
367 | 368 | sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j); |
|
368 | 369 | sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j); |
|
369 | 370 | END IF; |
|
370 | 371 | END PROCESS; |
|
371 | 372 | END GENERATE; |
|
372 | 373 | |
|
373 | 374 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; |
|
374 | 375 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE |
|
375 | 376 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE |
|
376 | 377 | sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j); |
|
377 | 378 | END GENERATE; |
|
378 | 379 | END GENERATE; |
|
379 | 380 | ----------------------------------------------------------------------------- |
|
380 | 381 | -- F0 -- @24.576 kHz |
|
381 | 382 | ----------------------------------------------------------------------------- |
|
382 | 383 | |
|
383 | 384 | Downsampling_f0 : Downsampling |
|
384 | 385 | GENERIC MAP ( |
|
385 | 386 | ChanelCount => 8, |
|
386 | 387 | SampleSize => 16, |
|
387 | 388 | DivideParam => 4) |
|
388 | 389 | PORT MAP ( |
|
389 | 390 | clk => clk, |
|
390 | 391 | rstn => rstn, |
|
391 | 392 | sample_in_val => sample_filter_v2_out_val_s, |
|
392 | 393 | sample_in => sample_filter_v2_out_s, |
|
393 | 394 | sample_out_val => sample_f0_val_s, |
|
394 | 395 | sample_out => sample_f0); |
|
395 | 396 | |
|
396 | 397 | -- TIME -- |
|
397 | 398 | PROCESS (clk, rstn) |
|
398 | 399 | BEGIN |
|
399 | 400 | IF rstn = '0' THEN |
|
400 | 401 | sample_f0_time_reg <= (OTHERS => '0'); |
|
401 | 402 | ELSIF clk'event AND clk = '1' THEN |
|
402 | 403 | IF sample_f0_val_s = '1' THEN |
|
403 | 404 | sample_f0_time_reg <= sample_filter_v2_out_time; |
|
404 | 405 | END IF; |
|
405 | 406 | END IF; |
|
406 | 407 | END PROCESS; |
|
407 | 408 | sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg; |
|
408 | 409 | sample_f0_time <= sample_f0_time_s; |
|
409 | 410 | ---------- |
|
410 | 411 | |
|
411 | 412 | sample_f0_val <= sample_f0_val_s; |
|
412 | 413 | |
|
413 | 414 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
414 | 415 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V |
|
415 | 416 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 |
|
416 | 417 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 |
|
417 | 418 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 |
|
418 | 419 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 |
|
419 | 420 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 |
|
420 | 421 | END GENERATE all_bit_sample_f0; |
|
421 | 422 | |
|
422 | 423 | ----------------------------------------------------------------------------- |
|
423 | 424 | -- F1 -- @4096 Hz |
|
424 | 425 | ----------------------------------------------------------------------------- |
|
425 | 426 | |
|
426 | 427 | all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
427 | 428 | sample_f0_f1_s(0,I) <= sample_f0(0,I); --V |
|
428 | 429 | sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1 |
|
429 | 430 | sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2 |
|
430 | 431 | sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1 |
|
431 | 432 | sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2 |
|
432 | 433 | sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3 |
|
433 | 434 | END GENERATE all_bit_sample_f0_f1; |
|
434 | 435 | all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE |
|
435 | 436 | sample_f0_f1_s(0,I) <= sample_f0(0,15); |
|
436 | 437 | sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1 |
|
437 | 438 | sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2 |
|
438 | 439 | sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1 |
|
439 | 440 | sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2 |
|
440 | 441 | sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3 |
|
441 | 442 | END GENERATE all_bit_sample_f0_f1_extended; |
|
442 | 443 | |
|
443 | 444 | |
|
444 | 445 | IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2 |
|
445 | 446 | GENERIC MAP ( |
|
446 |
tech => |
|
|
447 | tech => tech, | |
|
447 | 448 | Mem_use => Mem_use, -- use_RAM |
|
448 | 449 | Sample_SZ => 18, |
|
449 | 450 | Coef_SZ => f0_to_f1_COEFFICIENT_SIZE, |
|
450 | 451 | Coef_Nb => f0_to_f1_CEL_NUMBER*5, |
|
451 | 452 | Coef_sel_SZ => 5, |
|
452 | 453 | Cels_count => f0_to_f1_CEL_NUMBER, |
|
453 | 454 | ChanelsCount => 6) |
|
454 | 455 | PORT MAP ( |
|
455 | 456 | rstn => rstn, |
|
456 | 457 | clk => clk, |
|
457 | 458 | virg_pos => f0_to_f1_POINT_POSITION, |
|
458 | 459 | coefs => coefs_iir_cel_f0_to_f1, |
|
459 | 460 | |
|
460 | 461 | sample_in_val => sample_f0_val_s, |
|
461 | 462 | sample_in => sample_f0_f1_s, |
|
462 | 463 | |
|
463 | 464 | sample_out_val => sample_f1_val_s, |
|
464 | 465 | sample_out => sample_f1_s); |
|
465 | 466 | |
|
466 | 467 | Downsampling_f1 : Downsampling |
|
467 | 468 | GENERIC MAP ( |
|
468 | 469 | ChanelCount => 6, |
|
469 | 470 | SampleSize => 18, |
|
470 | 471 | DivideParam => 6) |
|
471 | 472 | PORT MAP ( |
|
472 | 473 | clk => clk, |
|
473 | 474 | rstn => rstn, |
|
474 | 475 | sample_in_val => sample_f1_val_s, |
|
475 | 476 | sample_in => sample_f1_s, |
|
476 | 477 | sample_out_val => sample_f1_val_ss, |
|
477 | 478 | sample_out => sample_f1); |
|
478 | 479 | |
|
479 | 480 | sample_f1_val <= sample_f1_val_ss; |
|
480 | 481 | |
|
481 | 482 | -- TIME -- |
|
482 | 483 | PROCESS (clk, rstn) |
|
483 | 484 | BEGIN |
|
484 | 485 | IF rstn = '0' THEN |
|
485 | 486 | sample_f1_time_reg <= (OTHERS => '0'); |
|
486 | 487 | ELSIF clk'event AND clk = '1' THEN |
|
487 | 488 | IF sample_f1_val_ss = '1' THEN |
|
488 | 489 | sample_f1_time_reg <= sample_f0_time_s; |
|
489 | 490 | END IF; |
|
490 | 491 | END IF; |
|
491 | 492 | END PROCESS; |
|
492 | 493 | sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg; |
|
493 | 494 | sample_f1_time <= sample_f1_time_s; |
|
494 | 495 | ---------- |
|
495 | 496 | |
|
496 | 497 | |
|
497 | 498 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
498 | 499 | all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE |
|
499 | 500 | sample_f1_wdata_s(16*J+I) <= sample_f1(J, I); |
|
500 | 501 | END GENERATE all_channel_sample_f1; |
|
501 | 502 | END GENERATE all_bit_sample_f1; |
|
502 | 503 | |
|
503 | 504 | ----------------------------------------------------------------------------- |
|
504 | 505 | -- F2 -- @256 Hz |
|
505 | 506 | -- F3 -- @16 Hz |
|
506 | 507 | ----------------------------------------------------------------------------- |
|
507 | 508 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE |
|
508 | 509 | sample_f0_s(0, I) <= sample_f0(0, I); -- V |
|
509 | 510 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 |
|
510 | 511 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 |
|
511 | 512 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 |
|
512 | 513 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 |
|
513 | 514 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 |
|
514 | 515 | sample_f0_s(6, I) <= sample_f0(3, I); -- |
|
515 | 516 | sample_f0_s(7, I) <= sample_f0(4, I); -- |
|
516 | 517 | END GENERATE all_bit_sample_f0_s; |
|
517 | 518 | |
|
518 | 519 | |
|
519 | 520 | cic_lfr_1: cic_lfr_r2 |
|
520 | 521 | GENERIC MAP ( |
|
521 |
tech => |
|
|
522 | tech => tech, | |
|
522 | 523 | use_RAM_nCEL => Mem_use) |
|
523 | 524 | PORT MAP ( |
|
524 | 525 | clk => clk, |
|
525 | 526 | rstn => rstn, |
|
526 | 527 | run => '1', |
|
527 | 528 | |
|
528 | 529 | param_r2 => data_shaping_R2, |
|
529 | 530 | |
|
530 | 531 | data_in => sample_f0_s, |
|
531 | 532 | data_in_valid => sample_f0_val_s, |
|
532 | 533 | |
|
533 | 534 | data_out_16 => sample_f2_cic, |
|
534 | 535 | data_out_16_valid => sample_f2_cic_val, |
|
535 | 536 | |
|
536 | 537 | data_out_256 => sample_f3_cic, |
|
537 | 538 | data_out_256_valid => sample_f3_cic_val); |
|
538 | 539 | |
|
539 | 540 | |
|
540 | 541 | |
|
541 | 542 | all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE |
|
542 | 543 | all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE |
|
543 | 544 | sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I); |
|
544 | 545 | sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I); |
|
545 | 546 | END GENERATE all_bit_sample_f_cic; |
|
546 | 547 | sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15); |
|
547 | 548 | sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15); |
|
548 | 549 | |
|
549 | 550 | sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15); |
|
550 | 551 | sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15); |
|
551 | 552 | END GENERATE all_channel_sample_f_cic; |
|
552 | 553 | |
|
553 | 554 | NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE |
|
554 | 555 | sample_f2_filter_val <= sample_f2_cic_val; |
|
555 | 556 | sample_f2_filter <= sample_f2_cic_filter; |
|
556 | 557 | sample_f3_filter_val <= sample_f3_cic_val; |
|
557 | 558 | sample_f3_filter <= sample_f3_cic_filter; |
|
558 | 559 | END GENERATE NO_IIR_FILTER_f2_f3; |
|
559 | 560 | |
|
560 | 561 | YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE |
|
561 | 562 | IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3 |
|
562 | 563 | GENERIC MAP ( |
|
563 |
tech => |
|
|
564 | tech => tech, | |
|
564 | 565 | Mem_use => Mem_use, |
|
565 | 566 | Sample_SZ => 18, |
|
566 | 567 | Coef_SZ => f2_f3_COEFFICIENT_SIZE, |
|
567 | 568 | Coef_Nb => f2_f3_CEL_NUMBER*5, |
|
568 | 569 | Coef_sel_SZ => 5, |
|
569 | 570 | Cels_count => f2_f3_CEL_NUMBER, |
|
570 | 571 | ChanelsCount => 6) |
|
571 | 572 | PORT MAP ( |
|
572 | 573 | rstn => rstn, |
|
573 | 574 | clk => clk, |
|
574 | 575 | virg_pos => f2_f3_POINT_POSITION, |
|
575 | 576 | coefs => coefs_iir_cel_f2_f3, |
|
576 | 577 | |
|
577 | 578 | sample_in1_val => sample_f2_cic_val, |
|
578 | 579 | sample_in1 => sample_f2_cic_filter, |
|
579 | 580 | |
|
580 | 581 | sample_in2_val => sample_f3_cic_val, |
|
581 | 582 | sample_in2 => sample_f3_cic_filter, |
|
582 | 583 | |
|
583 | 584 | sample_out1_val => sample_f2_filter_val, |
|
584 | 585 | sample_out1 => sample_f2_filter, |
|
585 | 586 | sample_out2_val => sample_f3_filter_val, |
|
586 | 587 | sample_out2 => sample_f3_filter); |
|
587 | 588 | END GENERATE YES_IIR_FILTER_f2_f3; |
|
588 | 589 | |
|
589 | 590 | all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE |
|
590 | 591 | all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE |
|
591 | 592 | sample_f2_cic_s(J,I) <= sample_f2_filter(J,I); |
|
592 | 593 | sample_f3_cic_s(J,I) <= sample_f3_filter(J,I); |
|
593 | 594 | END GENERATE all_bit_sample_f_filter; |
|
594 | 595 | END GENERATE all_channel_sample_f_filter; |
|
595 | 596 | |
|
596 | 597 | ----------------------------------------------------------------------------- |
|
597 | 598 | |
|
598 | 599 | Downsampling_f2 : Downsampling |
|
599 | 600 | GENERIC MAP ( |
|
600 | 601 | ChanelCount => 6, |
|
601 | 602 | SampleSize => 16, |
|
602 | 603 | DivideParam => 6) |
|
603 | 604 | PORT MAP ( |
|
604 | 605 | clk => clk, |
|
605 | 606 | rstn => rstn, |
|
606 | 607 | sample_in_val => sample_f2_filter_val , |
|
607 | 608 | sample_in => sample_f2_cic_s, |
|
608 | 609 | sample_out_val => sample_f2_val_s, |
|
609 | 610 | sample_out => sample_f2); |
|
610 | 611 | |
|
611 | 612 | sample_f2_val <= sample_f2_val_s; |
|
612 | 613 | |
|
613 | 614 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
614 | 615 | all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE |
|
615 | 616 | sample_f2_wdata_s(16*J+I) <= sample_f2(J,I); |
|
616 | 617 | END GENERATE all_channel_sample_f2; |
|
617 | 618 | END GENERATE all_bit_sample_f2; |
|
618 | 619 | |
|
619 | 620 | ----------------------------------------------------------------------------- |
|
620 | 621 | |
|
621 | 622 | Downsampling_f3 : Downsampling |
|
622 | 623 | GENERIC MAP ( |
|
623 | 624 | ChanelCount => 6, |
|
624 | 625 | SampleSize => 16, |
|
625 | 626 | DivideParam => 6) |
|
626 | 627 | PORT MAP ( |
|
627 | 628 | clk => clk, |
|
628 | 629 | rstn => rstn, |
|
629 | 630 | sample_in_val => sample_f3_filter_val , |
|
630 | 631 | sample_in => sample_f3_cic_s, |
|
631 | 632 | sample_out_val => sample_f3_val_s, |
|
632 | 633 | sample_out => sample_f3); |
|
633 | 634 | sample_f3_val <= sample_f3_val_s; |
|
634 | 635 | |
|
635 | 636 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
636 | 637 | all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE |
|
637 | 638 | sample_f3_wdata_s(16*J+I) <= sample_f3(J,I); |
|
638 | 639 | END GENERATE all_channel_sample_f3; |
|
639 | 640 | END GENERATE all_bit_sample_f3; |
|
640 | 641 | |
|
641 | 642 | ----------------------------------------------------------------------------- |
|
642 | 643 | |
|
643 | 644 | -- TIME -- |
|
644 | 645 | PROCESS (clk, rstn) |
|
645 | 646 | BEGIN |
|
646 | 647 | IF rstn = '0' THEN |
|
647 | 648 | sample_f2_time_reg <= (OTHERS => '0'); |
|
648 | 649 | sample_f3_time_reg <= (OTHERS => '0'); |
|
649 | 650 | ELSIF clk'event AND clk = '1' THEN |
|
650 | 651 | IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF; |
|
651 | 652 | IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF; |
|
652 | 653 | END IF; |
|
653 | 654 | END PROCESS; |
|
654 | 655 | sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg; |
|
655 | 656 | sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg; |
|
656 | 657 | ---------- |
|
657 | 658 | |
|
658 | 659 | ----------------------------------------------------------------------------- |
|
659 | 660 | -- |
|
660 | 661 | ----------------------------------------------------------------------------- |
|
661 | 662 | sample_f0_wdata <= sample_f0_wdata_s; |
|
662 | 663 | sample_f1_wdata <= sample_f1_wdata_s; |
|
663 | 664 | sample_f2_wdata <= sample_f2_wdata_s; |
|
664 | 665 | sample_f3_wdata <= sample_f3_wdata_s; |
|
665 | 666 | |
|
666 | 667 | END tb; |
@@ -1,412 +1,413 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY grlib; |
|
5 | 5 | USE grlib.amba.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
12 | 12 | LIBRARY techmap; |
|
13 | 13 | USE techmap.gencomp.ALL; |
|
14 | 14 | |
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
16 | 16 | ----------------------------------------------------------------------------- |
|
17 | 17 | -- TEMP |
|
18 | 18 | ----------------------------------------------------------------------------- |
|
19 | 19 | COMPONENT lpp_lfr_ms_test |
|
20 | 20 | GENERIC ( |
|
21 | 21 | Mem_use : INTEGER); |
|
22 | 22 | PORT ( |
|
23 | 23 | clk : IN STD_LOGIC; |
|
24 | 24 | rstn : IN STD_LOGIC; |
|
25 | 25 | |
|
26 | 26 | -- TIME |
|
27 | 27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
28 | 28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
29 | 29 | -- |
|
30 | 30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
31 | 31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
32 | 32 | -- |
|
33 | 33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | 34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
35 | 35 | -- |
|
36 | 36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | 37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
38 | 38 | |
|
39 | 39 | |
|
40 | 40 | |
|
41 | 41 | --------------------------------------------------------------------------- |
|
42 | 42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
43 | 43 | |
|
44 | 44 | -- |
|
45 | 45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | 46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | 47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
48 | 48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
49 | 49 | |
|
50 | 50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- IN |
|
53 | 53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | 54 | |
|
55 | 55 | ----------------------------------------------------------------------------- |
|
56 | 56 | |
|
57 | 57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
58 | 58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
59 | 59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | 60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
61 | 61 | |
|
62 | 62 | SM_correlation_start : OUT STD_LOGIC; |
|
63 | 63 | SM_correlation_auto : OUT STD_LOGIC; |
|
64 | 64 | SM_correlation_done : IN STD_LOGIC |
|
65 | 65 | ); |
|
66 | 66 | END COMPONENT; |
|
67 | 67 | |
|
68 | 68 | |
|
69 | 69 | ----------------------------------------------------------------------------- |
|
70 | 70 | COMPONENT lpp_lfr_ms |
|
71 | 71 | GENERIC ( |
|
72 | 72 | Mem_use : INTEGER; |
|
73 | 73 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER); |
|
74 | 74 | PORT ( |
|
75 | 75 | clk : IN STD_LOGIC; |
|
76 | 76 | rstn : IN STD_LOGIC; |
|
77 | 77 | run : IN STD_LOGIC; |
|
78 | 78 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
79 | 79 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | 80 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | 81 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | 82 | sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
83 | 83 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | 84 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | 85 | sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
86 | 86 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | 87 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | 88 | sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | 89 | dma_fifo_burst_valid : OUT STD_LOGIC; |
|
90 | 90 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 91 | dma_fifo_ren : IN STD_LOGIC; |
|
92 | 92 | dma_buffer_new : OUT STD_LOGIC; |
|
93 | 93 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
94 | 94 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
95 | 95 | dma_buffer_full : IN STD_LOGIC; |
|
96 | 96 | dma_buffer_full_err : IN STD_LOGIC; |
|
97 | 97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
98 | 98 | ready_matrix_f1 : OUT STD_LOGIC; |
|
99 | 99 | ready_matrix_f2 : OUT STD_LOGIC; |
|
100 | 100 | error_buffer_full : OUT STD_LOGIC; |
|
101 | 101 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
102 | 102 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
103 | 103 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
104 | 104 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
105 | 105 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | 106 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | 107 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | 108 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
109 | 109 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
110 | 110 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
111 | 111 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
112 | 112 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
113 | 113 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
114 | 114 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
|
115 | 115 | END COMPONENT; |
|
116 | 116 | |
|
117 | 117 | COMPONENT lpp_lfr_ms_fsmdma |
|
118 | 118 | PORT ( |
|
119 | 119 | clk : IN STD_ULOGIC; |
|
120 | 120 | rstn : IN STD_ULOGIC; |
|
121 | 121 | run : IN STD_LOGIC; |
|
122 | 122 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
123 | 123 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
124 | 124 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
125 | 125 | fifo_empty : IN STD_LOGIC; |
|
126 | 126 | fifo_empty_threshold : IN STD_LOGIC; |
|
127 | 127 | fifo_ren : OUT STD_LOGIC; |
|
128 | 128 | dma_fifo_valid_burst : OUT STD_LOGIC; |
|
129 | 129 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | 130 | dma_fifo_ren : IN STD_LOGIC; |
|
131 | 131 | dma_buffer_new : OUT STD_LOGIC; |
|
132 | 132 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 133 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
134 | 134 | dma_buffer_full : IN STD_LOGIC; |
|
135 | 135 | dma_buffer_full_err : IN STD_LOGIC; |
|
136 | 136 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
137 | 137 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
138 | 138 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
139 | 139 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | 140 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
141 | 141 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | 142 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
143 | 143 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
144 | 144 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
145 | 145 | ready_matrix_f0 : OUT STD_LOGIC; |
|
146 | 146 | ready_matrix_f1 : OUT STD_LOGIC; |
|
147 | 147 | ready_matrix_f2 : OUT STD_LOGIC; |
|
148 | 148 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
149 | 149 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
150 | 150 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
151 | 151 | error_buffer_full : OUT STD_LOGIC); |
|
152 | 152 | END COMPONENT; |
|
153 | 153 | |
|
154 | 154 | COMPONENT lpp_lfr_ms_FFT |
|
155 | 155 | GENERIC ( |
|
156 | 156 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER); |
|
157 | 157 | PORT ( |
|
158 | 158 | clk : IN STD_LOGIC; |
|
159 | 159 | rstn : IN STD_LOGIC; |
|
160 | 160 | sample_valid : IN STD_LOGIC; |
|
161 | 161 | fft_read : IN STD_LOGIC; |
|
162 | 162 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
163 | 163 | sample_load : OUT STD_LOGIC; |
|
164 | 164 | fft_pong : OUT STD_LOGIC; |
|
165 | 165 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
166 | 166 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
167 | 167 | fft_data_valid : OUT STD_LOGIC; |
|
168 | 168 | fft_ready : OUT STD_LOGIC); |
|
169 | 169 | END COMPONENT; |
|
170 | 170 | |
|
171 | 171 | COMPONENT lpp_lfr_filter |
|
172 | 172 | GENERIC ( |
|
173 | tech : INTEGER; | |
|
173 | 174 | Mem_use : INTEGER; |
|
174 | 175 | RTL_DESIGN_LIGHT : INTEGER |
|
175 | 176 | ); |
|
176 | 177 | PORT ( |
|
177 | 178 | sample : IN Samples(7 DOWNTO 0); |
|
178 | 179 | sample_val : IN STD_LOGIC; |
|
179 | 180 | sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
180 | 181 | clk : IN STD_LOGIC; |
|
181 | 182 | rstn : IN STD_LOGIC; |
|
182 | 183 | data_shaping_SP0 : IN STD_LOGIC; |
|
183 | 184 | data_shaping_SP1 : IN STD_LOGIC; |
|
184 | 185 | data_shaping_R0 : IN STD_LOGIC; |
|
185 | 186 | data_shaping_R1 : IN STD_LOGIC; |
|
186 | 187 | data_shaping_R2 : IN STD_LOGIC; |
|
187 | 188 | sample_f0_val : OUT STD_LOGIC; |
|
188 | 189 | sample_f1_val : OUT STD_LOGIC; |
|
189 | 190 | sample_f2_val : OUT STD_LOGIC; |
|
190 | 191 | sample_f3_val : OUT STD_LOGIC; |
|
191 | 192 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
192 | 193 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
193 | 194 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
194 | 195 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
195 | 196 | sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
196 | 197 | sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
197 | 198 | sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
198 | 199 | sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
199 | 200 | ); |
|
200 | 201 | END COMPONENT; |
|
201 | 202 | |
|
202 | 203 | COMPONENT lpp_lfr |
|
203 | 204 | GENERIC ( |
|
204 | 205 | Mem_use : INTEGER; |
|
205 | 206 | tech : INTEGER; |
|
206 | 207 | nb_data_by_buffer_size : INTEGER; |
|
207 | 208 | -- nb_word_by_buffer_size : INTEGER; |
|
208 | 209 | nb_snapshot_param_size : INTEGER; |
|
209 | 210 | delta_vector_size : INTEGER; |
|
210 | 211 | delta_vector_size_f0_2 : INTEGER; |
|
211 | 212 | pindex : INTEGER; |
|
212 | 213 | paddr : INTEGER; |
|
213 | 214 | pmask : INTEGER; |
|
214 | 215 | pirq_ms : INTEGER; |
|
215 | 216 | pirq_wfp : INTEGER; |
|
216 | 217 | hindex : INTEGER; |
|
217 | 218 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
218 | 219 | DEBUG_FORCE_DATA_DMA : INTEGER; |
|
219 | 220 | RTL_DESIGN_LIGHT : INTEGER; |
|
220 | 221 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER |
|
221 | 222 | ); |
|
222 | 223 | PORT ( |
|
223 | 224 | clk : IN STD_LOGIC; |
|
224 | 225 | rstn : IN STD_LOGIC; |
|
225 | 226 | sample_B : IN Samples(2 DOWNTO 0); |
|
226 | 227 | sample_E : IN Samples(4 DOWNTO 0); |
|
227 | 228 | sample_val : IN STD_LOGIC; |
|
228 | 229 | apbi : IN apb_slv_in_type; |
|
229 | 230 | apbo : OUT apb_slv_out_type; |
|
230 | 231 | ahbi : IN AHB_Mst_In_Type; |
|
231 | 232 | ahbo : OUT AHB_Mst_Out_Type; |
|
232 | 233 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
233 | 234 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
234 | 235 | data_shaping_BW : OUT STD_LOGIC; |
|
235 | 236 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
236 | 237 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
237 | 238 | ); |
|
238 | 239 | END COMPONENT; |
|
239 | 240 | |
|
240 | 241 | ----------------------------------------------------------------------------- |
|
241 | 242 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
242 | 243 | ----------------------------------------------------------------------------- |
|
243 | 244 | COMPONENT lpp_lfr_WFP_nMS |
|
244 | 245 | GENERIC ( |
|
245 | 246 | Mem_use : INTEGER; |
|
246 | 247 | nb_data_by_buffer_size : INTEGER; |
|
247 | 248 | nb_word_by_buffer_size : INTEGER; |
|
248 | 249 | nb_snapshot_param_size : INTEGER; |
|
249 | 250 | delta_vector_size : INTEGER; |
|
250 | 251 | delta_vector_size_f0_2 : INTEGER; |
|
251 | 252 | pindex : INTEGER; |
|
252 | 253 | paddr : INTEGER; |
|
253 | 254 | pmask : INTEGER; |
|
254 | 255 | pirq_ms : INTEGER; |
|
255 | 256 | pirq_wfp : INTEGER; |
|
256 | 257 | hindex : INTEGER; |
|
257 | 258 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
258 | 259 | PORT ( |
|
259 | 260 | clk : IN STD_LOGIC; |
|
260 | 261 | rstn : IN STD_LOGIC; |
|
261 | 262 | sample_B : IN Samples(2 DOWNTO 0); |
|
262 | 263 | sample_E : IN Samples(4 DOWNTO 0); |
|
263 | 264 | sample_val : IN STD_LOGIC; |
|
264 | 265 | apbi : IN apb_slv_in_type; |
|
265 | 266 | apbo : OUT apb_slv_out_type; |
|
266 | 267 | ahbi : IN AHB_Mst_In_Type; |
|
267 | 268 | ahbo : OUT AHB_Mst_Out_Type; |
|
268 | 269 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
269 | 270 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
270 | 271 | data_shaping_BW : OUT STD_LOGIC; |
|
271 | 272 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
272 | 273 | END COMPONENT; |
|
273 | 274 | ----------------------------------------------------------------------------- |
|
274 | 275 | |
|
275 | 276 | COMPONENT lpp_lfr_apbreg |
|
276 | 277 | GENERIC ( |
|
277 | 278 | nb_data_by_buffer_size : INTEGER; |
|
278 | 279 | nb_snapshot_param_size : INTEGER; |
|
279 | 280 | delta_vector_size : INTEGER; |
|
280 | 281 | delta_vector_size_f0_2 : INTEGER; |
|
281 | 282 | pindex : INTEGER; |
|
282 | 283 | paddr : INTEGER; |
|
283 | 284 | pmask : INTEGER; |
|
284 | 285 | pirq_ms : INTEGER; |
|
285 | 286 | pirq_wfp : INTEGER; |
|
286 | 287 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
287 | 288 | PORT ( |
|
288 | 289 | HCLK : IN STD_ULOGIC; |
|
289 | 290 | HRESETn : IN STD_ULOGIC; |
|
290 | 291 | apbi : IN apb_slv_in_type; |
|
291 | 292 | apbo : OUT apb_slv_out_type; |
|
292 | 293 | -- run_ms : OUT STD_LOGIC; |
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293 | 294 | ready_matrix_f0 : IN STD_LOGIC; |
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294 | 295 | ready_matrix_f1 : IN STD_LOGIC; |
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295 | 296 | ready_matrix_f2 : IN STD_LOGIC; |
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296 | 297 | error_buffer_full : IN STD_LOGIC; |
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297 | 298 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
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298 | 299 | status_ready_matrix_f0 : OUT STD_LOGIC; |
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299 | 300 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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300 | 301 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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301 | 302 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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302 | 303 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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303 | 304 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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304 | 305 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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305 | 306 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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306 | 307 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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307 | 308 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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308 | 309 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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309 | 310 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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310 | 311 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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311 | 312 | data_shaping_BW : OUT STD_LOGIC; |
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312 | 313 | data_shaping_SP0 : OUT STD_LOGIC; |
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313 | 314 | data_shaping_SP1 : OUT STD_LOGIC; |
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314 | 315 | data_shaping_R0 : OUT STD_LOGIC; |
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315 | 316 | data_shaping_R1 : OUT STD_LOGIC; |
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316 | 317 | data_shaping_R2 : OUT STD_LOGIC; |
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317 | 318 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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318 | 319 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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319 | 320 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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320 | 321 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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321 | 322 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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322 | 323 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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323 | 324 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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324 | 325 | enable_f0 : OUT STD_LOGIC; |
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325 | 326 | enable_f1 : OUT STD_LOGIC; |
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326 | 327 | enable_f2 : OUT STD_LOGIC; |
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327 | 328 | enable_f3 : OUT STD_LOGIC; |
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328 | 329 | burst_f0 : OUT STD_LOGIC; |
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329 | 330 | burst_f1 : OUT STD_LOGIC; |
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330 | 331 | burst_f2 : OUT STD_LOGIC; |
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331 | 332 | run : OUT STD_LOGIC; |
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332 | 333 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
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333 | 334 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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334 | 335 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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335 | 336 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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336 | 337 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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337 | 338 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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338 | 339 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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339 | 340 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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340 | 341 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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341 | 342 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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342 | 343 | sample_f3_valid : IN STD_LOGIC; |
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343 | 344 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
|
344 | 345 | END COMPONENT; |
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345 | 346 | |
|
346 | 347 | COMPONENT lpp_top_ms |
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347 | 348 | GENERIC ( |
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348 | 349 | Mem_use : INTEGER; |
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349 | 350 | nb_burst_available_size : INTEGER; |
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350 | 351 | nb_snapshot_param_size : INTEGER; |
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351 | 352 | delta_snapshot_size : INTEGER; |
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352 | 353 | delta_f2_f0_size : INTEGER; |
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353 | 354 | delta_f2_f1_size : INTEGER; |
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354 | 355 | pindex : INTEGER; |
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355 | 356 | paddr : INTEGER; |
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356 | 357 | pmask : INTEGER; |
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357 | 358 | pirq_ms : INTEGER; |
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358 | 359 | pirq_wfp : INTEGER; |
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359 | 360 | hindex_wfp : INTEGER; |
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360 | 361 | hindex_ms : INTEGER); |
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361 | 362 | PORT ( |
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362 | 363 | clk : IN STD_LOGIC; |
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363 | 364 | rstn : IN STD_LOGIC; |
|
364 | 365 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
365 | 366 | sample_E : IN Samples14v(4 DOWNTO 0); |
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366 | 367 | sample_val : IN STD_LOGIC; |
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367 | 368 | apbi : IN apb_slv_in_type; |
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368 | 369 | apbo : OUT apb_slv_out_type; |
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369 | 370 | ahbi_ms : IN AHB_Mst_In_Type; |
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370 | 371 | ahbo_ms : OUT AHB_Mst_Out_Type; |
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371 | 372 | data_shaping_BW : OUT STD_LOGIC; |
|
372 | 373 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
373 | 374 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
374 | 375 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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375 | 376 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
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376 | 377 | ); |
|
377 | 378 | END COMPONENT; |
|
378 | 379 | |
|
379 | 380 | COMPONENT lpp_apbreg_ms_pointer |
|
380 | 381 | PORT ( |
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381 | 382 | clk : IN STD_LOGIC; |
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382 | 383 | rstn : IN STD_LOGIC; |
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383 | 384 | run : IN STD_LOGIC; |
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384 | 385 | reg0_status_ready_matrix : IN STD_LOGIC; |
|
385 | 386 | reg0_ready_matrix : OUT STD_LOGIC; |
|
386 | 387 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
387 | 388 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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388 | 389 | reg1_status_ready_matrix : IN STD_LOGIC; |
|
389 | 390 | reg1_ready_matrix : OUT STD_LOGIC; |
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390 | 391 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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391 | 392 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
392 | 393 | ready_matrix : IN STD_LOGIC; |
|
393 | 394 | status_ready_matrix : OUT STD_LOGIC; |
|
394 | 395 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
395 | 396 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
396 | 397 | END COMPONENT; |
|
397 | 398 | |
|
398 | 399 | COMPONENT lpp_lfr_ms_reg_head |
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399 | 400 | PORT ( |
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400 | 401 | clk : IN STD_LOGIC; |
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401 | 402 | rstn : IN STD_LOGIC; |
|
402 | 403 | in_wen : IN STD_LOGIC; |
|
403 | 404 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
404 | 405 | in_full : IN STD_LOGIC; |
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405 | 406 | in_empty : IN STD_LOGIC; |
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406 | 407 | out_write_error : OUT STD_LOGIC; |
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407 | 408 | out_wen : OUT STD_LOGIC; |
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408 | 409 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
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409 | 410 | out_full : OUT STD_LOGIC); |
|
410 | 411 | END COMPONENT; |
|
411 | 412 | |
|
412 | 413 | END lpp_lfr_pkg; |
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