HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r640:06e69364220d

Exposed tech parameter from filters to top lpp_lfr_filter....

pellion -

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designs/Validation_IIR_f0_LFR/Makefile created 644 +56 0

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	1	#GRLIB=../..
	2	VHDLIB=../..
	3	SCRIPTSDIR=$(VHDLIB)/scripts/
	4	GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
	5	TOP=testbench
	6	BOARD=LFR-EQM
	7	include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
	8	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
	9	UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
	10	QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
	11	EFFORT=high
	12	XSTOPT=
	13	SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
	14	#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
	15	VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
	16	VHDLSIMFILES= tb.vhd
	17	SIMTOP=testbench
	18	#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
	19	PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
	20	SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
	21	BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
	22	CLEAN=soft-clean
	23
	24	TECHLIBS = axcelerator
	25
	26	LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
	27	tmtc openchip hynix ihp gleichmann micron usbhc opencores
	28
	29	DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
	30	pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
	31	./amba_lcd_16x2_ctrlr \
	32	./general_purpose/lpp_AMR \
	33	./general_purpose/lpp_balise \
	34	./general_purpose/lpp_delay \
	35	./lpp_bootloader \
	36	./lfr_management \
	37	./lpp_sim \
	38	./lpp_sim/CY7C1061DV33 \
	39	./lpp_cna \
	40	./lpp_uart \
	41	./lpp_usb \
	42	./dsp/lpp_fft \
	43
	44	FILESKIP = i2cmst.vhd \
	45	APB_MULTI_DIODE.vhd \
	46	APB_MULTI_DIODE.vhd \
	47	Top_MatrixSpec.vhd \
	48	APB_FFT.vhd \
	49	lpp_lfr_apbreg.vhd \
	50	CoreFFT.vhd
	51
	52	include $(GRLIB)/bin/Makefile
	53	include $(GRLIB)/software/leon3/Makefile
	54
	55	################## project specific targets ##########################
	56

designs/Validation_IIR_f0_LFR/generator.vhd created 644 +74 0

@@ -0,0 +1,74
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com
	22	----------------------------------------------------------------------------
	23
	24	LIBRARY ieee;
	25	USE ieee.std_logic_1164.ALL;
	26	use ieee.numeric_std.all;
	27	USE IEEE.std_logic_signed.ALL;
	28	USE IEEE.MATH_real.ALL;
	29
	30	ENTITY generator IS
	31
	32	GENERIC (
	33	AMPLITUDE : INTEGER := 100;
	34	NB_BITS : INTEGER := 16);
	35
	36	PORT (
	37	clk : IN STD_LOGIC;
	38	rstn : IN STD_LOGIC;
	39	run : IN STD_LOGIC;
	40
	41	data_ack : IN STD_LOGIC;
	42	offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
	43	data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
	44	);
	45
	46	END generator;
	47
	48	ARCHITECTURE beh OF generator IS
	49
	50	SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
	51	BEGIN -- beh
	52
	53
	54	PROCESS (clk, rstn)
	55	variable seed1, seed2: positive; -- seed values for random generator
	56	variable rand: real; -- random real-number value in range 0 to 1.0
	57	BEGIN -- PROCESS
	58	uniform(seed1, seed2, rand);--more entropy by skipping values
	59	IF rstn = '0' THEN -- asynchronous reset (active low)
	60	reg <= (OTHERS => '0');
	61	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	62	IF run = '0' THEN
	63	reg <= (OTHERS => '0');
	64	ELSE
	65	IF data_ack = '1' THEN
	66	reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
	67	END IF;
	68	END IF;
	69	END IF;
	70	END PROCESS;
	71
	72	data <= reg;
	73
	74	END beh;

designs/Validation_IIR_f0_LFR/tb.vhd created 644 +227 0

@@ -0,0 +1,227
	1
	2	LIBRARY ieee;
	3	USE ieee.std_logic_1164.ALL;
	4	USE ieee.numeric_std.ALL;
	5	USE IEEE.std_logic_signed.ALL;
	6	USE IEEE.MATH_real.ALL;
	7
	8	LIBRARY techmap;
	9	USE techmap.gencomp.ALL;
	10
	11	LIBRARY std;
	12	USE std.textio.ALL;
	13
	14	LIBRARY lpp;
	15	USE lpp.iir_filter.ALL;
	16	USE lpp.lpp_ad_conv.ALL;
	17	USE lpp.FILTERcfg.ALL;
	18	USE lpp.lpp_lfr_filter_coeff.ALL;
	19	USE lpp.general_purpose.ALL;
	20	USE lpp.data_type_pkg.ALL;
	21	USE lpp.lpp_lfr_pkg.ALL;
	22	USE lpp.general_purpose.ALL;
	23
	24	ENTITY testbench IS
	25	END;
	26
	27	ARCHITECTURE behav OF testbench IS
	28	CONSTANT ChanelCount : INTEGER := 8;
	29	CONSTANT Coef_SZ : INTEGER := 9;
	30	CONSTANT CoefCntPerCel : INTEGER := 6;
	31	CONSTANT CoefPerCel : INTEGER := 5;
	32	CONSTANT Cels_count : INTEGER := 5;
	33
	34	SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
	35	SIGNAL sample_val : STD_LOGIC;
	36
	37	SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
	38	SIGNAL sample_fx_val : STD_LOGIC;
	39
	40
	41
	42
	43
	44
	45	SIGNAL TSTAMP : INTEGER := 0;
	46	SIGNAL clk : STD_LOGIC := '0';
	47	SIGNAL clk_24k : STD_LOGIC := '0';
	48	SIGNAL clk_24k_r : STD_LOGIC := '0';
	49	SIGNAL rstn : STD_LOGIC;
	50
	51	SIGNAL signal_gen : Samples(7 DOWNTO 0);
	52	SIGNAL offset_gen : Samples(7 DOWNTO 0);
	53
	54	--SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
	55
	56	SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
	57
	58
	59	COMPONENT generator IS
	60	GENERIC (
	61	AMPLITUDE : INTEGER := 100;
	62	NB_BITS : INTEGER := 16);
	63
	64	PORT (
	65	clk : IN STD_LOGIC;
	66	rstn : IN STD_LOGIC;
	67	run : IN STD_LOGIC;
	68
	69	data_ack : IN STD_LOGIC;
	70	offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
	71	data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
	72	);
	73	END COMPONENT;
	74
	75
	76	FILE log_input : TEXT OPEN write_mode IS "log_input.txt";
	77	FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
	78
	79	SIGNAL end_of_simu : STD_LOGIC := '0';
	80
	81	BEGIN
	82
	83	-----------------------------------------------------------------------------
	84	-- CLOCK and RESET
	85	-----------------------------------------------------------------------------
	86	clk <= NOT clk AFTER 5 ns;
	87	PROCESS
	88	BEGIN -- PROCESS
	89	end_of_simu <= '0';
	90	WAIT UNTIL clk = '1';
	91	rstn <= '0';
	92	WAIT UNTIL clk = '1';
	93	WAIT UNTIL clk = '1';
	94	WAIT UNTIL clk = '1';
	95	rstn <= '1';
	96	WAIT FOR 2000 ms;
	97	end_of_simu <= '1';
	98	WAIT UNTIL clk = '1';
	99	REPORT "* END simulation *" SEVERITY failure;
	100	WAIT;
	101	END PROCESS;
	102	-----------------------------------------------------------------------------
	103
	104
	105	-----------------------------------------------------------------------------
	106	-- COMMON TIMESTAMPS
	107	-----------------------------------------------------------------------------
	108
	109	PROCESS(clk)
	110	BEGIN
	111	IF clk'EVENT AND clk = '1' THEN
	112	TSTAMP <= TSTAMP+1;
	113	END IF;
	114	END PROCESS;
	115	-----------------------------------------------------------------------------
	116
	117
	118	-----------------------------------------------------------------------------
	119	-- LPP_LFR_FILTER f0
	120	-----------------------------------------------------------------------------
	121
	122	IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
	123	GENERIC MAP (
	124	tech => axcel,
	125	Mem_use => use_RAM,
	126	Sample_SZ => 18,
	127	Coef_SZ => Coef_SZ,
	128	Coef_Nb => 25,
	129	Coef_sel_SZ => 5,
	130	Cels_count => Cels_count,
	131	ChanelsCount => ChanelCount)
	132	PORT MAP (
	133	rstn => rstn,
	134	clk => clk,
	135	virg_pos => 7,
	136	coefs => CoefsInitValCst_v2,
	137
	138	sample_in_val => sample_val,
	139	sample_in => sample,
	140	sample_out_val => sample_fx_val,
	141	sample_out => sample_fx);
	142	-----------------------------------------------------------------------------
	143
	144
	145	-----------------------------------------------------------------------------
	146	-- SAMPLE GENERATION
	147	-----------------------------------------------------------------------------
	148	clk_24k <= NOT clk_24k AFTER 20345 ns;
	149
	150	PROCESS (clk, rstn)
	151	BEGIN -- PROCESS
	152	IF rstn = '0' THEN -- asynchronous reset (active low)
	153	sample_val <= '0';
	154	clk_24k_r <= '0';
	155	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	156	clk_24k_r <= clk_24k;
	157	IF clk_24k = '1' AND clk_24k_r = '0' THEN
	158	sample_val <= '1';
	159	ELSE
	160	sample_val <= '0';
	161	END IF;
	162	END IF;
	163	END PROCESS;
	164	-----------------------------------------------------------------------------
	165	generators : FOR I IN 0 TO 7 GENERATE
	166	gen1 : generator
	167	GENERIC MAP (
	168	AMPLITUDE => 100,
	169	NB_BITS => 16)
	170	PORT MAP (
	171	clk => clk,
	172	rstn => rstn,
	173	run => '1',
	174	data_ack => sample_val,
	175	offset => offset_gen(I),
	176	data => signal_gen(I)
	177	);
	178	offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
	179	END GENERATE generators;
	180
	181	ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
	182	SampleLoop : FOR j IN 0 TO 15 GENERATE
	183	sample(i,j) <= signal_gen(i)(j);
	184	sample_fx_wdata(i)(j) <= sample_fx(i,j);
	185	END GENERATE;
	186
	187	sample(i, 16) <= signal_gen(i)(15);
	188	sample(i, 17) <= signal_gen(i)(15);
	189	END GENERATE;
	190
	191
	192
	193	-----------------------------------------------------------------------------
	194	-- RECORD SIGNALS
	195	-----------------------------------------------------------------------------
	196
	197	-- PROCESS(sample_val)
	198	-- VARIABLE line_var : LINE;
	199	-- BEGIN
	200	-- IF sample_val'EVENT AND sample_val = '1' THEN
	201	-- write(line_var, INTEGER'IMAGE(TSTAMP));
	202	-- FOR I IN 0 TO 7 LOOP
	203	-- write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
	204	-- END LOOP;
	205	-- writeline(log_input, line_var);
	206	-- END IF;
	207	-- END PROCESS;
	208
	209	PROCESS(sample_fx_val,end_of_simu)
	210	VARIABLE line_var : LINE;
	211	BEGIN
	212	IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
	213	write(line_var, INTEGER'IMAGE(TSTAMP));
	214	FOR I IN 0 TO 5 LOOP
	215	write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
	216	END LOOP;
	217	writeline(log_output_fx, line_var);
	218	END IF;
	219	IF end_of_simu = '1' THEN
	220	file_close(log_output_fx);
	221	END IF;
	222	END PROCESS;
	223
	224
	225
	226
	227	END;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +1 0

               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
+                  tech             => tech,
                   Mem_use          => Mem_use,
                   RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
                 PORT MAP (

lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +5 -4

             ENTITY lpp_lfr_filter IS
               GENERIC(
+                tech         : INTEGER := 0;
                 Mem_use                 : INTEGER := use_RAM;
                 RTL_DESIGN_LIGHT        : INTEGER := 0
                 );
               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
-                  tech         => 0,
+                  tech         => tech,
                   Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
               IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
-                  tech         => 0,
+                  tech         => tech,
                   Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => f0_to_f1_COEFFICIENT_SIZE,
               cic_lfr_1: cic_lfr_r2
                 GENERIC MAP (
-                  tech         => 0,
+                  tech         => tech,
                   use_RAM_nCEL => Mem_use)
                 PORT MAP (
                   clk                => clk,
               YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
                 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
                   GENERIC MAP (
-                    tech         => 0,
+                    tech         => tech,
                     Mem_use      => Mem_use,
                     Sample_SZ    => 18,
                     Coef_SZ      => f2_f3_COEFFICIENT_SIZE,

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +1 0

               COMPONENT lpp_lfr_filter
                 GENERIC (
+                  tech                    : INTEGER;
                   Mem_use                 : INTEGER;
                   RTL_DESIGN_LIGHT        : INTEGER
                   );

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