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r596:04687799528c simu_with_Leon3
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1 1 ################################################################################
2 2 # SDC WRITER VERSION "3.1";
3 3 # DESIGN "LFR_EQM";
4 4 # Timing constraints scenario: "Primary";
5 5 # DATE "Fri Apr 24 16:02:16 2015";
6 6 # VENDOR "Actel";
7 7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 9 ################################################################################
10 10
11 11
12 12 set sdc_version 1.7
13 13
14 14
15 15 ######## Clock Constraints ########
16 16
17 17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18 18
19 19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20 20
21 21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22 22
23 #create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24 24
25 25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26 26
27 27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28 28
29 29
30 30
31 31 ######## Generated Clock Constraints ########
32 32
33 33
34 34
35 35 ######## Clock Source Latency Constraints #########
36 36
37 37
38 38
39 39 ######## Input Delay Constraints ########
40 40
41 41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50 50
51 51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 54
55 55
56 56
57 57 ######## Output Delay Constraints ########
58 58
59 59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68 68
69 69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 73 address[7] address[8] address[9] }]
74 74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 77 address[7] address[8] address[9] }]
78 78
79 79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82 82
83 83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86 86
87 87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90 90
91 91
92 92
93 93 ######## Delay Constraints ########
94 94
95 95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
96 96
97 97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
98 98
99 99
100 100
101 101 ######## Delay Constraints ########
102 102
103 103
104 104
105 105 ######## Multicycle Constraints ########
106 106
107 107
108 108
109 109 ######## False Path Constraints ########
110 110
111 111
112 112
113 113 ######## Output load Constraints ########
114 114
115 115
116 116
117 117 ######## Disable Timing Constraints #########
118 118
119 119
120 120
121 121 ######## Clock Uncertainty Constraints #########
122 122
123 123
124 124
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@@ -1,603 +1,603
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.sim.ALL;
32 32 USE gaisler.memctrl.ALL;
33 33 USE gaisler.leon3.ALL;
34 34 USE gaisler.uart.ALL;
35 35 USE gaisler.misc.ALL;
36 36 USE gaisler.spacewire.ALL;
37 37 LIBRARY esa;
38 38 USE esa.memoryctrl.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 44 USE lpp.iir_filter.ALL;
45 45 USE lpp.general_purpose.ALL;
46 46 USE lpp.lpp_lfr_management.ALL;
47 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 USE lpp.lpp_bootloader_pkg.ALL;
49 49
50 50 --library proasic3l;
51 51 --use proasic3l.all;
52 52
53 53 ENTITY LFR_EQM IS
54 54 GENERIC (
55 55 Mem_use : INTEGER := use_RAM;
56 56 USE_BOOTLOADER : INTEGER := 0;
57 57 USE_ADCDRIVER : INTEGER := 1;
58 58 tech : INTEGER := apa3e;
59 59 tech_leon : INTEGER := apa3e;
60 60 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 61 USE_DEBUG_VECTOR : INTEGER := 0
62 62 );
63 63
64 64 PORT (
65 65 clk50MHz : IN STD_ULOGIC;
66 66 clk49_152MHz : IN STD_ULOGIC;
67 67 reset : IN STD_ULOGIC;
68 68
69 69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 70
71 71 -- TAG --------------------------------------------------------------------
72 72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 74 -- UART APB ---------------------------------------------------------------
75 75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 77 -- RAM --------------------------------------------------------------------
78 78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 85 nSRAM_W : OUT STD_LOGIC; -- new
86 86 nSRAM_G : OUT STD_LOGIC; -- new
87 87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 88 -- SPW --------------------------------------------------------------------
89 89 spw1_en : OUT STD_LOGIC; -- new
90 90 spw1_din : IN STD_LOGIC;
91 91 spw1_sin : IN STD_LOGIC;
92 92 spw1_dout : OUT STD_LOGIC;
93 93 spw1_sout : OUT STD_LOGIC;
94 94 spw2_en : OUT STD_LOGIC; -- new
95 95 spw2_din : IN STD_LOGIC;
96 96 spw2_sin : IN STD_LOGIC;
97 97 spw2_dout : OUT STD_LOGIC;
98 98 spw2_sout : OUT STD_LOGIC;
99 99 -- ADC --------------------------------------------------------------------
100 100 bias_fail_sw : OUT STD_LOGIC;
101 101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102 ADC_smpclk : OUT STD_LOGIC;
103 103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 104 -- DAC --------------------------------------------------------------------
105 105 DAC_SDO : OUT STD_LOGIC;
106 106 DAC_SCK : OUT STD_LOGIC;
107 107 DAC_SYNC : OUT STD_LOGIC;
108 108 DAC_CAL_EN : OUT STD_LOGIC;
109 109 -- HK ---------------------------------------------------------------------
110 110 HK_smpclk : OUT STD_LOGIC;
111 111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 113 ---------------------------------------------------------------------------
114 114 -- TAG8 : OUT STD_LOGIC
115 115 );
116 116
117 117 END LFR_EQM;
118 118
119 119
120 120 ARCHITECTURE beh OF LFR_EQM IS
121 121
122 122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_49 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 127
128 128 -- CONSTANTS
129 129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133 133
134 134 SIGNAL apbi_ext : apb_slv_in_type;
135 135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140 140
141 141 -- Spacewire signals
142 142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 147 SIGNAL spw_clk : STD_LOGIC;
148 148 SIGNAL swni : grspw_in_type;
149 149 SIGNAL swno : grspw_out_type;
150 150
151 151 --GPIO
152 152 SIGNAL gpioi : gpio_in_type;
153 153 SIGNAL gpioo : gpio_out_type;
154 154
155 155 -- AD Converter ADS7886
156 156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 158 SIGNAL sample_val : STD_LOGIC;
159 159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160 160
161 161 -----------------------------------------------------------------------------
162 162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 163
164 164 -----------------------------------------------------------------------------
165 165 SIGNAL rstn_25 : STD_LOGIC;
166 SIGNAL rstn_49 : STD_LOGIC;
166 SIGNAL rstn_24 : STD_LOGIC;
167 167
168 168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 169 SIGNAL LFR_rstn : STD_LOGIC;
170 170
171 171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172 172
173 173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 174
175 175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 176 SIGNAL clk_25_int : STD_LOGIC := '0';
177 177
178 178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179 179
180 180 SIGNAL rstn_50 : STD_LOGIC;
181 181 SIGNAL clk_lock : STD_LOGIC;
182 182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184 184
185 185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 186 SIGNAL ahbrxd: STD_LOGIC;
187 187 SIGNAL ahbtxd: STD_LOGIC;
188 188 SIGNAL urxd1 : STD_LOGIC;
189 189 SIGNAL utxd1 : STD_LOGIC;
190 190 BEGIN -- beh
191 191
192 192 -----------------------------------------------------------------------------
193 193 -- CLK_LOCK
194 194 -----------------------------------------------------------------------------
195 195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196 196
197 197 PROCESS (clk50MHz_int, rstn_50)
198 198 BEGIN -- PROCESS
199 199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 200 clk_lock <= '0';
201 201 clk_busy_counter <= (OTHERS => '0');
202 202 nSRAM_BUSY_reg <= '0';
203 203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 206 IF clk_busy_counter = "1111" THEN
207 207 clk_lock <= '1';
208 208 ELSE
209 209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 210 END IF;
211 211 END IF;
212 212 END IF;
213 213 END PROCESS;
214 214
215 215 -----------------------------------------------------------------------------
216 216 -- CLK
217 217 -----------------------------------------------------------------------------
218 218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_49, clk_lock, rstn_49, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220 220
221 221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 222 clk50MHz_int <= clk50MHz;
223 223
224 224 PROCESS(clk50MHz_int)
225 225 BEGIN
226 226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 227 --clk_25_int <= NOT clk_25_int;
228 228 clk_25 <= NOT clk_25;
229 229 END IF;
230 230 END PROCESS;
231 231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232 232
233 --PROCESS(clk49_152MHz)
234 --BEGIN
235 -- IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 -- clk_24 <= NOT clk_24;
237 -- END IF;
238 --END PROCESS;
239 clk_49 <= clk49_152MHz;
233 PROCESS(clk49_152MHz)
234 BEGIN
235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 clk_24 <= NOT clk_24;
237 END IF;
238 END PROCESS;
239 -- clk_49 <= clk49_152MHz;
240 240
241 241 -----------------------------------------------------------------------------
242 242 --
243 243 leon3_soc_1 : leon3_soc
244 244 GENERIC MAP (
245 245 fabtech => tech_leon,
246 246 memtech => tech_leon,
247 247 padtech => inferred,
248 248 clktech => inferred,
249 249 disas => 0,
250 250 dbguart => 0,
251 251 pclow => 2,
252 252 clk_freq => 25000,
253 253 IS_RADHARD => 0,
254 254 NB_CPU => 1,
255 255 ENABLE_FPU => 1,
256 256 FPU_NETLIST => 0,
257 257 ENABLE_DSU => 1,
258 258 ENABLE_AHB_UART => 1,
259 259 ENABLE_APB_UART => 1,
260 260 ENABLE_IRQMP => 1,
261 261 ENABLE_GPT => 1,
262 262 NB_AHB_MASTER => NB_AHB_MASTER,
263 263 NB_AHB_SLAVE => NB_AHB_SLAVE,
264 264 NB_APB_SLAVE => NB_APB_SLAVE,
265 265 ADDRESS_SIZE => 19,
266 266 USES_IAP_MEMCTRLR => 1,
267 267 BYPASS_EDAC_MEMCTRLR => '0',
268 268 SRBANKSZ => 8)
269 269 PORT MAP (
270 270 clk => clk_25,
271 271 reset => rstn_25,
272 272 errorn => OPEN,
273 273
274 274 ahbrxd => ahbrxd, -- INPUT
275 275 ahbtxd => ahbtxd, -- OUTPUT
276 276 urxd1 => urxd1, -- INPUT
277 277 utxd1 => utxd1, -- OUTPUT
278 278
279 279 address => address,
280 280 data => data,
281 281 nSRAM_BE0 => OPEN,
282 282 nSRAM_BE1 => OPEN,
283 283 nSRAM_BE2 => OPEN,
284 284 nSRAM_BE3 => OPEN,
285 285 nSRAM_WE => nSRAM_W,
286 286 nSRAM_CE => nSRAM_CE,
287 287 nSRAM_OE => nSRAM_G,
288 288 nSRAM_READY => nSRAM_BUSY,
289 289 SRAM_MBE => nSRAM_MBE,
290 290
291 291 apbi_ext => apbi_ext,
292 292 apbo_ext => apbo_ext,
293 293 ahbi_s_ext => ahbi_s_ext,
294 294 ahbo_s_ext => ahbo_s_ext,
295 295 ahbi_m_ext => ahbi_m_ext,
296 296 ahbo_m_ext => ahbo_m_ext);
297 297
298 298
299 299 nSRAM_E1 <= nSRAM_CE(0);
300 300 nSRAM_E2 <= nSRAM_CE(1);
301 301
302 302 -------------------------------------------------------------------------------
303 303 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
304 304 -------------------------------------------------------------------------------
305 305 apb_lfr_management_1 : apb_lfr_management
306 306 GENERIC MAP (
307 307 tech => tech,
308 308 pindex => 6,
309 309 paddr => 6,
310 310 pmask => 16#fff#,
311 311 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
312 312 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
313 313 PORT MAP (
314 314 clk25MHz => clk_25,
315 315 resetn_25MHz => rstn_25, -- TODO
316 316 --clk24_576MHz => clk_24, -- 49.152MHz/2
317 317 --resetn_24_576MHz => rstn_24, -- TODO
318 318
319 319 grspw_tick => swno.tickout,
320 320 apbi => apbi_ext,
321 321 apbo => apbo_ext(6),
322 322
323 323 HK_sample => sample_s(8),
324 324 HK_val => sample_val,
325 325 HK_sel => HK_SEL,
326 326
327 327 DAC_SDO => DAC_SDO,
328 328 DAC_SCK => DAC_SCK,
329 329 DAC_SYNC => DAC_SYNC,
330 330 DAC_CAL_EN => DAC_CAL_EN,
331 331
332 332 coarse_time => coarse_time,
333 333 fine_time => fine_time,
334 334 LFR_soft_rstn => LFR_soft_rstn
335 335 );
336 336
337 337 -----------------------------------------------------------------------
338 338 --- SpaceWire --------------------------------------------------------
339 339 -----------------------------------------------------------------------
340 340
341 341 ------------------------------------------------------------------------------
342 342 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
343 343 ------------------------------------------------------------------------------
344 344 spw1_en <= '1';
345 345 spw2_en <= '1';
346 346 ------------------------------------------------------------------------------
347 347 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
348 348 ------------------------------------------------------------------------------
349 349
350 350 --spw_clk <= clk50MHz;
351 351 --spw_rxtxclk <= spw_clk;
352 352 --spw_rxclkn <= NOT spw_rxtxclk;
353 353
354 354 -- PADS for SPW1
355 355 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
356 356 PORT MAP (spw1_din, dtmp(0));
357 357 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
358 358 PORT MAP (spw1_sin, stmp(0));
359 359 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
360 360 PORT MAP (spw1_dout, swno.d(0));
361 361 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
362 362 PORT MAP (spw1_sout, swno.s(0));
363 363 -- PADS FOR SPW2
364 364 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
365 365 PORT MAP (spw2_din, dtmp(1));
366 366 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
367 367 PORT MAP (spw2_sin, stmp(1));
368 368 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
369 369 PORT MAP (spw2_dout, swno.d(1));
370 370 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
371 371 PORT MAP (spw2_sout, swno.s(1));
372 372
373 373 -- GRSPW PHY
374 374 --spw1_input: if CFG_SPW_GRSPW = 1 generate
375 375 spw_inputloop : FOR j IN 0 TO 1 GENERATE
376 376 spw_phy0 : grspw_phy
377 377 GENERIC MAP(
378 378 tech => tech_leon,
379 379 rxclkbuftype => 1,
380 380 scantest => 0)
381 381 PORT MAP(
382 382 rxrst => swno.rxrst,
383 383 di => dtmp(j),
384 384 si => stmp(j),
385 385 rxclko => spw_rxclk(j),
386 386 do => swni.d(j),
387 387 ndo => swni.nd(j*5+4 DOWNTO j*5),
388 388 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
389 389 END GENERATE spw_inputloop;
390 390
391 391 -- SPW core
392 392 sw0 : grspwm GENERIC MAP(
393 393 tech => tech_leon,
394 394 hindex => 1,
395 395 pindex => 5,
396 396 paddr => 5,
397 397 pirq => 11,
398 398 sysfreq => 25000, -- CPU_FREQ
399 399 rmap => 1,
400 400 rmapcrc => 1,
401 401 fifosize1 => 16,
402 402 fifosize2 => 16,
403 403 rxclkbuftype => 1,
404 404 rxunaligned => 0,
405 405 rmapbufs => 4,
406 406 ft => 0,
407 407 netlist => 0,
408 408 ports => 2,
409 409 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
410 410 memtech => tech_leon,
411 411 destkey => 2,
412 412 spwcore => 1
413 413 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
414 414 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
415 415 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
416 416 )
417 417 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
418 418 spw_rxclk(1),
419 419 clk50MHz_int,
420 420 clk50MHz_int,
421 421 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
422 422 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
423 423 swni, swno);
424 424
425 425 swni.tickin <= '0';
426 426 swni.rmapen <= '1';
427 427 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
428 428 swni.tickinraw <= '0';
429 429 swni.timein <= (OTHERS => '0');
430 430 swni.dcrstval <= (OTHERS => '0');
431 431 swni.timerrstval <= (OTHERS => '0');
432 432
433 433 -------------------------------------------------------------------------------
434 434 -- LFR ------------------------------------------------------------------------
435 435 -------------------------------------------------------------------------------
436 436 LFR_rstn <= LFR_soft_rstn AND rstn_25;
437 437
438 438 lpp_lfr_1 : lpp_lfr
439 439 GENERIC MAP (
440 440 Mem_use => Mem_use,
441 441 tech => tech,
442 442 nb_data_by_buffer_size => 32,
443 443 --nb_word_by_buffer_size => 30,
444 444 nb_snapshot_param_size => 32,
445 445 delta_vector_size => 32,
446 446 delta_vector_size_f0_2 => 7, -- log2(96)
447 447 pindex => 15,
448 448 paddr => 15,
449 449 pmask => 16#fff#,
450 450 pirq_ms => 6,
451 451 pirq_wfp => 14,
452 452 hindex => 2,
453 453 top_lfr_version => X"020150", -- aa.bb.cc version
454 454 -- AA : BOARD NUMBER
455 455 -- 0 => MINI_LFR
456 456 -- 1 => EM
457 457 -- 2 => EQM (with A3PE3000)
458 458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
459 459 PORT MAP (
460 460 clk => clk_25,
461 461 rstn => LFR_rstn,
462 462 sample_B => sample_s(2 DOWNTO 0),
463 463 sample_E => sample_s(7 DOWNTO 3),
464 464 sample_val => sample_val,
465 465 apbi => apbi_ext,
466 466 apbo => apbo_ext(15),
467 467 ahbi => ahbi_m_ext,
468 468 ahbo => ahbo_m_ext(2),
469 469 coarse_time => coarse_time,
470 470 fine_time => fine_time,
471 471 data_shaping_BW => bias_fail_sw,
472 472 debug_vector => debug_vector,
473 473 debug_vector_ms => OPEN); --,
474 474 --observation_vector_0 => OPEN,
475 475 --observation_vector_1 => OPEN,
476 476 --observation_reg => observation_reg);
477 477
478 478
479 479 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
480 480 sample_s(I) <= sample(I) & '0' & '0';
481 481 END GENERATE all_sample;
482 482 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
483 483
484 484 -----------------------------------------------------------------------------
485 485 --
486 486 -----------------------------------------------------------------------------
487 487 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
488 488 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
489 489 GENERIC MAP (
490 490 ChanelCount => 9,
491 ncycle_cnv_high => 50,
492 ncycle_cnv => 100,
491 ncycle_cnv_high => 25,
492 ncycle_cnv => 50,
493 493 FILTER_ENABLED => 16#FF#)
494 494 PORT MAP (
495 cnv_clk => clk_49,
496 cnv_rstn => rstn_49,
495 cnv_clk => clk_24,
496 cnv_rstn => rstn_24,
497 497 cnv => ADC_smpclk_s,
498 498 clk => clk_25,
499 499 rstn => rstn_25,
500 500 ADC_data => ADC_data,
501 501 ADC_nOE => ADC_OEB_bar_CH_s,
502 502 sample => sample,
503 503 sample_val => sample_val);
504 504
505 505 END GENERATE USE_ADCDRIVER_true;
506 506
507 507 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
508 508 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
509 509 GENERIC MAP (
510 510 ChanelCount => 9,
511 511 ncycle_cnv_high => 25,
512 512 ncycle_cnv => 50,
513 513 FILTER_ENABLED => 16#FF#)
514 514 PORT MAP (
515 cnv_clk => clk_49,
516 cnv_rstn => rstn_49,
515 cnv_clk => clk_24,
516 cnv_rstn => rstn_24,
517 517 cnv => ADC_smpclk_s,
518 518 clk => clk_25,
519 519 rstn => rstn_25,
520 520 ADC_data => ADC_data,
521 521 ADC_nOE => OPEN,
522 522 sample => OPEN,
523 523 sample_val => sample_val);
524 524
525 525 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
526 526
527 527 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
528 528 ramp_generator_1: ramp_generator
529 529 GENERIC MAP (
530 530 DATA_SIZE => 14,
531 531 VALUE_UNSIGNED_INIT => 2**I,
532 532 VALUE_UNSIGNED_INCR => 0,
533 533 VALUE_UNSIGNED_MASK => 16#3FFF#)
534 534 PORT MAP (
535 535 clk => clk_25,
536 536 rstn => rstn_25,
537 537 new_data => sample_val,
538 538 output_data => sample(I) );
539 539 END GENERATE all_sample;
540 540
541 541
542 542 END GENERATE USE_ADCDRIVER_false;
543 543
544 544
545 545
546 546
547 547 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
548 548
549 549 ADC_smpclk <= ADC_smpclk_s;
550 550 HK_smpclk <= ADC_smpclk_s;
551 551
552 552
553 553 -----------------------------------------------------------------------------
554 554 -- HK
555 555 -----------------------------------------------------------------------------
556 556 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
557 557
558 558 -----------------------------------------------------------------------------
559 559 --
560 560 -----------------------------------------------------------------------------
561 561 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
562 562 lpp_bootloader_1: lpp_bootloader
563 563 GENERIC MAP (
564 564 pindex => 13,
565 565 paddr => 13,
566 566 pmask => 16#fff#,
567 567 hindex => 3,
568 568 haddr => 0,
569 569 hmask => 16#fff#)
570 570 PORT MAP (
571 571 HCLK => clk_25,
572 572 HRESETn => rstn_25,
573 573 apbi => apbi_ext,
574 574 apbo => apbo_ext(13),
575 575 ahbsi => ahbi_s_ext,
576 576 ahbso => ahbo_s_ext(3));
577 577 END GENERATE inst_bootloader;
578 578
579 579 -----------------------------------------------------------------------------
580 580 --
581 581 -----------------------------------------------------------------------------
582 582 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
583 583 PROCESS (clk_25, rstn_25)
584 584 BEGIN -- PROCESS
585 585 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
586 586 TAG <= (OTHERS => '0');
587 587 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
588 588 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
589 589 END IF;
590 590 END PROCESS;
591 591
592 592
593 593 END GENERATE USE_DEBUG_VECTOR_IF;
594 594
595 595 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
596 596 ahbrxd <= TAG(1);
597 597 TAG(3) <= ahbtxd;
598 598 urxd1 <= TAG(2);
599 599 TAG(4) <= utxd1;
600 600 TAG(8) <= nSRAM_BUSY;
601 601 END GENERATE USE_DEBUG_VECTOR_IF2;
602 602
603 603 END beh;
Show file before | Show file after | Hide comments
@@ -1,681 +1,684
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_sim_pkg.ALL;
32 32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.FILTERcfg.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_waveform_pkg.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_top_lfr_pkg.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL;
42 42 USE lpp.general_purpose.ALL;
43 43 --LIBRARY lpp;
44 44 USE lpp.lpp_ad_conv.ALL;
45 45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47 47
48 48 --USE work.debug.ALL;
49 49
50 50 LIBRARY gaisler;
51 51 USE gaisler.libdcom.ALL;
52 52 USE gaisler.sim.ALL;
53 53 USE gaisler.memctrl.ALL;
54 54 USE gaisler.leon3.ALL;
55 55 USE gaisler.uart.ALL;
56 56 USE gaisler.misc.ALL;
57 57 USE gaisler.spacewire.ALL;
58 58
59 59 ENTITY TB IS
60 60
61 61 END TB;
62 62
63 63 ARCHITECTURE beh OF TB IS
64 64 CONSTANT sramfile : STRING := "prom.srec";
65 65 -- CONSTANT sramfile : STRING;
66 66
67 67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
68 68
69 69 COMPONENT LFR_EQM
70 70 GENERIC (
71 71 Mem_use : INTEGER;
72 72 USE_BOOTLOADER : INTEGER;
73 73 USE_ADCDRIVER : INTEGER;
74 74 tech : INTEGER;
75 75 tech_leon : INTEGER;
76 76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 77 USE_DEBUG_VECTOR : INTEGER );
78 78 PORT (
79 79 clk50MHz : IN STD_ULOGIC;
80 80 clk49_152MHz : IN STD_ULOGIC;
81 81 reset : IN STD_ULOGIC;
82 82 --TAG1 : IN STD_ULOGIC;
83 83 --TAG3 : OUT STD_ULOGIC;
84 84 --TAG2 : IN STD_ULOGIC;
85 85 --TAG4 : OUT STD_ULOGIC;
86 86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
87 87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
88 88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 nSRAM_MBE : INOUT STD_LOGIC;
90 90 nSRAM_E1 : OUT STD_LOGIC;
91 91 nSRAM_E2 : OUT STD_LOGIC;
92 92 nSRAM_W : OUT STD_LOGIC;
93 93 nSRAM_G : OUT STD_LOGIC;
94 94 nSRAM_BUSY : IN STD_LOGIC;
95 95 spw1_en : OUT STD_LOGIC;
96 96 spw1_din : IN STD_LOGIC;
97 97 spw1_sin : IN STD_LOGIC;
98 98 spw1_dout : OUT STD_LOGIC;
99 99 spw1_sout : OUT STD_LOGIC;
100 100 spw2_en : OUT STD_LOGIC;
101 101 spw2_din : IN STD_LOGIC;
102 102 spw2_sin : IN STD_LOGIC;
103 103 spw2_dout : OUT STD_LOGIC;
104 104 spw2_sout : OUT STD_LOGIC;
105 105 bias_fail_sw : OUT STD_LOGIC;
106 106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
107 107 ADC_smpclk : OUT STD_LOGIC;
108 108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
109 109 DAC_SDO : OUT STD_LOGIC;
110 110 DAC_SCK : OUT STD_LOGIC;
111 111 DAC_SYNC : OUT STD_LOGIC;
112 112 DAC_CAL_EN : OUT STD_LOGIC;
113 113 HK_smpclk : OUT STD_LOGIC;
114 114 ADC_OEB_bar_HK : OUT STD_LOGIC;
115 115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
116 116 END COMPONENT;
117 117
118 118 SIGNAL clk50MHz : STD_ULOGIC := '0';
119 119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
120 120 SIGNAL reset : STD_ULOGIC;
121 121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
122 122 --SIGNAL TAG3 : STD_ULOGIC;
123 123 --SIGNAL TAG2 : STD_ULOGIC := '1';
124 124 --SIGNAL TAG4 : STD_ULOGIC;
125 125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 130 SIGNAL nSRAM_W : STD_LOGIC;
131 131 SIGNAL nSRAM_G : STD_LOGIC;
132 132 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 133 SIGNAL spw1_en : STD_LOGIC;
134 134 SIGNAL spw1_din : STD_LOGIC := '1';
135 135 SIGNAL spw1_sin : STD_LOGIC := '1';
136 136 SIGNAL spw1_dout : STD_LOGIC;
137 137 SIGNAL spw1_sout : STD_LOGIC;
138 138 SIGNAL spw2_en : STD_LOGIC;
139 139 SIGNAL spw2_din : STD_LOGIC := '1';
140 140 SIGNAL spw2_sin : STD_LOGIC := '1';
141 141 SIGNAL spw2_dout : STD_LOGIC;
142 142 SIGNAL spw2_sout : STD_LOGIC;
143 143 SIGNAL bias_fail_sw : STD_LOGIC;
144 144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 145 SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
147 147 SIGNAL ADC_smpclk : STD_LOGIC;
148 148 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
149 SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0);
149 150 SIGNAL DAC_SDO : STD_LOGIC;
150 151 SIGNAL DAC_SCK : STD_LOGIC;
151 152 SIGNAL DAC_SYNC : STD_LOGIC;
152 153 SIGNAL DAC_CAL_EN : STD_LOGIC;
153 154 SIGNAL HK_smpclk : STD_LOGIC;
154 155 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
155 156 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
156 157 -- SIGNAL TAG8 : STD_LOGIC;
157 158
158 159 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
159 160 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
160 161 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
161 162 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
162 163 SIGNAL counter_scrub_period : INTEGER;
163 164
164 165
165 166 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
166 167 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
167 168 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
168 169
169 170 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
170 171 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
171 172 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
172 173 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
173 174 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
174 175 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
175 176
176 177 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
177 178 SIGNAL data_message : STRING(1 TO 15) := "---------------";
178 179 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
179 180 SIGNAL TXD1 : STD_LOGIC;
180 181 SIGNAL RXD1 : STD_LOGIC;
181 182
182 183 -----------------------------------------------------------------------------
183 184 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
184 185 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
185 186 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
186 187 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
187 188 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
188 189 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
189 190 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
190 191 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
191 192 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
192 193 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
193 194 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
194 195 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
195 196 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
196 197 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
197 198
198 199
199 200 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
200 201 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
201 202
202 203 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
203 204 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
204 205
205 206 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 207 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 208 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 209 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
209 210
210 211 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
211 212 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
212 213 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
213 214
214 215
215 216 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
216 217 -----------------------------------------------------------------------------
217 218 CONSTANT srambanks : INTEGER := 2;
218 219 CONSTANT sramwidth : INTEGER := 32;
219 220 CONSTANT sramdepth : INTEGER := 19;
220 221 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
221 222 -----------------------------------------------------------------------------
222 223
223 224 BEGIN -- beh
224 225
225 226 LFR_EQM_1 : LFR_EQM
226 227 GENERIC MAP (
227 228 Mem_use => use_RAM,
228 229 USE_BOOTLOADER => 0,
229 230 USE_ADCDRIVER => 1,
230 231 tech => apa3e,
231 232 tech_leon => apa3e,
232 DEBUG_FORCE_DATA_DMA => 1,
233 DEBUG_FORCE_DATA_DMA => 0,
233 234 USE_DEBUG_VECTOR => 0)
234 235 PORT MAP (
235 236 clk50MHz => clk50MHz, --IN --ok
236 237 clk49_152MHz => clk49_152MHz, --in --ok
237 238 reset => reset, --IN --ok
238 239
239 240 TAG => TAG,
240 241 --TAG1 => TAG1, --in
241 242 --TAG3 => TAG3, --out
242 243 --TAG2 => TAG2, --IN --ok
243 244 --TAG4 => TAG4, --out --ok
244 245
245 246 address => address, --out
246 247 data => data, --inout
247 248 nSRAM_MBE => nSRAM_MBE, --inout
248 249 nSRAM_E1 => nSRAM_E1, --out
249 250 nSRAM_E2 => nSRAM_E2, --out
250 251 nSRAM_W => nSRAM_W, --out
251 252 nSRAM_G => nSRAM_G, --out
252 253 nSRAM_BUSY => nSRAM_BUSY, --in
253 254
254 255 spw1_en => spw1_en, --out --ok
255 256 spw1_din => spw1_din, --in --ok
256 257 spw1_sin => spw1_sin, --in --ok
257 258 spw1_dout => spw1_dout, --out --ok
258 259 spw1_sout => spw1_sout, --out --ok
259 260
260 261 spw2_en => spw2_en, --out --ok
261 262 spw2_din => spw2_din, --in --ok
262 263 spw2_sin => spw2_sin, --in --ok
263 264 spw2_dout => spw2_dout, --out --ok
264 265 spw2_sout => spw2_sout, --out --ok
265 266
266 267 bias_fail_sw => bias_fail_sw, --OUT --ok
267 268
268 269 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
269 270 ADC_smpclk => ADC_smpclk, --out --ok
270 271 ADC_data => ADC_data, --IN --ok
271 272
272 273 DAC_SDO => DAC_SDO, --out --ok
273 274 DAC_SCK => DAC_SCK, --out --ok
274 275 DAC_SYNC => DAC_SYNC, --out --ok
275 276 DAC_CAL_EN => DAC_CAL_EN, --out --ok
276 277
277 278 HK_smpclk => HK_smpclk, --out --ok
278 279 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
279 280 HK_SEL => HK_SEL); --out --ok
280 281
281 282
282 283 -----------------------------------------------------------------------------
283 284 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
284 285 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
285 286 -----------------------------------------------------------------------------
286 287
287 288 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
288 289 TestModule_RHF1401_1 : TestModule_RHF1401
289 290 GENERIC MAP (
290 freq => 24*(I+1),
291 amplitude => 8000/(I+1),
291 freq => 240*(I*5+1),
292 amplitude => 8000/(I*5+1),
292 293 impulsion => 0)
293 294 PORT MAP (
294 295 ADC_smpclk => ADC_smpclk,
295 ADC_OEB_bar => ADC_OEB_bar_CH(I),
296 ADC_data => ADC_data);
296 ADC_OEB_bar => ADC_OEB_bar_CH_s(I),
297 ADC_data => ADC_data_s);
297 298 END GENERATE MODULE_RHF1401;
298 299
300 ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns;
301 ADC_data <= TRANSPORT ADC_data_s AFTER 60 ns;
299 302 -----------------------------------------------------------------------------
300 303 PROCESS (clk50MHz, reset)
301 304 BEGIN -- PROCESS
302 305 IF reset = '0' THEN -- asynchronous reset (active low)
303 306 nSRAM_BUSY <= '1';
304 307 counter_scrub_period <= 0;
305 308 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
306 309 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
307 310 counter_scrub_period <= 0;
308 311 ELSE
309 312 counter_scrub_period <= counter_scrub_period + 1;
310 313 END IF;
311 314
312 315 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
313 316 nSRAM_BUSY <= '1';
314 317 ELSE
315 318 nSRAM_BUSY <= '0';
316 319 END IF;
317 320 END IF;
318 321 END PROCESS;
319 322
320 323 -----------------------------------------------------------------------------
321 324 -- TB
322 325 -----------------------------------------------------------------------------
323 326 TAG(1) <= TXD1;
324 327 TAG(2) <= '1';
325 328 RXD1 <= TAG(3);
326 329
327 330 PROCESS
328 331 CONSTANT txp : TIME := 320 ns;
329 332 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
330 333 BEGIN -- PROCESS
331 334 TXD1 <= '1';
332 335 reset <= '0';
333 336 WAIT FOR 500 ns;
334 337 reset <= '1';
335 338 WAIT FOR 100 us;
336 339 message_simu <= "0 - UART init ";
337 340 UART_INIT(TXD1, txp);
338 341
339 342 ---------------------------------------------------------------------------
340 343 -- LAUNCH leon 3 software
341 344 ---------------------------------------------------------------------------
342 345 message_simu <= "2- GO Leon3....";
343 346
344 347 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
345 348 --Force a debug break
346 349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
347 350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
348 351 --Clear time tag counter
349 352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
350 353 --Clear ASR registers
351 354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
352 355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
353 356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
354 357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
355 358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
356 359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
357 360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
358 361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
359 362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
360 363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
361 364 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
362 365 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
363 366 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
364 367 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
365 368 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
366 369
367 370 IF USE_ESA_MEMCTRL = 1 THEN
368 371 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
369 372 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
370 373 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
371 374 END IF;
372 375
373 376 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
374 377 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
375 378 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
376 379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
377 380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
378 381
379 382 --memSet(DSUBASEADDRESS+0x300000,0,1567);
380 383
381 384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
382 385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
383 386 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
384 387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
385 388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
386 389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
387 390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
388 391
389 392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
390 393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
391 394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
392 395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
393 396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
394 397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
395 398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
396 399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
397 400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
398 401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
399 402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
400 403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
401 404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
402 405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
403 406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
404 407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
405 408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
406 409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
407 410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
408 411 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
409 412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
410 413 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
411 414 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
412 415 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
413 416
414 417 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
415 418
416 419 --//Disable interrupts
417 420 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
418 421 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
419 422 -- return false;
420 423 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
421 424 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
422 425 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
423 426
424 427 -- //Set up timer
425 428 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
426 429 --if(APBTIMERBASEADD == (unsigned int)-1)
427 430 -- return false;
428 431 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
429 432 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
430 433 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
431 434
432 435
433 436 ---------------------------------------------------------------------------
434 437 --bool dsu3plugin::setCacheEnable(bool enabled)
435 438 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
436 439 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
437 440 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
438 441 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
439 442 data_read <= data_read_v;
440 443 --if(enabled){
441 444 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
442 445 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
443 446 --}else{
444 447 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
445 448 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
446 449 --}
447 450
448 451
449 452 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
450 453 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
451 454
452 455 ---------------------------------------------------------------------------
453 456 --message_simu <= "1 - UART test ";
454 457 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
455 458 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
456 459 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
457 460 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
458 461 --data_read <= data_read_v;
459 462 --data_message <= "GPIO_data_write";
460 463
461 464 -- UNSET the LFR reset
462 465 message_simu <= "2 - LFR UNRESET";
463 466 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
464 467 --
465 468 message_simu <= "3 - LFR CONFIG ";
466 469 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
467 470 ADDR_BUFFER_MS_F0_0,
468 471 ADDR_BUFFER_MS_F0_1,
469 472 ADDR_BUFFER_MS_F1_0,
470 473 ADDR_BUFFER_MS_F1_1,
471 474 ADDR_BUFFER_MS_F2_0,
472 475 ADDR_BUFFER_MS_F2_1);
473 476
474 477
475 478 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
476 479 LFR_MODE_SBM1,
477 480 X"7FFFFFFF", -- START DATE
478 481
479 482 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
480 483 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
481 484 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
482 485 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
483 486 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
484 487 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
485 488
486 489 ADDR_BASE_LFR,
487 490 ADDR_BUFFER_WFP_F0_0,
488 491 ADDR_BUFFER_WFP_F0_1,
489 492 ADDR_BUFFER_WFP_F1_0,
490 493 ADDR_BUFFER_WFP_F1_1,
491 494 ADDR_BUFFER_WFP_F2_0,
492 495 ADDR_BUFFER_WFP_F2_1,
493 496 ADDR_BUFFER_WFP_F3_0,
494 497 ADDR_BUFFER_WFP_F3_1);
495 498
496 499 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
497 500 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
498 501
499 502
500 503 ---------------------------------------------------------------------------
501 504 -- CONFIG LFR 2
502 505 ---------------------------------------------------------------------------
503 506 --message_simu <= "3 - LFR2 CONFIG";
504 507 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
505 508 -- X"40000000",
506 509 -- X"40001000",
507 510 -- X"40002000",
508 511 -- X"40003000",
509 512 -- X"40004000",
510 513 -- X"40005000");
511 514
512 515
513 516 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
514 517 -- LFR_MODE_SBM1,
515 518 -- X"7FFFFFFF", -- START DATE
516 519
517 520 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
518 521 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
519 522 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
520 523 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
521 524 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
522 525 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
523 526
524 527 -- ADDR_BASE_LFR_2,
525 528 -- X"40006000",
526 529 -- X"40007000",
527 530 -- X"40008000",
528 531 -- X"40009000",
529 532 -- X"4000A000",
530 533 -- X"4000B000",
531 534 -- X"4000C000",
532 535 -- X"4000D000");
533 536
534 537 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
535 538 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
536 539
537 540 ---------------------------------------------------------------------------
538 541 ---------------------------------------------------------------------------
539 542 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
540 543
541 544
542 545 message_simu <= "4 - GO GO GO !!";
543 546 data_message <= "---------------";
544 547 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
545 548 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
546 549
547 550
548 551 data_read_v := (OTHERS => '1');
549 552 READ_STATUS : LOOP
550 553 data_message <= "---------------";
551 554 WAIT FOR 2 ms;
552 555 data_message <= "READ_STATUS_SM_";
553 556 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
554 557 --data_message <= "--------------r";
555 558 --data_read <= data_read_v;
556 559 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
557 560
558 561 data_message <= "READ_STATUS_WF_";
559 562 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
560 563 --data_message <= "--------------r";
561 564 --data_read <= data_read_v;
562 565 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
563 566 END LOOP READ_STATUS;
564 567
565 568 WAIT;
566 569 END PROCESS;
567 570
568 571
569 572 -----------------------------------------------------------------------------
570 573 PROCESS (nSRAM_W, reset)
571 574 BEGIN -- PROCESS
572 575 IF reset = '0' THEN -- asynchronous reset (active low)
573 576 data_pre_f0 <= X"00020001";
574 577 data_pre_f1 <= X"00020001";
575 578 data_pre_f2 <= X"00020001";
576 579
577 580 addr_pre_f0 <= (OTHERS => '0');
578 581 addr_pre_f1 <= (OTHERS => '0');
579 582 addr_pre_f2 <= (OTHERS => '0');
580 583
581 584 error_wfp <= "000";
582 585 error_wfp_addr <= "000";
583 586
584 587 sample_counter <= (0,0,0);
585 588
586 589 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
587 590 error_wfp <= "000";
588 591 error_wfp_addr <= "000";
589 592 -------------------------------------------------------------------------
590 593 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
591 594 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
592 595
593 596 addr_pre_f0 <= address(13 DOWNTO 0);
594 597 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
595 598 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
596 599 error_wfp_addr(0) <= '1';
597 600 END IF;
598 601 END IF;
599 602
600 603 data_pre_f0 <= data;
601 604 CASE data_pre_f0 IS
602 605 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
603 606 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
604 607 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
605 608 WHEN OTHERS => error_wfp(0) <= '1';
606 609 END CASE;
607 610
608 611
609 612 END IF;
610 613 -------------------------------------------------------------------------
611 614 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
612 615 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
613 616
614 617 addr_pre_f1 <= address(13 DOWNTO 0);
615 618 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
616 619 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
617 620 error_wfp_addr(1) <= '1';
618 621 END IF;
619 622 END IF;
620 623
621 624 data_pre_f1 <= data;
622 625 CASE data_pre_f1 IS
623 626 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
624 627 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
625 628 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
626 629 WHEN OTHERS => error_wfp(1) <= '1';
627 630 END CASE;
628 631
629 632 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
630 633 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
631 634 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
632 635
633 636 END IF;
634 637 -------------------------------------------------------------------------
635 638 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
636 639 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
637 640
638 641 addr_pre_f2 <= address(13 DOWNTO 0);
639 642 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
640 643 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
641 644 error_wfp_addr(2) <= '1';
642 645 END IF;
643 646 END IF;
644 647
645 648 data_pre_f2 <= data;
646 649 CASE data_pre_f2 IS
647 650 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
648 651 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
649 652 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
650 653 WHEN OTHERS => error_wfp(2) <= '1';
651 654 END CASE;
652 655
653 656 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
654 657 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
655 658 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
656 659
657 660 END IF;
658 661 END IF;
659 662 END PROCESS;
660 663 -----------------------------------------------------------------------------
661 664 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
662 665
663 666 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
664 667 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
665 668 sr0 : sram
666 669 GENERIC MAP (
667 670 index => i,
668 671 abits => sramdepth,
669 672 fname => sramfile)
670 673 PORT MAP (
671 674 address,
672 675 data(31-i*8 DOWNTO 24-i*8),
673 676 ramsn(k),
674 677 nSRAM_W,
675 678 nSRAM_G
676 679 );
677 680 END GENERATE;
678 681 END GENERATE;
679 682
680 683 END beh;
681 684
Show file before | Show file after | Hide comments
@@ -1,170 +1,195
1 1 onerror {resume}
2 2 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc
3 3 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA
4 4 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA
5 5 quietly WaveActivateNextPane {} 0
6 6 add wave -noupdate -group ALL /tb/data_message
7 7 add wave -noupdate -group ALL /tb/message_simu
8 8 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
9 9 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
10 10 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
11 11 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
12 12 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
13 13 add wave -noupdate -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
14 14 add wave -noupdate -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
15 15 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
16 16 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
17 17 add wave -noupdate -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
18 18 add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
19 19 add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
20 20 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
21 21 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
22 22 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
23 23 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
24 24 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
25 25 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
26 26 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
27 27 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
28 28 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
29 29 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
30 30 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
31 31 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
32 32 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
33 33 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
34 34 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
35 35 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
36 36 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
37 37 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
38 38 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
39 39 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
40 40 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
41 41 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
42 42 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
43 43 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
44 44 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk
45 45 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
46 46 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid
47 47 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex
48 48 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn
49 49 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
50 50 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
51 51 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid
52 52 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version
53 53 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
54 54 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
55 55 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
56 56 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
57 57 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
58 58 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
59 59 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
60 60 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
61 61 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
62 62 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
63 63 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
64 64 add wave -noupdate -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0
65 65 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1
66 66 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2
67 67 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0
68 68 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1
69 69 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2
70 70 add wave -noupdate -group ALL /tb/error_wfp
71 71 add wave -noupdate -group ALL /tb/error_wfp_addr
72 72 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a
73 73 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1
74 74 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe
75 75 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we
76 76 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a
77 77 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1
78 78 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe
79 79 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we
80 80 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi
81 81 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo
82 82 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi
83 83 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso
84 84 add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi
85 85 add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo
86 86 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
87 87 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
88 88 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
89 89 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
90 90 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
91 91 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
92 92 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
93 93 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
94 94 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
95 95 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
96 96 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
97 97 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
98 98 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
99 99 add wave -noupdate -group ALL -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1)
100 100 add wave -noupdate -group ALL -height 74 -max 326.0 -min 256.0 /tb/sample_counter
101 101 add wave -noupdate -group ALL /tb/LFR_EQM_1/debug_vector
102 102 add wave -noupdate -group ALL /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
103 103 add wave -noupdate -group ALL -radix unsigned /tb/LFR_EQM_1/HWDATA
104 104 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
105 105 add wave -noupdate -group ALL -radix unsigned /tb/LFR_EQM_1/DMA_DATA
106 106 add wave -noupdate -group ALL -label DMA_REN /tb/LFR_EQM_1/debug_vector(8)
107 107 add wave -noupdate -group ALL -label HREADY /tb/LFR_EQM_1/debug_vector(5)
108 108 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk
109 109 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn
110 110 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
111 111 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
112 112 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
113 113 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
114 114 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8)
115 115 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7)
116 116 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6)
117 117 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5)
118 118 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4)
119 119 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3)
120 120 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2)
121 121 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1)
122 122 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0)
123 123 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv
124 124 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
125 125 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
126 126 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
127 127 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
128 128 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
129 129 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
130 130 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
131 131 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
132 132 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
133 133 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
134 134 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
135 135 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
136 136 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
137 137 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
138 138 add wave -noupdate -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
139 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal}} -expand -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
139 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 15 -max 7517.0 -min -7504.0 -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) {-height 15 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
140 140 add wave -noupdate -radix decimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in_val
141 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in
141 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in
142 142 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
143 143 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out
144 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg
145 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg
146 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg
147 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg
148 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg
149 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg
150 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg
151 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg
152 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim
144 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg
145 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg
146 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg
147 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg
148 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg
149 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg
150 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg
151 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix hexadecimal /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg
152 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) {-format Analog-Step -height 70 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) {-format Analog-Step -height 70 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) {-format Analog-Step -height 70 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) {-format Analog-Step -height 70 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) {-format Analog-Step -height 70 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) {-format Analog-Step -height 70 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim
153 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim
154 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim
155 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim
156 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/sample(8) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(7) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(6) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(5) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(4) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(3) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(2) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(1) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(0) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal}} /tb/LFR_EQM_1/sample
157 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample_s(8) -radix decimal} {/tb/LFR_EQM_1/sample_s(7) -radix decimal} {/tb/LFR_EQM_1/sample_s(6) -radix decimal} {/tb/LFR_EQM_1/sample_s(5) -radix decimal} {/tb/LFR_EQM_1/sample_s(4) -radix decimal} {/tb/LFR_EQM_1/sample_s(3) -radix decimal} {/tb/LFR_EQM_1/sample_s(2) -radix decimal} {/tb/LFR_EQM_1/sample_s(1) -radix decimal} {/tb/LFR_EQM_1/sample_s(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/sample_s(8) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/sample_s
158 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in
159 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim
160 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out
161 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0
162 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
163 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_data
164 add wave -noupdate /tb/LFR_EQM_1/sample_val
165 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn
166 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
167 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
168 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
169 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) {-radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) {-radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) {-radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) {-radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out
170 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_wen
171 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/wdata
172 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_data
173 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_ren
174 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_buffer_full
175 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/data
176 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
177 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/address
153 178 TreeUpdate [SetDefaultTree]
154 WaveRestoreCursors {{Cursor 1} {10205370000 ps} 0} {{Cursor 2} {3082130000 ps} 0} {{Cursor 3} {13658690000 ps} 0}
179 WaveRestoreCursors {{Cursor 1} {18490143333 ps} 0} {{Cursor 2} {3646693000 ps} 0} {{Cursor 3} {75952890000 ps} 0}
155 180 quietly wave cursor active 2
156 configure wave -namecolwidth 571
157 configure wave -valuecolwidth 347
181 configure wave -namecolwidth 493
182 configure wave -valuecolwidth 311
158 183 configure wave -justifyvalue left
159 184 configure wave -signalnamewidth 0
160 185 configure wave -snapdistance 10
161 186 configure wave -datasetprefix 0
162 187 configure wave -rowmargin 4
163 188 configure wave -childrowmargin 2
164 189 configure wave -gridoffset 0
165 190 configure wave -gridperiod 1
166 191 configure wave -griddelta 40
167 192 configure wave -timeline 0
168 193 configure wave -timelineunits ns
169 194 update
170 WaveRestoreZoom {0 ps} {6597182550 ps}
195 WaveRestoreZoom {3644529229 ps} {3652262871 ps}
Show file before | Show file after | Hide comments
@@ -1,250 +1,249
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 USE IEEE.numeric_std.ALL;
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.general_purpose.SYNC_FF;
8 8
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 12 ncycle_cnv_high : INTEGER := 25;
13 13 ncycle_cnv : INTEGER := 50;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
17 17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 18 cnv_rstn : IN STD_LOGIC;
19 19
20 20 cnv : OUT STD_LOGIC;
21 21
22 22 clk : IN STD_LOGIC; -- 25MHz
23 23 rstn : IN STD_LOGIC;
24 24 ADC_data : IN Samples14;
25 25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 27 sample_val : OUT STD_LOGIC
28 28 );
29 29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 33 SIGNAL cnv_cycle_counter : INTEGER;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
37 37 SIGNAL cnv_sync_reg : STD_LOGIC;
38 SIGNAL cnv_sync_rising : STD_LOGIC;
38 SIGNAL cnv_sync_falling : STD_LOGIC;
39 39
40 40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
41 41 SIGNAL enable_ADC : STD_LOGIC;
42 42
43 43
44 44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
45 45
46 46 SIGNAL channel_counter : INTEGER;
47 47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
48 48
49 49 SIGNAL ADC_data_selected : Samples14;
50 50 SIGNAL ADC_data_result : Samples15;
51 51
52 52 SIGNAL sample_counter : INTEGER;
53 53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54 54
55 55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
56 56
57 57 -----------------------------------------------------------------------------
58 58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 2;
59 59 CONSTANT DATA_CYCLE_VALID : INTEGER := 3;
60 60
61 61 -- GEN OutPut Enable
62 62 TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
63 63 SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
64 64 SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
65 65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1;
66 66 SIGNAL ADC_data_valid : STD_LOGIC;
67 67 SIGNAL ADC_data_reg : Samples14;
68 68 -----------------------------------------------------------------------------
69 69 CONSTANT SAMPLE_DIVISION : INTEGER := 5;
70 70 SIGNAL sample_val_s : STD_LOGIC;
71 71 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
72 72 BEGIN
73 73
74 74
75 75 -----------------------------------------------------------------------------
76 76 -- CNV GEN
77 77 -----------------------------------------------------------------------------
78 78 PROCESS (cnv_clk, cnv_rstn)
79 79 BEGIN -- PROCESS
80 80 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
81 81 cnv_cycle_counter <= 0;
82 82 cnv_s <= '0';
83 83 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
84 84 IF cnv_cycle_counter < ncycle_cnv-1 THEN
85 85 cnv_cycle_counter <= cnv_cycle_counter + 1;
86 86 IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
87 87 cnv_s <= '1';
88 88 ELSE
89 89 cnv_s <= '0';
90 90 END IF;
91 91 ELSE
92 92 cnv_s <= '1';
93 93 cnv_cycle_counter <= 0;
94 94 END IF;
95 95 END IF;
96 96 END PROCESS;
97 97
98 98 cnv <= cnv_s;
99 99
100 100 PROCESS (cnv_clk, cnv_rstn)
101 101 BEGIN -- PROCESS
102 102 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
103 103 cnv_s_reg <= '0';
104 104 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
105 105 cnv_s_reg <= cnv_s;
106 106 END IF;
107 107 END PROCESS;
108 108
109 109
110 110 -----------------------------------------------------------------------------
111 111 -- SYNC CNV
112 112 -----------------------------------------------------------------------------
113 113
114 114 SYNC_FF_cnv : SYNC_FF
115 115 GENERIC MAP (
116 116 NB_FF_OF_SYNC => 2)
117 117 PORT MAP (
118 118 clk => clk,
119 119 rstn => rstn,
120 120 A => cnv_s_reg,
121 121 A_sync => cnv_sync);
122 122
123 123 -----------------------------------------------------------------------------
124 124 --
125 125 -----------------------------------------------------------------------------
126 126 PROCESS (clk, rstn)
127 127 BEGIN -- PROCESS
128 128 IF rstn = '0' THEN -- asynchronous reset (active low)
129 129 cnv_sync_reg <= '0';
130 130 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
131 131 cnv_sync_reg <= cnv_sync;
132 132 END IF;
133 133 END PROCESS;
134 134
135 cnv_sync_rising <= '1' WHEN cnv_sync = '1' AND cnv_sync_reg = '0' ELSE '0';
135 cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0';
136 136
137 137 -----------------------------------------------------------------------------
138 138 -- GEN OutPut Enable
139 139 -----------------------------------------------------------------------------
140 140 PROCESS (clk, rstn)
141 141 BEGIN -- PROCESS
142 142 IF rstn = '0' THEN
143 143 -------------------------------------------------------------------------
144 144 ADC_nOE <= (OTHERS => '1');
145 145 ADC_current <= 0;
146 146 ADC_current_cycle_enabled <= 0;
147 147 state_GEN_OEn <= IDLE;
148 148 -------------------------------------------------------------------------
149 149 ADC_data_reg <= (OTHERS => '0');
150 150 all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
151 151 sample_reg(I) <= (OTHERS => '0');
152 152 sample(I) <= (OTHERS => '0');
153 153 END LOOP all_channel_sample_reg_init;
154 154 sample_val <= '0';
155 155 sample_val_s <= '0';
156 156 sample_val_counter <= 0;
157 157 -------------------------------------------------------------------------
158 158 ELSIF clk'event AND clk = '1' THEN
159 159 -------------------------------------------------------------------------
160 160 sample_val_s <= '0';
161 161 ADC_nOE <= (OTHERS => '1');
162 162 CASE state_GEN_OEn IS
163 163 WHEN IDLE =>
164 IF cnv_sync_rising = '1' THEN
164 IF cnv_sync_falling = '1' THEN
165 165 ADC_nOE(0) <= '0';
166 166 state_GEN_OEn <= GEN_OE;
167 167 ADC_current <= 0;
168 168 ADC_current_cycle_enabled <= 1;
169 169 END IF;
170 170
171 171 WHEN GEN_OE =>
172 172 ADC_nOE(ADC_current) <= '0';
173 173 ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
174 174 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
175 175 state_GEN_OEn <= WAIT_CYCLE;
176 176 END IF;
177 177
178 178 WHEN WAIT_CYCLE =>
179 179 ADC_current_cycle_enabled <= 0;
180 180 IF ADC_current = ChanelCount-1 THEN
181 181 state_GEN_OEn <= IDLE;
182 182 sample_val_s <= '1';
183 183 ELSE
184 184 ADC_current <= ADC_current + 1;
185 185 state_GEN_OEn <= GEN_OE;
186 186 END IF;
187 187 WHEN OTHERS => NULL;
188 188 END CASE;
189 189 -------------------------------------------------------------------------
190 190 ADC_data_reg <= ADC_data;
191 191
192 192 all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
193 193 IF ADC_data_valid = '1' AND ADC_current = I THEN
194 194 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
195 195 ELSE
196 196 sample_reg(I) <= sample_reg(I);
197 197 END IF;
198 198 END LOOP all_channel_sample_reg;
199 199 -------------------------------------------------------------------------
200 200 sample_val <= '0';
201 201 IF sample_val_s = '1' THEN
202 202 IF sample_val_counter = SAMPLE_DIVISION-1 THEN
203 203 sample_val_counter <= 0;
204 204 sample_val <= '1'; -- TODO
205 205 sample <= sample_reg;
206 206 ELSE
207 207 sample_val_counter <= sample_val_counter + 1;
208 208 sample_val <= '0';
209 209 END IF;
210 210 END IF;
211 211
212 212 END IF;
213 213 END PROCESS;
214 214
215 215 ADC_data_valid <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID ELSE '0';
216 216
217 217 WITH ADC_current SELECT
218 218 ADC_data_selected <= sample_reg(0) WHEN 0,
219 219 sample_reg(1) WHEN 1,
220 220 sample_reg(2) WHEN 2,
221 221 sample_reg(3) WHEN 3,
222 222 sample_reg(4) WHEN 4,
223 223 sample_reg(5) WHEN 5,
224 224 sample_reg(6) WHEN 6,
225 225 sample_reg(7) WHEN 7,
226 226 sample_reg(8) WHEN OTHERS ;
227 227
228 228 ADC_data_result <= std_logic_vector((
229 229 signed( ADC_data_selected(13) & ADC_data_selected) +
230 230 signed( ADC_data_reg(13) & ADC_data_reg)
231 231 ));
232 232
233 233 -- sample <= sample_reg;
234 234
235 235 END ar_top_ad_conv_RHF1401;
236 236
237 237
238 238
239 239
240 240
241 241
242 242
243 243
244 244
245 245
246 246
247 247
248 248
249 249
250
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@@ -1,579 +1,602
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 tech : INTEGER := inferred;
29 29 nb_data_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
43 43
44 44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45 45
46 46 );
47 47 PORT (
48 48 clk : IN STD_LOGIC;
49 49 rstn : IN STD_LOGIC;
50 50 -- SAMPLE
51 51 sample_B : IN Samples(2 DOWNTO 0);
52 52 sample_E : IN Samples(4 DOWNTO 0);
53 53 sample_val : IN STD_LOGIC;
54 54 -- APB
55 55 apbi : IN apb_slv_in_type;
56 56 apbo : OUT apb_slv_out_type;
57 57 -- AHB
58 58 ahbi : IN AHB_Mst_In_Type;
59 59 ahbo : OUT AHB_Mst_Out_Type;
60 60 -- TIME
61 61 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 62 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
63 63 --
64 64 data_shaping_BW : OUT STD_LOGIC;
65 65 --
66 66 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67 67 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
68 68 );
69 69 END lpp_lfr;
70 70
71 71 ARCHITECTURE beh OF lpp_lfr IS
72 72 SIGNAL sample_s : Samples(7 DOWNTO 0);
73 73 --
74 74 SIGNAL data_shaping_SP0 : STD_LOGIC;
75 75 SIGNAL data_shaping_SP1 : STD_LOGIC;
76 76 SIGNAL data_shaping_R0 : STD_LOGIC;
77 77 SIGNAL data_shaping_R1 : STD_LOGIC;
78 78 SIGNAL data_shaping_R2 : STD_LOGIC;
79 79 --
80 80 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 81 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 82 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 83 --
84 84 SIGNAL sample_f0_val : STD_LOGIC;
85 85 SIGNAL sample_f1_val : STD_LOGIC;
86 86 SIGNAL sample_f2_val : STD_LOGIC;
87 87 SIGNAL sample_f3_val : STD_LOGIC;
88 88 --
89 89 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 90 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
91 91 --
92 92 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 93 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 94 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 95 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 96 --
97 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
98 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
99 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
100 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
101 --
97 102 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 103 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 104 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 105
101 106 -- SM
102 107 SIGNAL ready_matrix_f0 : STD_LOGIC;
103 108 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
104 109 SIGNAL ready_matrix_f1 : STD_LOGIC;
105 110 SIGNAL ready_matrix_f2 : STD_LOGIC;
106 111 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
107 112 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
108 113 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
109 114 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
110 115 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 116 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 117 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 118 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
114 119 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
115 120 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
116 121
117 122 -- WFP
118 123 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 124 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 125 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 126 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
122 127 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 128 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124 129
125 130 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
126 131 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
127 132 SIGNAL enable_f0 : STD_LOGIC;
128 133 SIGNAL enable_f1 : STD_LOGIC;
129 134 SIGNAL enable_f2 : STD_LOGIC;
130 135 SIGNAL enable_f3 : STD_LOGIC;
131 136 SIGNAL burst_f0 : STD_LOGIC;
132 137 SIGNAL burst_f1 : STD_LOGIC;
133 138 SIGNAL burst_f2 : STD_LOGIC;
134 139
135 140 --SIGNAL run : STD_LOGIC;
136 141 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
137 142
138 143 -----------------------------------------------------------------------------
139 144 --
140 145 -----------------------------------------------------------------------------
141 146 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 147 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
143 148 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
144 149 --f1
145 150 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 151 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
147 152 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
148 153 --f2
149 154 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 155 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
151 156 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
152 157 --f3
153 158 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 159 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
155 160 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
156 161
157 162 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 163 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
159 164 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 165 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 166 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
162 167 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 168 -----------------------------------------------------------------------------
164 169 -- DMA RR
165 170 -----------------------------------------------------------------------------
166 171 -- SIGNAL dma_sel_valid : STD_LOGIC;
167 172 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 173 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 174 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 175 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 176
172 177 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 178 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 179
175 180 -----------------------------------------------------------------------------
176 181 -- DMA_REG
177 182 -----------------------------------------------------------------------------
178 183 -- SIGNAL ongoing_reg : STD_LOGIC;
179 184 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 185 -- SIGNAL dma_send_reg : STD_LOGIC;
181 186 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 187 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 188 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 189
185 190
186 191 -----------------------------------------------------------------------------
187 192 -- DMA
188 193 -----------------------------------------------------------------------------
189 194 -- SIGNAL dma_send : STD_LOGIC;
190 195 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
191 196 -- SIGNAL dma_done : STD_LOGIC;
192 197 -- SIGNAL dma_ren : STD_LOGIC;
193 198 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 199 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 200 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 201
197 202 -----------------------------------------------------------------------------
198 203 -- MS
199 204 -----------------------------------------------------------------------------
200 205
201 206 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 207 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 208 -- SIGNAL data_ms_valid : STD_LOGIC;
204 209 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
205 210 -- SIGNAL data_ms_ren : STD_LOGIC;
206 211 -- SIGNAL data_ms_done : STD_LOGIC;
207 212 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
208 213
209 214 -- SIGNAL run_ms : STD_LOGIC;
210 215 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
211 216
212 217 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
213 218 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
214 219 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
215 220 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
216 221
217 222
218 223 SIGNAL error_buffer_full : STD_LOGIC;
219 224 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
220 225
221 226 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 227 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 228
224 229 -----------------------------------------------------------------------------
225 230 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 231 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
227 232 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
228 233 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
229 234 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
230 235 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 236 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
232 237 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
233 238 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
234 239 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
235 240 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
236 241 SIGNAL dma_grant_error : STD_LOGIC;
237 242
238 243 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
239 244 -----------------------------------------------------------------------------
240 245 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 246 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
242 247 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 248 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 249 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 250
246 251 BEGIN
247 252
248 253 --apb_reg_debug_vector;
249 254 -----------------------------------------------------------------------------
250 255
251 256 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
252 257 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
253 258 sample_time <= coarse_time & fine_time;
254 259
255 260 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
256 261 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
257 262 --END GENERATE all_channel;
258 263
259 264 -----------------------------------------------------------------------------
260 265 lpp_lfr_filter_1 : lpp_lfr_filter
261 266 GENERIC MAP (
262 267 Mem_use => Mem_use)
263 268 PORT MAP (
264 269 sample => sample_s,
265 270 sample_val => sample_val,
266 271 sample_time => sample_time,
267 272 clk => clk,
268 273 rstn => rstn,
269 274 data_shaping_SP0 => data_shaping_SP0,
270 275 data_shaping_SP1 => data_shaping_SP1,
271 276 data_shaping_R0 => data_shaping_R0,
272 277 data_shaping_R1 => data_shaping_R1,
273 278 data_shaping_R2 => data_shaping_R2,
274 279 sample_f0_val => sample_f0_val,
275 280 sample_f1_val => sample_f1_val,
276 281 sample_f2_val => sample_f2_val,
277 282 sample_f3_val => sample_f3_val,
278 283 sample_f0_wdata => sample_f0_data,
279 284 sample_f1_wdata => sample_f1_data,
280 285 sample_f2_wdata => sample_f2_data,
281 286 sample_f3_wdata => sample_f3_data,
282 287 sample_f0_time => sample_f0_time,
283 288 sample_f1_time => sample_f1_time,
284 289 sample_f2_time => sample_f2_time,
285 290 sample_f3_time => sample_f3_time
286 291 );
287 292
288 293 -----------------------------------------------------------------------------
289 294 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
290 295 GENERIC MAP (
291 296 nb_data_by_buffer_size => nb_data_by_buffer_size,
292 297 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
293 298 nb_snapshot_param_size => nb_snapshot_param_size,
294 299 delta_vector_size => delta_vector_size,
295 300 delta_vector_size_f0_2 => delta_vector_size_f0_2,
296 301 pindex => pindex,
297 302 paddr => paddr,
298 303 pmask => pmask,
299 304 pirq_ms => pirq_ms,
300 305 pirq_wfp => pirq_wfp,
301 306 top_lfr_version => top_lfr_version)
302 307 PORT MAP (
303 308 HCLK => clk,
304 309 HRESETn => rstn,
305 310 apbi => apbi,
306 311 apbo => apbo,
307 312
308 313 run_ms => OPEN,--run_ms,
309 314
310 315 ready_matrix_f0 => ready_matrix_f0,
311 316 ready_matrix_f1 => ready_matrix_f1,
312 317 ready_matrix_f2 => ready_matrix_f2,
313 318 error_buffer_full => error_buffer_full, -- TODO
314 319 error_input_fifo_write => error_input_fifo_write, -- TODO
315 320 status_ready_matrix_f0 => status_ready_matrix_f0,
316 321 status_ready_matrix_f1 => status_ready_matrix_f1,
317 322 status_ready_matrix_f2 => status_ready_matrix_f2,
318 323
319 324 matrix_time_f0 => matrix_time_f0,
320 325 matrix_time_f1 => matrix_time_f1,
321 326 matrix_time_f2 => matrix_time_f2,
322 327
323 328 addr_matrix_f0 => addr_matrix_f0,
324 329 addr_matrix_f1 => addr_matrix_f1,
325 330 addr_matrix_f2 => addr_matrix_f2,
326 331
327 332 length_matrix_f0 => length_matrix_f0,
328 333 length_matrix_f1 => length_matrix_f1,
329 334 length_matrix_f2 => length_matrix_f2,
330 335 -------------------------------------------------------------------------
331 336 --status_full => status_full, -- TODo
332 337 --status_full_ack => status_full_ack, -- TODo
333 338 --status_full_err => status_full_err, -- TODo
334 339 status_new_err => status_new_err,
335 340 data_shaping_BW => data_shaping_BW,
336 341 data_shaping_SP0 => data_shaping_SP0,
337 342 data_shaping_SP1 => data_shaping_SP1,
338 343 data_shaping_R0 => data_shaping_R0,
339 344 data_shaping_R1 => data_shaping_R1,
340 345 data_shaping_R2 => data_shaping_R2,
341 346 delta_snapshot => delta_snapshot,
342 347 delta_f0 => delta_f0,
343 348 delta_f0_2 => delta_f0_2,
344 349 delta_f1 => delta_f1,
345 350 delta_f2 => delta_f2,
346 351 nb_data_by_buffer => nb_data_by_buffer,
347 352 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
348 353 nb_snapshot_param => nb_snapshot_param,
349 354 enable_f0 => enable_f0,
350 355 enable_f1 => enable_f1,
351 356 enable_f2 => enable_f2,
352 357 enable_f3 => enable_f3,
353 358 burst_f0 => burst_f0,
354 359 burst_f1 => burst_f1,
355 360 burst_f2 => burst_f2,
356 361 run => OPEN, --run,
357 362 start_date => start_date,
358 363 -- debug_signal => debug_signal,
359 364 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
360 365 wfp_addr_buffer => wfp_addr_buffer,-- TODO
361 366 wfp_length_buffer => wfp_length_buffer,-- TODO
362 367
363 368 wfp_ready_buffer => wfp_ready_buffer,-- TODO
364 369 wfp_buffer_time => wfp_buffer_time,-- TODO
365 370 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
366 371 -------------------------------------------------------------------------
367 372 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
368 373 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
369 374 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
370 375 sample_f3_valid => sample_f3_val,
371 376 debug_vector => apb_reg_debug_vector
372 377 );
373 378
374 379 -----------------------------------------------------------------------------
375 380 -----------------------------------------------------------------------------
376 381 lpp_waveform_1 : lpp_waveform
377 382 GENERIC MAP (
378 383 tech => tech,
379 384 data_size => 6*16,
380 385 nb_data_by_buffer_size => nb_data_by_buffer_size,
381 386 nb_snapshot_param_size => nb_snapshot_param_size,
382 387 delta_vector_size => delta_vector_size,
383 388 delta_vector_size_f0_2 => delta_vector_size_f0_2
384 389 )
385 390 PORT MAP (
386 391 clk => clk,
387 392 rstn => rstn,
388 393
389 394 reg_run => '1',--run,
390 395 reg_start_date => start_date,
391 396 reg_delta_snapshot => delta_snapshot,
392 397 reg_delta_f0 => delta_f0,
393 398 reg_delta_f0_2 => delta_f0_2,
394 399 reg_delta_f1 => delta_f1,
395 400 reg_delta_f2 => delta_f2,
396 401
397 402 enable_f0 => enable_f0,
398 403 enable_f1 => enable_f1,
399 404 enable_f2 => enable_f2,
400 405 enable_f3 => enable_f3,
401 406 burst_f0 => burst_f0,
402 407 burst_f1 => burst_f1,
403 408 burst_f2 => burst_f2,
404 409
405 410 nb_data_by_buffer => nb_data_by_buffer,
406 411 nb_snapshot_param => nb_snapshot_param,
407 412 status_new_err => status_new_err,
408 413
409 414 status_buffer_ready => wfp_status_buffer_ready,
410 415 addr_buffer => wfp_addr_buffer,
411 416 length_buffer => wfp_length_buffer,
412 417 ready_buffer => wfp_ready_buffer,
413 418 buffer_time => wfp_buffer_time,
414 419 error_buffer_full => wfp_error_buffer_full,
415 420
416 421 coarse_time => coarse_time,
417 422 -- fine_time => fine_time,
418 423
419 424 --f0
420 425 data_f0_in_valid => sample_f0_val,
421 426 data_f0_in => sample_f0_data,
422 427 data_f0_time => sample_f0_time,
423 428 --f1
424 429 data_f1_in_valid => sample_f1_val,
425 430 data_f1_in => sample_f1_data,
426 431 data_f1_time => sample_f1_time,
427 432 --f2
428 433 data_f2_in_valid => sample_f2_val,
429 434 data_f2_in => sample_f2_data,
430 435 data_f2_time => sample_f2_time,
431 436 --f3
432 437 data_f3_in_valid => sample_f3_val,
433 438 data_f3_in => sample_f3_data,
434 439 data_f3_time => sample_f3_time,
435 440 -- OUTPUT -- DMA interface
436 441
437 442 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
438 443 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
439 444 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
440 445 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
441 446 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
442 447 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
443 448 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
444 449 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
445 450
446 451 );
447 452
448 453 -----------------------------------------------------------------------------
449 454 -- Matrix Spectral
450 455 -----------------------------------------------------------------------------
451 456 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
452 457 NOT(sample_f0_val) & NOT(sample_f0_val);
453 458 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
454 459 NOT(sample_f1_val) & NOT(sample_f1_val);
455 460 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
456 461 NOT(sample_f2_val) & NOT(sample_f2_val);
457 462
458 463
459 464 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
460 465 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
461 466 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
462 467
463 468 -------------------------------------------------------------------------------
464 469
465 470 --ms_softandhard_rstn <= rstn AND run_ms AND run;
466 471
467 472 -----------------------------------------------------------------------------
468 473 lpp_lfr_ms_1 : lpp_lfr_ms
469 474 GENERIC MAP (
470 475 Mem_use => Mem_use)
471 476 PORT MAP (
472 477 clk => clk,
473 478 --rstn => ms_softandhard_rstn, --rstn,
474 479 rstn => rstn,
475 480
476 481 run => '1',--run_ms,
477 482
478 483 start_date => start_date,
479 484
480 485 coarse_time => coarse_time,
481 486
482 487 sample_f0_wen => sample_f0_wen,
483 488 sample_f0_wdata => sample_f0_wdata,
484 489 sample_f0_time => sample_f0_time,
485 490 sample_f1_wen => sample_f1_wen,
486 491 sample_f1_wdata => sample_f1_wdata,
487 492 sample_f1_time => sample_f1_time,
488 493 sample_f2_wen => sample_f2_wen,
489 494 sample_f2_wdata => sample_f2_wdata,
490 495 sample_f2_time => sample_f2_time,
491 496
492 497 --DMA
493 498 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
494 499 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
495 500 dma_fifo_ren => dma_fifo_ren(4), -- IN
496 501 dma_buffer_new => dma_buffer_new(4), -- OUT
497 502 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
498 503 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
499 504 dma_buffer_full => dma_buffer_full(4), -- IN
500 505 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
501 506
502 507
503 508
504 509 --REG
505 510 ready_matrix_f0 => ready_matrix_f0,
506 511 ready_matrix_f1 => ready_matrix_f1,
507 512 ready_matrix_f2 => ready_matrix_f2,
508 513 error_buffer_full => error_buffer_full,
509 514 error_input_fifo_write => error_input_fifo_write,
510 515
511 516 status_ready_matrix_f0 => status_ready_matrix_f0,
512 517 status_ready_matrix_f1 => status_ready_matrix_f1,
513 518 status_ready_matrix_f2 => status_ready_matrix_f2,
514 519 addr_matrix_f0 => addr_matrix_f0,
515 520 addr_matrix_f1 => addr_matrix_f1,
516 521 addr_matrix_f2 => addr_matrix_f2,
517 522
518 523 length_matrix_f0 => length_matrix_f0,
519 524 length_matrix_f1 => length_matrix_f1,
520 525 length_matrix_f2 => length_matrix_f2,
521 526
522 527 matrix_time_f0 => matrix_time_f0,
523 528 matrix_time_f1 => matrix_time_f1,
524 529 matrix_time_f2 => matrix_time_f2,
525 530
526 531 debug_vector => debug_vector_ms);
527 532
528 533 -----------------------------------------------------------------------------
529 534 PROCESS (clk, rstn)
530 535 BEGIN
531 536 IF rstn = '0' THEN
532 537 dma_fifo_data_forced_gen <= X"00040003";
533 538 ELSIF clk'event AND clk = '1' THEN
534 539 IF dma_fifo_ren(0) = '0' THEN
535 540 CASE dma_fifo_data_forced_gen IS
536 541 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
537 542 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
538 543 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
539 544 WHEN OTHERS => NULL;
540 545 END CASE;
541 546 END IF;
542 547 END IF;
543 548 END PROCESS;
544 549
545 550 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
546 551 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
547 552 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
548 553 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
549 554 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
550 555
551 556 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
552 557
553 558 DMA_SubSystem_1 : DMA_SubSystem
554 559 GENERIC MAP (
555 560 hindex => hindex,
556 561 CUSTOM_DMA => 1)
557 562 PORT MAP (
558 563 clk => clk,
559 564 rstn => rstn,
560 565 run => '1',--run_dma,
561 566 ahbi => ahbi,
562 567 ahbo => ahbo,
563 568
564 569 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
565 570 fifo_data => dma_fifo_data_debug, --fifo_data,
566 571 fifo_ren => dma_fifo_ren, --fifo_ren,
567 572
568 573 buffer_new => dma_buffer_new, --buffer_new,
569 574 buffer_addr => dma_buffer_addr, --buffer_addr,
570 575 buffer_length => dma_buffer_length, --buffer_length,
571 576 buffer_full => dma_buffer_full, --buffer_full,
572 577 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
573 578 grant_error => dma_grant_error,
574 579 debug_vector => debug_vector(8 DOWNTO 0)
575 580 ); --grant_error);
576 581
577
582 -----------------------------------------------------------------------------
583 -- OBSERVATION for SIMULATION
584 all_channel_sim: FOR I IN 0 TO 5 GENERATE
585 PROCESS (clk, rstn)
586 BEGIN -- PROCESS
587 IF rstn = '0' THEN -- asynchronous reset (active low)
588 sample_f0_data_sim(I) <= (OTHERS => '0');
589 sample_f1_data_sim(I) <= (OTHERS => '0');
590 sample_f2_data_sim(I) <= (OTHERS => '0');
591 sample_f3_data_sim(I) <= (OTHERS => '0');
592 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
593 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
594 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
595 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
596 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
597 END IF;
598 END PROCESS;
599 END GENERATE all_channel_sim;
600 -----------------------------------------------------------------------------
578 601
579 602 END beh;
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@@ -1,485 +1,485
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_waveform IS
42 42
43 43 GENERIC (
44 44 tech : INTEGER := inferred;
45 45 data_size : INTEGER := 96; --16*6
46 46 nb_data_by_buffer_size : INTEGER := 11;
47 47 -- nb_word_by_buffer_size : INTEGER := 11;
48 48 nb_snapshot_param_size : INTEGER := 11;
49 49 delta_vector_size : INTEGER := 20;
50 50 delta_vector_size_f0_2 : INTEGER := 3);
51 51
52 52 PORT (
53 53 clk : IN STD_LOGIC;
54 54 rstn : IN STD_LOGIC;
55 55
56 56 ---- AMBA AHB Master Interface
57 57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59 59
60 60 --config
61 61 reg_run : IN STD_LOGIC;
62 62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68 68
69 69 enable_f0 : IN STD_LOGIC;
70 70 enable_f1 : IN STD_LOGIC;
71 71 enable_f2 : IN STD_LOGIC;
72 72 enable_f3 : IN STD_LOGIC;
73 73
74 74 burst_f0 : IN STD_LOGIC;
75 75 burst_f1 : IN STD_LOGIC;
76 76 burst_f2 : IN STD_LOGIC;
77 77
78 78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 81
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83
84 84
85 85 -- REG DMA
86 86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89
90 90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93 93
94 94 ---------------------------------------------------------------------------
95 95 -- INPUT
96 96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98 98
99 99 --f0
100 100 data_f0_in_valid : IN STD_LOGIC;
101 101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 102 data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
103 103 --f1
104 104 data_f1_in_valid : IN STD_LOGIC;
105 105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 106 data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
107 107 --f2
108 108 data_f2_in_valid : IN STD_LOGIC;
109 109 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 110 data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
111 111 --f3
112 112 data_f3_in_valid : IN STD_LOGIC;
113 113 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
114 114 data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
115 115
116 116 ---------------------------------------------------------------------------
117 117 -- DMA --------------------------------------------------------------------
118 118
119 119 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
120 120 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
121 121 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 122 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
123 123 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
124 124 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
125 125 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
126 126 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
127 127
128 128 );
129 129
130 130 END lpp_waveform;
131 131
132 132 ARCHITECTURE beh OF lpp_waveform IS
133 133 SIGNAL start_snapshot_f0 : STD_LOGIC;
134 134 SIGNAL start_snapshot_f1 : STD_LOGIC;
135 135 SIGNAL start_snapshot_f2 : STD_LOGIC;
136 136
137 137 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 138 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 139 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 140 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141
142 142 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 143 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 144 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 145 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 146
147 147 SIGNAL data_f0_out_valid : STD_LOGIC;
148 148 SIGNAL data_f1_out_valid : STD_LOGIC;
149 149 SIGNAL data_f2_out_valid : STD_LOGIC;
150 150 SIGNAL data_f3_out_valid : STD_LOGIC;
151 151 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
152 152 --
153 153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 156 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 157 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 158 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 162 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 163 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 164 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 165 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 166 --
167 167 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 168 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 169 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 170 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 171 --
172 172 SIGNAL run : STD_LOGIC;
173 173 --
174 174 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
175 175 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
176 176 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
177 177 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
178 178 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
179 179 SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
180 180 SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
181 181 --
182 182
183 183 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
184 184 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 185 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 186 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
188 188
189 189 --
190 190 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 191 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 192
193 193 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
194 194
195 195 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
196 196
197 197 BEGIN -- beh
198 198
199 199 -----------------------------------------------------------------------------
200 200
201 201 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
202 202 GENERIC MAP (
203 203 delta_vector_size => delta_vector_size,
204 204 delta_vector_size_f0_2 => delta_vector_size_f0_2
205 205 )
206 206 PORT MAP (
207 207 clk => clk,
208 208 rstn => rstn,
209 209 reg_run => reg_run,
210 210 reg_start_date => reg_start_date,
211 211 reg_delta_snapshot => reg_delta_snapshot,
212 212 reg_delta_f0 => reg_delta_f0,
213 213 reg_delta_f0_2 => reg_delta_f0_2,
214 214 reg_delta_f1 => reg_delta_f1,
215 215 reg_delta_f2 => reg_delta_f2,
216 216 coarse_time => coarse_time(30 DOWNTO 0),
217 217 data_f0_valid => data_f0_in_valid,
218 218 data_f2_valid => data_f2_in_valid,
219 219 start_snapshot_f0 => start_snapshot_f0,
220 220 start_snapshot_f1 => start_snapshot_f1,
221 221 start_snapshot_f2 => start_snapshot_f2,
222 222 wfp_on => run);
223 223
224 224 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
225 225 GENERIC MAP (
226 226 data_size => data_size,
227 227 nb_snapshot_param_size => nb_snapshot_param_size)
228 228 PORT MAP (
229 229 clk => clk,
230 230 rstn => rstn,
231 231 run => run,
232 232 enable => enable_f0,
233 233 burst_enable => burst_f0,
234 234 nb_snapshot_param => nb_snapshot_param,
235 235 start_snapshot => start_snapshot_f0,
236 236 data_in => data_f0_in,
237 237 data_in_valid => data_f0_in_valid,
238 238 data_out => data_f0_out,
239 239 data_out_valid => data_f0_out_valid);
240 240
241 241 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
242 242
243 243 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
244 244 GENERIC MAP (
245 245 data_size => data_size,
246 246 nb_snapshot_param_size => nb_snapshot_param_size+1)
247 247 PORT MAP (
248 248 clk => clk,
249 249 rstn => rstn,
250 250 run => run,
251 251 enable => enable_f1,
252 252 burst_enable => burst_f1,
253 253 nb_snapshot_param => nb_snapshot_param_more_one,
254 254 start_snapshot => start_snapshot_f1,
255 255 data_in => data_f1_in,
256 256 data_in_valid => data_f1_in_valid,
257 257 data_out => data_f1_out,
258 258 data_out_valid => data_f1_out_valid);
259 259
260 260 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
261 261 GENERIC MAP (
262 262 data_size => data_size,
263 263 nb_snapshot_param_size => nb_snapshot_param_size+1)
264 264 PORT MAP (
265 265 clk => clk,
266 266 rstn => rstn,
267 267 run => run,
268 268 enable => enable_f2,
269 269 burst_enable => burst_f2,
270 270 nb_snapshot_param => nb_snapshot_param_more_one,
271 271 start_snapshot => start_snapshot_f2,
272 272 data_in => data_f2_in,
273 273 data_in_valid => data_f2_in_valid,
274 274 data_out => data_f2_out,
275 275 data_out_valid => data_f2_out_valid);
276 276
277 277 lpp_waveform_burst_f3 : lpp_waveform_burst
278 278 GENERIC MAP (
279 279 data_size => data_size)
280 280 PORT MAP (
281 281 clk => clk,
282 282 rstn => rstn,
283 283 run => run,
284 284 enable => enable_f3,
285 285 data_in => data_f3_in,
286 286 data_in_valid => data_f3_in_valid,
287 287 data_out => data_f3_out,
288 288 data_out_valid => data_f3_out_valid);
289 289
290 290 -----------------------------------------------------------------------------
291 291 -- DEBUG -- SNAPSHOT OUT
292 292 --debug_f0_data_valid <= data_f0_out_valid;
293 293 --debug_f0_data <= data_f0_out;
294 294 --debug_f1_data_valid <= data_f1_out_valid;
295 295 --debug_f1_data <= data_f1_out;
296 296 --debug_f2_data_valid <= data_f2_out_valid;
297 297 --debug_f2_data <= data_f2_out;
298 298 --debug_f3_data_valid <= data_f3_out_valid;
299 299 --debug_f3_data <= data_f3_out;
300 300 -----------------------------------------------------------------------------
301 301
302 302 PROCESS (clk, rstn)
303 303 BEGIN -- PROCESS
304 304 IF rstn = '0' THEN -- asynchronous reset (active low)
305 305 time_reg1 <= (OTHERS => '0');
306 306 time_reg2 <= (OTHERS => '0');
307 307 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
308 308 time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16);
309 309 time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16);
310 310 time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16);
311 311 time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16);
312 312 time_reg2 <= time_reg1;
313 313 END IF;
314 314 END PROCESS;
315 315
316 316 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
317 317 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
318 318 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
319 319 PORT MAP (
320 320 HCLK => clk,
321 321 HRESETn => rstn,
322 322 run => run,
323 323 valid_in => valid_in(I),
324 324 ack_in => valid_ack(I),
325 325 time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo
326 326 valid_out => valid_out(I),
327 327 time_out => time_out(I), -- Todo
328 328 error => status_new_err(I));
329 329 END GENERATE all_input_valid;
330 330
331 331 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
332 332 data_f0_out((16*6)-1 DOWNTO 16*5) &
333 333 data_f0_out((16*3)-1 DOWNTO 16*2) &
334 334 data_f0_out((16*4)-1 DOWNTO 16*3) &
335 335 data_f0_out((16*1)-1 DOWNTO 16*0) &
336 336 data_f0_out((16*2)-1 DOWNTO 16*1) ;
337 337
338 338 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
339 339 data_f1_out((16*6)-1 DOWNTO 16*5) &
340 340 data_f1_out((16*3)-1 DOWNTO 16*2) &
341 341 data_f1_out((16*4)-1 DOWNTO 16*3) &
342 342 data_f1_out((16*1)-1 DOWNTO 16*0) &
343 343 data_f1_out((16*2)-1 DOWNTO 16*1) ;
344 344
345 345 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
346 346 data_f2_out((16*6)-1 DOWNTO 16*5) &
347 347 data_f2_out((16*3)-1 DOWNTO 16*2) &
348 348 data_f2_out((16*4)-1 DOWNTO 16*3) &
349 349 data_f2_out((16*1)-1 DOWNTO 16*0) &
350 350 data_f2_out((16*2)-1 DOWNTO 16*1) ;
351 351
352 352 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
353 353 data_f3_out((16*6)-1 DOWNTO 16*5) &
354 354 data_f3_out((16*3)-1 DOWNTO 16*2) &
355 355 data_f3_out((16*4)-1 DOWNTO 16*3) &
356 356 data_f3_out((16*1)-1 DOWNTO 16*0) &
357 357 data_f3_out((16*2)-1 DOWNTO 16*1) ;
358 358
359 359 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
360 360 data_out(0, I) <= data_f0_out_swap(I);
361 361 data_out(1, I) <= data_f1_out_swap(I);
362 362 data_out(2, I) <= data_f2_out_swap(I);
363 363 data_out(3, I) <= data_f3_out_swap(I);
364 364 END GENERATE all_bit_of_data_out;
365 365
366 366 -----------------------------------------------------------------------------
367 367 -- TODO : debug
368 368 -----------------------------------------------------------------------------
369 369 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
370 370 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
371 371 time_out_2(J, I) <= time_out(J)(I);
372 372 END GENERATE all_sample_of_time_out;
373 373 END GENERATE all_bit_of_time_out;
374 374
375 375 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
376 376 GENERIC MAP (tech => tech,
377 377 nb_data_by_buffer_size => nb_data_by_buffer_size)
378 378 PORT MAP (
379 379 clk => clk,
380 380 rstn => rstn,
381 381 run => run,
382 382 nb_data_by_buffer => nb_data_by_buffer,
383 383 data_in_valid => valid_out,
384 384 data_in_ack => valid_ack,
385 385 data_in => data_out,
386 386 time_in => time_out_2,
387 387
388 388 data_out => wdata,
389 389 data_out_wen => data_wen,
390 390 full_almost => full_almost,
391 391 full => full,
392 392
393 393 time_out => arbiter_time_out,
394 394 time_out_new => arbiter_time_out_new
395 395
396 396 );
397 397
398 398 -----------------------------------------------------------------------------
399 399 -----------------------------------------------------------------------------
400 400
401 401 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
402 402 lpp_fifo_1: lpp_fifo
403 403 GENERIC MAP (
404 tech => tech,
404 tech => 0,
405 405 Mem_use => use_RAM,
406 406 EMPTY_THRESHOLD_LIMIT => 15,
407 407 FULL_THRESHOLD_LIMIT => 3,
408 408 DataSz => 32,
409 409 AddrSz => 7)
410 410 PORT MAP (
411 411 clk => clk,
412 412 rstn => rstn,
413 413 reUse => '0',
414 414 run => run,
415 415 ren => data_ren(I),
416 416 rdata => s_rdata_v((I+1)*32-1 downto I*32),
417 417 wen => data_wen(I),
418 418 wdata => wdata,
419 419 empty => empty(I),
420 420 full => full(I),
421 421 full_almost => OPEN,
422 422 empty_threshold => empty_almost(I),
423 423 full_threshold => full_almost(I) );
424 424
425 425 END GENERATE generate_all_fifo;
426 426
427 427 -----------------------------------------------------------------------------
428 428 --
429 429 -----------------------------------------------------------------------------
430 430
431 431 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
432 432
433 433 PROCESS (clk, rstn)
434 434 BEGIN
435 435 IF rstn = '0' THEN
436 436 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
437 437 ELSIF clk'event AND clk = '1' THEN
438 438 IF run = '0' THEN
439 439 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
440 440 ELSE
441 441 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
442 442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
443 443 END IF;
444 444 END IF;
445 445 END IF;
446 446 END PROCESS;
447 447
448 448 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
449 449 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
450 450
451 451 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
452 452 PORT MAP (
453 453 clk => clk,
454 454 rstn => rstn,
455 455 run => run,
456 456
457 457 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
458 458
459 459 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
460 460 fifo_empty => empty(I),
461 461 fifo_empty_threshold => empty_almost(I),
462 462 fifo_ren => data_ren(I),
463 463
464 464 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
465 465 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
466 466 dma_fifo_ren => dma_fifo_ren(I),
467 467 dma_buffer_new => dma_buffer_new(I),
468 468 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
469 469 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
470 470 dma_buffer_full => dma_buffer_full(I),
471 471 dma_buffer_full_err => dma_buffer_full_err(I),
472 472
473 473 status_buffer_ready => status_buffer_ready(I), -- TODO
474 474 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
475 475 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
476 476 ready_buffer => ready_buffer(I), -- TODO
477 477 buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
478 478 error_buffer_full => error_buffer_full(I)); -- TODO
479 479
480 480 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
481 481
482 482 END GENERATE all_channel;
483 483
484 484
485 485 END beh;
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