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Simu MINI-LFR_WFP_MS ...
pellion -
r459:04433c638db7 JC
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1 vcom -quiet -93 -work work MINI_LFR_top.vhd
2 vcom -quiet -93 -work work testbench.vhd
3
4 vsim work.testbench
5
6 log -r *
7
8 do wave.do
9
10 run 250 us
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
22 ENTITY testbench IS
23 END;
24
25 ARCHITECTURE behav OF testbench IS
26
27 COMPONENT MINI_LFR_top
28 PORT (
29 clk_50 : IN STD_LOGIC;
30 clk_49 : IN STD_LOGIC;
31 reset : IN STD_LOGIC;
32 BP0 : IN STD_LOGIC;
33 BP1 : IN STD_LOGIC;
34 LED0 : OUT STD_LOGIC;
35 LED1 : OUT STD_LOGIC;
36 LED2 : OUT STD_LOGIC;
37 TXD1 : IN STD_LOGIC;
38 RXD1 : OUT STD_LOGIC;
39 nCTS1 : OUT STD_LOGIC;
40 nRTS1 : IN STD_LOGIC;
41 TXD2 : IN STD_LOGIC;
42 RXD2 : OUT STD_LOGIC;
43 nCTS2 : OUT STD_LOGIC;
44 nDTR2 : IN STD_LOGIC;
45 nRTS2 : IN STD_LOGIC;
46 nDCD2 : OUT STD_LOGIC;
47 IO0 : INOUT STD_LOGIC;
48 IO1 : INOUT STD_LOGIC;
49 IO2 : INOUT STD_LOGIC;
50 IO3 : INOUT STD_LOGIC;
51 IO4 : INOUT STD_LOGIC;
52 IO5 : INOUT STD_LOGIC;
53 IO6 : INOUT STD_LOGIC;
54 IO7 : INOUT STD_LOGIC;
55 IO8 : INOUT STD_LOGIC;
56 IO9 : INOUT STD_LOGIC;
57 IO10 : INOUT STD_LOGIC;
58 IO11 : INOUT STD_LOGIC;
59 SPW_EN : OUT STD_LOGIC;
60 SPW_NOM_DIN : IN STD_LOGIC;
61 SPW_NOM_SIN : IN STD_LOGIC;
62 SPW_NOM_DOUT : OUT STD_LOGIC;
63 SPW_NOM_SOUT : OUT STD_LOGIC;
64 SPW_RED_DIN : IN STD_LOGIC;
65 SPW_RED_SIN : IN STD_LOGIC;
66 SPW_RED_DOUT : OUT STD_LOGIC;
67 SPW_RED_SOUT : OUT STD_LOGIC;
68 ADC_nCS : OUT STD_LOGIC;
69 ADC_CLK : OUT STD_LOGIC;
70 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
71 SRAM_nWE : OUT STD_LOGIC;
72 SRAM_CE : OUT STD_LOGIC;
73 SRAM_nOE : OUT STD_LOGIC;
74 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
76 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
77 END COMPONENT;
78
79 -----------------------------------------------------------------------------
80 SIGNAL clk_50 : STD_LOGIC := '0';
81 SIGNAL clk_49 : STD_LOGIC := '0';
82 SIGNAL reset : STD_LOGIC;
83 SIGNAL BP0 : STD_LOGIC;
84 SIGNAL BP1 : STD_LOGIC;
85 SIGNAL LED0 : STD_LOGIC;
86 SIGNAL LED1 : STD_LOGIC;
87 SIGNAL LED2 : STD_LOGIC;
88 SIGNAL TXD1 : STD_LOGIC;
89 SIGNAL RXD1 : STD_LOGIC;
90 SIGNAL nCTS1 : STD_LOGIC;
91 SIGNAL nRTS1 : STD_LOGIC;
92 SIGNAL TXD2 : STD_LOGIC;
93 SIGNAL RXD2 : STD_LOGIC;
94 SIGNAL nCTS2 : STD_LOGIC;
95 SIGNAL nDTR2 : STD_LOGIC;
96 SIGNAL nRTS2 : STD_LOGIC;
97 SIGNAL nDCD2 : STD_LOGIC;
98 SIGNAL IO0 : STD_LOGIC;
99 SIGNAL IO1 : STD_LOGIC;
100 SIGNAL IO2 : STD_LOGIC;
101 SIGNAL IO3 : STD_LOGIC;
102 SIGNAL IO4 : STD_LOGIC;
103 SIGNAL IO5 : STD_LOGIC;
104 SIGNAL IO6 : STD_LOGIC;
105 SIGNAL IO7 : STD_LOGIC;
106 SIGNAL IO8 : STD_LOGIC;
107 SIGNAL IO9 : STD_LOGIC;
108 SIGNAL IO10 : STD_LOGIC;
109 SIGNAL IO11 : STD_LOGIC;
110 SIGNAL SPW_EN : STD_LOGIC;
111 SIGNAL SPW_NOM_DIN : STD_LOGIC;
112 SIGNAL SPW_NOM_SIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
114 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
115 SIGNAL SPW_RED_DIN : STD_LOGIC;
116 SIGNAL SPW_RED_SIN : STD_LOGIC;
117 SIGNAL SPW_RED_DOUT : STD_LOGIC;
118 SIGNAL SPW_RED_SOUT : STD_LOGIC;
119 SIGNAL ADC_nCS : STD_LOGIC;
120 SIGNAL ADC_CLK : STD_LOGIC;
121 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
122 SIGNAL SRAM_nWE : STD_LOGIC;
123 SIGNAL SRAM_CE : STD_LOGIC;
124 SIGNAL SRAM_nOE : STD_LOGIC;
125 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
127 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
129
130 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
131 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
132 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
133
134
135 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
136
137 BEGIN
138
139 -----------------------------------------------------------------------------
140 -- TB
141 -----------------------------------------------------------------------------
142 PROCESS
143 CONSTANT txp : TIME := 320 ns;
144 BEGIN -- PROCESS
145 TXD1 <= '1';
146 reset <= '0';
147 WAIT FOR 500 ns;
148 reset <= '1';
149 WAIT FOR 10000 ns;
150 message_simu <= "0 - UART init ";
151 UART_INIT(TXD1,txp);
152
153 message_simu <= "1 - UART test ";
154 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
157
158 -- UNSET the LFR reset
159 message_simu <= "2 - LFR UNRESET";
160 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
162 --
163 message_simu <= "3 - LFR CONFIG ";
164 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
165
166 WAIT;
167 END PROCESS;
168
169 -----------------------------------------------------------------------------
170 -- CLOCK
171 -----------------------------------------------------------------------------
172 clk_50 <= NOT clk_50 AFTER 5 ns;
173 clk_49 <= NOT clk_49 AFTER 10172 ps;
174
175 -----------------------------------------------------------------------------
176 -- DON'T CARE
177 -----------------------------------------------------------------------------
178 BP0 <= '0';
179 BP1 <= '0';
180 nRTS1 <= '0' ;
181
182 TXD2 <= '1';
183 nRTS2 <= '1';
184 nDTR2 <= '1';
185
186 SPW_NOM_DIN <= '1';
187 SPW_NOM_SIN <= '1';
188 SPW_RED_DIN <= '1';
189 SPW_RED_SIN <= '1';
190
191 ADC_SDO <= x"AA";
192
193 SRAM_DQ <= (OTHERS => 'Z');
194
195 -----------------------------------------------------------------------------
196 -- DUT
197 -----------------------------------------------------------------------------
198 MINI_LFR_top_1: MINI_LFR_top
199 PORT MAP (
200 clk_50 => clk_50,
201 clk_49 => clk_49,
202 reset => reset,
203
204 BP0 => BP0,
205 BP1 => BP1,
206
207 LED0 => LED0,
208 LED1 => LED1,
209 LED2 => LED2,
210
211 TXD1 => TXD1,
212 RXD1 => RXD1,
213 nCTS1 => nCTS1,
214 nRTS1 => nRTS1,
215
216 TXD2 => TXD2,
217 RXD2 => RXD2,
218 nCTS2 => nCTS2,
219 nDTR2 => nDTR2,
220 nRTS2 => nRTS2,
221 nDCD2 => nDCD2,
222
223 IO0 => IO0,
224 IO1 => IO1,
225 IO2 => IO2,
226 IO3 => IO3,
227 IO4 => IO4,
228 IO5 => IO5,
229 IO6 => IO6,
230 IO7 => IO7,
231 IO8 => IO8,
232 IO9 => IO9,
233 IO10 => IO10,
234 IO11 => IO11,
235
236 SPW_EN => SPW_EN,
237 SPW_NOM_DIN => SPW_NOM_DIN,
238 SPW_NOM_SIN => SPW_NOM_SIN,
239 SPW_NOM_DOUT => SPW_NOM_DOUT,
240 SPW_NOM_SOUT => SPW_NOM_SOUT,
241 SPW_RED_DIN => SPW_RED_DIN,
242 SPW_RED_SIN => SPW_RED_SIN,
243 SPW_RED_DOUT => SPW_RED_DOUT,
244 SPW_RED_SOUT => SPW_RED_SOUT,
245
246 ADC_nCS => ADC_nCS,
247 ADC_CLK => ADC_CLK,
248 ADC_SDO => ADC_SDO,
249
250 SRAM_nWE => SRAM_nWE,
251 SRAM_CE => SRAM_CE,
252 SRAM_nOE => SRAM_nOE,ddr_buffer_f
253 SRAM_nBE => SRAM_nBE,
254 SRAM_A => SRAM_A,
255 SRAM_DQ => SRAM_DQ);
256
257
258 END;
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1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/message_simu
4 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
5 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
6 add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing
7 TreeUpdate [SetDefaultTree]
8 WaveRestoreCursors {{Cursor 1} {11527482482 ps} 0}
9 quietly wave cursor active 1
10 configure wave -namecolwidth 539
11 configure wave -valuecolwidth 100
12 configure wave -justifyvalue left
13 configure wave -signalnamewidth 0
14 configure wave -snapdistance 10
15 configure wave -datasetprefix 0
16 configure wave -rowmargin 4
17 configure wave -childrowmargin 2
18 configure wave -gridoffset 0
19 configure wave -gridperiod 1
20 configure wave -griddelta 40
21 configure wave -timeline 0
22 configure wave -timelineunits ns
23 update
24 WaveRestoreZoom {0 ps} {61313789250 ps}
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
27
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31
32 ENTITY cic_lfr_add_sub IS
33 PORT (
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
37
38 OP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
39 -- 00 A + B
40 -- 01 A - B
41 -- 10 A + B + Carry
42 -- 11 A - B - Carry
43
44 data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
45 data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
46 data_in_Carry : IN STD_LOGIC;
47
48 data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
49 data_out_Carry : OUT STD_LOGIC
50 );
51 END cic_lfr_add_sub;
52
53 ARCHITECTURE beh OF cic_lfr_add_sub IS
54
55 SIGNAL data_carry : STD_LOGIC;
56 SIGNAL STD_LOGIC_VECTOR_ZERO : STD_LOGIC_VECTOR(15 DOWNTO 0);
57 SIGNAL data_add : STD_LOGIC_VECTOR(16 DOWNTO 0);
58 SIGNAL data_sub : STD_LOGIC_VECTOR(16 DOWNTO 0);
59
60 SIGNAL data : STD_LOGIC_VECTOR(16 DOWNTO 0);
61
62 BEGIN
63
64 STD_LOGIC_VECTOR_ZERO <= (OTHERS => '0');
65 data_carry <= '0' WHEN OP(1) = '0' ELSE data_in_Carry;
66
67 data_add <= STD_LOGIC_VECTOR( SIGNED('0' & data_in_A)
68 + SIGNED('0' & data_in_B)
69 + SIGNED(STD_LOGIC_VECTOR_ZERO & data_carry));
70
71 data_sub <= STD_LOGIC_VECTOR( SIGNED('0' & data_in_A)
72 - SIGNED('0' & data_in_B)
73 - SIGNED(STD_LOGIC_VECTOR_ZERO & data_carry));
74
75 data <= data_add WHEN OP(0) = '0' ELSE data_sub;
76 PROCESS (clk, rstn)
77 BEGIN -- PROCESS
78 IF rstn = '0' THEN
79 data_out_Carry <= '0';
80 data_out <= (OTHERS => '0');
81 ELSIF clk'event AND clk = '1' THEN
82 IF run = '0' THEN
83 data_out_Carry <= '0';
84 data_out <= (OTHERS => '0');
85 ELSE
86 data_out_Carry <= data(16);
87 data_out <= data(15 DOWNTO 0);
88 END IF;
89 END IF;
90 END PROCESS;
91
92
93 END beh;
94
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 PACKAGE lpp_lfr_time_management_apbreg_pkg IS
6
7 CONSTANT ADDR_LFR_TM_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
8 CONSTANT ADDR_LFR_TM_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
9 CONSTANT ADDR_LFR_TM_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
10 CONSTANT ADDR_LFR_TM_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
11
12 END lpp_lfr_time_management_apbreg_pkg;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.stdlib.ALL;
28 LIBRARY gaisler;
29 USE gaisler.libdcom.ALL;
30 USE gaisler.sim.ALL;
31 USE gaisler.jtagtst.ALL;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
34
35 PACKAGE lpp_sim_pkg IS
36
37 PROCEDURE UART_INIT (
38 SIGNAL TX : OUT STD_LOGIC;
39 CONSTANT tx_period : IN TIME
40 );
41 PROCEDURE UART_WRITE_ADDR32 (
42 SIGNAL TX : OUT STD_LOGIC;
43 CONSTANT tx_period : IN TIME;
44 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
45 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
46 );
47 PROCEDURE UART_WRITE (
48 SIGNAL TX : OUT STD_LOGIC;
49 CONSTANT tx_period : IN TIME;
50 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
51 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
52 );
53
54 END lpp_sim_pkg;
55
56 PACKAGE BODY lpp_sim_pkg IS
57
58 PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
59 BEGIN
60 txc(TX, 16#55#, tx_period);
61 END;
62
63 PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
64 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
66 BEGIN
67 txc(TX, 16#c0#, tx_period);
68 txa(TX,
69 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
70 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
71 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
72 to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
73 tx_period);
74 txa(TX,
75 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
76 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
77 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
78 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
79 tx_period);
80 END;
81
82 PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
83 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
84 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
85
86 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
87
88 BEGIN
89 txc(TX, 16#c0#, tx_period);
90 txa(TX,
91 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
92 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
93 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
94 to_integer(UNSIGNED(ADDR_last)),
95 tx_period);
96 txa(TX,
97 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
98 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
99 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
100 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
101 tx_period);
102 END;
103
104 END lpp_sim_pkg;
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1 lpp_sim_pkg.vhd
2
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 PACKAGE lpp_lfr_apbreg_pkg IS
6
7 -----------------------------------------------------------------------------
8 -- SPECTRAL_MATRIX
9 -----------------------------------------------------------------------------
10 CONSTANT ADDR_LFR_SM_CONFIG : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
11 CONSTANT ADDR_LFR_SM_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
12 CONSTANT ADDR_LFR_SM_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
13 CONSTANT ADDR_LFR_SM_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
14
15 CONSTANT ADDR_LFR_SM_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
16 CONSTANT ADDR_LFR_SM_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
17 CONSTANT ADDR_LFR_SM_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
18 CONSTANT ADDR_LFR_SM_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
19
20 CONSTANT ADDR_LFR_SM_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
21 CONSTANT ADDR_LFR_SM_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
22 CONSTANT ADDR_LFR_SM_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
23 CONSTANT ADDR_LFR_SM_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
24
25 CONSTANT ADDR_LFR_SM_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";
26 CONSTANT ADDR_LFR_SM_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001101";
27 CONSTANT ADDR_LFR_SM_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001110";
28 CONSTANT ADDR_LFR_SM_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001111";
29
30 CONSTANT ADDR_LFR_SM_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010000";
31 CONSTANT ADDR_LFR_SM_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010001";
32 CONSTANT ADDR_LFR_SM_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010010";
33 CONSTANT ADDR_LFR_SM_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010011";
34
35 CONSTANT ADDR_LFR_SM_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010100";
36 -----------------------------------------------------------------------------
37 -- WAVEFORM PICKER
38 -----------------------------------------------------------------------------
39 CONSTANT ADDR_LFR_WP_DATASHAPING : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010101";
40 CONSTANT ADDR_LFR_WP_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010110";
41 CONSTANT ADDR_LFR_WP_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010111";
42
43 CONSTANT ADDR_LFR_WP_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011000";
44 CONSTANT ADDR_LFR_WP_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011001";
45 CONSTANT ADDR_LFR_WP_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011010";
46 CONSTANT ADDR_LFR_WP_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011011";
47
48 CONSTANT ADDR_LFR_WP_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011100";
49 CONSTANT ADDR_LFR_WP_F3_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011101";
50 CONSTANT ADDR_LFR_WP_F3_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011110";
51 CONSTANT ADDR_LFR_WP_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011111";
52
53 CONSTANT ADDR_LFR_WP_DELTASNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100000";
54 CONSTANT ADDR_LFR_WP_DELTA_F0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100001";
55 CONSTANT ADDR_LFR_WP_DELTA_F0_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100010";
56 CONSTANT ADDR_LFR_WP_DELTA_F1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100011";
57
58 CONSTANT ADDR_LFR_WP_DELTA_F2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100100";
59 CONSTANT ADDR_LFR_WP_DATA_IN_BUFFER : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100101";
60 CONSTANT ADDR_LFR_WP_NBSNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100110";
61 CONSTANT ADDR_LFR_WP_START_DATE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100111";
62
63 CONSTANT ADDR_LFR_WP_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101000";
64 CONSTANT ADDR_LFR_WP_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101001";
65 CONSTANT ADDR_LFR_WP_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101010";
66 CONSTANT ADDR_LFR_WP_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101011";
67
68 CONSTANT ADDR_LFR_WP_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101100";
69 CONSTANT ADDR_LFR_WP_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101101";
70 CONSTANT ADDR_LFR_WP_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101110";
71 CONSTANT ADDR_LFR_WP_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101111";
72
73 CONSTANT ADDR_LFR_WP_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110000";
74 CONSTANT ADDR_LFR_WP_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110001";
75 CONSTANT ADDR_LFR_WP_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110010";
76 CONSTANT ADDR_LFR_WP_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110011";
77
78 CONSTANT ADDR_LFR_WP_F3_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110100";
79 CONSTANT ADDR_LFR_WP_F3_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110101";
80 CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110";
81 CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111";
82
83 CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000";
84 -----------------------------------------------------------------------------
85 -- LFR
86 -----------------------------------------------------------------------------
87 CONSTANT ADDR_LFR_VERSION : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111100";
88
89
90 END lpp_lfr_apbreg_pkg;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
39
40
41 ENTITY lpp_waveform_fsmdma IS
42 PORT (
43 -- AMBA AHB system signals
44 clk : IN STD_ULOGIC;
45 rstn : IN STD_ULOGIC;
46 run : IN STD_LOGIC;
47
48 ---------------------------------------------------------------------------
49 -- FIFO - IN
50 fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 fifo_empty : IN STD_LOGIC;
53 fifo_empty_threshold : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55
56 ---------------------------------------------------------------------------
57 -- DMA - OUT
58 dma_fifo_valid_burst : OUT STD_LOGIC;
59 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_fifo_ren : IN STD_LOGIC;
61
62 dma_buffer_new : OUT STD_LOGIC;
63 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
65 dma_buffer_full : IN STD_LOGIC;
66 dma_buffer_full_err : IN STD_LOGIC;
67
68 ---------------------------------------------------------------------------
69 -- Reg In
70 status_buffer_ready : IN STD_LOGIC;
71 addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
73 -- Reg Out
74 ready_buffer : OUT STD_LOGIC;
75 buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 error_buffer_full : OUT STD_LOGIC
77 );
78 END;
79
80 ARCHITECTURE Behavioral OF lpp_waveform_fsmdma IS
81
82 TYPE FSM_DMA_STATE IS (IDLE, ONGOING);
83 SIGNAL state : FSM_DMA_STATE;
84 SIGNAL burst_valid_s : STD_LOGIC;
85
86 BEGIN
87 burst_valid_s <= NOT fifo_empty_threshold;
88
89 error_buffer_full <= dma_buffer_full_err;
90
91 fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1';
92 dma_fifo_data <= fifo_data;
93 dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '0';
94
95 PROCESS (clk, rstn)
96 BEGIN -- PROCESS
97 IF rstn = '0' THEN -- asynchronous reset (active low)
98 state <= IDLE;
99 buffer_time <= (OTHERS => '0');
100 dma_buffer_addr <= (OTHERS => '0');
101 dma_buffer_length <= (OTHERS => '0');
102 dma_buffer_new <= '0';
103 ready_buffer <= '0';
104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
105 ready_buffer <= '0';
106 dma_buffer_new <= '0';
107 IF run = '1' THEN
108 CASE state IS
109 WHEN IDLE =>
110 IF fifo_empty = '0' THEN
111 IF status_buffer_ready = '0' THEN
112 state <= ONGOING;
113 buffer_time <= fifo_buffer_time;
114 dma_buffer_addr <= addr_buffer;
115 dma_buffer_length <= length_buffer;
116 dma_buffer_new <= '1';
117 END IF;
118 END IF;
119 WHEN ONGOING =>
120 IF dma_buffer_full = '1' THEN
121 ready_buffer <= '1';
122 state <= IDLE;
123 END IF;
124 WHEN OTHERS => NULL;
125 END CASE;
126 ELSE
127 state <= IDLE;
128 buffer_time <= (OTHERS => '0');
129 dma_buffer_addr <= (OTHERS => '0');
130 dma_buffer_length <= (OTHERS => '0');
131 dma_buffer_new <= '0';
132 END IF;
133 END IF;
134 END PROCESS;
135
136 END Behavioral;
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