# HG changeset patch # User pellion # Date 2014-08-05 12:41:18 # Node ID fc21de09fe8a953ad2c7246968291da941a8a5eb # Parent 4ab4a470962c26a506b3fb283f188237a4141980 New RHF1401 ADC driver (with simple filter) diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -386,21 +386,40 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- - top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter GENERIC MAP ( ChanelCount => 8, - ncycle_cnv_high => 40, -- TODO : 79 - ncycle_cnv => 250) -- TODO : 500 + ncycle_cnv_high => 13, + ncycle_cnv => 25) PORT MAP ( - cnv_clk => clk_24, -- TODO : 49.152 - cnv_rstn => rstn, -- ok - cnv => ADC_smpclk_s, -- ok - clk => clk_25, -- ok - rstn => rstn, -- ok - ADC_data => ADC_data, -- ok - ADC_nOE => ADC_OEB_bar_CH, -- ok - sample => sample, -- ok - sample_val => sample_val); -- ok + cnv_clk => clk_24, + cnv_rstn => rstn, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + + + + + --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + -- GENERIC MAP ( + -- ChanelCount => 8, + -- ncycle_cnv_high => 40, -- TODO : 79 + -- ncycle_cnv => 250) -- TODO : 500 + -- PORT MAP ( + -- cnv_clk => clk_24, -- TODO : 49.152 + -- cnv_rstn => rstn, -- ok + -- cnv => ADC_smpclk_s, -- ok + -- clk => clk_25, -- ok + -- rstn => rstn, -- ok + -- ADC_data => ADC_data, -- ok + -- ADC_nOE => ADC_OEB_bar_CH, -- ok + -- sample => sample, -- ok + -- sample_val => sample_val); -- ok ADC_smpclk <= ADC_smpclk_s; diff --git a/designs/LFR_simu_ms/.config b/designs/LFR_simu_ms/.config new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/.config @@ -0,0 +1,288 @@ +# +# Automatically generated make config: don't edit +# + +# +# Synthesis +# +# CONFIG_SYN_INFERRED is not set +# CONFIG_SYN_STRATIX is not set +# CONFIG_SYN_STRATIXII is not set +# CONFIG_SYN_STRATIXIII is not set +# CONFIG_SYN_CYCLONEIII is not set +# CONFIG_SYN_ALTERA is not set +# CONFIG_SYN_AXCEL is not set +# CONFIG_SYN_PROASIC is not set +# CONFIG_SYN_PROASICPLUS is not set +CONFIG_SYN_PROASIC3=y +# CONFIG_SYN_UT025CRH is not set +# CONFIG_SYN_ATC18 is not set +# CONFIG_SYN_ATC18RHA is not set +# CONFIG_SYN_CUSTOM1 is not set +# CONFIG_SYN_EASIC90 is not set +# CONFIG_SYN_IHP25 is not set +# CONFIG_SYN_IHP25RH is not set +# CONFIG_SYN_LATTICE is not set +# CONFIG_SYN_ECLIPSE is not set +# CONFIG_SYN_PEREGRINE is not set +# CONFIG_SYN_RH_LIB18T is not set +# CONFIG_SYN_RHUMC is not set +# CONFIG_SYN_SMIC13 is not set +# CONFIG_SYN_SPARTAN2 is not set +# CONFIG_SYN_SPARTAN3 is not set +# CONFIG_SYN_SPARTAN3E is not set +# CONFIG_SYN_VIRTEX is not set +# CONFIG_SYN_VIRTEXE is not set +# CONFIG_SYN_VIRTEX2 is not set +# CONFIG_SYN_VIRTEX4 is not set +# CONFIG_SYN_VIRTEX5 is not set +# CONFIG_SYN_UMC is not set +# CONFIG_SYN_TSMC90 is not set +# CONFIG_SYN_INFER_RAM is not set +# CONFIG_SYN_INFER_PADS is not set +# CONFIG_SYN_NO_ASYNC is not set +# CONFIG_SYN_SCAN is not set + +# +# Clock generation +# +# CONFIG_CLK_INFERRED is not set +# CONFIG_CLK_HCLKBUF is not set +# CONFIG_CLK_ALTDLL is not set +# CONFIG_CLK_LATDLL is not set +CONFIG_CLK_PRO3PLL=y +# CONFIG_CLK_LIB18T is not set +# CONFIG_CLK_RHUMC is not set +# CONFIG_CLK_CLKDLL is not set +# CONFIG_CLK_DCM is not set +CONFIG_CLK_MUL=2 +CONFIG_CLK_DIV=8 +CONFIG_OCLK_DIV=2 +# CONFIG_PCI_SYSCLK is not set +CONFIG_LEON3=y +CONFIG_PROC_NUM=1 + +# +# Processor +# + +# +# Integer unit +# +CONFIG_IU_NWINDOWS=8 +# CONFIG_IU_V8MULDIV is not set +# CONFIG_IU_SVT is not set +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=0 +# CONFIG_PWD is not set +CONFIG_IU_RSTADDR=00000 + +# +# Floating-point unit +# +# CONFIG_FPU_ENABLE is not set + +# +# Cache system +# +CONFIG_ICACHE_ENABLE=y +CONFIG_ICACHE_ASSO1=y +# CONFIG_ICACHE_ASSO2 is not set +# CONFIG_ICACHE_ASSO3 is not set +# CONFIG_ICACHE_ASSO4 is not set +# CONFIG_ICACHE_SZ1 is not set +# CONFIG_ICACHE_SZ2 is not set +CONFIG_ICACHE_SZ4=y +# CONFIG_ICACHE_SZ8 is not set +# CONFIG_ICACHE_SZ16 is not set +# CONFIG_ICACHE_SZ32 is not set +# CONFIG_ICACHE_SZ64 is not set +# CONFIG_ICACHE_SZ128 is not set +# CONFIG_ICACHE_SZ256 is not set +# CONFIG_ICACHE_LZ16 is not set +CONFIG_ICACHE_LZ32=y +CONFIG_DCACHE_ENABLE=y +CONFIG_DCACHE_ASSO1=y +# CONFIG_DCACHE_ASSO2 is not set +# CONFIG_DCACHE_ASSO3 is not set +# CONFIG_DCACHE_ASSO4 is not set +# CONFIG_DCACHE_SZ1 is not set +# CONFIG_DCACHE_SZ2 is not set +CONFIG_DCACHE_SZ4=y +# CONFIG_DCACHE_SZ8 is not set +# CONFIG_DCACHE_SZ16 is not set +# CONFIG_DCACHE_SZ32 is not set +# CONFIG_DCACHE_SZ64 is not set +# CONFIG_DCACHE_SZ128 is not set +# CONFIG_DCACHE_SZ256 is not set +# CONFIG_DCACHE_LZ16 is not set +CONFIG_DCACHE_LZ32=y +# CONFIG_DCACHE_SNOOP is not set +CONFIG_CACHE_FIXED=0 + +# +# MMU +# +CONFIG_MMU_ENABLE=y +# CONFIG_MMU_COMBINED is not set +CONFIG_MMU_SPLIT=y +# CONFIG_MMU_REPARRAY is not set +CONFIG_MMU_REPINCREMENT=y +# CONFIG_MMU_I2 is not set +# CONFIG_MMU_I4 is not set +CONFIG_MMU_I8=y +# CONFIG_MMU_I16 is not set +# CONFIG_MMU_I32 is not set +# CONFIG_MMU_D2 is not set +# CONFIG_MMU_D4 is not set +CONFIG_MMU_D8=y +# CONFIG_MMU_D16 is not set +# CONFIG_MMU_D32 is not set +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +# CONFIG_MMU_PAGE_8K is not set +# CONFIG_MMU_PAGE_16K is not set +# CONFIG_MMU_PAGE_32K is not set +# CONFIG_MMU_PAGE_PROG is not set + +# +# Debug Support Unit +# +# CONFIG_DSU_ENABLE is not set + +# +# Fault-tolerance +# + +# +# VHDL debug settings +# +# CONFIG_IU_DISAS is not set +# CONFIG_DEBUG_PC32 is not set + +# +# AMBA configuration +# +CONFIG_AHB_DEFMST=0 +CONFIG_AHB_RROBIN=y +# CONFIG_AHB_SPLIT is not set +CONFIG_AHB_IOADDR=FFF +CONFIG_APB_HADDR=800 +# CONFIG_AHB_MON is not set + +# +# Debug Link +# +CONFIG_DSU_UART=y +# CONFIG_DSU_JTAG is not set + +# +# Peripherals +# + +# +# Memory controllers +# + +# +# 8/32-bit PROM/SRAM controller +# +CONFIG_SRCTRL=y +# CONFIG_SRCTRL_8BIT is not set +CONFIG_SRCTRL_PROMWS=3 +CONFIG_SRCTRL_RAMWS=0 +CONFIG_SRCTRL_IOWS=0 +# CONFIG_SRCTRL_RMW is not set +CONFIG_SRCTRL_SRBANKS1=y +# CONFIG_SRCTRL_SRBANKS2 is not set +# CONFIG_SRCTRL_SRBANKS3 is not set +# CONFIG_SRCTRL_SRBANKS4 is not set +# CONFIG_SRCTRL_SRBANKS5 is not set +# CONFIG_SRCTRL_BANKSZ0 is not set +# CONFIG_SRCTRL_BANKSZ1 is not set +# CONFIG_SRCTRL_BANKSZ2 is not set +# CONFIG_SRCTRL_BANKSZ3 is not set +# CONFIG_SRCTRL_BANKSZ4 is not set +# CONFIG_SRCTRL_BANKSZ5 is not set +# CONFIG_SRCTRL_BANKSZ6 is not set +# CONFIG_SRCTRL_BANKSZ7 is not set +# CONFIG_SRCTRL_BANKSZ8 is not set +# CONFIG_SRCTRL_BANKSZ9 is not set +# CONFIG_SRCTRL_BANKSZ10 is not set +# CONFIG_SRCTRL_BANKSZ11 is not set +# CONFIG_SRCTRL_BANKSZ12 is not set +# CONFIG_SRCTRL_BANKSZ13 is not set +CONFIG_SRCTRL_ROMASEL=19 + +# +# Leon2 memory controller +# +CONFIG_MCTRL_LEON2=y +# CONFIG_MCTRL_8BIT is not set +# CONFIG_MCTRL_16BIT is not set +# CONFIG_MCTRL_5CS is not set +# CONFIG_MCTRL_SDRAM is not set + +# +# PC133 SDRAM controller +# +# CONFIG_SDCTRL is not set + +# +# On-chip RAM/ROM +# +# CONFIG_AHBROM_ENABLE is not set +# CONFIG_AHBRAM_ENABLE is not set + +# +# Ethernet +# +# CONFIG_GRETH_ENABLE is not set + +# +# CAN +# +# CONFIG_CAN_ENABLE is not set + +# +# PCI +# +# CONFIG_PCI_SIMPLE_TARGET is not set +# CONFIG_PCI_MASTER_TARGET is not set +# CONFIG_PCI_ARBITER is not set +# CONFIG_PCI_TRACE is not set + +# +# Spacewire +# +# CONFIG_SPW_ENABLE is not set + +# +# UARTs, timers and irq control +# +CONFIG_UART1_ENABLE=y +# CONFIG_UA1_FIFO1 is not set +# CONFIG_UA1_FIFO2 is not set +CONFIG_UA1_FIFO4=y +# CONFIG_UA1_FIFO8 is not set +# CONFIG_UA1_FIFO16 is not set +# CONFIG_UA1_FIFO32 is not set +# CONFIG_UART2_ENABLE is not set +CONFIG_IRQ3_ENABLE=y +# CONFIG_IRQ3_SEC is not set +CONFIG_GPT_ENABLE=y +CONFIG_GPT_NTIM=2 +CONFIG_GPT_SW=8 +CONFIG_GPT_TW=32 +CONFIG_GPT_IRQ=8 +CONFIG_GPT_SEPIRQ=y +CONFIG_GPT_WDOGEN=y +CONFIG_GPT_WDOG=FFFF +CONFIG_GRGPIO_ENABLE=y +CONFIG_GRGPIO_WIDTH=8 +CONFIG_GRGPIO_IMASK=0000 + +# +# VHDL Debugging +# +# CONFIG_DEBUG_UART is not set diff --git a/designs/LFR_simu_ms/Makefile b/designs/LFR_simu_ms/Makefile new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/Makefile @@ -0,0 +1,50 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES=config.vhd leon3mp.vhd +VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/LFR_simu_ms/config.vhd b/designs/LFR_simu_ms/config.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/config.vhd @@ -0,0 +1,182 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is + + +-- Technology and synthesis options + constant CFG_FABTECH : integer := apa3e; + constant CFG_MEMTECH : integer := apa3e; + constant CFG_PADTECH : integer := inferred; + constant CFG_NOASYNC : integer := 0; + constant CFG_SCAN : integer := 0; + +-- Clock generator + constant CFG_CLKTECH : integer := inferred; + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; + +-- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := (1); + --constant CFG_NWIN : integer := (7); -- PLE + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist + --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE + constant CFG_GRFPUSH : integer := 0; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DFIXED : integer := 16#00F3#; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + constant CFG_DSU : integer := 1; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + constant CFG_LEON3FT_EN : integer := 0; + constant CFG_IUFT_EN : integer := 0; + constant CFG_FPUFT_EN : integer := 0; + constant CFG_RF_ERRINJ : integer := 0; + constant CFG_CACHE_FT_EN : integer := 0; + constant CFG_CACHE_ERRINJ : integer := 0; + constant CFG_LEON3_NETLIST: integer := 0; + constant CFG_DISAS : integer := 0 + 0; + constant CFG_PCLOW : integer := 2; + +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + +-- DSU UART + constant CFG_AHB_UART : integer := 1; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 0; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := 0 + 0; + constant CFG_ETH_BUF : integer := 1; + constant CFG_ETH_IPM : integer := 16#C0A8#; + constant CFG_ETH_IPL : integer := 16#0033#; + constant CFG_ETH_ENM : integer := 16#00007A#; + constant CFG_ETH_ENL : integer := 16#CC0001#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM16BIT : integer := 0; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; + +-- SSRAM controller + constant CFG_SSCTRL : integer := 0; + constant CFG_SSCTRLP16 : integer := 0; + +-- AHB ROM + constant CFG_AHBROMEN : integer := 0; + constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBRODDR : integer := 16#000#; + constant CFG_ROMADDR : integer := 16#000#; + constant CFG_ROMMASK : integer := 16#E00# + 16#000#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := 0; + constant CFG_AHBRSZ : integer := 1; + constant CFG_AHBRADDR : integer := 16#A00#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + constant CFG_GRETH1G : integer := 0; + constant CFG_ETH_FIFO : integer := 8; + +-- CAN 2.0 interface + constant CFG_CAN : integer := 0; + constant CFG_CANIO : integer := 16#0#; + constant CFG_CANIRQ : integer := 0; + constant CFG_CANLOOP : integer := 0; + constant CFG_CAN_SYNCRST : integer := 0; + constant CFG_CANFT : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 1; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := 1; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := 1; + constant CFG_GPT_NTIM : integer := (3); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := 1; + constant CFG_GRGPIO_IMASK : integer := 16#0000#; + constant CFG_GRGPIO_WIDTH : integer := (7); + +-- GRLIB debugging + constant CFG_DUART : integer := 0; + + +end; diff --git a/designs/LFR_simu_ms/leon3mp.vhd b/designs/LFR_simu_ms/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/leon3mp.vhd @@ -0,0 +1,524 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; + +ENTITY leon3mp IS + GENERIC ( + fabtech : INTEGER := CFG_FABTECH; + memtech : INTEGER := CFG_MEMTECH; + padtech : INTEGER := CFG_PADTECH; + clktech : INTEGER := CFG_CLKTECH; + disas : INTEGER := CFG_DISAS; -- Enable disassembly to console + dbguart : INTEGER := CFG_DUART; -- Print UART on console + pclow : INTEGER := CFG_PCLOW + ); + PORT ( + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- SPW -------------------------------------------------------------------- + spw1_din : IN STD_LOGIC; -- PLE + spw1_sin : IN STD_LOGIC; -- PLE + spw1_dout : OUT STD_LOGIC; -- PLE + spw1_sout : OUT STD_LOGIC; -- PLE + + spw2_din : IN STD_LOGIC; -- JCPE --TODO + spw2_sin : IN STD_LOGIC; -- JCPE --TODO + spw2_dout : OUT STD_LOGIC; -- JCPE --TODO + spw2_sout : OUT STD_LOGIC; -- JCPE --TODO + + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + + --------------------------------------------------------------------------- + led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF leon3mp IS + +--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ +-- CFG_GRETH+CFG_AHB_JTAG; + CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ + CFG_AHB_UART + +2; + -- 1 is for the SpaceWire module grspw, which is a master + -- 1 is for the LFR + + CONSTANT maxahbm : INTEGER := maxahbmsp; + +--Clk & Rst g�n� + SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL resetnl : STD_ULOGIC; + SIGNAL clk2x : STD_ULOGIC; + SIGNAL lclk2x : STD_ULOGIC; + SIGNAL lclk25MHz : STD_ULOGIC; + SIGNAL lclk50MHz : STD_ULOGIC; + SIGNAL lclk100MHz : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; +--- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); +--UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; +--MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + SIGNAL ramcs : STD_ULOGIC; +--IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); +--Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; +--DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- + CONSTANT IOAEN : INTEGER := CFG_CAN; + CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz + +-- time management signal + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; -- PLE + SIGNAL swno : grspw_out_type; -- PLE + SIGNAL clkmn : STD_ULOGIC; -- PLE + SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 + +-- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + + PROCESS(lclk100MHz) + BEGIN + IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN + lclk50MHz <= NOT lclk50MHz; + END IF; + END PROCESS; + + PROCESS(lclk50MHz) + BEGIN + IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN + lclk25MHz <= NOT lclk25MHz; + END IF; + END PROCESS; + + lclk2x <= lclk50MHz; + spw_clk <= lclk50MHz; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + led(2) <= dsuo.active; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + led(0) <= NOT ahbuarti.rxd; + led(1) <= NOT ahbuarto.txd; + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1: apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + pirq => 12) + PORT MAP ( + clk25MHz => clkm, + clk49_152MHz => clk49_152MHz, + resetn => rstn, + grspw_tick => swno.tickout, + apbi => apbi, + apbo => apbo(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sin, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sin, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => fabtech, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm + GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn, clkm, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbmi, ahbmo(1), apbi, apbo(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR +------------------------------------------------------------------------------- + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"00000002") + PORT MAP ( + clk => clkm, + rstn => rstn, + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi, + apbo => apbo(15), + ahbi => ahbmi, + ahbo => ahbmo(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw); + + top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk49_152MHz, + cnv_rstn => rstn, + cnv => ADC_smpclk, + clk => clkm, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + +END Behavioral; diff --git a/designs/LFR_simu_ms/run_tb_ms.do b/designs/LFR_simu_ms/run_tb_ms.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/run_tb_ms.do @@ -0,0 +1,27 @@ +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/fifo_latency_correction.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_ip.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_snapshot.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_fft/CoreFFT_simu.vhd + +vcom -quiet -93 -work lpp testbench_package.vhd +vcom -quiet -93 -work lpp tb_memory.vhd +vcom -quiet -93 -work work tb_ms.vhd + +vsim work.testbench + +log -r * +do wave_ms.do +##run 15 ms diff --git a/designs/LFR_simu_ms/tb_memory.vhd b/designs/LFR_simu_ms/tb_memory.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/tb_memory.vhd @@ -0,0 +1,146 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.AMBA_TestPackage.ALL; + +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.libdcom.ALL; +USE gaisler.sim.ALL; +USE gaisler.jtagtst.ALL; +USE gaisler.misc.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY esa; +USE esa.memoryctrl.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.testbench_package.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; + + +ENTITY tb_memory IS + GENERIC ( + n_ahb_m : INTEGER := 2; + n_ahb_s : INTEGER := 1); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ahbsi : OUT ahb_slv_in_type; + ahbso : IN ahb_slv_out_vector := (OTHERS => ahbs_none); + ahbmi : OUT ahb_mst_in_type; + ahbmo : IN ahb_mst_out_vector := (OTHERS => ahbm_none) + ); +END tb_memory; + +ARCHITECTURE beh OF tb_memory IS + ----------------------------------------------------------------------------- + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + ----------------------------------------------------------------------------- + SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; + SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nSRAM_BE0 : STD_LOGIC; + SIGNAL nSRAM_BE1 : STD_LOGIC; + SIGNAL nSRAM_BE2 : STD_LOGIC; + SIGNAL nSRAM_BE3 : STD_LOGIC; + SIGNAL nSRAM_WE : STD_LOGIC; + SIGNAL nSRAM_CE : STD_LOGIC; + SIGNAL nSRAM_OE : STD_LOGIC; + ----------------------------------------------------------------------------- +BEGIN -- beh + ahb0 : ahbctrl + GENERIC MAP ( + defmast => 0, + split => 0, + rrobin => 1, + ioaddr => 16#FFF#, + ioen => 0, + nahbm => n_ahb_s, + nahbs => n_ahb_m) + PORT MAP ( + rstn, + clk, + ahbmi, + ahbmo, + ahbsi, + ahbso); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => inferred, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + address <= memo.address(21 DOWNTO 2); + nSRAM_CE <= NOT(memo.ramsn(0)); + nSRAM_OE <= memo.ramoen(0); + nSRAM_WE <= memo.writen; + nSRAM_BE0 <= memo.mben(3); + nSRAM_BE1 <= memo.mben(2); + nSRAM_BE2 <= memo.mben(1); + nSRAM_BE3 <= memo.mben(0); + + async_1Mx16_0: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE1, + BLE_b => nSRAM_BE0, + A => address, + DQ => data(15 DOWNTO 0)); + + async_1Mx16_1: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE3, + BLE_b => nSRAM_BE2, + A => address, + DQ => data(31 DOWNTO 16)); + +END beh; diff --git a/designs/LFR_simu_ms/tb_ms.vhd b/designs/LFR_simu_ms/tb_ms.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/tb_ms.vhd @@ -0,0 +1,498 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.AMBA_TestPackage.ALL; + +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.libdcom.ALL; +USE gaisler.sim.ALL; +USE gaisler.jtagtst.ALL; +USE gaisler.misc.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY esa; +USE esa.memoryctrl.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.testbench_package.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; + +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- DMA + ----------------------------------------------------------------------------- + SIGNAL dma_send : STD_LOGIC; + SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + SIGNAL dma_done : STD_LOGIC; + SIGNAL dma_ren : STD_LOGIC; + SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- WFP + ----------------------------------------------------------------------------- + SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f0_data_out_valid : STD_LOGIC := '0'; + SIGNAL data_f0_data_out_valid_burst : STD_LOGIC := '0'; + SIGNAL data_f0_data_out_ren : STD_LOGIC; + SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_data_out_valid : STD_LOGIC := '0'; + SIGNAL data_f1_data_out_valid_burst : STD_LOGIC := '0'; + SIGNAL data_f1_data_out_ren : STD_LOGIC; + SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_data_out_valid : STD_LOGIC := '0'; + SIGNAL data_f2_data_out_valid_burst : STD_LOGIC := '0'; + SIGNAL data_f2_data_out_ren : STD_LOGIC; + SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_data_out_valid : STD_LOGIC := '0'; + SIGNAL data_f3_data_out_valid_burst : STD_LOGIC := '0'; + SIGNAL data_f3_data_out_ren : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- ARBITER + ----------------------------------------------------------------------------- + SIGNAL dma_sel_valid : STD_LOGIC; + SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- MS + ----------------------------------------------------------------------------- + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f3_val : STD_LOGIC; + -- + SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_ms_valid : STD_LOGIC; + SIGNAL data_ms_valid_burst : STD_LOGIC; + SIGNAL data_ms_ren : STD_LOGIC; + SIGNAL data_ms_done : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL run : STD_LOGIC := '1'; + ----------------------------------------------------------------------------- + SIGNAL dma_counter : INTEGER; + SIGNAL dma_done_reg : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL sample_counter_24k : INTEGER; + SIGNAL s_24576Hz : STD_LOGIC; + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + + SIGNAL s_24_sync_reg_0 : STD_LOGIC; + SIGNAL s_24_sync_reg_1 : STD_LOGIC; + + SIGNAL s_24576Hz_sync : STD_LOGIC; + + + SIGNAL sample_counter_f1 : INTEGER; + SIGNAL sample_counter_f2 : INTEGER; + ----------------------------------------------------------------------------- +BEGIN + + ----------------------------------------------------------------------------- + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + clk <= NOT clk AFTER 5 ns; -- 100 MHz + rstn <= '1' AFTER 30 ns; + ----------------------------------------------------------------------------- + PROCESS (clk49_152MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_counter_24k <= 0; + s_24576Hz <= '0'; + ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge + IF sample_counter_24k = 0 THEN + sample_counter_24k <= 2000; + s_24576Hz <= NOT s_24576Hz; + ELSE + sample_counter_24k <= sample_counter_24k - 1; + END IF; + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + s_24_sync_reg_0 <= '0'; + s_24_sync_reg_1 <= '0'; + s_24576Hz_sync <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + s_24_sync_reg_0 <= s_24576Hz; + s_24_sync_reg_1 <= s_24_sync_reg_0; + s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1; + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f3_val <= '0'; + + sample_counter_f1 <= 0; + sample_counter_f2 <= 0; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF s_24576Hz_sync = '1' THEN + sample_f0_val <= '1'; + IF sample_counter_f1 = 0 THEN + sample_f1_val <= '1'; + sample_counter_f1 <= 5; + ELSE + sample_f1_val <= '0'; + sample_counter_f1 <= sample_counter_f1 -1; + END IF; + IF sample_counter_f2 = 0 THEN + sample_f3_val <= '1'; + sample_counter_f2 <= 95; + ELSE + sample_f3_val <= '0'; + sample_counter_f2 <= sample_counter_f2 -1; + END IF; + ELSE + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f3_val <= '0'; + END IF; + END IF; + END PROCESS; + + sample_f0_data <= (OTHERS => '0'); + sample_f1_data <= (OTHERS => '0'); + sample_f3_data <= (OTHERS => '0'); + ----------------------------------------------------------------------------- + sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val); + sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val); + sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val); + + -- (MSB) E2 E1 B2 B1 B0 (LSB) + sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); + sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); + sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); + + ----------------------------------------------------------------------------- + tb: PROCESS + BEGIN + WAIT UNTIL rstn = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + status_ready_matrix_f0_0 <= '0'; + status_ready_matrix_f0_1 <= '0'; + status_ready_matrix_f1 <= '0'; + status_ready_matrix_f2 <= '0'; + status_error_anticipating_empty_fifo <= '0'; + status_error_bad_component_error <= '0'; + config_active_interruption_onNewMatrix <= '1'; + config_active_interruption_onError <= '0'; + + addr_matrix_f0_0 <= X"40000000"; + addr_matrix_f0_1 <= X"40020000"; + addr_matrix_f1 <= X"40040000"; + addr_matrix_f2 <= X"40060000"; + WAIT UNTIL clk = '1'; + END PROCESS tb; + + ----------------------------------------------------------------------------- + -- MS + ----------------------------------------------------------------------------- + lpp_lfr_ms_1 : lpp_lfr_ms + GENERIC MAP ( + Mem_use => use_RAM) + PORT MAP ( + clk => clk, + rstn => rstn, + + coarse_time => coarse_time, + fine_time => fine_time, + + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + + dma_addr => data_ms_addr, -- + dma_data => data_ms_data, -- + dma_valid => data_ms_valid, -- + dma_valid_burst => data_ms_valid_burst, -- + dma_ren => data_ms_ren, -- + dma_done => data_ms_done, -- + + -- reg out + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => observation_reg, --debug_reg, + + -- reg in + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + matrix_time_f0_0 => matrix_time_f0_0, + matrix_time_f0_1 => matrix_time_f0_1, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2); + + ----------------------------------------------------------------------------- + -- ARBITER + ----------------------------------------------------------------------------- + dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; + dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; + dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; + dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; + + RR_Arbiter_4_1 : RR_Arbiter_4 + PORT MAP ( + clk => clk, + rstn => rstn, + in_valid => dma_rr_valid, + out_grant => dma_rr_grant_s); + + dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; + dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; + dma_rr_valid_ms(2) <= '0'; + dma_rr_valid_ms(3) <= '0'; + + RR_Arbiter_4_2 : RR_Arbiter_4 + PORT MAP ( + clk => clk, + rstn => rstn, + in_valid => dma_rr_valid_ms, + out_grant => dma_rr_grant_ms); + + dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + dma_sel <= (OTHERS => '0'); + dma_send <= '0'; + dma_valid_burst <= '0'; + data_ms_done <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF run = '1' THEN + data_ms_done <= '0'; + IF dma_sel = "00000" OR dma_done = '1' THEN + dma_sel <= dma_rr_grant; + IF dma_rr_grant(0) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f0_data_out_valid_burst; + dma_sel_valid <= data_f0_data_out_valid; + ELSIF dma_rr_grant(1) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f1_data_out_valid_burst; + dma_sel_valid <= data_f1_data_out_valid; + ELSIF dma_rr_grant(2) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f2_data_out_valid_burst; + dma_sel_valid <= data_f2_data_out_valid; + ELSIF dma_rr_grant(3) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f3_data_out_valid_burst; + dma_sel_valid <= data_f3_data_out_valid; + ELSIF dma_rr_grant(4) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_ms_valid_burst; + dma_sel_valid <= data_ms_valid; + END IF; + + IF dma_sel(4) = '1' THEN + data_ms_done <= '1'; + END IF; + ELSE + dma_sel <= dma_sel; + dma_send <= '0'; + END IF; + ELSE + data_ms_done <= '0'; + dma_sel <= (OTHERS => '0'); + dma_send <= '0'; + dma_valid_burst <= '0'; + END IF; + END IF; + END PROCESS; + + + dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE + data_f1_addr_out WHEN dma_sel(1) = '1' ELSE + data_f2_addr_out WHEN dma_sel(2) = '1' ELSE + data_f3_addr_out WHEN dma_sel(3) = '1' ELSE + data_ms_addr; + + dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE + data_f1_data_out WHEN dma_sel(1) = '1' ELSE + data_f2_data_out WHEN dma_sel(2) = '1' ELSE + data_f3_data_out WHEN dma_sel(3) = '1' ELSE + data_ms_data; + + data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; + data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; + data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; + data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; + data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; + + ----------------------------------------------------------------------------- + -- DMA + ----------------------------------------------------------------------------- + --lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst + -- GENERIC MAP ( + -- tech => inferred, + -- hindex => 0) + -- PORT MAP ( + -- HCLK => clk, + -- HRESETn => rstn, + -- run => run, + -- AHB_Master_In => ahbmi, + -- AHB_Master_Out => ahbmo(0), + + -- send => dma_send, + -- valid_burst => dma_valid_burst, + -- done => dma_done, + -- ren => dma_ren, + -- address => dma_address, + -- data => dma_data); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + dma_counter <= 0; + dma_done_reg <= '0'; + dma_done <= '0'; + dma_ren <= '1'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + dma_done_reg <= '0'; + dma_ren <= '1'; + + IF dma_send = '1' THEN + dma_counter <= 15; + dma_done_reg <= '0'; + dma_ren <= '0'; + END IF; + + IF dma_counter > 0 THEN + IF dma_counter = 1 THEN + dma_done_reg <= '1'; + END IF; + dma_ren <= '0'; + dma_counter <= dma_counter - 1; + END IF; + + dma_done <= dma_done_reg; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- MEMORY + AHB CTRL + ----------------------------------------------------------------------------- + --tb_memory_1: tb_memory + -- GENERIC MAP ( + -- n_ahb_m => 2, + -- n_ahb_s => 1) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- ahbsi => ahbsi, + -- ahbso => ahbso, + -- ahbmi => ahbmi, + -- ahbmo => ahbmo); + ----------------------------------------------------------------------------- +END; diff --git a/designs/LFR_simu_ms/tb_waveform.do b/designs/LFR_simu_ms/tb_waveform.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/tb_waveform.do @@ -0,0 +1,54 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run +add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out +add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out +add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid +add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send +add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain +add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data +add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout +add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0 +add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0 +add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1 +add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1 +add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2 +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 +add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3 +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0} +configure wave -namecolwidth 540 +configure wave -valuecolwidth 316 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {628873035 ns} diff --git a/designs/LFR_simu_ms/tb_waveform.vhd b/designs/LFR_simu_ms/tb_waveform.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/tb_waveform.vhd @@ -0,0 +1,147 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.AMBA_TestPackage.ALL; + +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.libdcom.ALL; +USE gaisler.sim.ALL; +USE gaisler.jtagtst.ALL; +USE gaisler.misc.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY esa; +USE esa.memoryctrl.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.testbench_package.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk25MHz : STD_LOGIC; + SIGNAL rstn : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + ----------------------------------------------------------------------------- + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + ----------------------------------------------------------------------------- + SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; + SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nSRAM_BE0 : STD_LOGIC; + SIGNAL nSRAM_BE1 : STD_LOGIC; + SIGNAL nSRAM_BE2 : STD_LOGIC; + SIGNAL nSRAM_BE3 : STD_LOGIC; + SIGNAL nSRAM_WE : STD_LOGIC; + SIGNAL nSRAM_CE : STD_LOGIC; + SIGNAL nSRAM_OE : STD_LOGIC; + ----------------------------------------------------------------------------- + +BEGIN + + ----------------------------------------------------------------------------- + clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + ahb0 : ahbctrl + GENERIC MAP (defmast => 0, split => 0, rrobin => 1, ioaddr => 16#FFF#, ioen => 0, nahbm => 2, nahbs => 1) + PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); + + ---------------------------------------------------------------------- + memctrlr : mctrl + GENERIC MAP (hindex => 0, pindex => 0, paddr => 0, srbanks => 1) + PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + address <= memo.address(21 DOWNTO 2); + nSRAM_CE <= NOT(memo.ramsn(0)); + nSRAM_OE <= memo.ramoen(0); + nSRAM_WE <= memo.writen; + nSRAM_BE0 <= memo.mben(3); + nSRAM_BE1 <= memo.mben(2); + nSRAM_BE2 <= memo.mben(1); + nSRAM_BE3 <= memo.mben(0); + + async_1Mx16_0: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE1, + BLE_b => nSRAM_BE0, + A => address, + DQ => data(15 DOWNTO 0)); + + async_1Mx16_1: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE3, + BLE_b => nSRAM_BE2, + A => address, + DQ => data(31 DOWNTO 16)); + ----------------------------------------------------------------------------- + +END; diff --git a/designs/LFR_simu_ms/testbench_package.vhd b/designs/LFR_simu_ms/testbench_package.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/testbench_package.vhd @@ -0,0 +1,144 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; + + +PACKAGE testbench_package IS + + COMPONENT tb_memory + GENERIC ( + n_ahb_m : INTEGER; + n_ahb_s : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + ahbsi : OUT ahb_slv_in_type; + ahbso : IN ahb_slv_out_vector := (OTHERS => ahbs_none); + ahbmi : OUT ahb_mst_in_type; + ahbmo : IN ahb_mst_out_vector := (OTHERS => ahbm_none)); + END COMPONENT; + + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + + END APB_WRITE; + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + prdata <= apbo.prdata; + END APB_READ; + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + WAIT UNTIL clk = '1'; + ahbmo.HADDR <= haddr; + ahbmo.HPROT <= "0011"; + ahbmo.HIRQ <= (OTHERS => '0'); + ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); + ahbmo.HINDEX <= hindex; + ahbmo.HBUSREQ <= '1'; + ahbmo.HLOCK <= '1'; + ahbmo.HSIZE <= HSIZE_WORD; + ahbmo.HBURST <= HBURST_SINGLE; + ahbmo.HTRANS <= HTRANS_NONSEQ; + ahbmo.HWRITE <= '0'; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HBUSREQ <= '0'; + ahbmo.HLOCK <= '0'; + ahbmo.HTRANS <= HTRANS_IDLE; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + hrdata <= ahbmi.HRDATA; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HLOCK <= '0'; + WAIT UNTIL clk = '1'; + + END AHB_READ; + +END testbench_package; diff --git a/designs/LFR_simu_ms/wave.do b/designs/LFR_simu_ms/wave.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/wave.do @@ -0,0 +1,96 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/reuse +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/wen +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/ren +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/full +add wave -noupdate -expand -group FIFO_IN_f0 -expand /testbench/lpp_lfr_ms_1/memf0/empty +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/reuse +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/wen +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/ren +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/full +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/empty +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/reuse +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/wen +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/ren +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/full +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/empty +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/ect +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf1 +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf0 +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load_reg +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/i +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/ect +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/load +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/sload +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/fifocpt +add wave -noupdate -expand -group DRIVE -format Analog-Step -max 256.0 /testbench/lpp_lfr_ms_1/fft0/drive/datacount +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_write +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_datare +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_dataim +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/fft_load +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_dataim +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_datare +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_valid +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_ready +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/link_read +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/fft0/fft_ongoing +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/ect +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/fifocpt +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/full +add wave -noupdate -divider HeaderBuilder +add wave -noupdate -expand -group HeaderBuilder -expand -group in -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/statu +add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_type +add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_write +add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/valid +add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/datain +add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/emptyin +add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/renout +add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/emptyout +add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/renout +add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/dataout +add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_ack +add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header +add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_val +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/write_reg +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/max +add wave -noupdate -expand -group HeaderBuilder -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/matrix_param +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/data_cpt +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/ect +add wave -noupdate -divider FSM_DMA +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_ack +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_val +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_ack +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_val +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_done +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_addr +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_data +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_ren +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid_burst +add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_data +add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty +add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_ren +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_send +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_select +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {10070925926 ps} 0} {{Cursor 2} {22280568302 ps} 0} +configure wave -namecolwidth 374 +configure wave -valuecolwidth 44 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {10392795757 ps} {10479958650 ps} diff --git a/designs/LFR_simu_ms/wave_ms.do b/designs/LFR_simu_ms/wave_ms.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/wave_ms.do @@ -0,0 +1,99 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/reuse +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/wen +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/ren +add wave -noupdate -expand -group FIFO_IN_f0 /testbench/lpp_lfr_ms_1/memf0/full +add wave -noupdate -expand -group FIFO_IN_f0 -expand /testbench/lpp_lfr_ms_1/memf0/empty +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/reuse +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/wen +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/ren +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/full +add wave -noupdate -expand -group FIFO_IN_f1 /testbench/lpp_lfr_ms_1/memf1/empty +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/reuse +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/wen +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/ren +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/full +add wave -noupdate -expand -group FIFO_IN_f2 /testbench/lpp_lfr_ms_1/memf2/empty +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/ect +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf1 +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/countf0 +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/load_reg +add wave -noupdate -expand -group DMUX /testbench/lpp_lfr_ms_1/dmux0/i +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/ect +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/load +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/sload +add wave -noupdate -expand -group DRIVE /testbench/lpp_lfr_ms_1/fft0/drive/fifocpt +add wave -noupdate -expand -group DRIVE -format Analog-Step -max 256.0 /testbench/lpp_lfr_ms_1/fft0/drive/datacount +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_write +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_datare +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/drive_dataim +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_IN /testbench/lpp_lfr_ms_1/fft0/fft_load +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_dataim +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_datare +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_valid +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/fft_ready +add wave -noupdate -expand -group CORE_FFT -expand -group FFT_OUT /testbench/lpp_lfr_ms_1/fft0/link_read +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/fft0/fft_ongoing +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/ect +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/fifocpt +add wave -noupdate /testbench/lpp_lfr_ms_1/fft0/link/full +add wave -noupdate -divider HeaderBuilder +add wave -noupdate -expand -group HeaderBuilder -expand -group in -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/statu +add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_type +add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/matrix_write +add wave -noupdate -expand -group HeaderBuilder -expand -group in /testbench/lpp_lfr_ms_1/head0/valid +add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/datain +add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/emptyin +add wave -noupdate -expand -group HeaderBuilder -expand -group data_in /testbench/lpp_lfr_ms_1/head0/renout +add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/emptyout +add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/renout +add wave -noupdate -expand -group HeaderBuilder -expand -group data_out /testbench/lpp_lfr_ms_1/head0/dataout +add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_ack +add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header +add wave -noupdate -expand -group HeaderBuilder -expand -group HeaderOut /testbench/lpp_lfr_ms_1/head0/header_val +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/write_reg +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/max +add wave -noupdate -expand -group HeaderBuilder -radix hexadecimal /testbench/lpp_lfr_ms_1/head0/matrix_param +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/data_cpt +add wave -noupdate -expand -group HeaderBuilder /testbench/lpp_lfr_ms_1/head0/ect +add wave -noupdate -divider FSM_DMA +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_ack +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg_val +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_reg +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_ack +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_val +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_done +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_addr +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_data +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_ren +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid +add wave -noupdate -expand -group DMA /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/dma_valid_burst +add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_data +add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty +add wave -noupdate -expand -group FIFO /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_ren +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_send +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_select +add wave -noupdate /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {10452115000 ps} 0} {{Cursor 2} {20841165000 ps} 0} +configure wave -namecolwidth 374 +configure wave -valuecolwidth 44 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {20841123375 ps} {20841198726 ps} diff --git a/designs/LFR_simu_ms/wave_waveform_longsim.do b/designs/LFR_simu_ms/wave_waveform_longsim.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu_ms/wave_waveform_longsim.do @@ -0,0 +1,70 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate /testbench/lpp_lfr_1/lpp_lfr_apbreg_1/status_full +add wave -noupdate /testbench/state_read_buffer_on_going +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid +add wave -noupdate -expand -group MEM -expand -group f2 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(193) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(192) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(191) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(190) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(189) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(188) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(187) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(186) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(185) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(184) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(183) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(182) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(181) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(180) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(179) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(178) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(177) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(176) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(175) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(174) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(173) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(172) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(171) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(170) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(169) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(168) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(167) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(166) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(165) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(164) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(163) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(162) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(161) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(160) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(159) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(158) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(157) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(156) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(155) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(154) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(153) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(152) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(151) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(150) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(149) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(148) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(147) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(146) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(145) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(144) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(143) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(142) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(141) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(140) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(139) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(138) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(137) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(136) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(135) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(134) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(133) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(132) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(131) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(130) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(129) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(128) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2 +add wave -noupdate -expand -group MEM -expand -group f2 -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(193) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(192) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(191) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(190) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(189) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(188) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(187) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(186) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(185) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(184) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(183) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(182) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(181) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(180) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(179) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(178) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(177) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(176) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(175) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(174) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(173) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(172) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(171) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(170) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(169) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(168) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(167) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(166) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(165) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(164) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(163) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(162) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(161) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(160) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(159) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(158) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(157) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(156) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(155) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(154) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(153) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(152) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(151) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(150) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(149) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(148) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(147) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(146) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(145) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(144) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(143) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(142) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(141) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(140) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(139) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(138) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(137) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(136) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(135) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(134) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(133) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(132) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(131) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(130) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(129) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(128) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 +add wave -noupdate -expand -group MEM -expand -group f1 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(193) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(192) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(191) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(190) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(189) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(188) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(187) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(186) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(185) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(184) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(183) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(182) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(181) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(180) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(179) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(178) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(177) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(176) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(175) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(174) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(173) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(172) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(171) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(170) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(169) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(168) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(167) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(166) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(165) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(164) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(163) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(162) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(161) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(160) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(159) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(158) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(157) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(156) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(155) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(154) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(153) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(152) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(151) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(150) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(149) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(148) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(147) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(146) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(145) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(144) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(143) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(142) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(141) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(140) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(139) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(138) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(137) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(136) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(135) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(134) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(133) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(132) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(131) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(130) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(129) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(128) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1 +add wave -noupdate -expand -group MEM -expand -group f1 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(193) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(192) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(191) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(190) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(189) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(188) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(187) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(186) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(185) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(184) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(183) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(182) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(181) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(180) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(179) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(178) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(177) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(176) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(175) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(174) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(173) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(172) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(171) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(170) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(169) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(168) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(167) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(166) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(165) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(164) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(163) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(162) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(161) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(160) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(159) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(158) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(157) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(156) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(155) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(154) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(153) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(152) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(151) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(150) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(149) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(148) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(147) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(146) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(145) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(144) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(143) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(142) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(141) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(140) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(139) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(138) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(137) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(136) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(135) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(134) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(133) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(132) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(131) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(130) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(129) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(128) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1 +add wave -noupdate -expand -group MEM -expand -group f0 -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(193) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(192) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(191) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(190) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(189) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(188) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(187) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(186) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(185) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(184) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(183) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(182) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(181) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(180) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(179) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(178) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(177) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(176) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(175) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(174) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(173) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(172) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(171) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(170) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(169) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(168) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(167) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(166) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(165) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(164) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(163) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(162) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(161) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(160) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(159) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(158) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(157) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(156) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(155) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(154) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(153) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(152) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(151) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(150) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(149) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(148) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(147) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(146) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(145) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(144) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(143) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(142) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(141) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(140) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(139) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(138) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(137) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(136) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(135) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(134) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(133) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(132) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(131) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(130) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(129) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(128) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0 +add wave -noupdate -expand -group MEM -expand -group f0 -radix hexadecimal /testbench/async_1mx16_1/mem_array_0 +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hbusreq {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hlock {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.htrans {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwrite {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hsize {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hburst {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hprot {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hirq {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hconfig {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hindex {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hgrant {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hready {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hresp {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hrdata {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.hirq {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testen {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testrst {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.scanen {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testoen {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in.testin {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/ahbso(0).hready {-radix hexadecimal} /testbench/ahbso(0).hresp {-radix hexadecimal} /testbench/ahbso(0).hrdata {-radix hexadecimal} /testbench/ahbso(0).hsplit {-radix hexadecimal} /testbench/ahbso(0).hirq {-radix hexadecimal} /testbench/ahbso(0).hconfig {-radix hexadecimal} /testbench/ahbso(0).hindex {-radix hexadecimal}} /testbench/ahbso(0) +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/ahbsi.hsel {-radix hexadecimal} /testbench/ahbsi.haddr {-radix hexadecimal} /testbench/ahbsi.hwrite {-radix hexadecimal} /testbench/ahbsi.htrans {-radix hexadecimal} /testbench/ahbsi.hsize {-radix hexadecimal} /testbench/ahbsi.hburst {-radix hexadecimal} /testbench/ahbsi.hwdata {-radix hexadecimal} /testbench/ahbsi.hprot {-radix hexadecimal} /testbench/ahbsi.hready {-radix hexadecimal} /testbench/ahbsi.hmaster {-radix hexadecimal} /testbench/ahbsi.hmastlock {-radix hexadecimal} /testbench/ahbsi.hmbsel {-radix hexadecimal} /testbench/ahbsi.hirq {-radix hexadecimal} /testbench/ahbsi.testen {-radix hexadecimal} /testbench/ahbsi.testrst {-radix hexadecimal} /testbench/ahbsi.scanen {-radix hexadecimal} /testbench/ahbsi.testoen {-radix hexadecimal} /testbench/ahbsi.testin {-radix hexadecimal}} /testbench/ahbsi +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_3 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_2 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_1 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_rdata_0 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_empty_almost +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_empty +add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_headreg_1/o_data_ren +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_ren +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f3_data_out_valid_burst +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f3_data_out_valid +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f3_addr_out +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f2_data_out_valid_burst +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f2_data_out_valid +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f2_addr_out +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f1_data_out_valid_burst +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f1_data_out_valid +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f1_addr_out +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f0_data_out_valid_burst +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/data_f0_data_out_valid +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/state +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/send_ok +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/send_ko +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/send +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/ren +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/hresetn +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/hclk +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/grant_counter +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/dmaout +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/dmain +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/data_counter +add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/data +add wave -noupdate -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/lpp_dma_send_16word_1/address +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {130825265 ns} 1} {{Cursor 2} {130825145 ns} 1} {{Cursor 3} {130825745 ns} 0} +configure wave -namecolwidth 530 +configure wave -valuecolwidth 64 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {130825588 ns} {130825885 ns} diff --git a/designs/MINI-LFR_testFFT-MS/MINI_LFR_top.vhd b/designs/MINI-LFR_testFFT-MS/MINI_LFR_top.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFT-MS/MINI_LFR_top.vhd @@ -0,0 +1,696 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib +USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY MINI_LFR_top IS + + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END MINI_LFR_top; + + +ARCHITECTURE beh OF MINI_LFR_top IS + + COMPONENT lpp_lfr_ms_tb + GENERIC ( + Mem_use : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; + MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr_apbreg_tb + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Full_2 : IN STD_LOGIC; + MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)); + END COMPONENT; + + + + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_24 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- UART AHB --------------------------------------------------------------- + SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data + SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data + SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data + -- + SIGNAL I00_s : STD_LOGIC; + + -- CONSTANTS + CONSTANT CFG_PADTECH : INTEGER := inferred; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; +-- SIGNAL clkmn : STD_ULOGIC; +-- SIGNAL txclk : STD_ULOGIC; + +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_nCS_sig : STD_LOGIC; + SIGNAL ADC_CLK_sig : STD_LOGIC; + SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL bias_fail_sw_sig : STD_LOGIC; + + SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); + ----------------------------------------------------------------------------- + + + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC; + SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0); + + + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + + PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + + PROCESS(clk_50_s) + BEGIN + IF clk_50_s'EVENT AND clk_50_s = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + PROCESS(clk_49) + BEGIN + IF clk_49'EVENT AND clk_49 = '1' THEN + clk_24 <= NOT clk_24; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + --IO1 <= '0'; + --IO2 <= '1'; + --IO3 <= '0'; + --IO4 <= '0'; + --IO5 <= '0'; + --IO6 <= '0'; + --IO7 <= '0'; + --IO8 <= '0'; + --IO9 <= '0'; + --IO10 <= '0'; + --IO11 <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; + --IO1 <= '1'; + --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; + --IO3 <= ADC_SDO(0); + --IO4 <= ADC_SDO(1); + --IO5 <= ADC_SDO(2); + --IO6 <= ADC_SDO(3); + --IO7 <= ADC_SDO(4); + --IO8 <= ADC_SDO(5); + --IO9 <= ADC_SDO(6); + --IO10 <= ADC_SDO(7); + --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk_24, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; +-- IO0 <= I00_s; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + + --EXT CONNECTOR + + --SPACE WIRE + + leon3_soc_1 : leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE) + PORT MAP ( + clk => clk_25, + reset => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1 : apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk_25, + clk24_576MHz => clk_24, -- 49.152MHz/2 + resetn => reset, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + SPW_EN <= '1'; + + spw_clk <= clk_50_s; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DIN, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SIN, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DOUT, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SOUT, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_SIN, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_DIN, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_DOUT, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_SOUT, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(reset, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + + lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb + GENERIC MAP ( + pindex => 15, + paddr => 15, + pmask => 16#fff#) + PORT MAP ( + HCLK => clk_25, + HRESETn => reset, + apbi => apbi_ext, + apbo => apbo_ext(15), + + sample_f0_wen => sample_f0_wen, + sample_f1_wen => sample_f1_wen, + sample_f2_wen => sample_f2_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wdata => sample_f2_wdata, + + MEM_OUT_SM_ren => MEM_OUT_SM_ren , + MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , + MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , + MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , + MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); + + lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb + GENERIC MAP ( + Mem_use =>use_RAM) + PORT MAP ( + clk => clk_25, + rstn => reset, + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + + MEM_OUT_SM_Read => MEM_OUT_SM_ren , + MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , + MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad , + MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 , + MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad, + + error_input_fifo_write => OPEN, + observation_vector_0 => observation_vector_0, + observation_vector_1 => observation_vector_1); + + ----------------------------------------------------------------------------- + + + + + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; + END GENERATE all_sample; + + + + top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 + GENERIC MAP( + ChannelCount => 8, + SampleNbBits => 14, + ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 + ncycle_cnv => 249) -- 49 152 000 / 98304 /2 + PORT MAP ( + -- CONV + cnv_clk => clk_24, + cnv_rstn => reset, + cnv => ADC_nCS_sig, + -- DATA + clk => clk_25, + rstn => reset, + sck => ADC_CLK_sig, + sdo => ADC_SDO_sig, + -- SAMPLE + sample => sample, + sample_val => sample_val); + + --IO10 <= ADC_SDO_sig(5); + --IO9 <= ADC_SDO_sig(4); + --IO8 <= ADC_SDO_sig(3); + + ADC_nCS <= ADC_nCS_sig; + ADC_CLK <= ADC_CLK_sig; + ADC_SDO_sig <= ADC_SDO; + +---------------------------------------------------------------------- +--- GPIO ----------------------------------------------------------- +---------------------------------------------------------------------- + + grgpio0 : grgpio + GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) + PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); + + --pio_pad_0 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); + --pio_pad_1 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); + --pio_pad_2 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); + --pio_pad_3 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); + --pio_pad_4 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); + --pio_pad_5 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); + --pio_pad_6 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); + --pio_pad_7 : iopad + -- GENERIC MAP (tech => CFG_PADTECH) + -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + IO0 <= '0'; + IO1 <= '0'; + IO2 <= '0'; + IO3 <= '0'; + IO4 <= '0'; + IO5 <= '0'; + IO6 <= '0'; + IO7 <= '0'; + IO8 <= '0'; + IO9 <= '0'; + IO10 <= '0'; + IO11 <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + CASE gpioo.dout(2 DOWNTO 0) IS + WHEN "011" => + IO0 <= observation_reg(0); + IO1 <= observation_reg(1); + IO2 <= observation_reg(2); + IO3 <= observation_reg(3); + IO4 <= observation_reg(4); + IO5 <= observation_reg(5); + IO6 <= observation_reg(6); + IO7 <= observation_reg(7); + IO8 <= observation_reg(8); + IO9 <= observation_reg(9); + IO10 <= observation_reg(10); + IO11 <= observation_reg(11); + WHEN "001" => + IO0 <= observation_reg(0 + 12); + IO1 <= observation_reg(1 + 12); + IO2 <= observation_reg(2 + 12); + IO3 <= observation_reg(3 + 12); + IO4 <= observation_reg(4 + 12); + IO5 <= observation_reg(5 + 12); + IO6 <= observation_reg(6 + 12); + IO7 <= observation_reg(7 + 12); + IO8 <= observation_reg(8 + 12); + IO9 <= observation_reg(9 + 12); + IO10 <= observation_reg(10 + 12); + IO11 <= observation_reg(11 + 12); + WHEN "010" => + IO0 <= observation_reg(0 + 12 + 12); + IO1 <= observation_reg(1 + 12 + 12); + IO2 <= observation_reg(2 + 12 + 12); + IO3 <= observation_reg(3 + 12 + 12); + IO4 <= observation_reg(4 + 12 + 12); + IO5 <= observation_reg(5 + 12 + 12); + IO6 <= observation_reg(6 + 12 + 12); + IO7 <= observation_reg(7 + 12 + 12); + IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2); + IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5); + IO10 <= ADC_SDO(6) OR ADC_SDO(7) ; + IO11 <= '0'; + WHEN "000" => + IO0 <= observation_vector_0(0); + IO1 <= observation_vector_0(1); + IO2 <= observation_vector_0(2); + IO3 <= observation_vector_0(3); + IO4 <= observation_vector_0(4); + IO5 <= observation_vector_0(5); + IO6 <= observation_vector_0(6); + IO7 <= observation_vector_0(7); + IO8 <= observation_vector_0(8); + IO9 <= observation_vector_0(9); + IO10 <= observation_vector_0(10); + IO11 <= observation_vector_0(11); + WHEN "100" => + IO0 <= observation_vector_1(0); + IO1 <= observation_vector_1(1); + IO2 <= observation_vector_1(2); + IO3 <= observation_vector_1(3); + IO4 <= observation_vector_1(4); + IO5 <= observation_vector_1(5); + IO6 <= observation_vector_1(6); + IO7 <= observation_vector_1(7); + IO8 <= observation_vector_1(8); + IO9 <= observation_vector_1(9); + IO10 <= observation_vector_1(10); + IO11 <= observation_vector_1(11); + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + +END beh; \ No newline at end of file diff --git a/designs/MINI-LFR_testFFT-MS/Makefile b/designs/MINI-LFR_testFFT-MS/Makefile new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFT-MS/Makefile @@ -0,0 +1,47 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=MINI_LFR_top +BOARD=MINI-LFR +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd + +PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP =i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_SIMPLE_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/MINI-LFR_testFFT-MS/fft_test.vhd b/designs/MINI-LFR_testFFT-MS/fft_test.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFT-MS/fft_test.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; + +ENTITY lpp_lfr_ms IS + GENERIC ( + Mem_use : INTEGER := use_RAM + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms IS + +BEGIN + + ----------------------------------------------------------------------------- + + lppFIFOxN_f0_a : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f0_A_wen, + wdata => sample_f0_wdata, + + ren => sample_f0_A_ren, + rdata => sample_f0_A_rdata, + + empty => sample_f0_A_empty, + full => sample_f0_A_full, + almost_full => OPEN); + + ----------------------------------------------------------------------------- + + lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT + PORT MAP ( + clk => clk, + rstn => rstn, + sample_valid => sample_valid, -- WRITE in + fft_read => fft_read, -- READ in + sample_data => sample_data, -- WRITE in + sample_load => sample_load, -- WRITE out + fft_pong => fft_pong, -- READ out + fft_data_im => fft_data_im, -- READ out + fft_data_re => fft_data_re, -- READ out + fft_data_valid => fft_data_valid, -- READ out + fft_ready => fft_ready); -- READ out + + ----------------------------------------------------------------------------- + +END Behavioral; diff --git a/designs/MINI-LFR_testFFT-MS/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testFFT-MS/lpp_lfr_apbreg.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFT-MS/lpp_lfr_apbreg.vhd @@ -0,0 +1,195 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.lpp_lfr_pkg.ALL; +--USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_lfr_apbreg_tb IS + GENERIC ( + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + --------------------------------------------------------------------------- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + --------------------------------------------------------------------------- + MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Full_2 : IN STD_LOGIC; + MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0) + --------------------------------------------------------------------------- + ); + +END lpp_lfr_apbreg_tb; + +ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS + + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1), + 1 => apb_iobar(paddr, pmask)); + + TYPE reg_debug_fft IS RECORD + in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); + + in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0); + in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0); + in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + out_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); + END RECORD; + SIGNAL reg_ftt : reg_debug_fft; + + SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + --------------------------------------------------------------------------- + sample_f0_wen <= reg_ftt.in_wen_f0; + sample_f1_wen <= reg_ftt.in_wen_f1; + sample_f2_wen <= reg_ftt.in_wen_f2; + + sample_f0_wdata <= reg_ftt.in_data_f0; + sample_f1_wdata <= reg_ftt.in_data_f1; + sample_f2_wdata <= reg_ftt.in_data_f2; + --------------------------------------------------------------------------- + MEM_OUT_SM_ren <= reg_ftt.out_ren; + --------------------------------------------------------------------------- + + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); + BEGIN + IF HRESETn = '0' THEN + + reg_ftt.in_data_f0 <= (OTHERS => '0'); + reg_ftt.in_data_f1 <= (OTHERS => '0'); + reg_ftt.in_data_f2 <= (OTHERS => '0'); + + reg_ftt.in_wen_f0 <= (OTHERS => '1'); + reg_ftt.in_wen_f1 <= (OTHERS => '1'); + reg_ftt.in_wen_f2 <= (OTHERS => '1'); + + reg_ftt.out_ren <= (OTHERS => '1'); + + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + + reg_ftt.in_wen_f0 <= (OTHERS => '1'); + reg_ftt.in_wen_f1 <= (OTHERS => '1'); + reg_ftt.in_wen_f2 <= (OTHERS => '1'); + reg_ftt.out_ren <= (OTHERS => '1'); + + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + prdata <= (OTHERS => '0'); + IF apbi.psel(pindex) = '1' THEN + -- APB DMA READ -- + CASE paddr(7 DOWNTO 2) IS + --0 + WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0); + WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32); + WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64); + WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0; + + WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0); + WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32); + WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64); + WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1; + + WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0); + WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32); + WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64); + WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2; + + WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*1-1 DOWNTO 32*0); + WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*2-1 DOWNTO 32*1); + + WHEN "001110" => prdata(1 DOWNTO 0) <= reg_ftt.out_ren; + prdata(3 DOWNTO 2) <= MEM_OUT_SM_Full; + prdata(5 DOWNTO 4) <= MEM_OUT_SM_Empty; + prdata(6) <= MEM_OUT_SM_Full_2; + WHEN OTHERS => NULL; + + END CASE; + IF (apbi.pwrite AND apbi.penable) = '1' THEN + -- APB DMA WRITE -- + CASE paddr(7 DOWNTO 2) IS + WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata; + WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata; + WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata; + WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata; + WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata; + WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata; + WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0); + WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0); + + WHEN "001110" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); + + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + + END IF; + END PROCESS lpp_lfr_apbreg; + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.prdata <= prdata; + +END beh; \ No newline at end of file diff --git a/designs/MINI-LFR_testFFT-MS/lpp_lfr_ms_validation.vhd b/designs/MINI-LFR_testFFT-MS/lpp_lfr_ms_validation.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_testFFT-MS/lpp_lfr_ms_validation.vhd @@ -0,0 +1,1014 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; + +ENTITY lpp_lfr_ms_tb IS + GENERIC ( + Mem_use : INTEGER := use_RAM + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC; + MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + -- + observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS + + SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL error_wen_f0 : STD_LOGIC; + SIGNAL error_wen_f1 : STD_LOGIC; + SIGNAL error_wen_f2 : STD_LOGIC; + + SIGNAL one_sample_f1_full : STD_LOGIC; + SIGNAL one_sample_f1_wen : STD_LOGIC; + SIGNAL one_sample_f2_full : STD_LOGIC; + SIGNAL one_sample_f2_wen : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- FSM / SWITCH SELECT CHANNEL + ----------------------------------------------------------------------------- + TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); + SIGNAL state_fsm_select_channel : fsm_select_channel; + SIGNAL pre_state_fsm_select_channel : fsm_select_channel; + + SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- FSM LOAD FFT + ----------------------------------------------------------------------------- + TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); + SIGNAL state_fsm_load_FFT : fsm_load_FFT; + SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; + + SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_load : STD_LOGIC; + SIGNAL sample_valid : STD_LOGIC; + SIGNAL sample_valid_r : STD_LOGIC; + SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + + + ----------------------------------------------------------------------------- + -- FFT + ----------------------------------------------------------------------------- + SIGNAL fft_read : STD_LOGIC; + SIGNAL fft_pong : STD_LOGIC; + SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_valid : STD_LOGIC; + SIGNAL fft_ready : STD_LOGIC; + ----------------------------------------------------------------------------- +-- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); + SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; + SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL current_fifo_empty : STD_LOGIC; + SIGNAL current_fifo_locked : STD_LOGIC; + SIGNAL current_fifo_full : STD_LOGIC; + SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); + SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); + SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL SM_correlation_start : STD_LOGIC; + SIGNAL SM_correlation_auto : STD_LOGIC; + SIGNAL SM_correlation_done : STD_LOGIC; + SIGNAL SM_correlation_done_reg1 : STD_LOGIC; + SIGNAL SM_correlation_done_reg2 : STD_LOGIC; + SIGNAL SM_correlation_done_reg3 : STD_LOGIC; + SIGNAL SM_correlation_begin : STD_LOGIC; + + SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; + SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; + + SIGNAL current_matrix_write : STD_LOGIC; + SIGNAL current_matrix_wait_empty : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fifo_0_ready : STD_LOGIC; + SIGNAL fifo_1_ready : STD_LOGIC; + SIGNAL fifo_ongoing : STD_LOGIC; + + SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; + SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; + SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); +-- SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); +-- SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- TIME REG & INFOs + ----------------------------------------------------------------------------- + SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); + + SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + + SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + --SIGNAL time_update_f0_A : STD_LOGIC; + --SIGNAL time_update_f0_B : STD_LOGIC; + --SIGNAL time_update_f1 : STD_LOGIC; + --SIGNAL time_update_f2 : STD_LOGIC; + -- + SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); + SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); + SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); + + SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); + SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); + SIGNAL status_component_fifo_0_end : STD_LOGIC; + SIGNAL status_component_fifo_1_end : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); + + SIGNAL fft_ready_reg : STD_LOGIC; + SIGNAL fft_ready_rising_down : STD_LOGIC; + + SIGNAL sample_load_reg : STD_LOGIC; + SIGNAL sample_load_rising_down : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen_head_in : STD_LOGIC; + SIGNAL sample_f1_wen_head_out : STD_LOGIC; + SIGNAL sample_f1_full_head_in : STD_LOGIC; + SIGNAL sample_f1_full_head_out : STD_LOGIC; + SIGNAL sample_f1_empty_head_in : STD_LOGIC; + + SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + +BEGIN + + + error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; + + + switch_f0_inst : spectral_matrix_switch_f0 + PORT MAP ( + clk => clk, + rstn => rstn, + + sample_wen => sample_f0_wen, + + fifo_A_empty => sample_f0_A_empty, + fifo_A_full => sample_f0_A_full, + fifo_A_wen => sample_f0_A_wen, + + fifo_B_empty => sample_f0_B_empty, + fifo_B_full => sample_f0_B_full, + fifo_B_wen => sample_f0_B_wen, + + error_wen => error_wen_f0); -- TODO + + ----------------------------------------------------------------------------- + -- FIFO IN + ----------------------------------------------------------------------------- + lppFIFOxN_f0_a : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f0_A_wen, + wdata => sample_f0_wdata, + + ren => sample_f0_A_ren, + rdata => sample_f0_A_rdata, + + empty => sample_f0_A_empty, + full => sample_f0_A_full, + almost_full => OPEN); + + lppFIFOxN_f0_b : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f0_B_wen, + wdata => sample_f0_wdata, + ren => sample_f0_B_ren, + rdata => sample_f0_B_rdata, + empty => sample_f0_B_empty, + full => sample_f0_B_full, + almost_full => OPEN); + + ----------------------------------------------------------------------------- + -- sample_f1_wen in + -- sample_f1_wdata in + -- sample_f1_full OUT + + sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; + sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; + sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; + + lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head + PORT MAP ( + clk => clk, + rstn => rstn, + in_wen => sample_f1_wen_head_in, + in_data => sample_f1_wdata, + in_full => sample_f1_full_head_in, + in_empty => sample_f1_empty_head_in, + out_wen => sample_f1_wen_head_out, + out_data => sample_f1_wdata_head, + out_full => sample_f1_full_head_out); + + sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; + + + lppFIFOxN_f1 : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f1_wen_head, + wdata => sample_f1_wdata_head, + ren => sample_f1_ren, + rdata => sample_f1_rdata, + empty => sample_f1_empty, + full => sample_f1_full, + almost_full => sample_f1_almost_full); + + + one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + one_sample_f1_full <= '0'; + error_wen_f1 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_f1_full_head_out = '0' THEN + one_sample_f1_full <= '0'; + ELSE + one_sample_f1_full <= '1'; + END IF; + error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + + lppFIFOxN_f2 : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => sample_f2_wen, + wdata => sample_f2_wdata, + ren => sample_f2_ren, + rdata => sample_f2_rdata, + empty => sample_f2_empty, + full => sample_f2_full, + almost_full => OPEN); + + + one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + one_sample_f2_full <= '0'; + error_wen_f2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_f2_full = "00000" THEN + one_sample_f2_full <= '0'; + ELSE + one_sample_f2_full <= '1'; + END IF; + error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- FSM SELECT CHANNEL + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_fsm_select_channel <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_select_channel IS + WHEN IDLE => + IF sample_f1_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F1; + ELSIF sample_f1_almost_full = "00000" THEN + IF sample_f0_A_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F0_A; + ELSIF sample_f0_B_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F0_B; + ELSIF sample_f2_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F2; + END IF; + END IF; + + WHEN SWITCH_F0_A => + IF sample_f0_A_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F0_B => + IF sample_f0_B_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F1 => + IF sample_f1_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F2 => + IF sample_f2_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + pre_state_fsm_select_channel <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + pre_state_fsm_select_channel <= state_fsm_select_channel; + END IF; + END PROCESS; + + + ----------------------------------------------------------------------------- + -- SWITCH SELECT CHANNEL + ----------------------------------------------------------------------------- + sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE + (OTHERS => '1'); + + sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE + (OTHERS => '0'); + + sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE + + + sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); + sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); + sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); + sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); + + + status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE + time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 + + ----------------------------------------------------------------------------- + -- FSM LOAD FFT + ----------------------------------------------------------------------------- + + sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE + sample_ren_s WHEN sample_load = '1' ELSE + (OTHERS => '1'); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= IDLE; + status_MS_input <= (OTHERS => '0'); + --next_state_fsm_load_FFT <= IDLE; + --sample_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_load_FFT IS + WHEN IDLE => + --sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + IF sample_full = "11111" AND sample_load = '1' THEN + state_fsm_load_FFT <= FIFO_1; + status_MS_input <= status_channel; + END IF; + + WHEN FIFO_1 => + sample_ren_s <= "1111" & NOT(sample_load); + IF sample_empty(0) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_2; + END IF; + + WHEN FIFO_2 => + sample_ren_s <= "111" & NOT(sample_load) & '1'; + IF sample_empty(1) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_3; + END IF; + + WHEN FIFO_3 => + sample_ren_s <= "11" & NOT(sample_load) & "11"; + IF sample_empty(2) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_4; + END IF; + + WHEN FIFO_4 => + sample_ren_s <= '1' & NOT(sample_load) & "111"; + IF sample_empty(3) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_5; + END IF; + + WHEN FIFO_5 => + sample_ren_s <= NOT(sample_load) & "1111"; + IF sample_empty(4) = '1' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_valid_r <= '0'; + next_state_fsm_load_FFT <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + next_state_fsm_load_FFT <= state_fsm_load_FFT; + IF sample_ren_s = "11111" THEN + sample_valid_r <= '0'; + ELSE + sample_valid_r <= '1'; + END IF; + END IF; + END PROCESS; + + sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; + + sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE + sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE + sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE + sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE + sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE + + ----------------------------------------------------------------------------- + -- FFT + ----------------------------------------------------------------------------- + lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT + PORT MAP ( + clk => clk, + rstn => rstn, + sample_valid => sample_valid, + fft_read => fft_read, + sample_data => sample_data, + sample_load => sample_load, + fft_pong => fft_pong, + fft_data_im => fft_data_im, + fft_data_re => fft_data_re, + fft_data_valid => fft_data_valid, + fft_ready => fft_ready); + + observation_vector_0(11 DOWNTO 0) <= "000" & --11 10 + fft_ongoing_counter & --9 8 + sample_load_rising_down & --7 + fft_ready_rising_down & --6 + fft_ready & --5 + fft_data_valid & --4 + fft_pong & --3 + sample_load & --2 + fft_read & --1 + sample_valid; --0 + + ----------------------------------------------------------------------------- + fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; + sample_load_rising_down <= sample_load_reg AND NOT sample_load; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + fft_ready_reg <= '0'; + sample_load_reg <= '0'; + + fft_ongoing_counter <= '0'; + ELSIF clk'event AND clk = '1' THEN + fft_ready_reg <= fft_ready; + sample_load_reg <= sample_load; + + IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN + fft_ongoing_counter <= '0'; + +-- CASE fft_ongoing_counter IS +-- WHEN "01" => fft_ongoing_counter <= "00"; +---- WHEN "10" => fft_ongoing_counter <= "01"; +-- WHEN OTHERS => NULL; +-- END CASE; + ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN + fft_ongoing_counter <= '1'; +-- CASE fft_ongoing_counter IS +-- WHEN "00" => fft_ongoing_counter <= "01"; +---- WHEN "01" => fft_ongoing_counter <= "10"; +-- WHEN OTHERS => NULL; +-- END CASE; + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_fsm_load_MS_memory <= IDLE; + current_fifo_load <= "00001"; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_load_MS_memory IS + WHEN IDLE => + IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN + state_fsm_load_MS_memory <= LOAD_FIFO; + END IF; + WHEN LOAD_FIFO => + IF current_fifo_full = '1' THEN + state_fsm_load_MS_memory <= TRASH_FFT; + END IF; + WHEN TRASH_FFT => + IF fft_ready = '0' THEN + state_fsm_load_MS_memory <= IDLE; + current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); + END IF; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE + MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE + MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE + MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE + MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE + + current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE + MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE + MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE + MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE + MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE + + current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE + MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE + MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE + MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE + MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE + + fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; + + all_fifo : FOR I IN 4 DOWNTO 0 GENERATE + MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' + AND state_fsm_load_MS_memory = LOAD_FIFO + AND current_fifo_load(I) = '1' + ELSE '1'; + END GENERATE all_fifo; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + MEM_IN_SM_wen <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN + MEM_IN_SM_wen <= MEM_IN_SM_wen_s; + END IF; + END PROCESS; + + MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re) & + (fft_data_im & fft_data_re); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + Mem_In_SpectralMatrix : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 32, --16, + Addr_sz => 7, --8 + FifoCnt => 5) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => MEM_IN_SM_ReUse, + + wen => MEM_IN_SM_wen, + wdata => MEM_IN_SM_wData, + + ren => MEM_IN_SM_ren, + rdata => MEM_IN_SM_rData, + full => MEM_IN_SM_Full, + empty => MEM_IN_SM_Empty, + almost_full => OPEN); + + ----------------------------------------------------------------------------- + + observation_vector_1(11 DOWNTO 0) <= '0' & + SM_correlation_done & --4 + SM_correlation_auto & --3 + SM_correlation_start & + SM_correlation_start & --7 + status_MS_input(1 DOWNTO 0)& --6..5 + MEM_IN_SM_locked(4 DOWNTO 0); --4..0 + + ----------------------------------------------------------------------------- + MS_control_1 : MS_control + PORT MAP ( + clk => clk, + rstn => rstn, + + current_status_ms => status_MS_input, + + fifo_in_lock => MEM_IN_SM_locked, + fifo_in_data => MEM_IN_SM_rdata, + fifo_in_full => MEM_IN_SM_Full, + fifo_in_empty => MEM_IN_SM_Empty, + fifo_in_ren => MEM_IN_SM_ren, + fifo_in_reuse => MEM_IN_SM_ReUse, + + fifo_out_data => SM_in_data, + fifo_out_ren => SM_in_ren, + fifo_out_empty => SM_in_empty, + + current_status_component => status_component, + + correlation_start => SM_correlation_start, + correlation_auto => SM_correlation_auto, + correlation_done => SM_correlation_done); + + + MS_calculation_1 : MS_calculation + PORT MAP ( + clk => clk, + rstn => rstn, + + fifo_in_data => SM_in_data, + fifo_in_ren => SM_in_ren, + fifo_in_empty => SM_in_empty, + + fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO + fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO + fifo_out_full => MEM_OUT_SM_Full_s, -- TODO + + correlation_start => SM_correlation_start, + correlation_auto => SM_correlation_auto, + correlation_begin => SM_correlation_begin, + correlation_done => SM_correlation_done); + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + current_matrix_write <= '0'; + current_matrix_wait_empty <= '1'; + status_component_fifo_0 <= (OTHERS => '0'); + status_component_fifo_1 <= (OTHERS => '0'); + status_component_fifo_0_end <= '0'; + status_component_fifo_1_end <= '0'; + SM_correlation_done_reg1 <= '0'; + SM_correlation_done_reg2 <= '0'; + SM_correlation_done_reg3 <= '0'; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + SM_correlation_done_reg1 <= SM_correlation_done; + SM_correlation_done_reg2 <= SM_correlation_done_reg1; + SM_correlation_done_reg3 <= SM_correlation_done_reg2; + status_component_fifo_0_end <= '0'; + status_component_fifo_1_end <= '0'; + IF SM_correlation_begin = '1' THEN + IF current_matrix_write = '0' THEN + status_component_fifo_0 <= status_component; + ELSE + status_component_fifo_1 <= status_component; + END IF; + END IF; + + IF SM_correlation_done_reg3 = '1' THEN + IF current_matrix_write = '0' THEN + status_component_fifo_0_end <= '1'; + ELSE + status_component_fifo_1_end <= '1'; + END IF; + current_matrix_wait_empty <= '1'; + current_matrix_write <= NOT current_matrix_write; + END IF; + + IF current_matrix_wait_empty <= '1' THEN + IF current_matrix_write = '0' THEN + current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); + ELSE + current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); + END IF; + END IF; + + END IF; + END PROCESS; + + MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE + '1' WHEN SM_correlation_done_reg1 = '1' ELSE + '1' WHEN SM_correlation_done_reg2 = '1' ELSE + '1' WHEN SM_correlation_done_reg3 = '1' ELSE + '1' WHEN current_matrix_wait_empty = '1' ELSE + MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE + MEM_OUT_SM_Full(1); + + MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; + MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; + + MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; + ----------------------------------------------------------------------------- + + Mem_Out_SpectralMatrix : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 32, + Addr_sz => 8, + FifoCnt => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + + ReUse => (OTHERS => '0'), + + wen => MEM_OUT_SM_Write, + wdata => MEM_OUT_SM_Data_in, + + ren => MEM_OUT_SM_Read, + rdata => MEM_OUT_SM_Data_out, + + full => MEM_OUT_SM_Full, + empty => MEM_OUT_SM_Empty, + almost_full => OPEN); + + MEM_OUT_SM_Full_pad <= MEM_OUT_SM_Full; + MEM_OUT_SM_Full_pad_2 <= MEM_OUT_SM_Full_s; + MEM_OUT_SM_Empty_pad <= MEM_OUT_SM_Empty; + +-- ----------------------------------------------------------------------------- +---- MEM_OUT_SM_Read <= "00"; +-- PROCESS (clk, rstn) +-- BEGIN +-- IF rstn = '0' THEN +-- fifo_0_ready <= '0'; +-- fifo_1_ready <= '0'; +-- fifo_ongoing <= '0'; +-- ELSIF clk'EVENT AND clk = '1' THEN +-- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN +-- fifo_ongoing <= '1'; +-- fifo_0_ready <= '0'; +-- ELSIF status_component_fifo_0_end = '1' THEN +-- fifo_0_ready <= '1'; +-- END IF; + +-- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN +-- fifo_ongoing <= '0'; +-- fifo_1_ready <= '0'; +-- ELSIF status_component_fifo_1_end = '1' THEN +-- fifo_1_ready <= '1'; +-- END IF; + +-- END IF; +-- END PROCESS; + +-- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE +-- '1' WHEN fifo_0_ready = '0' ELSE +-- FSM_DMA_fifo_ren; + +-- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE +-- '1' WHEN fifo_1_ready = '0' ELSE +-- FSM_DMA_fifo_ren; + +-- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE +-- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE +-- '1'; + +-- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE +-- status_component_fifo_1; + +-- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE +-- MEM_OUT_SM_Data_out(63 DOWNTO 32); + +-- ----------------------------------------------------------------------------- +-- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma +-- PORT MAP ( +-- HCLK => clk, +-- HRESETn => rstn, + +-- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), +-- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), +-- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), +-- fifo_data => FSM_DMA_fifo_data, +-- fifo_empty => FSM_DMA_fifo_empty, +-- fifo_ren => FSM_DMA_fifo_ren, + +-- dma_addr => dma_addr, +-- dma_data => dma_data, +-- dma_valid => dma_valid, +-- dma_valid_burst => dma_valid_burst, +-- dma_ren => dma_ren, +-- dma_done => dma_done, + +-- ready_matrix_f0 => ready_matrix_f0, +-- ready_matrix_f1 => ready_matrix_f1, +-- ready_matrix_f2 => ready_matrix_f2, + +-- error_bad_component_error => error_bad_component_error, +-- error_buffer_full => error_buffer_full, + +-- debug_reg => debug_reg, +-- status_ready_matrix_f0 => status_ready_matrix_f0, +-- status_ready_matrix_f1 => status_ready_matrix_f1, +-- status_ready_matrix_f2 => status_ready_matrix_f2, + +-- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, +-- config_active_interruption_onError => config_active_interruption_onError, + +-- addr_matrix_f0 => addr_matrix_f0, +-- addr_matrix_f1 => addr_matrix_f1, +-- addr_matrix_f2 => addr_matrix_f2, + +-- matrix_time_f0 => matrix_time_f0, +-- matrix_time_f1 => matrix_time_f1, +-- matrix_time_f2 => matrix_time_f2 +-- ); +-- ----------------------------------------------------------------------------- + + + + + +-- ----------------------------------------------------------------------------- +-- -- TIME MANAGMENT +-- ----------------------------------------------------------------------------- +-- all_time <= coarse_time & fine_time; +-- -- +-- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; +-- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; +-- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; +-- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; + +-- all_time_reg: FOR I IN 0 TO 3 GENERATE + +-- PROCESS (clk, rstn) +-- BEGIN +-- IF rstn = '0' THEN +-- f_empty_reg(I) <= '1'; +-- ELSIF clk'event AND clk = '1' THEN +-- f_empty_reg(I) <= f_empty(I); +-- END IF; +-- END PROCESS; + +-- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; + +-- s_m_t_m_f0_A : spectral_matrix_time_managment +-- PORT MAP ( +-- clk => clk, +-- rstn => rstn, +-- time_in => all_time, +-- update_1 => time_update_f(I), +-- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) +-- ); + +-- END GENERATE all_time_reg; + +-- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); +-- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); +-- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); +-- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); + +-- ----------------------------------------------------------------------------- + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -338,6 +338,24 @@ COMPONENT ADS7886_drvr_v2 IS sample_val : OUT STD_LOGIC ); END COMPONENT; + +COMPONENT top_ad_conv_RHF1401_withFilter + GENERIC ( + ChanelCount : INTEGER; + ncycle_cnv_high : INTEGER; + ncycle_cnv : INTEGER); + PORT ( + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + ADC_data : IN Samples14; + ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC); +END COMPONENT; + END lpp_ad_conv; diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd @@ -0,0 +1,221 @@ + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.general_purpose.SYNC_FF; + +ENTITY top_ad_conv_RHF1401_withFilter IS + GENERIC( + ChanelCount : INTEGER := 8; + ncycle_cnv_high : INTEGER := 13; + ncycle_cnv : INTEGER := 25); + PORT ( + cnv_clk : IN STD_LOGIC; -- 24Mhz + cnv_rstn : IN STD_LOGIC; + + cnv : OUT STD_LOGIC; + + clk : IN STD_LOGIC; -- 25MHz + rstn : IN STD_LOGIC; + ADC_data : IN Samples14; + ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END top_ad_conv_RHF1401_withFilter; + +ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS + + SIGNAL cnv_cycle_counter : INTEGER; + SIGNAL cnv_s : STD_LOGIC; + SIGNAL cnv_sync : STD_LOGIC; + SIGNAL cnv_sync_pre : STD_LOGIC; + + SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + SIGNAL enable_ADC : STD_LOGIC; + + + SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); + + SIGNAL channel_counter : INTEGER; + CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; + + SIGNAL ADC_data_selected : Samples14; + SIGNAL ADC_data_result : Samples14; + + SIGNAL sample_counter : INTEGER; + +BEGIN + + + ----------------------------------------------------------------------------- + -- CNV GEN + ----------------------------------------------------------------------------- + PROCESS (cnv_clk, cnv_rstn) + BEGIN -- PROCESS + IF cnv_rstn = '0' THEN -- asynchronous reset (active low) + cnv_cycle_counter <= 0; + cnv_s <= '0'; + ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge + IF cnv_cycle_counter < ncycle_cnv-1 THEN + cnv_cycle_counter <= cnv_cycle_counter + 1; + IF cnv_cycle_counter < ncycle_cnv_high THEN + cnv_s <= '1'; + ELSE + cnv_s <= '0'; + END IF; + ELSE + cnv_s <= '1'; + cnv_cycle_counter <= 0; + END IF; + END IF; + END PROCESS; + + cnv <= cnv_s; + + + ----------------------------------------------------------------------------- + -- SYNC CNV + ----------------------------------------------------------------------------- + + SYNC_FF_cnv : SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + A => cnv_s, + A_sync => cnv_sync); + + + ----------------------------------------------------------------------------- + -- DATA GEN Output Enable + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1'); + cnv_sync_pre <= '0'; + enable_ADC <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + cnv_sync_pre <= cnv_sync; + IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN + enable_ADC <= '1'; + ADC_nOE_reg(0) <= '0'; + ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1'); + ELSE + enable_ADC <= NOT enable_ADC; + IF enable_ADC = '0' THEN + ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1'; + END IF; + END IF; + + END IF; + END PROCESS; + + ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg; + + ----------------------------------------------------------------------------- + -- ADC READ DATA + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + channel_counter <= MAX_COUNTER; + sample_reg(0) <= (OTHERS => '0'); + sample_reg(1) <= (OTHERS => '0'); + sample_reg(2) <= (OTHERS => '0'); + sample_reg(3) <= (OTHERS => '0'); + sample_reg(4) <= (OTHERS => '0'); + sample_reg(5) <= (OTHERS => '0'); + sample_reg(6) <= (OTHERS => '0'); + sample_reg(7) <= (OTHERS => '0'); + + sample_val <= '0'; + sample_counter <= 0; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN + channel_counter <= 0; + ELSE + IF channel_counter < MAX_COUNTER THEN + channel_counter <= channel_counter + 1; + END IF; + END IF; + sample_val <= '0'; + + CASE channel_counter IS + WHEN 0*2 => sample_reg(0) <= ADC_data_result; + WHEN 1*2 => sample_reg(1) <= ADC_data_result; + WHEN 2*2 => sample_reg(2) <= ADC_data_result; + WHEN 3*2 => sample_reg(3) <= ADC_data_result; + WHEN 4*2 => sample_reg(4) <= ADC_data_result; + WHEN 5*2 => sample_reg(5) <= ADC_data_result; + WHEN 6*2 => sample_reg(6) <= ADC_data_result; + WHEN 7*2 => sample_reg(7) <= ADC_data_result; + IF sample_counter = 9 THEN + sample_counter <= 0 ; + sample_val <= '1'; + ELSE + sample_counter <= sample_counter +1; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + + WITH channel_counter SELECT + ADC_data_selected <= sample_reg(0) WHEN 0*2, + sample_reg(1) WHEN 1*2, + sample_reg(2) WHEN 2*2, + sample_reg(3) WHEN 3*2, + sample_reg(4) WHEN 4*2, + sample_reg(5) WHEN 5*2, + sample_reg(6) WHEN 6*2, + sample_reg(7) WHEN OTHERS ; + + + ADC_data_result <= std_logic_vector( (signed(ADC_data_selected) + signed(ADC_data)) / 2); + + sample <= sample_reg; + + + + + --RHF1401_drvr_1: RHF1401_drvr + -- GENERIC MAP ( + -- ChanelCount => ChanelCount) + -- PORT MAP ( + -- cnv_clk => cnv_sync, + -- clk => clk, + -- rstn => rstn, + -- ADC_data => ADC_data, + -- --ADC_smpclk => OPEN, + -- ADC_nOE => ADC_nOE, + -- sample => sample, + -- sample_val => sample_val); + + + + +END ar_top_ad_conv_RHF1401; + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt --- a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt +++ b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt @@ -1,6 +1,7 @@ lpp_ad_Conv.vhd RHF1401.vhd top_ad_conv_RHF1401.vhd +top_ad_conv_RHF1401_withFilter.vhd TestModule_RHF1401.vhd top_ad_conv_ADS7886_v2.vhd ADS7886_drvr_v2.vhd