# HG changeset patch # User Alexis Jeandet # Date 2016-11-25 16:47:44 # Node ID c45d52d9ef549fef1cf86de8bc5fbb97d6cdb51c # Parent a51e161e84faeb108ab63ba76918c27128518f19 Added AdvancedTrigger IP. Added DiscoSpace board. Added Timegen design. diff --git a/boards/DISCOSPACE/DISCOSPACE.sdc b/boards/DISCOSPACE/DISCOSPACE.sdc new file mode 100644 --- /dev/null +++ b/boards/DISCOSPACE/DISCOSPACE.sdc @@ -0,0 +1,114 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Fri Apr 24 16:02:16 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } + +create_clock -name { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] +set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \ +data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \ +data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \ +data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \ +data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \ +data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \ +data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}] + +#set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] +#set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] +#set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] +set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \ +data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \ +data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \ +data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \ +data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \ +data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \ +data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \ +address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \ +address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \ +address[7] SRAM_A[8] SRAM_A[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \ +address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \ +address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \ +address[7] SRAM_A[8] SRAM_A[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }] + + +######## Delay Constraints ######## + +set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/DISCOSPACE/Makefile.inc b/boards/DISCOSPACE/Makefile.inc new file mode 100644 --- /dev/null +++ b/boards/DISCOSPACE/Makefile.inc @@ -0,0 +1,19 @@ +PACKAGE=\"\" +SPEED=Std +SYNFREQ=50 + +TECHNOLOGY=ProASIC3E +LIBERO_DIE=IT14X14M4 +PART=A3PE3000 + +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM +DESIGNER_PACKAGE=FBGA +DESIGNER_PINS=324 + +MANUFACTURER=Actel +MGCTECHNOLOGY=Proasic3 +MGCPART=$(PART) +MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} +LIBERO_PACKAGE=fg$(DESIGNER_PINS) + diff --git a/boards/DISCOSPACE/default.pdc b/boards/DISCOSPACE/default.pdc new file mode 100644 --- /dev/null +++ b/boards/DISCOSPACE/default.pdc @@ -0,0 +1,521 @@ +# Actel Physical design constraints file +# Generated file + +# Version: 9.1 SP3 9.1.3.4 +# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA +# Date generated: Tue Oct 18 08:21:45 2011 + + +# +# IO banks setting +# + + +# +# I/O constraints +# + +set_io clk100MHz \ + -pinname F7 \ + -fixed yes \ + -DIRECTION Inout + +set_io clk49_152MHz \ + -pinname F8 \ + -fixed yes \ + -DIRECTION Inout + +set_io reset \ + -pinname J12 \ + -fixed yes \ + -DIRECTION Inout +#==================================================================== +# BPs +#==================================================================== +set_io BP0 \ + -pinname F16 \ + -fixed yes \ + -DIRECTION Inout + +set_io BP1 \ + -pinname F13 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# LEDs +#==================================================================== + +set_io LED0 \ + -pinname R13 \ + -fixed yes \ + -DIRECTION Inout + +set_io LED1 \ + -pinname P13 \ + -fixed yes \ + -DIRECTION Inout + +set_io LED2 \ + -pinname N11 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# TRIGGERs +#==================================================================== + +set_io DISCO1_TRIG1 \ + -pinname J15 \ + -fixed yes \ + -DIRECTION Inout + +set_io DISCO2_TRIG1 \ + -pinname H15 \ + -fixed yes \ + -DIRECTION Inout + +set_io DISCO3_TRIG1 \ + -pinname D14 \ + -fixed yes \ + -DIRECTION Inout + +set_io DISCO4_TRIG1 \ + -pinname A8 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# UARTS +#==================================================================== + +set_io TXD1 \ + -pinname N12 \ + -fixed yes \ + -DIRECTION Inout + +set_io RXD1 \ + -pinname N10 \ + -fixed yes \ + -DIRECTION Inout + +set_io nCTS1 \ + -pinname L13 \ + -fixed yes \ + -DIRECTION Inout + +set_io nRTS1 \ + -pinname M9 \ + -fixed yes \ + -DIRECTION Inout + + +set_io TXD2 \ + -pinname G6 \ + -fixed yes \ + -DIRECTION Inout + +set_io RXD2 \ + -pinname F6 \ + -fixed yes \ + -DIRECTION Inout + + + +#==================================================================== +# SPACE WIRE +#==================================================================== + +set_io SPW_EN \ + -pinname U9 \ + -fixed yes \ + -DIRECTION Inout + + #================================ + # NOMINAL LINK + #================================ + +set_io SPW_NOM_DIN \ + -pinname T9 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_NOM_SIN \ + -pinname T8 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_NOM_DOUT \ + -pinname U7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_NOM_SOUT \ + -pinname U1 \ + -fixed yes \ + -DIRECTION Inout + + #================================ + # REDUNDANT LINK + #================================ + +set_io SPW_RED_DIN \ + -pinname R10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_RED_SIN \ + -pinname T10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_RED_DOUT \ + -pinname V2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SPW_RED_SOUT \ + -pinname T11 \ + -fixed yes \ + -DIRECTION Inout + + +#==================================================================== +# SRAM +#==================================================================== + + #================================ + # SRAM CTRL + #================================ + +set_io SRAM_nWE \ + -pinname D4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_CE \ + -pinname J6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nOE \ + -pinname J1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[0\] \ + -pinname N2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[1\] \ + -pinname K5 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[2\] \ + -pinname G2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBE\[3\] \ + -pinname J2 \ + -fixed yes \ + -DIRECTION Inout + + + #================================ + # SRAM ADDRESS + #================================ + +set_io SRAM_A\[0\] \ + -pinname A3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[1\] \ + -pinname A2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[2\] \ + -pinname B1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[3\] \ + -pinname C1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[4\] \ + -pinname D1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[5\] \ + -pinname B6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[6\] \ + -pinname F1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[7\] \ + -pinname C6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[8\] \ + -pinname H1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[9\] \ + -pinname A5 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[10\] \ + -pinname D5 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[11\] \ + -pinname K1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[12\] \ + -pinname A4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[13\] \ + -pinname E10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[14\] \ + -pinname C4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[15\] \ + -pinname G4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[16\] \ + -pinname K7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[17\] \ + -pinname F4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[18\] \ + -pinname K2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[19\] \ + -pinname E4 \ + -fixed yes \ + -DIRECTION Inout + + + #================================ + # SRAM DATA + #================================ + +set_io SRAM_DQ\[0\] \ + -pinname M3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[1\] \ + -pinname N8 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[2\] \ + -pinname M2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[3\] \ + -pinname N9 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[4\] \ + -pinname R11 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[5\] \ + -pinname K12 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[6\] \ + -pinname J4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[7\] \ + -pinname N3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[8\] \ + -pinname M6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[9\] \ + -pinname L3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[10\] \ + -pinname L6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[11\] \ + -pinname K4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[12\] \ + -pinname L4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[13\] \ + -pinname N7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[14\] \ + -pinname M7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[15\] \ + -pinname K6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[16\] \ + -pinname E1 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[17\] \ + -pinname J7 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[18\] \ + -pinname H4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[19\] \ + -pinname F10 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[20\] \ + -pinname B3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[21\] \ + -pinname F3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[22\] \ + -pinname C3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[23\] \ + -pinname G3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[24\] \ + -pinname R6 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[25\] \ + -pinname P4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[26\] \ + -pinname R4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[27\] \ + -pinname M4 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[28\] \ + -pinname F9 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[29\] \ + -pinname B2 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[30\] \ + -pinname H3 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[31\] \ + -pinname C2 \ + -fixed yes \ + -DIRECTION Inout + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/designs/TIMEGEN/DISCOSPACE_top - Copie.vhd b/designs/TIMEGEN/DISCOSPACE_top - Copie.vhd new file mode 100644 --- /dev/null +++ b/designs/TIMEGEN/DISCOSPACE_top - Copie.vhd @@ -0,0 +1,584 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +use lpp.lpp_amba.all; +USE lpp.lpp_lfr_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY DISCOSPACE_top IS + + PORT ( + clk100MHz : IN STD_LOGIC; + clk49_152MHz : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + DISCO1_TRIG1 : OUT STD_LOGIC; + DISCO2_TRIG1 : OUT STD_LOGIC; + DISCO3_TRIG1 : OUT STD_LOGIC; + DISCO4_TRIG1 : OUT STD_LOGIC; + + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END DISCOSPACE_top; + + +ARCHITECTURE beh OF DISCOSPACE_top IS + +--========================================================================== +-- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board +-- when enabled, chip enable polarity should be reversed and bank size also +-- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 +-- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 +--========================================================================== + CONSTANT USE_IAP_MEMCTRL : integer := 1; +--========================================================================== + + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_24 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- + SIGNAL I00_s : STD_LOGIC; + + -- CONSTANTS + CONSTANT CFG_PADTECH : INTEGER := inferred; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; + + +-- AdvancedTrigger + SIGNAL Trigger : STD_LOGIC; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_nCS_sig : STD_LOGIC; + SIGNAL ADC_CLK_sig : STD_LOGIC; + SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL bias_fail_sw_sig : STD_LOGIC; + + + ----------------------------------------------------------------------------- + + SIGNAL LFR_soft_rstn : STD_LOGIC; + SIGNAL LFR_rstn : STD_LOGIC; + + + SIGNAL rstn_25 : STD_LOGIC; + SIGNAL rstn_25_d1 : STD_LOGIC; + SIGNAL rstn_25_d2 : STD_LOGIC; + SIGNAL rstn_25_d3 : STD_LOGIC; + + SIGNAL rstn_24 : STD_LOGIC; + SIGNAL rstn_24_d1 : STD_LOGIC; + SIGNAL rstn_24_d2 : STD_LOGIC; + SIGNAL rstn_24_d3 : STD_LOGIC; + + SIGNAL rstn_50 : STD_LOGIC; + SIGNAL rstn_50_d1 : STD_LOGIC; + SIGNAL rstn_50_d2 : STD_LOGIC; + SIGNAL rstn_50_d3 : STD_LOGIC; + -- + SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- + SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL nSRAM_READY : STD_LOGIC; + +BEGIN -- beh + + ----------------------------------------------------------------------------- + PROCESS (clk100MHz, reset) + BEGIN -- PROCESS + IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + PROCESS (clk_50_s, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + clk_25 <= '0'; + rstn_25 <= '0'; + rstn_25_d1 <= '0'; + rstn_25_d2 <= '0'; + rstn_25_d3 <= '0'; + ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge + clk_25 <= NOT clk_25; + rstn_25_d1 <= '1'; + rstn_25_d2 <= rstn_25_d1; + rstn_25_d3 <= rstn_25_d2; + rstn_25 <= rstn_25_d3; + END IF; + END PROCESS; + + PROCESS (clk49_152MHz, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + clk_24 <= '0'; + rstn_24_d1 <= '0'; + rstn_24_d2 <= '0'; + rstn_24_d3 <= '0'; + rstn_24 <= '0'; + ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge + clk_24 <= NOT clk_24; + rstn_24_d1 <= '1'; + rstn_24_d2 <= rstn_24_d1; + rstn_24_d3 <= rstn_24_d2; + rstn_24 <= rstn_24_d3; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, rstn_25) + BEGIN -- PROCESS + IF rstn_25 = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk49_152MHz, rstn_24) + BEGIN -- PROCESS + IF rstn_24 = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + -- No AHB UART + RXD1 <= TXD1; + + -- + + leon3_soc_1 : leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + IS_RADHARD => 0, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 0, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE, + ADDRESS_SIZE => 20, + USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, + BYPASS_EDAC_MEMCTRLR => '0', + SRBANKSZ => 9) + PORT MAP ( + clk => clk_25, + reset => rstn_25, + errorn => errorn, + ahbrxd => OPEN,--TXD1, + ahbtxd => OPEN,--RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE_s, + nSRAM_OE => SRAM_nOE, + nSRAM_READY => nSRAM_READY, + SRAM_MBE => OPEN, + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + + PROCESS (clk_25, rstn_25) + BEGIN -- PROCESS + IF rstn_25 = '0' THEN -- asynchronous reset (active low) + nSRAM_READY <= '1'; + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + nSRAM_READY <= '1'; + END IF; + END PROCESS; + + + + IAP:if USE_IAP_MEMCTRL = 1 GENERATE + SRAM_CE <= not SRAM_CE_s(0); + END GENERATE; + + NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE + SRAM_CE <= SRAM_CE_s(0); + END GENERATE; +------------------------------------------------------------------------------- +-- APB_LFR_MANAGEMENT --------------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_management_1 : apb_lfr_management + GENERIC MAP ( + tech => apa3e, + pindex => 6, + paddr => 6, + pmask => 16#fff#, + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk_25, + resetn_25MHz => rstn_25, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + HK_sample => sample_hk, + HK_val => sample_val, + HK_sel => HK_SEL, + DAC_SDO => OPEN, + DAC_SCK => OPEN, + DAC_SYNC => OPEN, + DAC_CAL_EN => OPEN, + coarse_time => coarse_time, + fine_time => fine_time, + LFR_soft_rstn => LFR_soft_rstn + ); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + SPW_EN <= '1'; + + spw_clk <= clk_50_s; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DIN, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SIN, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DOUT, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SOUT, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_SIN, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_DIN, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_DOUT, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_SOUT, swno.s(1)); + + -- GRSPW PHY + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + swni.rmapnodeaddr <= (OTHERS => '0'); + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn_25, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + + + LFR_rstn <= LFR_soft_rstn AND rstn_25; + + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"000159") -- aa.bb.cc version + PORT MAP ( + clk => clk_25, + rstn => LFR_rstn, + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi_ext, + apbo => apbo_ext(15), + ahbi => ahbi_m_ext, + ahbo => ahbo_m_ext(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw_sig, + debug_vector => open, + debug_vector_ms => open + ); + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; + END GENERATE all_sample; + + top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 + GENERIC MAP( + ChannelCount => 8, + SampleNbBits => 14, + ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 + ncycle_cnv => 249) -- 49 152 000 / 98304 /2 + PORT MAP ( + -- CONV + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_nCS_sig, + -- DATA + clk => clk_25, + rstn => rstn_25, + sck => ADC_CLK_sig, + sdo => ADC_SDO_sig, + -- SAMPLE + sample => sample, + sample_val => sample_val); + + ADC_nCS <= ADC_nCS_sig; + ADC_CLK <= ADC_CLK_sig; + ADC_SDO_sig <= ADC_SDO; + + sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE + "0010001000100010" WHEN HK_SEL = "01" ELSE + "0100010001000100" WHEN HK_SEL = "10" ELSE + (OTHERS => '0'); + + + +---------------------------------------------------------------------- +--- APB_ADVANCED_TRIGGER ----------------------------------------------------------- +---------------------------------------------------------------------- +advtrig0: APB_ADVANCED_TRIGGER + generic map( + pindex => 12, + paddr => 12) + port map( + rstn => rstn_25, + clk => clk_25, + apbi => apbi_ext, + apbo => apbo_ext(12), + + SPW_Tickout => swno.tickout, + CoarseTime => coarse_time, + FineTime => fine_time, + + Trigger => Trigger + ); + + + DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO1_TRIG1, Trigger); + DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO2_TRIG1, Trigger); + DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO3_TRIG1, Trigger); + DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO4_TRIG1, Trigger); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE + apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE + apbo_ext(I) <= apb_none; + END GENERATE apbo_ext_not_used; + END GENERATE all_apbo_ext; + + + all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE + ahbo_s_ext(I) <= ahbs_none; + END GENERATE all_ahbo_ext; + + all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE + ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE + ahbo_m_ext(I) <= ahbm_none; + END GENERATE ahbo_m_ext_not_used; + END GENERATE all_ahbo_m_ext; + +END beh; \ No newline at end of file diff --git a/designs/TIMEGEN/DISCOSPACE_top.vhd b/designs/TIMEGEN/DISCOSPACE_top.vhd new file mode 100644 --- /dev/null +++ b/designs/TIMEGEN/DISCOSPACE_top.vhd @@ -0,0 +1,584 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +use lpp.lpp_amba.all; +USE lpp.lpp_lfr_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY DISCOSPACE_top IS + + PORT ( + clk100MHz : IN STD_LOGIC; + clk49_152MHz : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + DISCO1_TRIG1 : OUT STD_LOGIC; + DISCO2_TRIG1 : OUT STD_LOGIC; + DISCO3_TRIG1 : OUT STD_LOGIC; + DISCO4_TRIG1 : OUT STD_LOGIC; + + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END DISCOSPACE_top; + + +ARCHITECTURE beh OF DISCOSPACE_top IS + +--========================================================================== +-- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board +-- when enabled, chip enable polarity should be reversed and bank size also +-- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 +-- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 +--========================================================================== + CONSTANT USE_IAP_MEMCTRL : integer := 1; +--========================================================================== + + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_24 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- + SIGNAL I00_s : STD_LOGIC; + + -- CONSTANTS + CONSTANT CFG_PADTECH : INTEGER := inferred; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; + + +-- AdvancedTrigger + SIGNAL Trigger : STD_LOGIC; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_nCS_sig : STD_LOGIC; + SIGNAL ADC_CLK_sig : STD_LOGIC; + SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL bias_fail_sw_sig : STD_LOGIC; + + + ----------------------------------------------------------------------------- + + SIGNAL LFR_soft_rstn : STD_LOGIC; + SIGNAL LFR_rstn : STD_LOGIC; + + + SIGNAL rstn_25 : STD_LOGIC; + SIGNAL rstn_25_d1 : STD_LOGIC; + SIGNAL rstn_25_d2 : STD_LOGIC; + SIGNAL rstn_25_d3 : STD_LOGIC; + + SIGNAL rstn_24 : STD_LOGIC; + SIGNAL rstn_24_d1 : STD_LOGIC; + SIGNAL rstn_24_d2 : STD_LOGIC; + SIGNAL rstn_24_d3 : STD_LOGIC; + + SIGNAL rstn_50 : STD_LOGIC; + SIGNAL rstn_50_d1 : STD_LOGIC; + SIGNAL rstn_50_d2 : STD_LOGIC; + SIGNAL rstn_50_d3 : STD_LOGIC; + -- + SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + + -- + SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL nSRAM_READY : STD_LOGIC; + +BEGIN -- beh + + ----------------------------------------------------------------------------- + PROCESS (clk100MHz, reset) + BEGIN -- PROCESS + IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + PROCESS (clk_50_s, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + clk_25 <= '0'; + rstn_25 <= '0'; + rstn_25_d1 <= '0'; + rstn_25_d2 <= '0'; + rstn_25_d3 <= '0'; + ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge + clk_25 <= NOT clk_25; + rstn_25_d1 <= '1'; + rstn_25_d2 <= rstn_25_d1; + rstn_25_d3 <= rstn_25_d2; + rstn_25 <= rstn_25_d3; + END IF; + END PROCESS; + + PROCESS (clk49_152MHz, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + clk_24 <= '0'; + rstn_24_d1 <= '0'; + rstn_24_d2 <= '0'; + rstn_24_d3 <= '0'; + rstn_24 <= '0'; + ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge + clk_24 <= NOT clk_24; + rstn_24_d1 <= '1'; + rstn_24_d2 <= rstn_24_d1; + rstn_24_d3 <= rstn_24_d2; + rstn_24 <= rstn_24_d3; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, rstn_25) + BEGIN -- PROCESS + IF rstn_25 = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk49_152MHz, rstn_24) + BEGIN -- PROCESS + IF rstn_24 = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + -- No AHB UART + RXD1 <= TXD1; + + -- + + leon3_soc_1 : leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + IS_RADHARD => 0, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 0, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE, + ADDRESS_SIZE => 20, + USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, + BYPASS_EDAC_MEMCTRLR => '0', + SRBANKSZ => 9) + PORT MAP ( + clk => clk_25, + reset => rstn_25, + errorn => errorn, + ahbrxd => OPEN,--TXD1, + ahbtxd => OPEN,--RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE_s, + nSRAM_OE => SRAM_nOE, + nSRAM_READY => nSRAM_READY, + SRAM_MBE => OPEN, + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + + PROCESS (clk_25, rstn_25) + BEGIN -- PROCESS + IF rstn_25 = '0' THEN -- asynchronous reset (active low) + nSRAM_READY <= '1'; + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + nSRAM_READY <= '1'; + END IF; + END PROCESS; + + + + IAP:if USE_IAP_MEMCTRL = 1 GENERATE + SRAM_CE <= not SRAM_CE_s(0); + END GENERATE; + + NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE + SRAM_CE <= SRAM_CE_s(0); + END GENERATE; +------------------------------------------------------------------------------- +-- APB_LFR_MANAGEMENT --------------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_management_1 : apb_lfr_management + GENERIC MAP ( + tech => apa3e, + pindex => 6, + paddr => 6, + pmask => 16#fff#, + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk_25, + resetn_25MHz => rstn_25, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + HK_sample => sample_hk, + HK_val => sample_val, + HK_sel => HK_SEL, + DAC_SDO => OPEN, + DAC_SCK => OPEN, + DAC_SYNC => OPEN, + DAC_CAL_EN => OPEN, + coarse_time => coarse_time, + fine_time => fine_time, + LFR_soft_rstn => LFR_soft_rstn + ); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + SPW_EN <= '1'; + + spw_clk <= clk_50_s; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DIN, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SIN, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DOUT, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SOUT, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_SIN, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_DIN, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_DOUT, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_SOUT, swno.s(1)); + + -- GRSPW PHY + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + swni.rmapnodeaddr <= (OTHERS => '0'); + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn_25, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + + + LFR_rstn <= LFR_soft_rstn AND rstn_25; + + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"000159") -- aa.bb.cc version + PORT MAP ( + clk => clk_25, + rstn => LFR_rstn, + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi_ext, + apbo => apbo_ext(15), + ahbi => ahbi_m_ext, + ahbo => ahbo_m_ext(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw_sig, + debug_vector => open, + debug_vector_ms => open + ); + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; + END GENERATE all_sample; + + top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 + GENERIC MAP( + ChannelCount => 8, + SampleNbBits => 14, + ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 + ncycle_cnv => 249) -- 49 152 000 / 98304 /2 + PORT MAP ( + -- CONV + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_nCS_sig, + -- DATA + clk => clk_25, + rstn => rstn_25, + sck => ADC_CLK_sig, + sdo => ADC_SDO_sig, + -- SAMPLE + sample => sample, + sample_val => sample_val); + + ADC_nCS <= ADC_nCS_sig; + ADC_CLK <= ADC_CLK_sig; + ADC_SDO_sig <= ADC_SDO; + + sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE + "0010001000100010" WHEN HK_SEL = "01" ELSE + "0100010001000100" WHEN HK_SEL = "10" ELSE + (OTHERS => '0'); + + + +---------------------------------------------------------------------- +--- APB_ADVANCED_TRIGGER ----------------------------------------------------------- +---------------------------------------------------------------------- +advtrig0: APB_ADVANCED_TRIGGER + generic map( + pindex => 12, + paddr => 12) + port map( + rstn => rstn_25, + clk => clk_25, + apbi => apbi_ext, + apbo => apbo_ext(12), + + SPW_Tickout => swno.tickout, + CoarseTime => coarse_time, + FineTime => fine_time, + + Trigger => Trigger + ); + + + DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO1_TRIG1, Trigger); + DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO2_TRIG1, Trigger); + DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO3_TRIG1, Trigger); + DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred) + PORT MAP (DISCO4_TRIG1, Trigger); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE + apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE + apbo_ext(I) <= apb_none; + END GENERATE apbo_ext_not_used; + END GENERATE all_apbo_ext; + + + all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE + ahbo_s_ext(I) <= ahbs_none; + END GENERATE all_ahbo_ext; + + all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE + ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE + ahbo_m_ext(I) <= ahbm_none; + END GENERATE ahbo_m_ext_not_used; + END GENERATE all_ahbo_m_ext; + +END beh; diff --git a/designs/TIMEGEN/DISCOSPACE_top_libero.prj b/designs/TIMEGEN/DISCOSPACE_top_libero.prj new file mode 100644 --- /dev/null +++ b/designs/TIMEGEN/DISCOSPACE_top_libero.prj @@ -0,0 +1,4865 @@ +KEY LIBERO "9.1" +KEY CAPTURE "9.1.5.1" +KEY DEFAULT_IMPORT_LOC "C:\opt\VHDLIB\tests\Validation_LFR_Filters" +KEY DEFAULT_OPEN_LOC "" +KEY ProjectID "2f64e589-285c-45b2-b6c4-709f59f83db9" +KEY HDLTechnology "VHDL" +KEY VendorTechnology_Family "ProASIC3E" +KEY VendorTechnology_Die "IT14X14M4" +KEY VendorTechnology_Package "fg324" +KEY ProjectLocation "C:\opt\VHDLIB\designs\TIMEGEN" +KEY SimulationType "VHDL" +KEY Vendor "Actel" +KEY ActiveRoot "DISCOSPACE_top::work" +LIST REVISIONS +VALUE="Impl1",NUM=1 +VALUE="Impl2",NUM=2 +CURREV=2 +ENDLIST +LIST LIBRARIES +grlib +synplify +techmap +spw +eth +opencores +gaisler +esa +fmf +spansion +gsi +iap +lpp +cypress +ENDLIST +LIST LIBRARY_grlib +ALIAS=grlib +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_synplify +ALIAS=synplify +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_techmap +ALIAS=techmap +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_spw +ALIAS=spw +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_eth +ALIAS=eth +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_opencores +ALIAS=opencores +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_gaisler +ALIAS=gaisler +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_esa +ALIAS=esa +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_fmf +ALIAS=fmf +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_spansion +ALIAS=spansion +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_gsi +ALIAS=gsi +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_iap +ALIAS=iap +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_lpp +ALIAS=lpp +COMPILE_OPTION=COMPILE +ENDLIST +LIST LIBRARY_cypress +ALIAS=cypress +COMPILE_OPTION=COMPILE +ENDLIST +LIST FileManager +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3091" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1890" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4795" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3112" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3141" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2735" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="15484" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2919" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3324" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="10820" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="10988" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl" 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+SIZE="17692" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="6368" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl" +STATE="utd" +TIME="1478688463" +SIZE="11622" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2383" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl" +STATE="utd" +TIME="1478688463" +SIZE="3777" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl" +STATE="utd" +TIME="1478196483" +SIZE="5046" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2773" +LIBRARY="lpp" +ENDFILE +VALUE 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"\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4946" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3069" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2981" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2284" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1930" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2952" +LIBRARY="lpp" +ENDFILE +VALUE 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"\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2014" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1985" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="9428" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2314" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1941" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1667" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1731" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2185" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1692" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3295" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2482" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="1812" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl" 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"\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2677" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="7740" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl" +STATE="utd" +TIME="1479920608" +SIZE="5053" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl" +STATE="utd" +TIME="1479911446" +SIZE="2143" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl" +STATE="utd" +TIME="1479913560" +SIZE="2634" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="6288" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3856" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4819" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="9925" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="5162" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2965" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4811" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl" 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+VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4291" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="5071" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="8480" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="14356" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="12064" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="9280" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="6032" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4061" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="6996" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="3724" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="4664" +LIBRARY="lpp" +ENDFILE +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl" +STATE="utd" +TIME="1472547172" +SIZE="2306" +LIBRARY="lpp" +ENDFILE +VALUE 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"\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl" +VALUE "\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl" +VALUE "\DISCOSPACE_top.vhd,hdl" +ENDFILELIST +ENDLIST +ENDLIST +ENDLIST +LIST OpenedFileList +ENDLIST diff --git a/designs/TIMEGEN/Makefile b/designs/TIMEGEN/Makefile new file mode 100644 --- /dev/null +++ b/designs/TIMEGEN/Makefile @@ -0,0 +1,47 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=DISCOSPACE_top +BOARD=DISCOSPACE +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +VHDLSYNFILES= DISCOSPACE_top.vhd +VHDLSIMFILES= testbench.vhd +SIMTOP=testbench +PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +SDCFILE=$(VHDLIB)/boards/$(BOARD)/DISCOSPACE.sdc +SDC=$(VHDLIB)/boards/$(BOARD)/DISCOSPACE.sdc +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./lpp_bootloader \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP =i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_SIMPLE_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd \ + sgmii.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/lib/lpp/general_purpose/TimeGenAdvancedTrigger.vhd b/lib/lpp/general_purpose/TimeGenAdvancedTrigger.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/TimeGenAdvancedTrigger.vhd @@ -0,0 +1,128 @@ +-- TimeGenAdvancedTrigger.vhd +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +ENTITY TimeGenAdvancedTrigger IS +PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + SPW_Tickout : IN STD_LOGIC; + + CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15 + TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps + Restart : IN STD_LOGIC; + StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch + + BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout + -- else Trigger output is driven by advanced trig + Trigger : OUT STD_LOGIC + +); + +END TimeGenAdvancedTrigger; + + +ARCHITECTURE beh OF TimeGenAdvancedTrigger IS + +SIGNAL AdvancedTrigger : STD_LOGIC:='0'; +SIGNAL AdvancedTrigger_l0 : STD_LOGIC:='0'; +SIGNAL AdvancedTrigger_l1 : STD_LOGIC:='0'; +SIGNAL started : STD_LOGIC:='0'; +SIGNAL periodCntr : STD_LOGIC_VECTOR(3 DOWNTO 0):=(OTHERS=>'0'); +SIGNAL coarseTime0 : STD_LOGIC:='0'; + + +BEGIN + +Trigger <= SPW_Tickout WHEN BypassTickout = '1' ELSE AdvancedTrigger; +AdvancedTrigger <= AdvancedTrigger_l0 AND AdvancedTrigger_l1; + + +PROCESS(clk,rstn) +BEGIN +IF rstn = '0' THEN + started <= '0'; + AdvancedTrigger_l0 <='0'; + AdvancedTrigger_l1 <='0'; + coarseTime0 <= '0'; + periodCntr <= (OTHERS => '0'); + +ELSIF clk'event AND clk = '1' THEN + + coarseTime0 <= CoarseTime(0); + +-- Detection of start date and handling of Restart + IF Restart = '1' THEN + started <= '0'; + ELSIF StartDate = CoarseTime THEN + started <= '1'; + END IF; + +-- Fine time based comparator for phase shift + IF TrigShift = FineTime THEN + AdvancedTrigger_l0 <='1'; + ELSE + AdvancedTrigger_l0 <='0'; + END IF; + +-- Second filter, generates a pulse for each N seconds since StartDate + IF started = '1' THEN + IF periodCntr = "0000" THEN + AdvancedTrigger_l1 <='1'; + periodCntr <= TrigPeriod; + ELSIF CoarseTime(0) /= coarseTime0 THEN + periodCntr <= STD_LOGIC_VECTOR(SIGNED(periodCntr) - 1); + AdvancedTrigger_l1 <='0'; + END IF; + ELSE + periodCntr <= (OTHERS => '0'); + AdvancedTrigger_l1 <='0'; + END IF; + +END IF; +END PROCESS; + +END beh; + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -14,7 +14,7 @@ -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Author : Alexis Jeandet -- Mail : alexis.jeandet@lpp.polytechnique.fr @@ -32,7 +32,7 @@ USE IEEE.NUMERIC_STD.ALL; PACKAGE general_purpose IS - + COMPONENT general_counter GENERIC ( CYCLIC : STD_LOGIC; @@ -417,4 +417,26 @@ PACKAGE general_purpose IS output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); END COMPONENT; + COMPONENT TimeGenAdvancedTrigger + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + SPW_Tickout : IN STD_LOGIC; + + CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15 + TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps + Restart : IN STD_LOGIC; + StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch + + BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout + -- else Trigger output is driven by advanced trig + Trigger : OUT STD_LOGIC + + ); + END COMPONENT; + END; diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -25,3 +25,4 @@ SYNC_VALID_BIT.vhd RR_Arbiter_4.vhd general_counter.vhd ramp_generator.vhd +TimeGenAdvancedTrigger.vhd diff --git a/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.apb_devices_list.all; +use lpp.lpp_amba.all; +use lpp.general_purpose.TimeGenAdvancedTrigger; + + +entity APB_ADVANCED_TRIGGER is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + rstn : in std_ulogic; + clk : in std_ulogic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + + SPW_Tickout : IN STD_LOGIC; + CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + Trigger : OUT STD_LOGIC + ); +end; + + +architecture beh of APB_ADVANCED_TRIGGER is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + + + +type adv_trig_type is record + TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15 + TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps + Restart : STD_LOGIC; + StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch + BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout +end record; + +type adv_trig_regs is record + CFG : STD_LOGIC_VECTOR(31 DOWNTO 0); + Restart : STD_LOGIC_VECTOR(31 DOWNTO 0); + StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); +end record; + +signal r : adv_trig_regs; +signal adv_trig : adv_trig_type; +signal Rdata : std_logic_vector(31 downto 0); + + +begin + + + +adv_trig0: TimeGenAdvancedTrigger + PORT MAP( + clk => clk, + rstn => rstn, + + SPW_Tickout => SPW_Tickout, + + CoarseTime => CoarseTime, + FineTime => FineTime, + + TrigPeriod => adv_trig.TrigPeriod, + TrigShift => adv_trig.TrigShift, + Restart => adv_trig.Restart, + StartDate => adv_trig.StartDate, + + BypassTickout => adv_trig.BypassTickout, + Trigger => Trigger + + ); + + adv_trig.BypassTickout <= r.CFG(0); + adv_trig.TrigPeriod <= r.CFG(7 downto 4); + adv_trig.TrigShift <= r.CFG(31 downto 16); + adv_trig.Restart <= r.Restart(0); + adv_trig.StartDate <= r.StartDate; + + +process(rstn,clk) +begin + if rstn = '0' then + r.CFG <= (others=>'0'); + r.Restart <= (others=>'0'); + r.StartDate <= (others=>'0'); + elsif clk'event and clk = '1' then + +--APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + r.CFG <= apbi.pwdata; + when "000001" => + r.Restart <= apbi.pwdata; + when "000010" => + r.StartDate <= apbi.pwdata; + when others => + null; + end case; + end if; + +--APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata <= r.CFG; + when "000001" => + Rdata <= r.Restart; + when "000010" => + Rdata <= r.StartDate; + when others => + Rdata <= r.Restart; + end case; + end if; + + end if; + apbo.pconfig <= pconfig; +end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +end beh; \ No newline at end of file diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd --- a/lib/lpp/lpp_amba/apb_devices_list.vhd +++ b/lib/lpp/lpp_amba/apb_devices_list.vhd @@ -42,7 +42,8 @@ PACKAGE apb_devices_list IS CONSTANT LPP_LFR_MANAGEMENT : amba_device_type := 16#22#; CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; - constant APB_ADC_READER : amba_device_type := 16#F1#; + constant APB_ADC_READER : amba_device_type := 16#F1#; CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; + CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#; END; diff --git a/lib/lpp/lpp_amba/lpp_amba.vhd b/lib/lpp/lpp_amba/lpp_amba.vhd --- a/lib/lpp/lpp_amba/lpp_amba.vhd +++ b/lib/lpp/lpp_amba/lpp_amba.vhd @@ -29,7 +29,7 @@ use std.textio.all; package lpp_amba is -component APB_CHENILLARD is +component APB_ADVANCED_TRIGGER is generic ( pindex : integer := 0; paddr : integer := 0; @@ -37,12 +37,16 @@ component APB_CHENILLARD is pirq : integer := 0; abits : integer := 8); port ( - rst : in std_ulogic; + rstn : in std_ulogic; clk : in std_ulogic; - RegLed : in std_logic_vector (7 downto 0); apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; - Leds : out std_logic_vector (7 downto 0) + + SPW_Tickout : IN STD_LOGIC; + CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + Trigger : OUT STD_LOGIC ); end component; diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt --- a/lib/lpp/lpp_amba/vhdlsyn.txt +++ b/lib/lpp/lpp_amba/vhdlsyn.txt @@ -1,2 +1,3 @@ apb_devices_list.vhd lpp_amba.vhd +APB_ADVANCED_TRIGGER.vhd