# HG changeset patch
# User pellion
# Date 2013-03-25 15:31:35
# Node ID 75d2aca111a9486aab3764e5c374f5b5e4708a43
# Parent  ff6ca9d2a8d8f856e07619fa21cce2f48d9ca403

LPP IIR FILTER v2.0.0
ADConv         v1.1.0
- Re-design of the IIR Filter to compute more "rapidly" (in term of number of cycle)
- Re-design of the ADConv to respect the resync rules
- Add a global TB for IIR Filter and ADConv in designs/Projet-LeonLFR-AP3K-Sheldon_sim-all

diff --git a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
--- a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
+++ b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
@@ -39,6 +39,7 @@ constant ChanelsCount :   integer :=  1;
 constant Sample_SZ    :   integer := 18;
 constant Coef_SZ    :   integer := 9;
 constant CoefCntPerCel:   integer := 6;
+constant CoefPerCel:   integer := 5;
 constant Cels_count :   integer := 5;
 constant virgPos      : integer := 7;
 constant Mem_use    :   integer := 1;
@@ -69,13 +70,13 @@ constant b4_0       :   std_logic_vector
 constant b4_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
 constant b4_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
 
-constant b5_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
-constant b5_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
-constant b5_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
+--constant b5_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
+--constant b5_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
+--constant b5_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
 
-constant b6_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
-constant b6_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
-constant b6_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
+--constant b6_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
+--constant b6_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
+--constant b6_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
 
 
 constant a0_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
@@ -98,15 +99,22 @@ constant a4_0       :   std_logic_vector
 constant a4_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
 constant a4_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
 
-constant a5_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
-constant a5_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
-constant a5_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
-constant a6_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
-constant a6_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
-constant a6_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
+--constant a5_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
+--constant a5_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+--constant a5_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
+--constant a6_0       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
+--constant a6_1       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
+--constant a6_2       :   std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
 
 constant CoefsInitValCst  :   std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 &  b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
 
+constant CoefsInitValCst_JC  :   std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
+  (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
+   a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
+   a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
+   a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
+   a0_1 & a0_2 & b0_0 & b0_1 & b0_2  );
+
 
 end;
 
diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd
--- a/lib/lpp/dsp/iir_filter/iir_filter.vhd
+++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd
@@ -19,34 +19,35 @@
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
 ----------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE grlib.stdlib.ALL;
+USE grlib.devices.ALL;
+LIBRARY lpp;
 
 
 
 
-package iir_filter is
+PACKAGE iir_filter IS
 
 
 --===========================================================|
 --================A L U   C O N T R O L======================|
 --===========================================================|
-constant    IDLE    :   std_logic_vector(3 downto 0) := "0000";
-constant    MAC_op  :   std_logic_vector(3 downto 0) := "0001";
-constant    MULT    :   std_logic_vector(3 downto 0) := "0010";
-constant    ADD     :   std_logic_vector(3 downto 0) := "0011";
-constant    clr_mac :   std_logic_vector(3 downto 0) := "0100";
+  CONSTANT IDLE                : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
+  CONSTANT MAC_op              : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
+  CONSTANT MULT                : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
+  CONSTANT ADD                 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
+  CONSTANT clr_mac             : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
+  CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
 
 --____
 --RAM |
 --____|
-constant use_RAM    :   integer := 1;
-constant use_CEL    :   integer := 0;
+  CONSTANT use_RAM : INTEGER := 1;
+  CONSTANT use_CEL : INTEGER := 0;
 
 
 --===========================================================|
@@ -55,71 +56,91 @@ constant use_CEL    :   integer := 0;
 --  create a specific type of data for coefs to avoid errors |
 --===========================================================|
 
-type    scaleValT   is array(natural range <>) of integer;
+  TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
 
-type    samplT   is array(natural range <>,natural range <>) of std_logic;
+  TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
 
-type in_IIR_CEL_reg is record
-  config    :   std_logic_vector(31 downto 0);
-  virgPos   :   std_logic_vector(4 downto 0);
-end record;
+  TYPE in_IIR_CEL_reg IS RECORD
+    config  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+    virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  END RECORD;
 
-type out_IIR_CEL_reg is record
-  config    :   std_logic_vector(31 downto 0);
-  status    :   std_logic_vector(31 downto 0);
-end record;
+  TYPE out_IIR_CEL_reg IS RECORD
+    config : STD_LOGIC_VECTOR(31 DOWNTO 0);
+    status : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  END RECORD;
 
 
-component APB_IIR_CEL is
-   generic (
-    tech : integer := 0;
-    pindex   : integer  := 0;
-    paddr    : integer  := 0;
-    pmask    : integer  := 16#fff#;
-    pirq     : integer  := 0;
-    abits    : integer  := 8;
-    Sample_SZ : integer := 16;
-    ChanelsCount : integer := 6;
-    Coef_SZ      : integer := 9;
-    CoefCntPerCel: integer := 6;
-    Cels_count   : integer := 5;
-    virgPos      : integer := 7;
-    Mem_use      : integer := use_RAM
-    );
-  port (
-    rst             : in  std_logic;
-    clk             : in  std_logic;
-    apbi            : in  apb_slv_in_type;
-    apbo            : out apb_slv_out_type;
-    sample_clk      : in  std_logic;
-    sample_clk_out  : out std_logic;
-    sample_in   :   in  samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    sample_out  :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
-    );
-end component;
+  COMPONENT APB_IIR_CEL IS
+    GENERIC (
+      tech          : INTEGER := 0;
+      pindex        : INTEGER := 0;
+      paddr         : INTEGER := 0;
+      pmask         : INTEGER := 16#fff#;
+      pirq          : INTEGER := 0;
+      abits         : INTEGER := 8;
+      Sample_SZ     : INTEGER := 16;
+      ChanelsCount  : INTEGER := 6;
+      Coef_SZ       : INTEGER := 9;
+      CoefCntPerCel : INTEGER := 6;
+      Cels_count    : INTEGER := 5;
+      virgPos       : INTEGER := 7;
+      Mem_use       : INTEGER := use_RAM
+      );
+    PORT (
+      rst            : IN  STD_LOGIC;
+      clk            : IN  STD_LOGIC;
+      apbi           : IN  apb_slv_in_type;
+      apbo           : OUT apb_slv_out_type;
+      sample_clk     : IN  STD_LOGIC;
+      sample_clk_out : OUT STD_LOGIC;
+      sample_in      : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      sample_out     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      CoefsInitVal   : IN  STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
+      );
+  END COMPONENT;
 
 
-component Top_IIR is
-generic(
-        Sample_SZ : integer := 18;
-		  ChanelsCount : integer := 1;
-		  Coef_SZ      : integer := 9;
-		  CoefCntPerCel: integer := 6;
-		  Cels_count   : integer := 5);
-    port(
-        reset       :   in  std_logic;
-        clk         :   in  std_logic;
-        sample_clk  :   in  std_logic;
- --       BP : in std_logic;
- --       BPinput       :   in std_logic_vector(3 downto 0);
-        LVLinput       :   in std_logic_vector(15 downto 0);
-        INsample      :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-        OUTsample      :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
-    ); 
-end component;
+  COMPONENT Top_IIR IS
+    GENERIC(
+      Sample_SZ     : INTEGER := 18;
+      ChanelsCount  : INTEGER := 1;
+      Coef_SZ       : INTEGER := 9;
+      CoefCntPerCel : INTEGER := 6;
+      Cels_count    : INTEGER := 5);
+    PORT(
+      reset      : IN  STD_LOGIC;
+      clk        : IN  STD_LOGIC;
+      sample_clk : IN  STD_LOGIC;
+      --       BP : in std_logic;
+      --       BPinput       :   in std_logic_vector(3 downto 0);
+      LVLinput   : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+      INsample   : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      OUTsample  : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
+      ); 
+  END COMPONENT;
 
-
+  COMPONENT IIR_CEL_CTRLR_v2
+    GENERIC (
+      tech          : INTEGER;
+      Mem_use       : INTEGER;
+      Sample_SZ     : INTEGER;
+      Coef_SZ       : INTEGER;
+      Coef_Nb       : INTEGER;
+      Coef_sel_SZ   : INTEGER;
+      Cels_count    : INTEGER;
+      ChanelsCount  : INTEGER);
+    PORT (
+      rstn          : IN  STD_LOGIC;
+      clk            : IN  STD_LOGIC;
+      virg_pos       : IN  INTEGER;
+      coefs          : IN  STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
+      sample_in_val  : IN  STD_LOGIC;
+      sample_in      : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      sample_out_val : OUT  STD_LOGIC;
+      sample_out     : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
+  END COMPONENT;
+  
 
 --component  FilterCTRLR is
 --port(
@@ -149,118 +170,121 @@ end component;
 --end component;
 
 
-component  IIR_CEL_CTRLR is
-generic(
-        tech : integer := 0;
-        Sample_SZ : integer := 16;
-		  ChanelsCount : integer := 1;
-		  Coef_SZ      : integer := 9;
-		  CoefCntPerCel: integer := 3;
-		  Cels_count   : integer := 5;
-        Mem_use      : integer := use_RAM
-);
-port(
-    reset       :   in  std_logic;
-    clk         :   in  std_logic;
-    sample_clk  :   in  std_logic;
-    sample_in   :   in  samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    sample_out  :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    virg_pos    :   in  integer;
-    GOtest : out std_logic;
-    coefs       :   in  std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
-);
-end component;
-
-
-component RAM is 
-generic(
-    Input_SZ_1      :   integer := 8
-);
-    port( WD : in std_logic_vector(Input_SZ_1-1 downto 0); RD : out 
-        std_logic_vector(Input_SZ_1-1 downto 0);WEN, REN : in std_logic; 
-        WADDR : in std_logic_vector(7 downto 0); RADDR : in 
-        std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
-        ) ;
-end component;
+  COMPONENT IIR_CEL_CTRLR IS
+    GENERIC(
+      tech          : INTEGER := 0;
+      Sample_SZ     : INTEGER := 16;
+      ChanelsCount  : INTEGER := 1;
+      Coef_SZ       : INTEGER := 9;
+      CoefCntPerCel : INTEGER := 3;
+      Cels_count    : INTEGER := 5;
+      Mem_use       : INTEGER := use_RAM
+      );
+    PORT(
+      reset      : IN  STD_LOGIC;
+      clk        : IN  STD_LOGIC;
+      sample_clk : IN  STD_LOGIC;
+      sample_in  : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      virg_pos   : IN  INTEGER;
+      GOtest     : OUT STD_LOGIC;
+      coefs      : IN  STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
 
-component RAM_CEL is 
-    port( WD : in std_logic_vector(35 downto 0); RD : out 
-        std_logic_vector(35 downto 0);WEN, REN : in std_logic; 
-        WADDR : in std_logic_vector(7 downto 0); RADDR : in 
-        std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
-        ) ;
-end component;
+  COMPONENT RAM IS
+    GENERIC(
+      Input_SZ_1 : INTEGER := 8
+      );
+    PORT(WD                                           : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
+    STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
+    WADDR                                             : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
+    STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET        : IN STD_LOGIC
+          ) ;
+  END COMPONENT;
+
+  COMPONENT RAM_CEL
+    GENERIC (
+      Sample_SZ : INTEGER);
+    PORT (
+      WD           : IN  STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
+      RD           : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
+      WEN, REN     : IN  STD_LOGIC;
+      WADDR        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+      RADDR        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+      RWCLK, RESET : IN  STD_LOGIC);
+  END COMPONENT;
 
-component  IIR_CEL_FILTER is
-generic(
-        tech : integer := 0;
-        Sample_SZ : integer := 16;
-		  ChanelsCount : integer := 1;
-		  Coef_SZ      : integer := 9;
-		  CoefCntPerCel: integer := 3;
-		  Cels_count   : integer := 5;
-        Mem_use      : integer := use_RAM);
-port(
-    reset       :   in  std_logic;
-    clk         :   in  std_logic;
-    sample_clk  :   in  std_logic;
-    regs_in     :   in  in_IIR_CEL_reg;
-    regs_out    :   in  out_IIR_CEL_reg;
-    sample_in   :   in  samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    sample_out  :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    GOtest : out std_logic;
-	 coefs       :   in  std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
-    
-);
-end component;
+  COMPONENT IIR_CEL_FILTER IS
+    GENERIC(
+      tech          : INTEGER := 0;
+      Sample_SZ     : INTEGER := 16;
+      ChanelsCount  : INTEGER := 1;
+      Coef_SZ       : INTEGER := 9;
+      CoefCntPerCel : INTEGER := 3;
+      Cels_count    : INTEGER := 5;
+      Mem_use       : INTEGER := use_RAM);
+    PORT(
+      reset      : IN  STD_LOGIC;
+      clk        : IN  STD_LOGIC;
+      sample_clk : IN  STD_LOGIC;
+      regs_in    : IN  in_IIR_CEL_reg;
+      regs_out   : IN  out_IIR_CEL_reg;
+      sample_in  : IN  samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
+      GOtest     : OUT STD_LOGIC;
+      coefs      : IN  STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
+
+      );
+  END COMPONENT;
 
 
-component  RAM_CTRLR2 is
-generic(
-        tech : integer := 0;
-    Input_SZ_1      :   integer := 16;
-	 Mem_use         :   integer := use_RAM
-);
-port(
-    reset       :   in  std_logic;
-    clk         :   in  std_logic;
-    WD_sel      :   in  std_logic;
-    Read        :   in  std_logic;
-    WADDR_sel   :   in  std_logic;
-    count       :   in  std_logic;
-    SVG_ADDR    :   in  std_logic;
-    Write       :   in  std_logic;
-    GO_0        :   in  std_logic;
-    sample_in   :   in  std_logic_vector(Input_SZ_1-1 downto 0);
-    sample_out  :   out std_logic_vector(Input_SZ_1-1 downto 0)
-);
-end component;
+  COMPONENT RAM_CTRLR2 IS
+    GENERIC(
+      tech       : INTEGER := 0;
+      Input_SZ_1 : INTEGER := 16;
+      Mem_use    : INTEGER := use_RAM
+      );
+    PORT(
+      reset      : IN  STD_LOGIC;
+      clk        : IN  STD_LOGIC;
+      WD_sel     : IN  STD_LOGIC;
+      Read       : IN  STD_LOGIC;
+      WADDR_sel  : IN  STD_LOGIC;
+      count      : IN  STD_LOGIC;
+      SVG_ADDR   : IN  STD_LOGIC;
+      Write      : IN  STD_LOGIC;
+      GO_0       : IN  STD_LOGIC;
+      sample_in  : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
+      sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
-component APB_IIR_Filter is
-  generic (
-    tech : integer := 0;
-    pindex   : integer  := 0;
-    paddr    : integer  := 0;
-    pmask    : integer  := 16#fff#;
-    pirq     : integer  := 0;
-    abits    : integer  := 8;
-    Sample_SZ : integer := 16;
-    ChanelsCount : integer := 1;
-    Coef_SZ      : integer := 9;
-    CoefCntPerCel: integer := 6;
-    Cels_count   : integer := 5;
-    virgPos      : integer := 3;
-    Mem_use      : integer := use_RAM
-    );
-  port (
-    rst             : in  std_logic;
-    clk             : in  std_logic;
-    apbi            : in  apb_slv_in_type;
-    apbo            : out apb_slv_out_type;
-    sample_clk_out  : out std_logic;
-    GOtest : out std_logic;
-    CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
-    );
-end component;
-end;
+  COMPONENT APB_IIR_Filter IS
+    GENERIC (
+      tech          : INTEGER := 0;
+      pindex        : INTEGER := 0;
+      paddr         : INTEGER := 0;
+      pmask         : INTEGER := 16#fff#;
+      pirq          : INTEGER := 0;
+      abits         : INTEGER := 8;
+      Sample_SZ     : INTEGER := 16;
+      ChanelsCount  : INTEGER := 1;
+      Coef_SZ       : INTEGER := 9;
+      CoefCntPerCel : INTEGER := 6;
+      Cels_count    : INTEGER := 5;
+      virgPos       : INTEGER := 3;
+      Mem_use       : INTEGER := use_RAM
+      );
+    PORT (
+      rst            : IN  STD_LOGIC;
+      clk            : IN  STD_LOGIC;
+      apbi           : IN  apb_slv_in_type;
+      apbo           : OUT apb_slv_out_type;
+      sample_clk_out : OUT STD_LOGIC;
+      GOtest         : OUT STD_LOGIC;
+      CoefsInitVal   : IN  STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
+      );
+  END COMPONENT;
+END;
diff --git a/lib/lpp/general_purpose/ALU.vhd b/lib/lpp/general_purpose/ALU.vhd
--- a/lib/lpp/general_purpose/ALU.vhd
+++ b/lib/lpp/general_purpose/ALU.vhd
@@ -19,54 +19,50 @@
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
 ----------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-library lpp;
-use lpp.general_purpose.all;
---IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
---NOT =0101 AND =0110 OR =0111 XOR =1000 
---SHIFTleft =1001 SHIFTright =1010
-
-entity ALU is
-generic(
-    Arith_en        :   integer := 1;
-    Logic_en        :   integer := 1;
-    Input_SZ_1      :   integer := 16;
-    Input_SZ_2      :   integer := 9
-
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    ctrl    :   in  std_logic_vector(3 downto 0);
-    OP1     :   in  std_logic_vector(Input_SZ_1-1 downto 0);
-    OP2     :   in  std_logic_vector(Input_SZ_2-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
-);
-end entity;
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+LIBRARY lpp;
+USE lpp.general_purpose.ALL;
+--IDLE                  = 0000
+--MAC                   = 0001
+--MULT                  = 0010 and set MULT in ADD reg
+--ADD                   = 0011
+--CLRMAC                = 0100
 
 
-
-architecture    ar_ALU of ALU is
-
-
-
-signal clr_MAC          :   std_logic:='1';
-
-
-begin
+ENTITY ALU IS
+  GENERIC(
+    Arith_en   : INTEGER := 1;
+    Logic_en   : INTEGER := 1;
+    Input_SZ_1 : INTEGER := 16;
+    Input_SZ_2 : INTEGER := 9
 
-clr_MAC     <=  '1' when    ctrl = "0100" else '0';
+    );
+  PORT(
+    clk   : IN  STD_LOGIC;
+    reset : IN  STD_LOGIC;
+    ctrl  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
+    OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
+    RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
+    );
+END ENTITY;
 
+ARCHITECTURE ar_ALU OF ALU IS
 
-arith : if Arith_en = 1 generate
-MACinst : MAC  
-generic map(Input_SZ_1,Input_SZ_2)
-port map(clk,reset,clr_MAC,ctrl(1 downto 0),OP1,OP2,RES);
-end generate;
+  SIGNAL clr_MAC : STD_LOGIC := '1';
+  
+BEGIN
+  clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110"  ELSE '0';
 
-end architecture;
+  arith : IF Arith_en = 1 GENERATE
+    MACinst : MAC
+      GENERIC MAP(Input_SZ_1, Input_SZ_2)
+      PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
+  END GENERATE;
+
+END ARCHITECTURE;
 
 
 
diff --git a/lib/lpp/general_purpose/Adder.vhd b/lib/lpp/general_purpose/Adder.vhd
--- a/lib/lpp/general_purpose/Adder.vhd
+++ b/lib/lpp/general_purpose/Adder.vhd
@@ -19,54 +19,57 @@
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
 ----------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-library lpp;
-use lpp.general_purpose.all;
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+LIBRARY lpp;
+USE lpp.general_purpose.ALL;
 
 
 
-entity Adder is 
-generic(
-    Input_SZ_A     :   integer := 16;
-    Input_SZ_B     :   integer := 16
+ENTITY Adder IS
+  GENERIC(
+    Input_SZ_A : INTEGER := 16;
+    Input_SZ_B : INTEGER := 16
 
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    clr     :   in  std_logic;
-    add     :   in  std_logic;
-    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
-    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ_A-1 downto 0)
-);
-end entity;
+    );
+  PORT(
+    clk   : IN  STD_LOGIC;
+    reset : IN  STD_LOGIC;
+    clr   : IN  STD_LOGIC;
+    load  : IN  STD_LOGIC;
+    add   : IN  STD_LOGIC;
+    OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+    OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+    RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
+    );
+END ENTITY;
 
 
 
 
-architecture ar_Adder of Adder is
+ARCHITECTURE ar_Adder OF Adder IS
 
-signal  REG     :   std_logic_vector(Input_SZ_A-1 downto 0);
-signal  RESADD  :   std_logic_vector(Input_SZ_A-1 downto 0);
+  SIGNAL REG    : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+  SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
 
-begin
+BEGIN
 
-RES     <=  REG;
-RESADD  <=  std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
+  RES    <= REG;
+  RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
 
-process(clk,reset)
-begin
-if reset = '0' then
-    REG     <=  (others => '0');
-elsif clk'event and clk ='1' then
-    if clr = '1' then
-        REG     <=  (others => '0');
-    elsif add = '1' then
-        REG     <=  RESADD;
-    end if;
-end if;
-end process;
-end ar_Adder;
+  PROCESS(clk, reset)
+  BEGIN
+    IF reset = '0' THEN
+      REG <= (OTHERS => '0');
+    ELSIF clk'EVENT AND clk = '1' then
+      IF clr = '1' THEN
+        REG <= (OTHERS => '0');
+      ELSIF add = '1' THEN
+        REG <= RESADD;
+      ELSIF load = '1' THEN
+        REG <= OP2;
+      END IF;
+    END IF;
+  END PROCESS;
+END ar_Adder;
diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd
--- a/lib/lpp/general_purpose/general_purpose.vhd
+++ b/lib/lpp/general_purpose/general_purpose.vhd
@@ -19,190 +19,223 @@
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
 ----------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
+--UPDATE
+-------------------------------------------------------------------------------
+-- 14-03-2013 - Jean-christophe Pellion
+-- ADD MUXN (a parametric multiplexor (N stage of MUX2))
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
 
 
 
-package general_purpose is
+PACKAGE general_purpose IS
 
 
 
-component Clk_divider is
-	 generic(OSC_freqHz	:	integer := 50000000;
-		TargetFreq_Hz	:	integer := 50000);
-    Port ( clk         : in   STD_LOGIC;
-           reset       : in   STD_LOGIC;
-           clk_divided : out  STD_LOGIC);
-end component;
+  COMPONENT Clk_divider IS
+    GENERIC(OSC_freqHz    : INTEGER := 50000000;
+            TargetFreq_Hz : INTEGER := 50000);
+    PORT (clk          : IN  STD_LOGIC;
+           reset       : IN  STD_LOGIC;
+           clk_divided : OUT STD_LOGIC);
+  END COMPONENT;
 
 
-component Adder is 
-generic(
-    Input_SZ_A     :   integer := 16;
-    Input_SZ_B     :   integer := 16
+  COMPONENT Adder IS
+    GENERIC(
+      Input_SZ_A : INTEGER := 16;
+      Input_SZ_B : INTEGER := 16
 
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    clr     :   in  std_logic;
-    add     :   in  std_logic;
-    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
-    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ_A-1 downto 0)
-);
-end component;
+      );
+    PORT(
+      clk   : IN  STD_LOGIC;
+      reset : IN  STD_LOGIC;
+      clr   : IN  STD_LOGIC;
+      load  : IN STD_LOGIC;
+      add   : IN  STD_LOGIC;
+      OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+      OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+      RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
-component ADDRcntr is 
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    count   :   in  std_logic;
-    clr     :   in  std_logic;
-    Q       :   out std_logic_vector(7 downto 0)
-);
-end component;
+  COMPONENT ADDRcntr IS
+    PORT(
+      clk   : IN  STD_LOGIC;
+      reset : IN  STD_LOGIC;
+      count : IN  STD_LOGIC;
+      clr   : IN  STD_LOGIC;
+      Q     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+  END COMPONENT;
 
-component ALU is
-generic(
-    Arith_en        :   integer := 1;
-    Logic_en        :   integer := 1;
-    Input_SZ_1      :   integer := 16;
-    Input_SZ_2      :   integer := 9
+  COMPONENT ALU IS
+    GENERIC(
+      Arith_en   : INTEGER := 1;
+      Logic_en   : INTEGER := 1;
+      Input_SZ_1 : INTEGER := 16;
+      Input_SZ_2 : INTEGER := 9
 
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    ctrl    :   in  std_logic_vector(3 downto 0);
-    OP1     :   in  std_logic_vector(Input_SZ_1-1 downto 0);
-    OP2     :   in  std_logic_vector(Input_SZ_2-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
-);
-end component;
+      );
+    PORT(
+      clk   : IN  STD_LOGIC;
+      reset : IN  STD_LOGIC;
+      ctrl  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+      OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
+      OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
+      RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
 
-component MAC is 
-generic(
-    Input_SZ_A     :   integer := 8;
-    Input_SZ_B     :   integer := 8
+  COMPONENT MAC IS
+    GENERIC(
+      Input_SZ_A : INTEGER := 8;
+      Input_SZ_B : INTEGER := 8
 
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    clr_MAC :   in  std_logic;
-    MAC_MUL_ADD :   in  std_logic_vector(1 downto 0);
-    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
-    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
-);
-end component;
+      );
+    PORT(
+      clk         : IN  STD_LOGIC;
+      reset       : IN  STD_LOGIC;
+      clr_MAC     : IN  STD_LOGIC;
+      MAC_MUL_ADD : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+      OP1         : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+      OP2         : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+      RES         : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
 
-component MAC_CONTROLER is
-port(
-    ctrl        :   in  std_logic_vector(1 downto 0);
-    MULT        :   out std_logic;
-    ADD         :   out std_logic;
-    MACMUX_sel  :   out std_logic;
-    MACMUX2_sel :   out std_logic
-
-);
-end component;
+  COMPONENT MAC_CONTROLER IS
+    PORT(
+      ctrl        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+      MULT        : OUT STD_LOGIC;
+      ADD         : OUT STD_LOGIC;
+      LOAD_ADDER  : out std_logic;
+      MACMUX_sel  : OUT STD_LOGIC;
+      MACMUX2_sel : OUT STD_LOGIC
+      );
+  END COMPONENT;
 
-component MAC_MUX is 
-generic(
-    Input_SZ_A     :   integer := 16;
-    Input_SZ_B     :   integer := 16
+  COMPONENT MAC_MUX IS
+    GENERIC(
+      Input_SZ_A : INTEGER := 16;
+      Input_SZ_B : INTEGER := 16
 
-);
-port(
-    sel     :   in  std_logic;
-    INA1    :   in  std_logic_vector(Input_SZ_A-1 downto 0);
-    INA2    :   in  std_logic_vector(Input_SZ_A-1 downto 0);
-    INB1    :   in  std_logic_vector(Input_SZ_B-1 downto 0);
-    INB2    :   in  std_logic_vector(Input_SZ_B-1 downto 0);
-    OUTA    :   out std_logic_vector(Input_SZ_A-1 downto 0);
-    OUTB    :   out std_logic_vector(Input_SZ_B-1 downto 0)
-);
-end component;
+      );
+    PORT(
+      sel  : IN  STD_LOGIC;
+      INA1 : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+      INA2 : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+      INB1 : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+      INB2 : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+      OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+      OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
 
-component MAC_MUX2 is 
-generic(Input_SZ     :   integer := 16);
-port(
-    sel     :   in  std_logic;
-    RES1    :   in  std_logic_vector(Input_SZ-1 downto 0);
-    RES2    :   in  std_logic_vector(Input_SZ-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ-1 downto 0)
-);
-end component;
+  COMPONENT MAC_MUX2 IS
+    GENERIC(Input_SZ : INTEGER := 16);
+    PORT(
+      sel  : IN  STD_LOGIC;
+      RES1 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
+      RES2 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
+      RES  : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
+      );
+  END COMPONENT;
+
+
+  COMPONENT MAC_REG IS
+    GENERIC(size : INTEGER := 16);
+    PORT(
+      reset : IN  STD_LOGIC;
+      clk   : IN  STD_LOGIC;
+      D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
+      Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
 
-component MAC_REG is 
-generic(size    :   integer := 16);
-port(
-    reset   :   in  std_logic;
-    clk     :   in  std_logic;
-    D       :   in  std_logic_vector(size-1 downto 0);
-    Q       :   out std_logic_vector(size-1 downto 0)
-);
-end component;
+  COMPONENT MUX2 IS
+    GENERIC(Input_SZ : INTEGER := 16);
+    PORT(
+      sel : IN  STD_LOGIC;
+      IN1 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
+      IN2 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
+      RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
+  TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
+  TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
+  
+  COMPONENT MUXN
+    GENERIC (
+      Input_SZ : INTEGER;
+      NbStage  : INTEGER);
+    PORT (
+      sel   : IN  STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
+      INPUT : IN  MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
+      --INPUT : IN  ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
+      RES   : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
+  END COMPONENT;
 
-component MUX2 is 
-generic(Input_SZ     :   integer := 16);
-port(
-    sel     :   in  std_logic;
-    IN1     :   in  std_logic_vector(Input_SZ-1 downto 0);
-    IN2     :   in  std_logic_vector(Input_SZ-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ-1 downto 0)
-);
-end component;
+  
 
-component Multiplier is 
-generic(
-    Input_SZ_A     :   integer := 16;
-    Input_SZ_B     :   integer := 16
+  COMPONENT Multiplier IS
+    GENERIC(
+      Input_SZ_A : INTEGER := 16;
+      Input_SZ_B : INTEGER := 16
 
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    mult    :   in  std_logic;
-    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
-    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
-);
-end component;
+      );
+    PORT(
+      clk   : IN  STD_LOGIC;
+      reset : IN  STD_LOGIC;
+      mult  : IN  STD_LOGIC;
+      OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+      OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+      RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
-component REG is 
-generic(size    :   integer := 16 ; initial_VALUE : integer := 0);
-port(
-    reset   :   in  std_logic;
-    clk     :   in  std_logic;
-    D       :   in  std_logic_vector(size-1 downto 0);
-    Q       :   out std_logic_vector(size-1 downto 0)
-);
-end component;
+  COMPONENT REG IS
+    GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
+    PORT(
+      reset : IN  STD_LOGIC;
+      clk   : IN  STD_LOGIC;
+      D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
+      Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
 
 
-component RShifter is 
-generic(
-    Input_SZ       :   integer := 16;
-    shift_SZ       :   integer := 4
-);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    shift   :   in  std_logic;
-    OP      :   in  std_logic_vector(Input_SZ-1 downto 0);
-    cnt     :   in  std_logic_vector(shift_SZ-1 downto 0);
-    RES     :   out std_logic_vector(Input_SZ-1 downto 0)
-);
-end component;
+  COMPONENT RShifter IS
+    GENERIC(
+      Input_SZ : INTEGER := 16;
+      shift_SZ : INTEGER := 4
+      );
+    PORT(
+      clk   : IN  STD_LOGIC;
+      reset : IN  STD_LOGIC;
+      shift : IN  STD_LOGIC;
+      OP    : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
+      cnt   : IN  STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
+      RES   : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
+      );
+  END COMPONENT;
 
-end;
+  COMPONENT SYNC_FF
+    GENERIC (
+      NB_FF_OF_SYNC : INTEGER);
+    PORT (
+      clk    : IN  STD_LOGIC;
+      rstn   : IN  STD_LOGIC;
+      A      : IN  STD_LOGIC;
+      A_sync : OUT STD_LOGIC);
+  END COMPONENT;
+
+END;
diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt
--- a/lib/lpp/general_purpose/vhdlsyn.txt
+++ b/lib/lpp/general_purpose/vhdlsyn.txt
@@ -8,7 +8,9 @@ MAC_MUX.vhd
 MAC_MUX2.vhd
 MAC_REG.vhd
 MUX2.vhd
+MUXN.vhd
 Multiplier.vhd
 REG.vhd
 Shifter.vhd
+SYNC_FF.vhd
 general_purpose.vhd
diff --git a/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd b/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
--- a/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
+++ b/lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
@@ -18,88 +18,176 @@
 -------------------------------------------------------------------------------
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
-----------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library lpp;
-use lpp.lpp_ad_conv.all;
-use lpp.general_purpose.Clk_divider;
+-------------------------------------------------------------------------------
+-- MODIFIED by  Jean-christophe PELLION
+--              jean-christophe.pellion@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY lpp;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.general_purpose.SYNC_FF;
+
+ENTITY ADS7886_drvr IS
+  GENERIC(
+    ChanelCount     : INTEGER;
+    ncycle_cnv_high : INTEGER := 79;
+    ncycle_cnv      : INTEGER := 500);
+  PORT (
+    -- CONV --
+    cnv_clk   : IN  STD_LOGIC;
+    cnv_rstn  : IN  STD_LOGIC;
+    cnv_run : IN  STD_LOGIC;
+    cnv       : OUT STD_LOGIC;
 
-entity ADS7886_drvr is
-    generic(ChanelCount	:	integer; 
-				clkkHz		:	integer);
-		 Port ( clk 	: in  STD_LOGIC;
-				  reset 	: in  STD_LOGIC;
-				  smplClk: in	STD_LOGIC;
-				  DataReady : out std_logic;
-				  smpout : out Samples_out(ChanelCount-1 downto 0);	
-				  AD_in	: in	AD7688_in(ChanelCount-1 downto 0);	
-				  AD_out : out AD7688_out);
-end ADS7886_drvr;
+    -- DATA --
+    clk  : IN  STD_LOGIC;
+    rstn : IN  STD_LOGIC;
+    sck  : OUT STD_LOGIC;
+    sdo  : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
+
+    sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
+    sample_val : OUT STD_LOGIC
+    );    
+END ADS7886_drvr;
 
-architecture ar_ADS7886_drvr of ADS7886_drvr is
-
-constant		convTrigger	:	integer:=  clkkHz*1/1000;  --tconv = 1.6µs
+ARCHITECTURE ar_ADS7886_drvr OF ADS7886_drvr IS
 
-signal i		:       integer range 0 to convTrigger :=0;
-signal clk_int		:       std_logic;
-signal smplClk_reg	:       std_logic;
-signal cnv_int		:       std_logic;
-signal smpout_int       :       Samples_out(ChanelCount-1 downto 0);
-
-
-begin
+  COMPONENT SYNC_FF
+    GENERIC (
+      NB_FF_OF_SYNC : INTEGER);
+    PORT (
+      clk    : IN  STD_LOGIC;
+      rstn   : IN  STD_LOGIC;
+      A      : IN  STD_LOGIC;
+      A_sync : OUT STD_LOGIC);
+  END COMPONENT;
 
 
-clkdiv: if clkkHz>=20000 generate 
-	clkdivider: Clk_divider
-       generic map(clkkHz*1000,19000000)
-		 Port map( clk ,reset,clk_int);
-end generate;
-		
+  SIGNAL cnv_cycle_counter  : INTEGER;
+  SIGNAL cnv_s              : STD_LOGIC;
+  SIGNAL cnv_sync           : STD_LOGIC;
+  SIGNAL cnv_sync_r         : STD_LOGIC;
+  SIGNAL cnv_done           : STD_LOGIC;
+  SIGNAL sample_bit_counter : INTEGER;
+  SIGNAL shift_reg          : Samples(ChanelCount-1 DOWNTO 0);
 
-clknodiv: if clkkHz<20000 generate 
-nodiv:		 clk_int <=	clk;
-end generate;
+  SIGNAL cnv_run_sync : STD_LOGIC;
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- CONV
+  -----------------------------------------------------------------------------
+  PROCESS (cnv_clk, cnv_rstn)
+  BEGIN  -- PROCESS
+    IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+      cnv_cycle_counter <= 0;
+      cnv_s             <= '0';
+    ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+      IF cnv_run = '1' THEN
+        IF cnv_cycle_counter < ncycle_cnv THEN
+          cnv_cycle_counter <= cnv_cycle_counter +1;
+          IF cnv_cycle_counter < ncycle_cnv_high THEN
+            cnv_s <= '1';
+          ELSE
+            cnv_s <= '0';
+          END IF;
+        ELSE
+          cnv_s             <= '1';
+          cnv_cycle_counter <= 0;
+        END IF;
+      ELSE
+        cnv_s             <= '0';
+        cnv_cycle_counter <= 0;
+      END IF;
+    END IF;
+  END PROCESS;
 
-AD_out.CNV	<=	cnv_int;	
-AD_out.SCK	<=	clk_int;
+  cnv <= cnv_s;
+
+  -----------------------------------------------------------------------------
 
 
-sckgen: process(clk,reset)
-begin
-	if reset = '0' then
-		i <= 0;
-		cnv_int		<=	'0';
-		smplClk_reg	<=	'0';
-	elsif clk'event and clk = '1' then
-		if smplClk = '1' and smplClk_reg = '0' then
-			if i = convTrigger then
-				smplClk_reg	<=	'1';
-				i	<=	0;
-				cnv_int	<=	'0';
-			else
-				i	<=	i+1;
-				cnv_int	<=	'1';
-			end if;
-		elsif smplClk = '0' and smplClk_reg = '1' then
-			smplClk_reg	<=	'0';
-		end if;
-	end if;
-end process;
+  -----------------------------------------------------------------------------
+  -- SYNC CNV
+  -----------------------------------------------------------------------------
+  
+  SYNC_FF_cnv : SYNC_FF
+    GENERIC MAP (
+      NB_FF_OF_SYNC => 2)
+    PORT MAP (
+      clk    => clk,
+      rstn   => rstn,
+      A      => cnv_s,
+      A_sync => cnv_sync);
+
+  PROCESS (clk, rstn)
+  BEGIN
+    IF rstn = '0' THEN
+      cnv_sync_r <= '0';
+      cnv_done   <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN
+      cnv_sync_r <= cnv_sync;
+      cnv_done   <= (NOT cnv_sync) AND cnv_sync_r;
+    END IF;
+  END PROCESS;
+
+  -----------------------------------------------------------------------------
+  
+  SYNC_FF_run : SYNC_FF
+    GENERIC MAP (
+      NB_FF_OF_SYNC => 2)
+    PORT MAP (
+      clk    => clk,
+      rstn   => rstn,
+      A      => cnv_run,
+      A_sync => cnv_run_sync);
 
 
-NDMSK: for i in 0 to ChanelCount-1
-generate
-	smpout(i)     <=    smpout_int(i) and X"0FFF";
-end generate;
-
+  
+  -----------------------------------------------------------------------------
+  -- DATA
+  -----------------------------------------------------------------------------
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN
+      FOR l IN 0 TO ChanelCount-1 LOOP
+        shift_reg(l) <= (OTHERS => '0');
+      END LOOP;
+      sample_bit_counter <= 0;
+      sample_val         <= '0';
+      SCK                <= '1';
+    ELSIF clk'EVENT AND clk = '1' THEN
+      
+      IF cnv_run_sync = '0' THEN
+        sample_bit_counter <= 0;
+      ELSIF cnv_done = '1' THEN
+        sample_bit_counter <= 1;
+      ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
+        sample_bit_counter <= sample_bit_counter + 1;
+      END IF;
 
-spidrvr: AD7688_spi_if 
-   generic map(ChanelCount)
-   Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int);
+      IF (sample_bit_counter MOD 2) = 1 THEN
+        FOR l IN 0 TO ChanelCount-1 LOOP
+          shift_reg(l)(15)          <= sdo(l);
+          shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+        END LOOP;
+        SCK <= '0';
+      ELSE
+        SCK <= '1';
+      END IF;
 
-
+      IF sample_bit_counter = 31 THEN
+        sample_val <= '1';
+        FOR l IN 0 TO ChanelCount-1 LOOP
+          sample(l)(15)           <= sdo(l);
+          sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+        END LOOP;
+      ELSE
+        sample_val <= '0';
+      END IF;
+    END IF;
+  END PROCESS;
+  
+END ar_ADS7886_drvr;
 
-end ar_ADS7886_drvr;
-