# HG changeset patch # User pellion # Date 2014-04-28 13:56:10 # Node ID 326fa6e964757b54c72a84f86de09b5a0aed5125 # Parent 4dc758b28af050d752896fd96c54f9c2ba9307b6 Update Sample transformation from ADC to IIR_FILTER diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -127,6 +127,7 @@ ARCHITECTURE beh OF LFR_em IS -- AD Converter ADS7886 SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); SIGNAL sample_val : STD_LOGIC; SIGNAL ADC_nCS_sig : STD_LOGIC; SIGNAL ADC_CLK_sig : STD_LOGIC; @@ -353,15 +354,15 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00010A") -- aa.bb.cc version + top_lfr_version => X"00010B") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM PORT MAP ( clk => clk_25, rstn => rstn, - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), sample_val => sample_val, apbi => apbi_ext, apbo => apbo_ext(15), @@ -372,6 +373,11 @@ BEGIN -- beh data_shaping_BW => bias_fail_sw, observation_reg => observation_reg); + + all_sample: FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I) & '0' & '0'; + END GENERATE all_sample; + ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -163,6 +163,7 @@ ARCHITECTURE beh OF MINI_LFR_top IS -- AD Converter ADS7886 SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); SIGNAL sample_val : STD_LOGIC; SIGNAL ADC_nCS_sig : STD_LOGIC; SIGNAL ADC_CLK_sig : STD_LOGIC; @@ -429,8 +430,8 @@ BEGIN -- beh PORT MAP ( clk => clk_25, rstn => reset, - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), sample_val => sample_val, apbi => apbi_ext, apbo => apbo_ext(15), @@ -441,6 +442,12 @@ BEGIN -- beh data_shaping_BW => bias_fail_sw_sig, observation_reg => observation_reg); + all_sample: FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I) & '0' & '0'; + END GENERATE all_sample; + + + top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 GENERIC MAP( ChannelCount => 8, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -46,8 +46,8 @@ ENTITY lpp_lfr IS clk : IN STD_LOGIC; rstn : IN STD_LOGIC; -- SAMPLE - sample_B : IN Samples14v(2 DOWNTO 0); - sample_E : IN Samples14v(4 DOWNTO 0); + sample_B : IN Samples(2 DOWNTO 0); + sample_E : IN Samples(4 DOWNTO 0); sample_val : IN STD_LOGIC; -- APB apbi : IN apb_slv_in_type; @@ -106,7 +106,7 @@ ENTITY lpp_lfr IS END lpp_lfr; ARCHITECTURE beh OF lpp_lfr IS - SIGNAL sample : Samples14v(7 DOWNTO 0); + --SIGNAL sample : Samples14v(7 DOWNTO 0); SIGNAL sample_s : Samples(7 DOWNTO 0); -- SIGNAL data_shaping_SP0 : STD_LOGIC; @@ -299,12 +299,12 @@ ARCHITECTURE beh OF lpp_lfr IS BEGIN - sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); - sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); + sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); + sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); - all_channel : FOR i IN 7 DOWNTO 0 GENERATE - sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); - END GENERATE all_channel; + --all_channel : FOR i IN 7 DOWNTO 0 GENERATE + -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); + --END GENERATE all_channel; ----------------------------------------------------------------------------- lpp_lfr_filter_1 : lpp_lfr_filter diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_WFP_nMS.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_WFP_nMS.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_WFP_nMS.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_WFP_nMS.vhd @@ -46,8 +46,8 @@ ENTITY lpp_lfr_WFP_nMS IS clk : IN STD_LOGIC; rstn : IN STD_LOGIC; -- SAMPLE - sample_B : IN Samples14v(2 DOWNTO 0); - sample_E : IN Samples14v(4 DOWNTO 0); + sample_B : IN Samples(2 DOWNTO 0); + sample_E : IN Samples(4 DOWNTO 0); sample_val : IN STD_LOGIC; -- APB apbi : IN apb_slv_in_type; @@ -106,7 +106,7 @@ ENTITY lpp_lfr_WFP_nMS IS END lpp_lfr_WFP_nMS; ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS - SIGNAL sample : Samples14v(7 DOWNTO 0); +-- SIGNAL sample : Samples14v(7 DOWNTO 0); SIGNAL sample_s : Samples(7 DOWNTO 0); -- SIGNAL data_shaping_SP0 : STD_LOGIC; @@ -299,12 +299,13 @@ ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS BEGIN - sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); - sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); + sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); + sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); - all_channel : FOR i IN 7 DOWNTO 0 GENERATE - sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); - END GENERATE all_channel; + --all_channel : FOR i IN 7 DOWNTO 0 GENERATE + -- --sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); + -- sample_s(i) <= sample(i) & '0' & '0'; + --END GENERATE all_channel; ----------------------------------------------------------------------------- lpp_lfr_filter_1 : lpp_lfr_filter diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -151,8 +151,8 @@ PACKAGE lpp_lfr_pkg IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - sample_B : IN Samples14v(2 DOWNTO 0); - sample_E : IN Samples14v(4 DOWNTO 0); + sample_B : IN Samples(2 DOWNTO 0); + sample_E : IN Samples(4 DOWNTO 0); sample_val : IN STD_LOGIC; apbi : IN apb_slv_in_type; apbo : OUT apb_slv_out_type; @@ -186,8 +186,8 @@ PACKAGE lpp_lfr_pkg IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - sample_B : IN Samples14v(2 DOWNTO 0); - sample_E : IN Samples14v(4 DOWNTO 0); + sample_B : IN Samples(2 DOWNTO 0); + sample_E : IN Samples(4 DOWNTO 0); sample_val : IN STD_LOGIC; apbi : IN apb_slv_in_type; apbo : OUT apb_slv_out_type;