# HG changeset patch # User pellion # Date 2015-07-13 13:59:39 # Node ID 12ec00ce062ef8d7611840bfb569774870764789 # Parent 7ac14cef3eb0fa66af6099b61a056c74734472a9 LFR-EQM (edn file send to Altran) diff --git a/boards/LFR-EQM/LFR_EQM_RTAX.pdc b/boards/LFR-EQM/LFR_EQM_RTAX.pdc --- a/boards/LFR-EQM/LFR_EQM_RTAX.pdc +++ b/boards/LFR-EQM/LFR_EQM_RTAX.pdc @@ -75,10 +75,10 @@ set_io spw2_sin -pinname 304 -fixed yes set_io spw2_dout -pinname 335 -fixed yes -DIRECTION Inout set_io spw2_sout -pinname 330 -fixed yes -DIRECTION Inout -set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout -#set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout -set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout -#set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout +#set_io {TAG[1]} -pinname 195 -fixed yes -DIRECTION Inout +set_io {TAG[2]} -pinname 190 -fixed yes -DIRECTION Inout +#set_io {TAG[3]} -pinname 189 -fixed yes -DIRECTION Inout +set_io {TAG[4]} -pinname 188 -fixed yes -DIRECTION Inout #set_io {TAG[5]} -pinname 187 -fixed yes -DIRECTION Inout #set_io {TAG[6]} -pinname 184 -fixed yes -DIRECTION Inout #set_io {TAG[7]} -pinname 200 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route.sdc --- a/boards/LFR-EQM/LFR_EQM_place_and_route.sdc +++ b/boards/LFR-EQM/LFR_EQM_place_and_route.sdc @@ -92,10 +92,9 @@ set_min_delay 0.000 -from [get_clocks {c ######## Delay Constraints ######## -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] - +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] ######## Delay Constraints ######## diff --git a/boards/MINI-LFR/MINI_LFR_place_and_route.sdc b/boards/MINI-LFR/MINI_LFR_place_and_route.sdc --- a/boards/MINI-LFR/MINI_LFR_place_and_route.sdc +++ b/boards/MINI-LFR/MINI_LFR_place_and_route.sdc @@ -29,3 +29,7 @@ create_clock -name SPW_CLOCK -period 100 # set_wire_load_mode top # Other Constraints + +set_max_delay 4.000 -from [get_ports { SPW_NOM_DIN SPW_NOM_SIN SPW_RED_DIN SPW_RED_SIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { SPW_NOM_DIN SPW_NOM_SIN SPW_RED_DIN SPW_RED_SIN reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] diff --git a/designs/LFR-EQM-WFP_MS/TB.vhd b/designs/LFR-EQM-WFP_MS/TB.vhd --- a/designs/LFR-EQM-WFP_MS/TB.vhd +++ b/designs/LFR-EQM-WFP_MS/TB.vhd @@ -143,8 +143,7 @@ ARCHITECTURE beh OF TB IS SIGNAL spw2_sout : STD_LOGIC; SIGNAL bias_fail_sw : STD_LOGIC; SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL ADC_smpclk : STD_LOGIC; SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0); @@ -286,7 +285,7 @@ BEGIN -- beh clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz ----------------------------------------------------------------------------- - MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE + MODULE_RHF1401 : FOR I IN 0 TO 8 GENERATE TestModule_RHF1401_1 : TestModule_RHF1401 GENERIC MAP ( freq => 2400,--24*(I*5+1), @@ -299,8 +298,8 @@ BEGIN -- beh --ADC_data_s <= "00" & X"190"; END GENERATE MODULE_RHF1401; - ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns; - ADC_data <= TRANSPORT ADC_data_s AFTER 35 ns; + ADC_OEB_bar_CH_s <= TRANSPORT (ADC_OEB_bar_HK & ADC_OEB_bar_CH) AFTER 10 ns; + ADC_data <= TRANSPORT ADC_data_s AFTER 55 ns; ----------------------------------------------------------------------------- PROCESS (clk50MHz, reset) BEGIN -- PROCESS @@ -664,6 +663,9 @@ BEGIN -- beh END PROCESS; ----------------------------------------------------------------------------- ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; + + data_ram <= TRANSPORT data AFTER 45 ns WHEN nSRAM_W = '0' ELSE (OTHERS => 'Z'); + data <= TRANSPORT data_ram AFTER 45 ns WHEN nSRAM_W = '1' ELSE (OTHERS => 'Z'); sbanks : FOR k IN 0 TO srambanks-1 GENERATE sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE @@ -674,7 +676,7 @@ BEGIN -- beh fname => sramfile) PORT MAP ( address, - data(31-i*8 DOWNTO 24-i*8), + data_ram(31-i*8 DOWNTO 24-i*8), ramsn(k), nSRAM_W, nSRAM_G diff --git a/designs/LFR-EQM-WFP_MS/wave.do b/designs/LFR-EQM-WFP_MS/wave.do --- a/designs/LFR-EQM-WFP_MS/wave.do +++ b/designs/LFR-EQM-WFP_MS/wave.do @@ -5,32 +5,26 @@ quietly virtual signal -install /tb/LFR_ quietly WaveActivateNextPane {} 0 add wave -noupdate -expand -group ALL /tb/data_message add wave -noupdate -expand -group ALL /tb/message_simu -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data -add wave -noupdate -expand -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY -add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_falling -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_reg -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled -add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data -add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk -add wave -noupdate -expand -group ALL -expand -group ADC -format Analog-Step -height 74 -max 24.0 /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter -add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/ADC_OEB_bar_HK -add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_OEB_bar_CH +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data +add wave -noupdate -expand -group ALL -expand -group RAM /tb/data_ram +add wave -noupdate -expand -group ALL -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY +add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE +add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val +add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data +add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s +add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg +add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync +add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data +add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk +add wave -noupdate -expand -group ALL -group ADC -format Analog-Step -height 74 -max 24.0 /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter +add wave -noupdate -expand -group ALL -group ADC /tb/LFR_EQM_1/ADC_OEB_bar_HK +add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_OEB_bar_CH add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val @@ -46,7 +40,6 @@ add wave -noupdate -expand -group ALL -g add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send -add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done @@ -68,7 +61,6 @@ add wave -noupdate -expand -group ALL -g add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig -add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window @@ -124,10 +116,6 @@ add wave -noupdate -expand -group ALL -r add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data -add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid_s -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val_s2 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) @@ -143,62 +131,47 @@ add wave -noupdate -expand -group ALL -r add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled -add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val -add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 15 -max 7517.0 -min -7504.0 -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) {-height 15 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample -add wave -noupdate -radix decimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in_val -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in -add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val -add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg -add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) {-format Analog-Step -height 74 -max 14061.999999999998 -min -14378.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/sample(8) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(7) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(6) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(5) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(4) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(3) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(2) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(1) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(0) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal}} /tb/LFR_EQM_1/sample -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample_s(8) -radix decimal} {/tb/LFR_EQM_1/sample_s(7) -radix decimal} {/tb/LFR_EQM_1/sample_s(6) -radix decimal} {/tb/LFR_EQM_1/sample_s(5) -radix decimal} {/tb/LFR_EQM_1/sample_s(4) -radix decimal} {/tb/LFR_EQM_1/sample_s(3) -radix decimal} {/tb/LFR_EQM_1/sample_s(2) -radix decimal} {/tb/LFR_EQM_1/sample_s(1) -radix decimal} {/tb/LFR_EQM_1/sample_s(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/sample_s(8) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/sample_s -add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in -add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim -add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out -add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0 -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH -add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data -add wave -noupdate /tb/LFR_EQM_1/sample_val -add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg -add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg -add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current -add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_wen -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/wdata -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_data -add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_ren -add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_buffer_full -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/data -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W -add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/address -add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state -add wave -noupdate -expand /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/fifo_ren -add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample +add wave -noupdate -expand /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_pre +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_falling_edge +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_sel_n +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter_r +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter_r2 +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter_d1 +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/channel_counter +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/MAX_CHANNEL_COUNTER +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/FILTER_ENABLED_STDLOGIC +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_d1 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val +add wave -noupdate -expand /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/FILTER_ENABLED +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ChanelCount +add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data +add wave -noupdate -expand /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/ahbo +add wave -noupdate -expand -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/ahbi.hgrant -expand} /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/ahbi TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {42970000 ps} 0} {{Cursor 2} {33108681 ps} 0} {{Cursor 3} {515290000 ps} 0} {{Cursor 4} {8300650000 ps} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 1} {42970000 ps} 0} {{Cursor 2} {35941209 ps} 0} {{Cursor 3} {2025053000 ps} 0} {{Cursor 4} {8300650000 ps} 0} +quietly wave cursor active 3 configure wave -namecolwidth 619 configure wave -valuecolwidth 311 configure wave -justifyvalue left @@ -213,4 +186,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {31103383 ps} {50275736 ps} +WaveRestoreZoom {1879745491179 ps} {1880033658360 ps} diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -317,7 +317,7 @@ BEGIN -- beh FPU_NETLIST => 0, ENABLE_DSU => 1, ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 0, + ENABLE_APB_UART => 1, ENABLE_IRQMP => 1, ENABLE_GPT => 1, NB_AHB_MASTER => NB_AHB_MASTER, @@ -331,8 +331,8 @@ BEGIN -- beh clk => clk_25, reset => rstn_25, errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, + ahbrxd => OPEN,--TXD1, + ahbtxd => OPEN,--RXD1, urxd1 => TXD2, utxd1 => RXD2, address => SRAM_A, @@ -653,4 +653,4 @@ BEGIN -- beh END GENERATE ahbo_m_ext_not_used; END GENERATE all_ahbo_m_ext; -END beh; +END beh; \ No newline at end of file diff --git a/designs/MINI-LFR_WFP_MS/Makefile b/designs/MINI-LFR_WFP_MS/Makefile --- a/designs/MINI-LFR_WFP_MS/Makefile +++ b/designs/MINI-LFR_WFP_MS/Makefile @@ -13,8 +13,9 @@ SYNPOPT="set_option -pipe 0; set_option VHDLSYNFILES= MINI_LFR_top.vhd VHDLSIMFILES= testbench.vhd SIMTOP=testbench -PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +##PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc +PDC=$(VHDLIB)/boards/$(BOARD)/no_uart.pdc SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut diff --git a/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd b/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd --- a/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_control_r2.vhd @@ -180,7 +180,12 @@ BEGIN STATE_CIC_LFR <= RUN_PROG_I; current_cmd <= PROG_START_I; current_channel <= 0; - nb_data_receipt <= nb_data_receipt + 1; + IF nb_data_receipt = 255 THEN + nb_data_receipt <= 0; + ELSE + nb_data_receipt <= nb_data_receipt + 1; + END IF; + END IF; WHEN RUN_PROG_I => @@ -246,4 +251,4 @@ BEGIN END IF; END PROCESS; -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd --- a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd @@ -29,28 +29,37 @@ ENTITY top_ad_conv_RHF1401_withFilter IS END top_ad_conv_RHF1401_withFilter; ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS - + + ----------------------------------------------------------------------------- + -- CNV GEN + ----------------------------------------------------------------------------- SIGNAL cnv_cycle_counter : INTEGER RANGE 0 TO ncycle_cnv-1; SIGNAL cnv_s : STD_LOGIC; SIGNAL cnv_s_reg : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- SYNC CNV + ----------------------------------------------------------------------------- SIGNAL cnv_sync : STD_LOGIC; SIGNAL cnv_sync_pre : STD_LOGIC; SIGNAL cnv_sync_falling_edge : STD_LOGIC; - SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - SIGNAL enable_ADC : STD_LOGIC; - - - SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); - - SIGNAL channel_counter : INTEGER; - CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; - + ----------------------------------------------------------------------------- + -- DATA Read and Data Output Enable + ----------------------------------------------------------------------------- + CONSTANT MAX_CHANNEL_COUNTER : INTEGER := (ChanelCount-1)*2 + 5; + SIGNAL channel_counter : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; + SIGNAL channel_counter_r : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; + SIGNAL channel_counter_r2 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; + SIGNAL channel_counter_d1 : INTEGER RANGE 0 TO MAX_CHANNEL_COUNTER; + + SIGNAL channel_sel_n : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + + SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); + SIGNAL ADC_data_d1 : Samples14; SIGNAL ADC_data_selected : Samples14; SIGNAL ADC_data_result : Samples15; - - SIGNAL sample_counter : INTEGER; - CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9; + CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED, ChanelCount)); @@ -105,112 +114,97 @@ BEGIN A => cnv_s_reg, A_sync => cnv_sync); - cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0'; - - ----------------------------------------------------------------------------- - -- DATA GEN Output Enable - ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1'); - cnv_sync_pre <= '0'; - enable_ADC <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - cnv_sync_pre <= cnv_sync; - IF cnv_sync_falling_edge = '1' THEN - enable_ADC <= '1'; - ADC_nOE_reg(0) <= '0'; - ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1'); - ELSE - enable_ADC <= NOT enable_ADC; - IF enable_ADC = '0' THEN - ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1'; - END IF; - END IF; - + cnv_sync_pre <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + cnv_sync_pre <= cnv_sync; END IF; END PROCESS; - ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg; + cnv_sync_falling_edge <= '1' WHEN cnv_sync = '0' AND cnv_sync_pre = '1' ELSE '0'; + ----------------------------------------------------------------------------- - -- ADC READ DATA + -- DATA Read and Data Output Enable ----------------------------------------------------------------------------- + PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - channel_counter <= MAX_COUNTER; - - all_sample_reg_init : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - sample_reg(I) <= (OTHERS => '0'); - END LOOP all_sample_reg_init; - - sample_val <= '0'; - sample_counter <= 0; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + channel_counter <= MAX_CHANNEL_COUNTER; + sample_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge IF cnv_sync_falling_edge = '1' THEN channel_counter <= 0; ELSE - IF channel_counter < MAX_COUNTER THEN + IF channel_counter < MAX_CHANNEL_COUNTER THEN channel_counter <= channel_counter + 1; END IF; END IF; - sample_val <= '0'; - all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - IF channel_counter = I*2 THEN - IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN - sample_reg(I) <= ADC_data_result(14 DOWNTO 1); - ELSE - sample_reg(I) <= ADC_data; - END IF; - END IF; - END LOOP all_sample_reg; - - IF channel_counter = (ChanelCount-1)*2 THEN - - IF sample_counter = MAX_SAMPLE_COUNTER THEN - sample_counter <= 0; - sample_val <= '1'; - ELSE - sample_counter <= sample_counter +1; - END IF; - - END IF; + IF channel_counter = MAX_CHANNEL_COUNTER-1 THEN + sample_val <= '1'; + ELSE + sample_val <= '0'; + END IF; END IF; END PROCESS; --- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg) --- BEGIN -- PROCESS mux_adc --- CASE channel_counter IS --- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2); --- END CASE; --- END PROCESS mux_adc; + all_channel: FOR I IN 0 TO ChanelCount-1 GENERATE + channel_sel_n(I) <= '0' WHEN channel_counter = 2*I ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_reg(I) <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF channel_counter_d1 = 2*I THEN + IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN + sample_reg(I) <= ADC_data_result(14 DOWNTO 1); + ELSE + sample_reg(I) <= ADC_data_d1; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_channel; - ----------------------------------------------------------------------------- - -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/ - ----------------------------------------------------------------------------- - - WITH channel_counter SELECT + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + ADC_nOE <= (OTHERS => '1'); + channel_counter_r <= MAX_CHANNEL_COUNTER; + channel_counter_r2 <= MAX_CHANNEL_COUNTER; + channel_counter_d1 <= MAX_CHANNEL_COUNTER; + ADC_data_d1 <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ADC_nOE <= channel_sel_n; + channel_counter_r <= channel_counter; + channel_counter_r2 <= channel_counter_r; + channel_counter_d1 <= channel_counter_r2; + ADC_data_d1 <= ADC_data; + END IF; + END PROCESS; + + WITH channel_counter_d1 SELECT ADC_data_selected <= sample_reg(0) WHEN 0*2, - sample_reg(1) WHEN 1*2, - sample_reg(2) WHEN 2*2, - sample_reg(3) WHEN 3*2, - sample_reg(4) WHEN 4*2, - sample_reg(5) WHEN 5*2, - sample_reg(6) WHEN 6*2, - sample_reg(7) WHEN 7*2, - sample_reg(8) WHEN OTHERS; + sample_reg(1) WHEN 1*2, + sample_reg(2) WHEN 2*2, + sample_reg(3) WHEN 3*2, + sample_reg(4) WHEN 4*2, + sample_reg(5) WHEN 5*2, + sample_reg(6) WHEN 6*2, + sample_reg(7) WHEN 7*2, + sample_reg(8) WHEN OTHERS; - ----------------------------------------------------------------------------- - -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\ - ----------------------------------------------------------------------------- + ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data_d1(13) & ADC_data_d1))); - ADC_data_result <= STD_LOGIC_VECTOR((SIGNED(ADC_data_selected(13) & ADC_data_selected) + SIGNED(ADC_data(13) & ADC_data))); + sample <= sample_reg; - sample <= sample_reg; + END ar_top_ad_conv_RHF1401; diff --git a/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd b/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd --- a/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd +++ b/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd @@ -42,41 +42,61 @@ ENTITY SPI_DAC_DRIVER IS END ENTITY SPI_DAC_DRIVER; ARCHITECTURE behav OF SPI_DAC_DRIVER IS - SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL SMP_CLK_R : STD_LOGIC := '0'; - SIGNAL shiftcnt : INTEGER := 0; - SIGNAL shifting : STD_LOGIC := '0'; + SIGNAL DATA_s : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL SMP_CLK_R : STD_LOGIC := '0'; + SIGNAL SMP_CLK_RisingEdge : STD_LOGIC := '0'; + SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0'; + SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0'; + + SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL shiftcnt : INTEGER := 0; + SIGNAL shifting : STD_LOGIC := '0'; SIGNAL SCLK_s : STD_LOGIC; BEGIN + ----------------------------------------------------------------------------- + -- Data Re-Orderng + ----------------------------------------------------------------------------- MSB : IF MSBFIRST = 1 GENERATE - INPUTREG <= DATA; + DATA_s <= DATA; END GENERATE; LSB : IF MSBFIRST = 0 GENERATE - INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1); + DATA_s(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1); END GENERATE; + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + PROCESS(clk, rstn) + BEGIN + IF rstn = '0' THEN + SMP_CLK_R <= '0'; + SMP_CLK_RisingEdge_2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + SMP_CLK_R <= SMP_CLK; + SMP_CLK_RisingEdge_2 <= SMP_CLK_RisingEdge_1; + END IF; + END PROCESS; + + SMP_CLK_RisingEdge_1 <= '1' WHEN SMP_CLK = '1' AND SMP_CLK_R = '0' ELSE '0'; + SMP_CLK_RisingEdge <= '1' WHEN SMP_CLK_RisingEdge_1 = '1' OR SMP_CLK_RisingEdge_2 = '1' ELSE '0'; + + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + SCLK <= SCLK_s; + DOUT <= SHIFTREG(datawidth-1); + PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) SCLK_s <= '0'; ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge SCLK_s <= NOT SCLK_s; - - END IF; - END PROCESS; - SCLK <= SCLK_s; - - PROCESS(clk, rstn) - BEGIN - IF rstn = '0' THEN - SMP_CLK_R <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN - SMP_CLK_R <= SMP_CLK; END IF; END PROCESS; @@ -87,28 +107,30 @@ BEGIN SHIFTREG <= (OTHERS => '0'); SYNC <= '0'; shiftcnt <= 0; - DOUT <= '0'; ELSIF clk'EVENT AND clk = '1' THEN - DOUT <= SHIFTREG(datawidth-1); - IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN - SYNC <= '1'; - shifting <= '1'; - ELSE - SYNC <= '0'; - IF shiftcnt = datawidth-1 THEN - shifting <= '0'; + + IF SCLK_s = '0' THEN + + IF SMP_CLK_RisingEdge = '1' THEN + SYNC <= '1'; + shifting <= '1'; + ELSE + SYNC <= '0'; + IF shiftcnt = datawidth-1 THEN + shifting <= '0'; + END IF; END IF; - END IF; - IF shifting = '1' THEN - shiftcnt <= shiftcnt + 1; - SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0'; - ELSE - SHIFTREG <= INPUTREG; - shiftcnt <= 0; + IF shifting = '1' THEN + shiftcnt <= shiftcnt + 1; + SHIFTREG(datawidth-1 DOWNTO 1) <= SHIFTREG (datawidth-2 DOWNTO 0); + ELSE + SHIFTREG <= DATA_s; + shiftcnt <= 0; + END IF; + END IF; END IF; END PROCESS; END ARCHITECTURE behav; - diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -234,7 +234,7 @@ BEGIN apbi => apbi, apbo => apbo, - run_ms => OPEN,--run_ms, +-- run_ms => OPEN,--run_ms, ready_matrix_f0 => ready_matrix_f0, ready_matrix_f1 => ready_matrix_f1, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -40,10 +40,10 @@ USE techmap.gencomp.ALL; ENTITY lpp_lfr_apbreg IS GENERIC ( - nb_data_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 3; + nb_data_by_buffer_size : INTEGER := 32; + nb_snapshot_param_size : INTEGER := 32; + delta_vector_size : INTEGER := 32; + delta_vector_size_f0_2 : INTEGER := 7; pindex : INTEGER := 4; paddr : INTEGER := 4; @@ -62,7 +62,7 @@ ENTITY lpp_lfr_apbreg IS --------------------------------------------------------------------------- -- Spectral Matrix Reg - run_ms : OUT STD_LOGIC; +-- run_ms : OUT STD_LOGIC; -- IN ready_matrix_f0 : IN STD_LOGIC; ready_matrix_f1 : IN STD_LOGIC; @@ -165,7 +165,7 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS TYPE lpp_SpectralMatrix_regs IS RECORD config_active_interruption_onNewMatrix : STD_LOGIC; config_active_interruption_onError : STD_LOGIC; - config_ms_run : STD_LOGIC; +-- config_ms_run : STD_LOGIC; status_ready_matrix_f0_0 : STD_LOGIC; status_ready_matrix_f1_0 : STD_LOGIC; status_ready_matrix_f2_0 : STD_LOGIC; @@ -357,14 +357,23 @@ BEGIN -- beh END IF; END PROCESS; + + reg_sp.length_matrix <= "00" & X"0000C8"; + reg_sp.config_active_interruption_onError <= '0'; + reg_wp.delta_f0 <= X"0001280A"; + reg_wp.delta_f0_2 <= "0110000"; + reg_wp.delta_f1 <= X"0001283F"; + reg_wp.delta_f2 <= X"000127FF"; + reg_wp.nb_data_by_buffer <= X"00000A7F"; + reg_wp.nb_snapshot_param <= X"00000A80"; + reg_wp.length_buffer <= "00" & X"0001F8"; --25 .. 0 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); BEGIN -- PROCESS lpp_dma_top IF HRESETn = '0' THEN -- asynchronous reset (active low) reg_sp.config_active_interruption_onNewMatrix <= '0'; - reg_sp.config_active_interruption_onError <= '0'; - reg_sp.config_ms_run <= '0'; +-- reg_sp.config_ms_run <= '0'; reg_sp.status_ready_matrix_f0_0 <= '0'; reg_sp.status_ready_matrix_f1_0 <= '0'; reg_sp.status_ready_matrix_f2_0 <= '0'; @@ -382,7 +391,7 @@ BEGIN -- beh reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); - reg_sp.length_matrix <= (OTHERS => '0'); +-- reg_sp.length_matrix <= (OTHERS => '0'); -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok @@ -420,16 +429,16 @@ BEGIN -- beh reg_wp.status_new_err <= (OTHERS => '0'); reg_wp.error_buffer_full <= (OTHERS => '0'); reg_wp.delta_snapshot <= (OTHERS => '0'); - reg_wp.delta_f0 <= (OTHERS => '0'); - reg_wp.delta_f0_2 <= (OTHERS => '0'); - reg_wp.delta_f1 <= (OTHERS => '0'); - reg_wp.delta_f2 <= (OTHERS => '0'); - reg_wp.nb_data_by_buffer <= (OTHERS => '0'); - reg_wp.nb_snapshot_param <= (OTHERS => '0'); + --reg_wp.delta_f0 <= (OTHERS => '0'); + --reg_wp.delta_f0_2 <= (OTHERS => '0'); + --reg_wp.delta_f1 <= (OTHERS => '0'); + --reg_wp.delta_f2 <= (OTHERS => '0'); + --reg_wp.nb_data_by_buffer <= (OTHERS => '0'); + --reg_wp.nb_snapshot_param <= (OTHERS => '0'); reg_wp.start_date <= (OTHERS => '1'); reg_wp.status_ready_buffer_f <= (OTHERS => '0'); - reg_wp.length_buffer <= (OTHERS => '0'); + --reg_wp.length_buffer <= (OTHERS => '0'); pirq_temp <= (OTHERS => '0'); @@ -473,8 +482,8 @@ BEGIN -- beh WHEN ADDR_LFR_SM_CONFIG => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; - prdata(1) <= reg_sp.config_active_interruption_onError; - prdata(2) <= reg_sp.config_ms_run; +-- prdata(1) <= reg_sp.config_active_interruption_onError; +-- prdata(2) <= reg_sp.config_ms_run; WHEN ADDR_LFR_SM_STATUS => prdata(0) <= reg_sp.status_ready_matrix_f0_0; @@ -507,7 +516,7 @@ BEGIN -- beh WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); - WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; +-- WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; --------------------------------------------------------------------- WHEN ADDR_LFR_WP_DATASHAPING => prdata(0) <= reg_wp.data_shaping_BW; @@ -540,12 +549,12 @@ BEGIN -- beh prdata(15 DOWNTO 12) <= reg_wp.status_new_err; WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; - WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; - WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; - WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; - WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; - WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; - WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; +-- WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; +-- WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; +-- WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; +-- WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; +-- WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; +-- WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date; WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); @@ -568,7 +577,7 @@ BEGIN -- beh WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); - WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; +-- WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg; prdata(31 DOWNTO 16) <= (OTHERS => '0'); @@ -587,8 +596,8 @@ BEGIN -- beh -- WHEN ADDR_LFR_SM_CONFIG => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); - reg_sp.config_active_interruption_onError <= apbi.pwdata(1); - reg_sp.config_ms_run <= apbi.pwdata(2); +-- reg_sp.config_active_interruption_onError <= apbi.pwdata(1); +-- reg_sp.config_ms_run <= apbi.pwdata(2); WHEN ADDR_LFR_SM_STATUS => reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0; @@ -608,7 +617,7 @@ BEGIN -- beh WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; - WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); +-- WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); --------------------------------------------------------------------- WHEN ADDR_LFR_WP_DATASHAPING => reg_wp.data_shaping_BW <= apbi.pwdata(0); @@ -643,15 +652,15 @@ BEGIN -- beh END LOOP all_reg_wp_status_bit; WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); - WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); - WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); - WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + --WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + --WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); + --WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + --WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); + --WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); + --WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); - WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); + --WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); WHEN OTHERS => NULL; END CASE; @@ -664,14 +673,15 @@ BEGIN -- beh ready_matrix_f1 OR ready_matrix_f2) ) - OR - (reg_sp.config_active_interruption_onError AND ( --- error_bad_component_error OR - error_buffer_full - OR error_input_fifo_write(0) - OR error_input_fifo_write(1) - OR error_input_fifo_write(2)) - )); + --OR + --(reg_sp.config_active_interruption_onError AND + -- ( + -- error_buffer_full + -- OR error_input_fifo_write(0) + -- OR error_input_fifo_write(1) + -- OR error_input_fifo_write(2)) + -- ) + ); -- apbo.pirq(pirq_wfp) apbo_irq_wfp <= ored_irq_wfp; @@ -721,7 +731,7 @@ BEGIN -- beh irq_wfp_ZERO <= (OTHERS => '0'); ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; - run_ms <= reg_sp.config_ms_run; +-- run_ms <= reg_sp.config_ms_run; ----------------------------------------------------------------------------- -- diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -282,7 +282,7 @@ PACKAGE lpp_lfr_pkg IS HRESETn : IN STD_ULOGIC; apbi : IN apb_slv_in_type; apbo : OUT apb_slv_out_type; - run_ms : OUT STD_LOGIC; +-- run_ms : OUT STD_LOGIC; ready_matrix_f0 : IN STD_LOGIC; ready_matrix_f1 : IN STD_LOGIC; ready_matrix_f2 : IN STD_LOGIC;