diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd --- a/designs/BeagleSynth/BeagleSynth.vhd +++ b/designs/BeagleSynth/BeagleSynth.vhd @@ -142,8 +142,6 @@ resetn_pad : inpad generic map (tech => port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); - - DAC0 : entity work.beagleSigGen generic map( memtech, @@ -159,15 +157,16 @@ DAC0 : entity work.beagleSigGen address => GPMC_SLAVE_ADDRESS(3 downto 1), DATA => GPMC_SLAVE_DATA, WEN => GPMC_SLAVE_WEN, - REN_debug => LED(1), + REN_debug => open, FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0), FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8) ); -LED(0) <= GPMC_SLAVE_WEN; -LED(2) <= GPMC_WEN; +--LED(0) <= GPMC_SLAVE_ADDRESS(1); +--LED(1) <= GPMC_SLAVE_ADDRESS(2); +LED(2) <= GPMC_SLAVE_WEN; gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); GPMCS0: entity work.GPMC_SLAVE @@ -179,6 +178,8 @@ GPMCS0: entity work.GPMC_SLAVE DATA => GPMC_SLAVE_DATA, ADDRESS => GPMC_SLAVE_ADDRESS, WEN => GPMC_SLAVE_WEN, + SMP_CKL => LED(0), + SMP_WEN => LED(1), GPMC_AD => GPMC_AD, GPMC_A => GPMC_A, GPMC_CLK => gpmc_clk, diff --git a/designs/BeagleSynth/GPMC_SLAVE.vhd b/designs/BeagleSynth/GPMC_SLAVE.vhd --- a/designs/BeagleSynth/GPMC_SLAVE.vhd +++ b/designs/BeagleSynth/GPMC_SLAVE.vhd @@ -39,6 +39,8 @@ entity GPMC_SLAVE is DATA : out STD_LOGIC_VECTOR(15 downto 0); ADDRESS : out std_logic_vector(19 downto 0); WEN : out STD_LOGIC; + SMP_CKL : out STD_LOGIC; + SMP_WEN : out STD_LOGIC; GPMC_AD : inout std_logic_vector(15 downto 0); GPMC_A : in std_logic_vector(19 downto 0); GPMC_CLK : in std_logic; @@ -55,12 +57,20 @@ end GPMC_SLAVE; architecture Behavioral of GPMC_SLAVE is -signal data_out : std_logic_vector(15 downto 0) := (others => '0'); -signal data_in : std_logic_vector(15 downto 0) := (others => '0'); +signal data_out : std_logic_vector(15 downto 0) := (others => '0'); +signal data_in : std_logic_vector(15 downto 0) := (others => '0'); +signal data_in_reg0 : std_logic_vector(15 downto 0) := (others => '0'); +signal data_in_reg1 : std_logic_vector(15 downto 0) := (others => '0'); +signal data_in_reg2 : std_logic_vector(15 downto 0) := (others => '0'); +signal address_reg0 : std_logic_vector(19 downto 0) := (others => '0'); +signal address_reg1 : std_logic_vector(19 downto 0) := (others => '0'); +signal address_reg2 : std_logic_vector(19 downto 0) := (others => '0'); +signal ADVN_ALE_reg : std_logic_vector(3 downto 0) := (others => '0'); + signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0'); signal data_r : std_logic_vector(15 downto 0) := (others => '0'); - +signal GPMC_WEN_reg : std_logic_vector(3 downto 0) := (others => '0'); signal outen : std_logic := '0'; @@ -79,29 +89,59 @@ port map ( ); GPMC_WAIT0 <= '1'; +SMP_CKL <= GPMC_CLK_reg(0); +SMP_WEN <= GPMC_WEN_reg(2); +process(reset,clk) +begin +if reset = '0' then + GPMC_CLK_reg <= "0000"; + ADDRESS <= (others => '0'); + ADVN_ALE_reg <= (others => '0'); + address_reg0 <= (others => '0'); + address_reg1 <= (others => '0'); + address_reg2 <= (others => '0'); +elsif clk'event and clk = '1' then + GPMC_CLK_reg(0) <= GPMC_CLK; + GPMC_CLK_reg(1) <= GPMC_CLK_reg(0); + GPMC_CLK_reg(2) <= GPMC_CLK_reg(1); + ADVN_ALE_reg(0) <= GPMC_ADVN_ALE; + ADVN_ALE_reg(1) <= ADVN_ALE_reg(0); + ADVN_ALE_reg(2) <= ADVN_ALE_reg(1); + address_reg0 <= GPMC_A; + address_reg1 <= address_reg0; + address_reg2 <= address_reg1; + if GPMC_CLK_reg(1) = '1' and GPMC_CLK_reg(2) = '0' then + if ADVN_ALE_reg(2) = '0' then + ADDRESS <= address_reg2; + end if; + end if; + +end if; +end process; process(reset,clk) begin if reset = '0' then WEN <= '1'; - GPMC_CLK_reg <= "0000"; - ADDRESS <= (others => '0'); + GPMC_WEN_reg <= "0000"; + data_in_reg0 <= (others => '0'); + data_in_reg1 <= (others => '0'); + data_in_reg2 <= (others => '0'); elsif clk'event and clk = '1' then - GPMC_CLK_reg(0) <= GPMC_CLK; - if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then - if GPMC_WEN = '0' then - WEN <= '0'; - DATA <= data_in; - end if; - if GPMC_ADVN_ALE = '0' then - ADDRESS <= GPMC_A; - end if; + GPMC_WEN_reg(0) <= GPMC_WEN; + GPMC_WEN_reg(1) <= GPMC_WEN_reg(0); + GPMC_WEN_reg(2) <= GPMC_WEN_reg(1); + data_in_reg0 <= data_in; + data_in_reg1 <= data_in_reg0; + data_in_reg2 <= data_in_reg1; + if GPMC_WEN_reg(2) = '1' and GPMC_WEN_reg(1) = '0' then + WEN <= '0'; + DATA <= data_in_reg2; else - WEN <= '1'; + WEN <= '1'; end if; - end if; end process; diff --git a/designs/BeagleSynth/beagleSigGen.vhd b/designs/BeagleSynth/beagleSigGen.vhd --- a/designs/BeagleSynth/beagleSigGen.vhd +++ b/designs/BeagleSynth/beagleSigGen.vhd @@ -75,174 +75,174 @@ begin FIFO_FULL <= FIFO_FULL_net; FIFO_EMPTY <= FIFO_EMPTY_net; ---fron_fifo1: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(0), --- empty => FIFO_EMPTY_net(0), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(0), --- wdata => DATA_reg, --- full => FIFO_FULL_net(0), --- waddr => open --- ); ---fron_fifo2: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(1), --- empty => FIFO_EMPTY_net(1), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(1), --- wdata => DATA_reg, --- full => FIFO_FULL_net(1), --- waddr => open --- ); ---fron_fifo3: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(2), --- empty => FIFO_EMPTY_net(2), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(2), --- wdata => DATA_reg, --- full => FIFO_FULL_net(2), --- waddr => open --- ); ---fron_fifo4: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(3), --- empty => FIFO_EMPTY_net(3), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(3), --- wdata => DATA_reg, --- full => FIFO_FULL_net(3), --- waddr => open --- ); ---fron_fifo5: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(4), --- empty => FIFO_EMPTY_net(4), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(4), --- wdata => DATA_reg, --- full => FIFO_FULL_net(4), --- waddr => open --- ); ---fron_fifo6: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(5), --- empty => FIFO_EMPTY_net(5), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(5), --- wdata => DATA_reg, --- full => FIFO_FULL_net(5), --- waddr => open --- ); ---fron_fifo7: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(6), --- empty => FIFO_EMPTY_net(6), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(6), --- wdata => DATA_reg, --- full => FIFO_FULL_net(6), --- waddr => open --- ); ---fron_fifo8: lpp_fifo --- generic map( --- tech => memtech, --- Mem_use => 1, --use RAM not CELS --- DataSz => 16, --- AddrSz => 8 --- ) --- port map( --- rstn => rstn, --- ReUse => '0', --- rclk => clk, --- ren => FIFO_REN, --- rdata => FIFO_out(7), --- empty => FIFO_EMPTY_net(7), --- raddr => open, --- wclk => clk, --- wen => FIFO_WEN(7), --- wdata => DATA_reg, --- full => FIFO_FULL_net(7), --- waddr => open --- ); +fron_fifo1: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(0), + empty => FIFO_EMPTY_net(0), + raddr => open, + wclk => clk, + wen => FIFO_WEN(0), + wdata => DATA_reg, + full => FIFO_FULL_net(0), + waddr => open + ); +fron_fifo2: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(1), + empty => FIFO_EMPTY_net(1), + raddr => open, + wclk => clk, + wen => FIFO_WEN(1), + wdata => DATA_reg, + full => FIFO_FULL_net(1), + waddr => open + ); +fron_fifo3: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(2), + empty => FIFO_EMPTY_net(2), + raddr => open, + wclk => clk, + wen => FIFO_WEN(2), + wdata => DATA_reg, + full => FIFO_FULL_net(2), + waddr => open + ); +fron_fifo4: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(3), + empty => FIFO_EMPTY_net(3), + raddr => open, + wclk => clk, + wen => FIFO_WEN(3), + wdata => DATA_reg, + full => FIFO_FULL_net(3), + waddr => open + ); +fron_fifo5: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(4), + empty => FIFO_EMPTY_net(4), + raddr => open, + wclk => clk, + wen => FIFO_WEN(4), + wdata => DATA_reg, + full => FIFO_FULL_net(4), + waddr => open + ); +fron_fifo6: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(5), + empty => FIFO_EMPTY_net(5), + raddr => open, + wclk => clk, + wen => FIFO_WEN(5), + wdata => DATA_reg, + full => FIFO_FULL_net(5), + waddr => open + ); +fron_fifo7: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(6), + empty => FIFO_EMPTY_net(6), + raddr => open, + wclk => clk, + wen => FIFO_WEN(6), + wdata => DATA_reg, + full => FIFO_FULL_net(6), + waddr => open + ); +fron_fifo8: lpp_fifo + generic map( + tech => memtech, + Mem_use => 1, --use RAM not CELS + DataSz => 16, + AddrSz => 8 + ) + port map( + rstn => rstn, + ReUse => '0', + rclk => clk, + ren => FIFO_REN, + rdata => FIFO_out(7), + empty => FIFO_EMPTY_net(7), + raddr => open, + wclk => clk, + wen => FIFO_WEN(7), + wdata => DATA_reg, + full => FIFO_FULL_net(7), + waddr => open + ); REN_debug <= FIFO_REN; @@ -257,28 +257,20 @@ begin case address is when "000"=> FIFO_WEN <= "11111110"; - FIFO_out(0) <= DATA; when "001"=> FIFO_WEN <= "11111101"; - FIFO_out(1) <= DATA; when "010"=> FIFO_WEN <= "11111011"; - FIFO_out(2) <= DATA; when "011"=> FIFO_WEN <= "11110111"; - FIFO_out(3) <= DATA; when "100"=> FIFO_WEN <= "11101111"; - FIFO_out(4) <= DATA; when "101"=> FIFO_WEN <= "11011111"; - FIFO_out(5) <= DATA; when "110"=> FIFO_WEN <= "10111111"; - FIFO_out(6) <= DATA; when "111"=> FIFO_WEN <= "01111111"; - FIFO_out(7) <= DATA; when others => FIFO_WEN <= "11111111"; end case; @@ -326,7 +318,7 @@ DAC0 : DAC8581 smpclk0: Clk_divider GENERIC map(OSC_freqHz => 150000000, - TargetFreq_Hz => 32000) + TargetFreq_Hz => 256000) PORT map( clk => clk, reset => rstn,