diff --git a/boards/BeagleSynth/default.ucf b/boards/BeagleSynth/default.ucf --- a/boards/BeagleSynth/default.ucf +++ b/boards/BeagleSynth/default.ucf @@ -1,20 +1,28 @@ -NET "CLK" LOC = "A6" | IOSTANDARD = LVCMOS33; + +NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; +NET "CLK" LOC = "K20"; NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; -NET "RESET" LOC = "AB11" | IOSTANDARD = LVTTL; +NET "RESET" LOC = "AB11"; -NET "DAC_nCLR" LOC = "R11" | IOSTANDARD = LVCMOS33; -NET "DAC_nCS" LOC = "T12" | IOSTANDARD = LVCMOS33; -NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD = LVCMOS33; -NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD = LVCMOS33; +NET "DAC_nCLR" LOC = "R11"; +NET "DAC_nCS" LOC = "T12"; +NET "CAL_IN_SCK" LOC = "R13"; +NET "DAC_SDI(0)" LOC = "P5"; +NET "DAC_SDI(1)" LOC = "M5"; +NET "DAC_SDI(2)" LOC = "C8"; +NET "DAC_SDI(3)" LOC = "M6"; +NET "DAC_SDI(4)" LOC = "K22"; +NET "DAC_SDI(5)" LOC = "L22"; +NET "DAC_SDI(6)" LOC = "G19"; +NET "DAC_SDI(7)" LOC = "F20"; +NET "TDX" LOC = "V22"; +NET "RXD" LOC = "U22"; +NET "LED(0)" LOC = "AB9"; +NET "LED(1)" LOC = "AB8"; +NET "LED(2)" LOC = "AA8"; - +NET "urxd1" LOC = "D3"; # Unused PIN +NET "utxd1" LOC = "C4"; # Unused PIN \ No newline at end of file diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd --- a/designs/BeagleSynth/BeagleSynth.vhd +++ b/designs/BeagleSynth/BeagleSynth.vhd @@ -24,8 +24,7 @@ use work.config.all; --================================================================== -- -- --- FPGA FREQ = 48MHz --- ADC Oscillator frequency = 12MHz +-- FPGA FREQ = 100MHz -- -- --================================================================== @@ -43,11 +42,68 @@ entity BeagleSynth is DAC_nCLR : out std_ulogic; DAC_nCS : out std_ulogic; CAL_IN_SCK : out std_ulogic; - DAC_SDI : out std_ulogic_vector(7 downto 0) + DAC_SDI : out std_ulogic_vector(7 downto 0); + TXD : out std_ulogic; + RXD : in std_ulogic; + urxd1 : in std_ulogic; + utxd1 : out std_ulogic; + LED : out std_ulogic_vector(2 downto 0); +-------------------------------------------------------- +---- SDRAM +---- For SDRAM config have a look on leon3-altera-ep1c20 +---- design from GRLIB, the IS42S32400E is similar to +---- MT48LC4M32B2. +-------------------------------------------------------- + sdcke : out std_logic_vector ( 1 downto 0); -- clk en + sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel + sdwen : out std_logic; -- write en + sdrasn : out std_logic; -- row addr stb + sdcasn : out std_logic; -- col addr stb + sddqm : out std_logic_vector (3 downto 0); -- data i/o mask + sdclk : out std_logic; -- sdram clk output + sdba : out std_logic_vector (3 downto 0); -- bank select address + Address : out std_logic_vector(11 downto 0); -- sdram address + Data : inout std_logic_vector(31 downto 0) -- optional sdram data ); end; architecture rtl of BeagleSynth is +constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ + CFG_GRETH+CFG_AHB_JTAG; +constant maxahbm : integer := maxahbmsp; +constant IOAEN : integer := CFG_CAN; +constant boardfreq : integer := 100000; + +signal clk2x : std_ulogic; +signal lclk : std_ulogic; +signal clkm : std_ulogic; +signal rstn : std_ulogic; +signal rstraw : std_ulogic; +signal pciclk : std_ulogic; +signal sdclkl : std_ulogic; +signal cgi : clkgen_in_type; +signal cgo : clkgen_out_type; + +--- AHB / APB +signal apbi : apb_slv_in_type; +signal apbo : apb_slv_out_vector := (others => apb_none); +signal ahbsi : ahb_slv_in_type; +signal ahbso : ahb_slv_out_vector := (others => ahbs_none); +signal ahbmi : ahb_mst_in_type; +signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); + +--- MEM CTRLR +signal memi : memory_in_type; +signal memo : memory_out_type; +signal sdo : sdram_out_type; + +--UART +signal ahbuarti : uart_in_type; +signal ahbuarto : uart_out_type; +signal apbuarti : uart_in_type; +signal apbuarto : uart_out_type; + +signal led2int : std_logic; begin @@ -56,6 +112,116 @@ DAC_nCS <= '1'; CAL_IN_SCK <= '1'; DAC_SDI <= (others =>'1'); + rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); + + lclk <= clk; + + clkgen0 : clkgen -- clock generatorsa + generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); + + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + dcomgen : if CFG_AHB_UART = 1 generate + dcom0: ahbuart -- Debug UART + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + ahbuarti.rxd <= RXD; + TXD <= ahbuarto.txd; + led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; + end generate; + nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 1, haddr => CFG_APBADDR) + port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + ua1 : if CFG_UART1_ENABLE /= 0 generate + uart1 : apbuart -- UART 1 + generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, + fifosize => CFG_UART1_FIFO) + port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); + apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + end generate; + noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; + + + + +--div0: Clk_divider +-- generic map( 100000000,1) +-- Port map( clkm,rstn,LED(2)); + +LED(2) <= led2int; + +process(clkm,rstn) +begin + if rstn = '0' then + led2int <= '0'; + elsif clkm'event and clkm='1' then + led2int <= not led2int; + end if; +end process; + + + + +mctrl0 : mctrl generic map (srbanks => 4, sden => 1) + port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo); + +-- memory controller inputs not used in this configuration +memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111"; + +memi.sd <= Data; +-- prom width at reset +memi.bwidth <= "10"; +-- I/O pads driving data memory bus data signals +datapads : for i in 0 to 3 generate + data_pad : iopadv generic map (width => 8) + port map ( + pad => data(31-i*8 downto 24-i*8), + o => memi.data(31-i*8 downto 24-i*8), + en => memo.bdrive(i), + i => memo.data(31-i*8 downto 24-i*8) + ); +end generate; +-- connect memory controller outputs to entity output signals +Address <= memo.sa(11 downto 0); +sdba <= memo.sa(13 downto 12); +writen <= memo.writen; read <= memo.read; iosn <= memo.iosn; +sdcke <= sdo.sdcke; +sdwen <= sdo.sdwen; +sdcsn <= sdo.sdcsn; +sdrasn <= sdo.rasn; +sdcasn <= sdo.casn; +sddqm <= sdo.dqm(3 downto 0); + +end; + + end rtl; diff --git a/designs/BeagleSynth/Makefile b/designs/BeagleSynth/Makefile --- a/designs/BeagleSynth/Makefile +++ b/designs/BeagleSynth/Makefile @@ -43,4 +43,4 @@ include $(GRLIB)/software/leon3/Makefile ################## project specific targets ########################## flash: - xc3sprog -c ftdi -p 1 ici4.bit + xc3sprog -c ftdi -p 1 BeagleSynth.bit diff --git a/designs/BeagleSynth/config.vhd b/designs/BeagleSynth/config.vhd --- a/designs/BeagleSynth/config.vhd +++ b/designs/BeagleSynth/config.vhd @@ -19,127 +19,59 @@ package config is constant CFG_FABTECH : integer := spartan6; constant CFG_MEMTECH : integer := spartan6; constant CFG_PADTECH : integer := spartan6; + -- Clock generator constant CFG_CLKTECH : integer := spartan6; - constant SEND_CONSTANT_DATA : integer := 0; - constant SEND_MINF_VALUE : integer := 0; - - + constant CFG_CLKMUL : integer := (2); + constant CFG_CLKDIV : integer := (8); + constant CFG_OCLKDIV : integer := (1); + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; -constant LF1cst : std_logic_vector(15 downto 0) := X"1111"; -constant LF2cst : std_logic_vector(15 downto 0) := X"2222"; -constant LF3cst : std_logic_vector(15 downto 0) := X"3333"; - - -constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001"; -constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111"; -constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF"; - -constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000"; -constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002"; -constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001"; - -constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA"; -constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB"; -constant AMR3Zcst : std_logic_vector(23 downto 0):= X"CCCCCC"; - -constant AMR4Xcst : std_logic_vector(23 downto 0):= X"DDDDDD"; -constant AMR4Ycst : std_logic_vector(23 downto 0):= X"EEEEEE"; -constant AMR4Zcst : std_logic_vector(23 downto 0):= X"FFFFFF"; +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + +-- LEON3 processor core + constant CFG_LEON3 : integer := 0; + constant CFG_NCPU : integer := (0); -constant Temp1cst : std_logic_vector(23 downto 0):= X"121212"; -constant Temp2cst : std_logic_vector(23 downto 0):= X"343434"; -constant Temp3cst : std_logic_vector(23 downto 0):= X"565656"; -constant Temp4cst : std_logic_vector(23 downto 0):= X"787878"; - - - ---===========================================================| ---========F I L T E R C O N F I G V A L U E S=============| ---===========================================================| ---____________________________ ---Bus Width and chanels number| ---____________________________| -constant ChanelsCount : integer := 3; -constant Sample_SZ : integer := 16; -constant Coef_SZ : integer := 9; -constant CoefCntPerCel: integer := 6; -constant CoefPerCel: integer := 5; -constant Cels_count : integer := 5; -constant virgPos : integer := 7; -constant Mem_use : integer := 1; - - - ---============================================================ --- create each initial values for each coefs ============ ---!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! ---============================================================ -constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); -constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ)); -constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); +-- DSU UART + constant CFG_AHB_UART : integer := 1; -constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); -constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ)); -constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); - -constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ)); -constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ)); -constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ)); - -constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); -constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ)); -constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); - -constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); -constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ)); -constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); - ---constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ)); ---constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ)); ---constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ)); - ---constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ)); ---constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ)); ---constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ)); - - -constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); -constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ)); -constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ)); - -constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); -constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ)); -constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ)); - -constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); -constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ)); -constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ)); - -constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); -constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ)); -constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ)); - -constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); -constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ)); -constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ)); - ---constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ)); ---constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); ---constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ)); ---constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ)); ---constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); ---constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ)); - -constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0); - -constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) := - (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 & - a3_1 & a3_2 & b3_0 & b3_1 & b3_2 & - a2_1 & a2_2 & b2_0 & b2_1 & b2_2 & - a1_1 & a1_2 & b1_0 & b1_1 & b1_2 & - a0_1 & a0_2 & b0_0 & b0_1 & b0_2 ); - +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 1; + +-- GRLIB debugging + constant CFG_DUART : integer := 0; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM16BIT : integer := 0; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + +-- CAN 2.0 interface + constant CFG_CAN : integer := 0; end;