diff --git a/Makefile b/Makefile
--- a/Makefile
+++ b/Makefile
@@ -52,6 +52,7 @@ Patch-GRLIB: init doc
 	sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
 
 link:
+	sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
 	sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
 	sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
 
diff --git a/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd
--- a/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd
+++ b/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd
@@ -8,6 +8,8 @@ use lpp.apb_devices_list.all;
 use lpp.general_purpose.all;
 use lpp.Rocket_PCM_Encoder.all;
 
+use work.config.all;
+
 
 entity DC_ACQ_TOP is
 generic(
@@ -15,7 +17,9 @@ generic(
 	WordCnt    : integer := 144;
 	MinFCount  : integer := 64;
 	EnableSR   : integer := 1;
-	FakeADC	  : integer := 0
+	CstDATA    : integer := 0;
+	FakeADC	  : integer := 0;
+	CDS        : integer := 0
 );
 port(
 
@@ -113,65 +117,93 @@ port map(
 --			DC	ADC
 --
 ------------------------------------------------------------------
-ADC : IF FakeADC /=1 GENERATE
-	 
-DC_ADC0 : DUAL_ADS1278_DRIVER                 
-port map(
-    Clk     =>  clk,
-    reset   =>  reset,
-    SpiClk  =>  DC_ADC_Sclk,
-    DIN     =>  DC_ADC_IN,
-    SmplClk =>  DC_ADC_SmplClk,
-    OUT00   =>  AMR1X_Sync,
-    OUT01   =>  AMR1Y_Sync,
-    OUT02   =>  AMR1Z_Sync,
-    OUT03   =>  AMR2X_Sync,
-    OUT04   =>  AMR2Y_Sync,
-    OUT05   =>  AMR2Z_Sync,
-    OUT06   =>  Temp1_Sync,
-    OUT07   =>  Temp2_Sync,
-    OUT10   =>  AMR3X_Sync,
-    OUT11   =>  AMR3Y_Sync,
-    OUT12   =>  AMR3Z_Sync,
-    OUT13   =>  AMR4X_Sync,
-    OUT14   =>  AMR4Y_Sync,
-    OUT15   =>  AMR4Z_Sync,
-    OUT16   =>  Temp3_Sync,
-    OUT17   =>  Temp4_Sync,
-    FSynch  =>  DC_ADC_FSynch
-);
-END GENERATE;
+ADC1: IF CstDATA /= 1 GENERATE
+	ADC : IF FakeADC /=1 GENERATE
+		 
+	DC_ADC0 : DUAL_ADS1278_DRIVER                 
+	port map(
+		 Clk     =>  clk,
+		 reset   =>  reset,
+		 SpiClk  =>  DC_ADC_Sclk,
+		 DIN     =>  DC_ADC_IN,
+		 SmplClk =>  DC_ADC_SmplClk,
+		 OUT00   =>  AMR1X_Sync,
+		 OUT01   =>  AMR1Y_Sync,
+		 OUT02   =>  AMR1Z_Sync,
+		 OUT03   =>  AMR2X_Sync,
+		 OUT04   =>  AMR2Y_Sync,
+		 OUT05   =>  AMR2Z_Sync,
+		 OUT06   =>  Temp1_Sync,
+		 OUT07   =>  Temp2_Sync,
+		 OUT10   =>  AMR3X_Sync,
+		 OUT11   =>  AMR3Y_Sync,
+		 OUT12   =>  AMR3Z_Sync,
+		 OUT13   =>  AMR4X_Sync,
+		 OUT14   =>  AMR4Y_Sync,
+		 OUT15   =>  AMR4Z_Sync,
+		 OUT16   =>  Temp3_Sync,
+		 OUT17   =>  Temp4_Sync,
+		 FSynch  =>  DC_ADC_FSynch
+	);
+	END GENERATE;
 
-NOADC: IF FakeADC=1 GENERATE
-	 
-DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER                 
-port map(
-    Clk     =>  clk,
-    reset   =>  reset,
-    SpiClk  =>  DC_ADC_Sclk,
-    DIN     =>  DC_ADC_IN,
-    SmplClk =>  DC_ADC_SmplClk,
-    OUT00   =>  AMR1X_Sync,
-    OUT01   =>  AMR1Y_Sync,
-    OUT02   =>  AMR1Z_Sync,
-    OUT03   =>  AMR2X_Sync,
-    OUT04   =>  AMR2Y_Sync,
-    OUT05   =>  AMR2Z_Sync,
-    OUT06   =>  Temp1_Sync,
-    OUT07   =>  Temp2_Sync,
-    OUT10   =>  AMR3X_Sync,
-    OUT11   =>  AMR3Y_Sync,
-    OUT12   =>  AMR3Z_Sync,
-    OUT13   =>  AMR4X_Sync,
-    OUT14   =>  AMR4Y_Sync,
-    OUT15   =>  AMR4Z_Sync,
-    OUT16   =>  Temp3_Sync,
-    OUT17   =>  Temp4_Sync,
-    FSynch  =>  DC_ADC_FSynch
-);
+	NOADC: IF FakeADC=1 GENERATE
+		 
+	DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER                 
+	port map(
+		 Clk     =>  clk,
+		 reset   =>  reset,
+		 SpiClk  =>  DC_ADC_Sclk,
+		 DIN     =>  DC_ADC_IN,
+		 SmplClk =>  DC_ADC_SmplClk,
+		 OUT00   =>  AMR1X_Sync,
+		 OUT01   =>  AMR1Y_Sync,
+		 OUT02   =>  AMR1Z_Sync,
+		 OUT03   =>  AMR2X_Sync,
+		 OUT04   =>  AMR2Y_Sync,
+		 OUT05   =>  AMR2Z_Sync,
+		 OUT06   =>  Temp1_Sync,
+		 OUT07   =>  Temp2_Sync,
+		 OUT10   =>  AMR3X_Sync,
+		 OUT11   =>  AMR3Y_Sync,
+		 OUT12   =>  AMR3Z_Sync,
+		 OUT13   =>  AMR4X_Sync,
+		 OUT14   =>  AMR4Y_Sync,
+		 OUT15   =>  AMR4Z_Sync,
+		 OUT16   =>  Temp3_Sync,
+		 OUT17   =>  Temp4_Sync,
+		 FSynch  =>  DC_ADC_FSynch
+	);
+	END GENERATE;
+
 END GENERATE;
 ------------------------------------------------------------------
 
+NOADC: IF CstDATA = 1 GENERATE
+
+AMR1X_Sync  <=  AMR1Xcst;
+AMR1Y_Sync  <=  AMR1Ycst;
+AMR1Z_Sync  <=  AMR1Zcst;
+AMR2X_Sync  <=  AMR2Xcst;
+AMR2Y_Sync  <=  AMR2Ycst;
+AMR2Z_Sync  <=  AMR2Zcst;
+Temp1_Sync  <=  Temp1cst;
+Temp2_Sync  <=  Temp2cst;
+AMR3X_Sync  <=  AMR3Xcst;
+AMR3Y_Sync  <=  AMR3Ycst;
+AMR3Z_Sync  <=  AMR3Zcst;
+AMR4X_Sync  <=  AMR4Xcst;
+AMR4Y_Sync  <=  AMR4Ycst;
+AMR4Z_Sync  <=  AMR4Zcst;
+Temp3_Sync  <=  Temp3cst;
+Temp4_Sync  <=  Temp4cst;
+
+
+
+
+
+END GENERATE;
+
 
 
 
@@ -214,7 +246,7 @@ SET_RESET1  <= SET_RESET1_sig;
 --
 ------------------------------------------------------------------
 
-
+IF CDS =1 GENERATE
 
 AMR1Xsync: entity work.Fast2SlowSync
 generic map(N	=> 24)
@@ -271,6 +303,29 @@ TEMP4sync: entity work.Fast2SlowSync
 generic map(N	=> 24)
 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
 
+END GENERATE;
+
+IF CDS /= 1 GENERATE
+
+
+AMR1X_Sync  <=  AMR1X;
+AMR1Y_Sync  <=  AMR1Y;
+AMR1Z_Sync  <=  AMR1Z;
+AMR2X_Sync  <=  AMR2X;
+AMR2Y_Sync  <=  AMR2Y;
+AMR2Z_Sync  <=  AMR2Z;
+Temp1_Sync  <=  Temp1;
+Temp2_Sync  <=  Temp2;
+AMR3X_Sync  <=  AMR3X;
+AMR3Y_Sync  <=  AMR3Y;
+AMR3Z_Sync  <=  AMR3Z;
+AMR4X_Sync  <=  AMR4X;
+AMR4Y_Sync  <=  AMR4Y;
+AMR4Z_Sync  <=  AMR4Z;
+Temp3_Sync  <=  Temp3;
+Temp4_Sync  <=  Temp4;
+
+END GENERATE;
 ------------------------------------------------------------------
 
 
diff --git a/designs/ICI4-Integ1/ICI4HDL/IIR_FILTER_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/IIR_FILTER_TOP.vhd
new file mode 100644
--- /dev/null
+++ b/designs/ICI4-Integ1/ICI4HDL/IIR_FILTER_TOP.vhd
@@ -0,0 +1,143 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library lpp;
+use lpp.lpp_ad_conv.all;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+use lpp.general_purpose.all;
+use lpp.Rocket_PCM_Encoder.all;
+use lpp.iir_filter.all;
+use work.config.all;
+
+
+entity IIR_FILTER_TOP is
+generic
+(
+	V2	:	integer :=0		-- IF 1 uses V2 else use V1
+);
+port
+(
+    rstn : IN STD_LOGIC;
+    clk  : IN STD_LOGIC;
+
+    SMPclk : IN STD_LOGIC;
+    LF1_IN : IN std_logic_vector(15 downto 0);
+    LF2_IN : IN std_logic_vector(15 downto 0);
+    LF3_IN : IN std_logic_vector(15 downto 0);
+
+    SMPCLKOut : OUT STD_LOGIC;
+    LF1_OUT : OUT std_logic_vector(15 downto 0);
+    LF2_OUT : OUT std_logic_vector(15 downto 0);
+    LF3_OUT : OUT std_logic_vector(15 downto 0)
+);
+end IIR_FILTER_TOP;
+
+architecture AR_IIR_FILTER_TOP of IIR_FILTER_TOP is
+signal	sps	    		:	Samples(2 DOWNTO 0);
+
+signal	LFX   			:	Samples(2 DOWNTO 0);
+signal   Filter_sp_in   :  samplT(2 DOWNTO 0, 15 DOWNTO 0);
+signal   Filter_sp_out  :  samplT(2 DOWNTO 0, 15 DOWNTO 0);
+signal   sample_out_val :  std_logic;
+signal	LF_ADC_SpPulse	:	std_logic;
+
+begin
+
+sps(0)   <= LF1_IN;
+sps(1)   <= LF2_IN;
+sps(2)   <= LF3_IN;
+
+LF1_OUT	<= LFX(0);
+LF2_OUT	<=	LFX(1);
+LF3_OUT	<=	LFX(2);
+
+SMPCLKOut	<= sample_out_val;
+
+loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
+
+ loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
+		process(rstn,clk)
+		begin
+			if rstn ='0' then
+				Filter_sp_in(I,J)	<=	'0';
+--					LFX(I)					<=	(others => '0');
+			elsif clk'event and clk ='1' then
+				if sample_out_val = '1' then
+					LFX(I)(J)	<=	Filter_sp_out(I,J);
+					Filter_sp_in(I,J)	<=	sps(I)(J);
+				end if;
+			end if;
+		end process;
+	END GENERATE;
+END GENERATE;
+
+V2FILTER: IF V2 = 1 GENERATE
+
+smpPulse: entity work.OneShot 
+    Port map( 
+	 reset  => rstn,
+    clk    => clk,
+    input  => SMPclk,
+    output => LF_ADC_SpPulse
+);
+
+FilterV2: IIR_CEL_CTRLR_v2 
+  GENERIC map(
+    tech          => CFG_MEMTECH,
+    Mem_use       => use_RAM,
+    Sample_SZ     => Sample_SZ,
+    Coef_SZ       => Coef_SZ,
+    Coef_Nb       => 25,
+    Coef_sel_SZ   => 5,
+    Cels_count    => 5,
+    ChanelsCount  => ChanelsCount
+	 )
+  PORT map(
+    rstn => rstn,
+    clk  => clk,
+
+    virg_pos => virgPos,
+    coefs    => CoefsInitValCst_v2,
+
+    sample_in_val => LF_ADC_SpPulse,
+    sample_in     => Filter_sp_in,
+
+    sample_out_val => sample_out_val,
+    sample_out     => Filter_sp_out
+);
+
+	
+
+END GENERATE;
+
+V1FILTER: IF V2 /= 1 GENERATE
+
+sample_out_val	<= SMPclk;
+
+
+FilterV1: IIR_CEL_CTRLR 
+generic map(
+        tech 			=> CFG_MEMTECH,
+        Sample_SZ 	=> Sample_SZ,
+		  ChanelsCount => 3,
+		  Coef_SZ      => Coef_SZ,
+		  CoefCntPerCel=> CoefCntPerCel,
+		  Cels_count   => Cels_count,
+        Mem_use      => use_RAM
+)
+port map(
+    reset       => rstn,
+    clk         => clk,
+    sample_clk  => SMPclk,
+    sample_in   => Filter_sp_in,
+    sample_out  => Filter_sp_out,
+    virg_pos    => virgPos,
+    GOtest      => open,
+    coefs       => CoefsInitValCst
+);
+	
+END GENERATE;
+
+
+end AR_IIR_FILTER_TOP;
+
diff --git a/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd
--- a/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd
+++ b/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd
@@ -15,7 +15,7 @@ generic(
 	WordCnt     : integer := 144;
 	MinFCount   : integer := 64;
 	CstDATA     : integer := 0;
-	IIRFilter   : integer := 1
+	IIRFilter   : integer := 0
 );
 port(
 
@@ -53,6 +53,10 @@ signal   Filter_sp_in   :  samplT(2 DOWN
 signal   Filter_sp_out  :  samplT(2 DOWNTO 0, 15 DOWNTO 0);
 signal   sample_out_val :  std_logic;
 
+signal   LF1_sync   	:     std_logic_vector(15 downto 0);
+signal   LF2_sync   	:     std_logic_vector(15 downto 0);
+signal   LF3_sync   	:     std_logic_vector(15 downto 0);
+
 begin
 
 
@@ -101,70 +105,49 @@ smpPulse: entity work.OneShot
 
 
 
-Filter: IIR_CEL_CTRLR_v2 
-  GENERIC map(
-    tech          => CFG_MEMTECH,
-    Mem_use       => use_RAM,
-    Sample_SZ     => Sample_SZ,
-    Coef_SZ       => Coef_SZ,
-    Coef_Nb       => 25,
-    Coef_sel_SZ   => 5,
-    Cels_count    => 5,
-    ChanelsCount  => ChanelsCount
-	 )
-  PORT map(
-    rstn => reset,
-    clk  => clk,
-
-    virg_pos => virgPos,
-    coefs    => CoefsInitValCst_v2,
-
-    sample_in_val => LF_ADC_SpPulse,
-    sample_in     => Filter_sp_in,
-
-    sample_out_val => sample_out_val,
-    sample_out     => Filter_sp_out
-);
 
 NOfilt:	IF IIRFilter = 0 GENERATE
 		process(reset,clk)
 		begin
 			if reset ='0' then
-				LF1	<=	(others => '0');
-				LF2	<=	(others => '0');
-				LF3	<=	(others => '0');
+				LF1_sync	<=	(others => '0');
+				LF2_sync	<=	(others => '0');
+				LF3_sync	<=	(others => '0');
 			elsif clk'event and clk ='1' then
 				if sample_val = '1' then
-					LF1	<=	sps(0);
-					LF2	<=	sps(1);
-					LF3	<=	sps(2);
+					LF1_sync	<=	sps(0);
+					LF2_sync	<=	sps(1);
+					LF3_sync	<=	sps(2);
 				end if;
 			end if;
 		end process;
 	END GENERATE;
+	
+	
 filt:	IF IIRFilter /= 0 GENERATE
 
-	LF1	<= LFX(0);
-	LF2	<=	LFX(1);
-	LF3	<=	LFX(2);
 
-  loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
+filtertop: entity work.IIR_FILTER_TOP 
+generic map
+(
+	V2	=> 0
+)
+port map
+(
+    rstn 	=> reset,
+    clk  	=> clk,
 
-    loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
-			process(reset,clk)
-			begin
-				if reset ='0' then
-					Filter_sp_in(I,J)	<=	'0';
---					LFX(I)					<=	(others => '0');
-				elsif clk'event and clk ='1' then
-					if sample_out_val = '1' then
-						LFX(I)(J)	<=	Filter_sp_out(I,J);
-						Filter_sp_in(I,J)	<=	sps(I)(J);
-					end if;
-				end if;
-			end process;
-		END GENERATE;
-	END GENERATE;
+    SMPclk  => LF_ADC_SmplClk,
+    LF1_IN  => sps(0),
+    LF2_IN  => sps(1),
+    LF3_IN  => sps(2),
+
+    SMPCLKOut => open,
+    LF1_OUT   => LF1_sync,
+    LF2_OUT   => LF2_sync,
+    LF3_OUT   => LF3_sync
+);
+
 END GENERATE;
 
 
@@ -174,14 +157,25 @@ END GENERATE;
 
 CST: IF CstDATA /=0 GENERATE
 
-	LF1	<=	LF1cst;
-	LF2	<=	LF2cst;
-	LF3	<=	LF3cst;
+	LF1_sync	<=	LF1cst;
+	LF2_sync	<=	LF2cst;
+	LF3_sync	<=	LF3cst;
 
 END GENERATE;
 
 
 
+LF1sync: entity work.Fast2SlowSync
+generic map(N	=> 16)
+port map( LF1_sync,clk,sclk,SyncSig,LF1);
+
+LF2sync: entity work.Fast2SlowSync
+generic map(N	=> 16)
+port map( LF2_sync,clk,sclk,SyncSig,LF2);
+
+LF3sync: entity work.Fast2SlowSync
+generic map(N	=> 16)
+port map( LF3_sync,clk,sclk,SyncSig,LF3);
 
 --Filter: IIR_CEL_FILTER 
 --    GENERIC map(
diff --git a/designs/ICI4-Integ1/Makefile b/designs/ICI4-Integ1/Makefile
--- a/designs/ICI4-Integ1/Makefile
+++ b/designs/ICI4-Integ1/Makefile
@@ -27,7 +27,8 @@ VHDLOPTSYNFILES= \
                  ICI4HDL/DC_ACQ_TOP.vhd \
                  ICI4HDL/LF_ACQ_TOP.vhd \
            	 ICI4HDL/FAKE_ADC.vhd \
-                 ICI4HDL/OneShot.vhd
+                 ICI4HDL/OneShot.vhd \
+                 ICI4HDL/IIR_FILTER_TOP.vhd
 
 
 VHDLSYNFILES= \
diff --git a/designs/ICI4-Integ1/ici4.vhd b/designs/ICI4-Integ1/ici4.vhd
--- a/designs/ICI4-Integ1/ici4.vhd
+++ b/designs/ICI4-Integ1/ici4.vhd
@@ -172,7 +172,8 @@ generic map (
 	WordCnt   => WordCnt,
 	MinFCount => MinFCount,
 	EnableSR  => 0,
-	FakeADC	 => 1
+	CstDATA   => SEND_CONSTANT_DATA,
+	FakeADC	 => 0
 )
 port map(
 
@@ -219,7 +220,8 @@ generic map(
 	WordSize  => WordSize,
 	WordCnt   => WordCnt,
 	MinFCount => MinFCount,
-	CstDATA   => 0
+	CstDATA   => SEND_CONSTANT_DATA,
+	IIRFilter => 0
 )
 port map(
 
diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
--- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
+++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
@@ -137,7 +137,7 @@ port map(
 
 
 
-ALU_inst :ALU
+ALU_inst : ALU_V0
 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
 port map(
     clk     =>  clk,
@@ -178,7 +178,7 @@ if reset = '0' then
 
     smpl_clk_old    <=  '0';
     RAM_sample_in   <=  (others=> '0');
-    ALU_ctrl        <=  IDLE;
+    ALU_ctrl        <=  IDLE_V0;
     ALU_sample_in   <=  (others=> '0');
     ALU_Coef_in     <=  (others=> '0');
     RAM_sample_in_bk<=  (others=> '0');
@@ -206,7 +206,7 @@ elsif clk'event and clk = '1' then
                 ALU_sample_in   <=  std_logic_vector(sample_in_BUFF(0));
                 
             else
-                ALU_ctrl        <=  IDLE; 
+                ALU_ctrl        <=  IDLE_V0; 
                 smplConnectL0: for i in 0 to ChanelsCount-1 loop
                     smplConnectL1: for j in 0 to Sample_SZ-1 loop
 						      sample_in_BUFF(i)(j)  <=  sample_in(i,j);
@@ -219,12 +219,12 @@ elsif clk'event and clk = '1' then
 
         when pipe1 =>
                 IIR_CEL_STATE   <=  computeb1;
-                ALU_ctrl        <=  MAC_op;
+                ALU_ctrl        <=  MAC_op_V0;
                 ALU_Coef_in     <=  std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
 
         when computeb1 =>
             
-            ALU_ctrl        <=  MAC_op;
+            ALU_ctrl        <=  MAC_op_V0;
             ALU_sample_in   <=  RAM_sample_out;
             ALU_Coef_in     <=  std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
             IIR_CEL_STATE   <=  computeb2;
@@ -248,7 +248,7 @@ elsif clk'event and clk = '1' then
             
 
         when next_cel =>
-            ALU_ctrl        <=  clr_mac;
+            ALU_ctrl        <=  clr_mac_V0;
             IIR_CEL_STATE   <=  pipe2;            
 
         when pipe2 =>
@@ -281,7 +281,7 @@ rotate :    for i in 1 to ChanelsCount-1
                 
             if curentChan   = (ChanelsCount-1) then
                 IIR_CEL_STATE   <=  waiting;
-                ALU_ctrl        <=  clr_mac;
+                ALU_ctrl        <=  clr_mac_V0;
             elsif ChanelsCount>1 then
                 curentChan       <=  curentChan + 1;
                 IIR_CEL_STATE    <=  pipe1;
diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt
--- a/lib/lpp/dsp/iir_filter/vhdlsyn.txt
+++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt
@@ -1,19 +1,19 @@
 APB_IIR_CEL.vhd
 APB_IIR_Filter.vhd
-FILTER.vhd
-FILTER_RAM_CTRLR.vhd
 FILTERcfg.vhd
 FilterCTRLR.vhd
-IIR_CEL_CTRLR.vhd
-IIR_CEL_CTRLR_v2.vhd
+FILTER_RAM_CTRLR.vhd
+FILTER.vhd
 IIR_CEL_CTRLR_v2_CONTROL.vhd
 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
+IIR_CEL_CTRLR_v2.vhd
+IIR_CEL_CTRLR.vhd
 IIR_CEL_FILTER.vhd
-RAM.vhd
+iir_filter.vhd
+RAM_CEL_N.vhd
 RAM_CEL.vhd
-RAM_CEL_N.vhd
 RAM_CTRLR2.vhd
 RAM_CTRLR_v2.vhd
+RAM.vhd
 Top_Filtre_IIR.vhd
 Top_IIR.vhd
-iir_filter.vhd
diff --git a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt
--- a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt
+++ b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt
@@ -1,10 +1,10 @@
+APB_FFT_half.vhd
 APB_FFT.vhd
-APB_FFT_half.vhd
 Driver_FFT.vhd
+FFTamont.vhd
+FFTaval.vhd
 FFT.vhd
 FFT.vhd.bak
-FFTamont.vhd
-FFTaval.vhd
 Flag_Extremum.vhd
 Flag_Extremum.vhd.bak
 Linker_FFT.vhd
diff --git a/lib/lpp/general_purpose/ALU_V0.vhd b/lib/lpp/general_purpose/ALU_V0.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/ALU_V0.vhd
@@ -0,0 +1,65 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+-------------------------------------------------------------------------------
+--                    Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+----------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+LIBRARY lpp;
+USE lpp.general_purpose.ALL;
+--IDLE                  = 0000
+--MAC                   = 0001
+--MULT                  = 0010 and set MULT in ADD reg
+--ADD                   = 0011
+--CLRMAC                = 0100
+
+
+ENTITY ALU_V0 IS
+  GENERIC(
+    Arith_en   : INTEGER := 1;
+    Logic_en   : INTEGER := 1;
+    Input_SZ_1 : INTEGER := 16;
+    Input_SZ_2 : INTEGER := 9
+
+    );
+  PORT(
+    clk   : IN  STD_LOGIC;
+    reset : IN  STD_LOGIC;
+    ctrl  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
+    OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
+    RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
+    );
+END ENTITY;
+
+ARCHITECTURE ar_ALU OF ALU_V0 IS
+
+  SIGNAL clr_MAC : STD_LOGIC := '1';
+
+BEGIN
+  clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110"  ELSE '0';
+
+  arith : IF Arith_en = 1 GENERATE
+    MACinst : MAC_V0
+      GENERIC MAP(Input_SZ_1, Input_SZ_2)
+      PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
+  END GENERATE;
+
+END ARCHITECTURE;
diff --git a/lib/lpp/general_purpose/Adder_V0.vhd b/lib/lpp/general_purpose/Adder_V0.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/Adder_V0.vhd
@@ -0,0 +1,72 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+-------------------------------------------------------------------------------
+--                    Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+----------------------------------------------------------------------------
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity Adder_V0 is
+generic(
+    Input_SZ_A     :   integer := 16;
+    Input_SZ_B     :   integer := 16
+
+);
+port(
+    clk     :   in  std_logic;
+    reset   :   in  std_logic;
+    clr     :   in  std_logic;
+    add     :   in  std_logic;
+    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
+    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
+    RES     :   out std_logic_vector(Input_SZ_A-1 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_Adder of Adder_V0 is
+
+signal  REG     :   std_logic_vector(Input_SZ_A-1 downto 0);
+signal  RESADD  :   std_logic_vector(Input_SZ_A-1 downto 0);
+
+begin
+
+RES     <=  REG;
+RESADD  <=  std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
+
+process(clk,reset)
+begin
+if reset = '0' then
+    REG     <=  (others => '0');
+elsif clk'event and clk ='1' then
+    if clr = '1' then
+        REG     <=  (others => '0');
+    elsif add = '1' then
+        REG     <=  RESADD;
+    end if;
+end if;
+end process;
+end ar_Adder;
diff --git a/lib/lpp/general_purpose/MAC_V0.vhd b/lib/lpp/general_purpose/MAC_V0.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MAC_V0.vhd
@@ -0,0 +1,262 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+--TODO
+--terminer le testbensh puis changer le resize dans les instanciations
+--par un resize sur un vecteur en combi
+
+
+
+
+
+entity MAC_V0 is
+generic(
+    Input_SZ_A     :   integer := 8;
+    Input_SZ_B     :   integer := 8
+
+);
+port(
+    clk     :   in  std_logic;
+    reset   :   in  std_logic;
+    clr_MAC :   in  std_logic;
+    MAC_MUL_ADD :   in  std_logic_vector(1 downto 0);
+    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
+    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
+    RES     :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
+);
+end MAC_V0;
+
+
+
+
+architecture ar_MAC of MAC_V0 is
+
+
+
+
+
+signal  add,mult    :   std_logic;
+signal  MULTout     :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+signal  ADDERinA    :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal  ADDERinB    :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal  ADDERout    :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+
+signal  MACMUXsel   :   std_logic;
+signal  OP1_D_Resz  :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal  OP2_D_Resz  :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+
+
+signal  MACMUX2sel  :   std_logic;
+
+signal  add_D           :   std_logic;
+signal  OP1_D           :   std_logic_vector(Input_SZ_A-1 downto 0);
+signal  OP2_D           :   std_logic_vector(Input_SZ_B-1 downto 0);
+signal  MULTout_D       :   std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal  MACMUXsel_D     :   std_logic;
+signal  MACMUX2sel_D    :   std_logic;
+signal  MACMUX2sel_D_D  :   std_logic;
+signal  clr_MAC_D       :   std_logic;
+signal  clr_MAC_D_D     :   std_logic;
+
+
+
+
+
+begin
+
+
+
+
+--==============================================================
+--=============M A C  C O N T R O L E R=========================
+--==============================================================
+MAC_CONTROLER1 : MAC_CONTROLER
+port map(
+    ctrl        =>  MAC_MUL_ADD,
+    MULT        =>  mult,
+    ADD         =>  add,
+    MACMUX_sel  =>  MACMUXsel,
+    MACMUX2_sel =>  MACMUX2sel
+
+);
+--==============================================================
+
+
+
+
+--==============================================================
+--=============M U L T I P L I E R==============================
+--==============================================================
+Multiplieri_nst : Multiplier
+generic map(
+    Input_SZ_A     =>   Input_SZ_A,
+    Input_SZ_B     =>   Input_SZ_B
+)
+port map(
+    clk         =>  clk,
+    reset       =>  reset,
+    mult        =>  mult,
+    OP1         =>  OP1,
+    OP2         =>  OP2,
+    RES         =>  MULTout
+);
+
+--==============================================================
+
+
+
+
+--==============================================================
+--======================A D D E R ==============================
+--==============================================================
+adder_inst : Adder_V0
+generic map(
+    Input_SZ_A     =>   Input_SZ_A+Input_SZ_B,
+    Input_SZ_B     =>   Input_SZ_A+Input_SZ_B
+)
+port map(
+    clk         =>  clk,
+    reset       =>  reset,
+    clr         =>  clr_MAC_D,
+    add         =>  add_D,
+    OP1         =>  ADDERinA,
+    OP2         =>  ADDERinB,
+    RES         =>  ADDERout
+);
+
+--==============================================================
+
+
+clr_MACREG1 : MAC_REG
+generic map(size    =>  1)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D(0)    =>  clr_MAC,
+    Q(0)    =>  clr_MAC_D
+);
+
+clr_MACREG2 : MAC_REG
+generic map(size    =>  1)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D(0)    =>  clr_MAC_D,
+    Q(0)    =>  clr_MAC_D_D
+);
+
+addREG : MAC_REG
+generic map(size    =>  1)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D(0)    =>  add,
+    Q(0)    =>  add_D
+);
+
+OP1REG : MAC_REG
+generic map(size    =>  Input_SZ_A)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D       =>  OP1,
+    Q       =>  OP1_D
+);
+
+
+OP2REG : MAC_REG
+generic map(size    =>  Input_SZ_B)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D       =>  OP2,
+    Q       =>  OP2_D
+);
+
+
+MULToutREG : MAC_REG
+generic map(size    =>  Input_SZ_A+Input_SZ_B)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D       =>  MULTout,
+    Q       =>  MULTout_D
+);
+
+
+MACMUXselREG : MAC_REG
+generic map(size    =>  1)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D(0)    =>  MACMUXsel,
+    Q(0)    =>  MACMUXsel_D
+);
+
+MACMUX2selREG : MAC_REG
+generic map(size    =>  1)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D(0)    =>  MACMUX2sel,
+    Q(0)    =>  MACMUX2sel_D
+);
+
+MACMUX2selREG2 : MAC_REG
+generic map(size    =>  1)
+port map(
+    reset   =>  reset,
+    clk     =>  clk,
+    D(0)    =>  MACMUX2sel_D,
+    Q(0)    =>  MACMUX2sel_D_D
+);
+
+--==============================================================
+--======================M A C  M U X ===========================
+--==============================================================
+MACMUX_inst : MAC_MUX
+generic map(
+    Input_SZ_A     =>   Input_SZ_A+Input_SZ_B,
+    Input_SZ_B     =>   Input_SZ_A+Input_SZ_B
+
+)
+port map(
+    sel         =>  MACMUXsel_D,
+    INA1        =>  ADDERout,
+    INA2        =>  OP2_D_Resz,
+    INB1        =>  MULTout,
+    INB2        =>  OP1_D_Resz,
+    OUTA        =>  ADDERinA,
+    OUTB        =>  ADDERinB
+);
+OP1_D_Resz  <=  std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
+OP2_D_Resz  <=  std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
+--==============================================================
+
+
+--==============================================================
+--======================M A C  M U X2 ==========================
+--==============================================================
+MAC_MUX2_inst   : MAC_MUX2
+generic map(Input_SZ     => Input_SZ_A+Input_SZ_B)
+port map(
+    sel     =>  MACMUX2sel_D_D,
+    RES2    =>  MULTout_D,
+    RES1    =>  ADDERout,
+    RES     =>  RES
+);
+
+
+--==============================================================
+
+end ar_MAC;
diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd
--- a/lib/lpp/general_purpose/general_purpose.vhd
+++ b/lib/lpp/general_purpose/general_purpose.vhd
@@ -68,6 +68,23 @@ PACKAGE general_purpose IS
       );
   END COMPONENT;
 
+COMPONENT Adder_V0 is
+generic(
+    Input_SZ_A     :   integer := 16;
+    Input_SZ_B     :   integer := 16
+
+);
+port(
+    clk     :   in  std_logic;
+    reset   :   in  std_logic;
+    clr     :   in  std_logic;
+    add     :   in  std_logic;
+    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
+    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
+    RES     :   out std_logic_vector(Input_SZ_A-1 downto 0)
+);
+end COMPONENT;
+
   COMPONENT ADDRcntr IS
     PORT(
       clk   : IN  STD_LOGIC;
@@ -98,14 +115,56 @@ PACKAGE general_purpose IS
       );
   END COMPONENT;
 
+COMPONENT ALU_V0 IS
+  GENERIC(
+    Arith_en   : INTEGER := 1;
+    Logic_en   : INTEGER := 1;
+    Input_SZ_1 : INTEGER := 16;
+    Input_SZ_2 : INTEGER := 9
+
+    );
+  PORT(
+    clk   : IN  STD_LOGIC;
+    reset : IN  STD_LOGIC;
+    ctrl  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
+    OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
+    RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
+    );
+END COMPONENT;
+
+COMPONENT MAC_V0 is
+generic(
+    Input_SZ_A     :   integer := 8;
+    Input_SZ_B     :   integer := 8
+
+);
+port(
+    clk     :   in  std_logic;
+    reset   :   in  std_logic;
+    clr_MAC :   in  std_logic;
+    MAC_MUL_ADD :   in  std_logic_vector(1 downto 0);
+    OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
+    OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
+    RES     :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
+);
+end COMPONENT;
+
 ---------------------------------------------------------
--------- // Sélection grace a l'entrée "ctrl" \\ --------
+-------- // Sélection grace a l'entrée "ctrl" \\ --------
 ---------------------------------------------------------
 Constant ctrl_IDLE   : std_logic_vector(2 downto 0) := "000";
 Constant ctrl_MAC    : std_logic_vector(2 downto 0) := "001";
 Constant ctrl_MULT   : std_logic_vector(2 downto 0) := "010";
 Constant ctrl_ADD    : std_logic_vector(2 downto 0) := "011";
 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
+
+
+Constant IDLE_V0    : std_logic_vector(3 downto 0) := "0000";
+Constant MAC_op_V0  : std_logic_vector(3 downto 0) := "0001";
+Constant MULT_V0    : std_logic_vector(3 downto 0) := "0010";
+Constant ADD_V0     : std_logic_vector(3 downto 0) := "0011";
+Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
 ---------------------------------------------------------
 
   COMPONENT MAC IS
@@ -132,10 +191,10 @@ Constant ctrl_CLRMAC : std_logic_vector(
   port(
       clk     : in  std_logic;                                --! Horloge du composant
       reset   : in  std_logic;                                --! Reset general du composant
-      clr     : in  std_logic;                                --! Un reset spécifique au programme
-      TwoComp : in  std_logic;                                --! Autorise l'utilisation du complément
-      OP      : in  std_logic_vector(Input_SZ-1 downto 0);    --! Opérande d'entrée
-      RES     : out std_logic_vector(Input_SZ-1 downto 0)     --! Résultat, opérande complémenté ou non
+      clr     : in  std_logic;                                --! Un reset spécifique au programme
+      TwoComp : in  std_logic;                                --! Autorise l'utilisation du complément
+      OP      : in  std_logic_vector(Input_SZ-1 downto 0);    --! Opérande d'entrée
+      RES     : out std_logic_vector(Input_SZ-1 downto 0)     --! Résultat, opérande complémenté ou non
   );
   end COMPONENT;
 
diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt
--- a/lib/lpp/general_purpose/vhdlsyn.txt
+++ b/lib/lpp/general_purpose/vhdlsyn.txt
@@ -1,18 +1,24 @@
+Adder_V0.vhd
+Adder.vhd
 ADDRcntr.vhd
+ALU_V0.vhd
+ALU_V0.vhd~
 ALU.vhd
-Adder.vhd
 Clk_Divider2.vhd
+Clk_Divider2.vhd~
 Clk_divider.vhd
-MAC.vhd
+general_purpose.vhd
+general_purpose.vhd~
 MAC_CONTROLER.vhd
+MAC_MUX2.vhd
 MAC_MUX.vhd
-MAC_MUX2.vhd
 MAC_REG.vhd
+MAC_V0.vhd
+MAC.vhd
+Multiplier.vhd
 MUX2.vhd
 MUXN.vhd
-Multiplier.vhd
 REG.vhd
+Shifter.vhd
 SYNC_FF.vhd
-Shifter.vhd
 TwoComplementer.vhd
-general_purpose.vhd
diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd
deleted file mode 100644
--- a/lib/lpp/leon3mp.vhd
+++ /dev/null
@@ -1,703 +0,0 @@
------------------------------------------------------------------------------
---  LEON3 Demonstration design
---  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 2 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-------------------------------------------------------------------------------
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-library techmap;
-use techmap.gencomp.all;
-library gaisler;
-use gaisler.memctrl.all;
-use gaisler.leon3.all;
-use gaisler.uart.all;
-use gaisler.misc.all;
-library esa;
-use esa.memoryctrl.all;
-use work.config.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.lpp_memory.all;
-use lpp.lpp_uart.all;
-use lpp.lpp_matrix.all;
-use lpp.lpp_delay.all;
-use lpp.lpp_fft.all;
-use lpp.fft_components.all;
-use lpp.lpp_ad_conv.all;
-use lpp.iir_filter.all;
-use lpp.general_purpose.all;
-use lpp.Filtercfg.all;
-use lpp.lpp_demux.all;
-use lpp.lpp_top_lfr_pkg.all;
-use lpp.lpp_dma_pkg.all;
-use lpp.lpp_Header.all;
-
-entity leon3mp is
-  generic (
-    fabtech   : integer := CFG_FABTECH;
-    memtech   : integer := CFG_MEMTECH;
-    padtech   : integer := CFG_PADTECH;
-    clktech   : integer := CFG_CLKTECH;
-    disas     : integer := CFG_DISAS;	-- Enable disassembly to console
-    dbguart   : integer := CFG_DUART;	-- Print UART on console
-    pclow     : integer := CFG_PCLOW
-  );
-  port (
-    clk50MHz    : in  std_ulogic;
-    reset	    : in  std_ulogic;
-    ramclk 	    : out std_logic;    
-
-    ahbrxd  : in  std_ulogic;  			-- DSU rx data  
-    ahbtxd  : out std_ulogic; 			-- DSU tx data
-    dsubre  : in std_ulogic;
-    dsuact  : out std_ulogic;
-    urxd1  : in  std_ulogic;  			-- UART1 rx data
-    utxd1  : out std_ulogic; 			-- UART1 tx data
-    errorn	: out std_ulogic;     
-
-    address : out std_logic_vector(18 downto 0);
-    data	: inout std_logic_vector(31 downto 0);
-    gpio    : inout std_logic_vector(6 downto 0); 	-- I/O port    
-
-    nBWa        : out std_logic;
-    nBWb        : out std_logic;
-    nBWc        : out std_logic;
-    nBWd        : out std_logic;
-    nBWE        : out std_logic;
-    nADSC       : out std_logic;
-    nADSP       : out std_logic;
-    nADV        : out std_logic;
-    nGW         : out std_logic;
-    nCE1        : out std_logic;
-    CE2         : out std_logic;
-    nCE3        : out std_logic;
-    nOE         : out std_logic;		
-    MODE        : out std_logic;        
-    SSRAM_CLK   : out std_logic;
-    ZZ          : out std_logic;
----------------------------------------------------------------------
----  AJOUT TEST ------------------------In/Out-----------------------
----------------------------------------------------------------------
--- UART 
-    UART_RXD : in std_logic;
-    UART_TXD : out std_logic;
--- ACQ
-    CNV_CH1     : OUT STD_LOGIC;
-    SCK_CH1     : OUT STD_LOGIC;
-    SDO_CH1     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
-    Bias_Fails  : out std_logic;
--- ADC
---    ADC_in  : in AD7688_in(4 downto 0);
---    ADC_out : out AD7688_out;
-
--- CNA
---    DAC_SYNC : out std_logic;
---    DAC_SCLK : out std_logic;
---    DAC_DATA : out std_logic;
--- Diver
-    SPW1_EN : out std_logic;
-    SPW2_EN : out std_logic;
-    TEST : out std_logic_vector(3 downto 0);
-
-    BP : in std_logic;
----------------------------------------------------------------------    
-    led     : out std_logic_vector(1 downto 0)
-	);
-end;
-
-architecture Behavioral of leon3mp is
-
-constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
-	CFG_GRETH+CFG_AHB_JTAG+1;                       -- +1 pour le DMA
-constant maxahbm : integer := maxahbmsp;
-
---Clk & Rst géné
-signal vcc      : std_logic_vector(4 downto 0);
-signal gnd      : std_logic_vector(4 downto 0);
-signal resetnl  : std_ulogic;
-signal clk2x    : std_ulogic;
-signal lclk     : std_ulogic;
-signal lclk2x   : std_ulogic;
-signal clkm     : std_ulogic;
-signal rstn     : std_ulogic;
-signal rstraw   : std_ulogic;
-signal pciclk   : std_ulogic;
-signal sdclkl   : std_ulogic;
-signal cgi      : clkgen_in_type;
-signal cgo      : clkgen_out_type;
---- AHB / APB
-signal apbi     : apb_slv_in_type;
-signal apbo     : apb_slv_out_vector := (others => apb_none);
-signal ahbsi    : ahb_slv_in_type;
-signal ahbso    : ahb_slv_out_vector := (others => ahbs_none);
-signal ahbmi    : ahb_mst_in_type;
-signal ahbmo    : ahb_mst_out_vector := (others => ahbm_none);
---UART
-signal ahbuarti : uart_in_type;
-signal ahbuarto : uart_out_type;
-signal apbuarti : uart_in_type;
-signal apbuarto : uart_out_type;
---MEM CTRLR
-signal memi     : memory_in_type;
-signal memo     : memory_out_type;
-signal wpo      : wprot_out_type;
-signal sdo      : sdram_out_type;
---IRQ
-signal irqi     : irq_in_vector(0 to CFG_NCPU-1);
-signal irqo     : irq_out_vector(0 to CFG_NCPU-1);
---Timer
-signal gpti     : gptimer_in_type;
-signal gpto     : gptimer_out_type;
---GPIO
-signal gpioi    : gpio_in_type;
-signal gpioo    : gpio_out_type;
---DSU
-signal dbgi     : l3_debug_in_vector(0 to CFG_NCPU-1);
-signal dbgo     : l3_debug_out_vector(0 to CFG_NCPU-1);
-signal dsui     : dsu_in_type;
-signal dsuo     : dsu_out_type; 
-
----------------------------------------------------------------------
----  AJOUT TEST ------------------------Signaux----------------------
----------------------------------------------------------------------
--- FIFOs
-signal FifoF0_Empty     : std_logic_vector(4 downto 0);
-signal FifoF0_Data      : std_logic_vector(79 downto 0);
-signal FifoF1_Empty     : std_logic_vector(4 downto 0);
-signal FifoF1_Data      : std_logic_vector(79 downto 0);
-signal FifoF3_Empty     : std_logic_vector(4 downto 0);
-signal FifoF3_Data      : std_logic_vector(79 downto 0);
-
-signal FifoINT_Full     : std_logic_vector(4 downto 0);
-signal FifoINT_Data     : std_logic_vector(79 downto 0);
-
-signal FifoOUT_Full     : std_logic_vector(1 downto 0);
-signal FifoOUT_Empty     : std_logic_vector(1 downto 0);
-signal FifoOUT_Data     : std_logic_vector(63 downto 0);
-
-
--- MATRICE SPECTRALE
-signal SM_FlagError : std_logic;
-signal SM_Pong      : std_logic;
-signal SM_Wen      : std_logic;
-signal SM_Read      : std_logic_vector(4 downto 0);
-signal SM_Write     : std_logic_vector(1 downto 0);
-signal SM_ReUse      : std_logic_vector(4 downto 0);
-signal SM_Param      : std_logic_vector(3 downto 0);
-signal SM_Data      : std_logic_vector(63 downto 0);
-
---signal Dma_acq      : std_logic;
---signal Head_Valid    : std_logic;
-
--- FFT
-signal FFT_Load        : std_logic;
-signal FFT_Read        : std_logic_vector(4 downto 0);
-signal FFT_Write       : std_logic_vector(4 downto 0);
-signal FFT_ReUse       : std_logic_vector(4 downto 0);
-signal FFT_Data        : std_logic_vector(79 downto 0);
-
--- DEMUX
-signal DMUX_Read    : std_logic_vector(14 downto 0);
-signal DMUX_Empty   : std_logic_vector(4 downto 0);
-signal DMUX_Data    : std_logic_vector(79 downto 0);
-signal DMUX_WorkFreq : std_logic_vector(1 downto 0);
-
--- ACQ
-signal sample_val : STD_LOGIC;
-signal sample : Samples(8-1 DOWNTO 0);
-
-signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
-signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
-signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
-signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-
--- Header
-signal Head_Read : std_logic_vector(1 downto 0);
-signal Head_Data  : std_logic_vector(31 downto 0);
-signal Head_Empty : std_logic;
-signal Head_Header     : std_logic_vector(31 DOWNTO 0);
-signal Head_Valid : std_logic;
-signal Head_Val : std_logic;
-
---DMA
-signal DMA_Read : std_logic;
-signal DMA_ack : std_logic;
---signal AHB_Master_In  :  AHB_Mst_In_Type;
---signal AHB_Master_Out  :  AHB_Mst_Out_Type;
-
-
--- ADC
---signal SmplClk          : std_logic;
---signal ADC_DataReady    : std_logic;
---signal ADC_SmplOut      : Samples_out(4 downto 0);
---signal enableADC        : std_logic;
---
---signal WG_Write         : std_logic_vector(4 downto 0);
---signal WG_ReUse         : std_logic_vector(4 downto 0);
---signal WG_DATA          : std_logic_vector(79 downto 0);
---signal s_out          : std_logic_vector(79 downto 0);
---
---signal fuller : std_logic_vector(4 downto 0);
---signal reader : std_logic_vector(4 downto 0);
---signal try : std_logic_vector(1 downto 0);
---signal TXDint : std_logic;
---
----- IIR Filter
---signal sample_clk_out  :   std_logic;
---
---signal Rd : std_logic_vector(0 downto 0);
---signal Ept : std_logic_vector(4 downto 0);
---
---signal Bwr : std_logic_vector(0 downto 0);
---signal Bre : std_logic_vector(0 downto 0);
---signal DataTMP : std_logic_vector(15 downto 0);
---signal FullUp : std_logic_vector(0 downto 0);
---signal EmptyUp : std_logic_vector(0 downto 0);
---signal FullDown : std_logic_vector(0 downto 0);
---signal EmptyDown : std_logic_vector(0 downto 0);
----------------------------------------------------------------------
-constant IOAEN  : integer := CFG_CAN;
-constant boardfreq : integer := 50000;
-
-begin
-
----------------------------------------------------------------------
----  AJOUT TEST -------------------------------------IPs-------------
----------------------------------------------------------------------
-led(1 downto 0) <= gpio(1 downto 0);
-
---- COM USB ---------------------------------------------------------
---    MemIn0 : APB_FifoWrite
---        generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
---        port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
---
---    BUF0 : APB_USB
---      generic map (6,6,DataMax => 1024)
---      port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
---
---    MemOut0 : APB_FifoRead
---        generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
---        port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
---
---slrd <= usb_Read;
---slwr <= usb_Write;
-
---- CNA -------------------------------------------------------------
-
---    CONV : APB_CNA
---        generic map (5,5)
---        port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
-
---TEST(0) <= SmplClk;
---TEST(1) <= WG_Write(0);
---TEST(2) <= Fuller(0);
---TEST(3) <= s_out(s_out'length-1);
-
-
---SPW1_EN <= '1';
---SPW2_EN <= '0';
-
---- CAN -------------------------------------------------------------
-
---    Divider : Clk_divider
---        generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
---        Port map(clkm,rstn,SmplClk);
---
---    ADC : AD7688_drvr
---        generic map (ChanelCount => 5, clkkHz => 24_576)
---        port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
---
---    WG : WriteGen_ADC
---        port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
---
---enableADC <= gpio(0);
-
---WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
---
---
---    MemIn1 : APB_FIFO
---        generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
-    
---  DIGITAL_acquisition : ADS7886_drvr
---    GENERIC MAP (
---      ChanelCount     => 8,
---      ncycle_cnv_high => 79,
---      ncycle_cnv      => 500)
---    PORT MAP (
---      cnv_clk    => clk50MHz,                      -- 
---      cnv_rstn   => rstn,                     -- 
---      cnv_run    => '1',                      --
---      cnv        => CNV_CH1,                          -- 
---      clk        => clkm,                          -- 
---      rstn       => rstn,                         -- 
---      sck        => SCK_CH1,                          -- 
---      sdo        => SDO_CH1,  -- 
---      sample     => sample,
---      sample_val => sample_val);
---
---TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val;
---TopACQ_DataF0 <= E & D & C & B & A;
-
---
---TEST(0) <= TopACQ_WenF0(1);
---TEST(1) <= SDO_CH1(1);
---
---process(clkm,rstn)
---begin
---      if(rstn='0')then
---        TopACQ_WenF0a <= (others => '1');
---            
---        elsif(clkm'event and clkm='1')then
---            TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
---
---    end if;
---end process;
-
-    ACQ0 : lpp_top_acq
-        port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3);
-
-Bias_Fails <= '0';    
---------- FIFO IN -------------------------------------------------------------
-----
---    Memf0 : APB_FIFO
---        generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9));
---
---    Memf1 : APB_FIFO
---        generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8));
---
---    Memf3 : APB_FIFO
---        generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5));
-
-    Memf0 : lppFIFOxN
-        generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
-    
-    Memf1 : lppFIFOxN
-        generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
-    
-    Memf3 : lppFIFOxN
-        generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
---
------ DEMUX -------------------------------------------------------------
-
-    DMUX0 : DEMUX
-        generic map(Data_sz => 16)
-        port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data);
-
-------- FFT -------------------------------------------------------------
-
---    MemIn : APB_FIFO
---        generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8));
-
-    FFT0 : FFT
-        generic map(Data_sz => 16,NbData => 256)
-        port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
-
---------- LINK MEMORY -------------------------------------------------------
-
---    MemOut : APB_FIFO
---        generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
-
-    MemInt : lppFIFOxN
-        generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1')
-        port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
-
---    MemIn : APB_FIFO
---        generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
-
------ MATRICE SPECTRALE ---------------------5 FIFO Input---------------
-
-    SM0 : MatriceSpectrale
-        generic map(Input_SZ => 16,Result_SZ => 32)
-        port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data);
-
-
---DMA_ack <= '1';
---Head_Valid <= '1';
-
---    MemOut : APB_FIFO
---        generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
-
-    MemOut : lppFIFOxN
-        generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty);
-
------------ Header -------------------------------------------------------
-
-    Head0 : HeaderBuilder
-        generic map(Data_sz => 32)
-        port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
-
-
---- DMA -------------------------------------------------------
-
-    DMA0 : lpp_dma
-        generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH)
-        port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack);
-        
-
------ FIFO -------------------------------------------------------------
-
---    Memtest : APB_FIFO
---        generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
-
---***************************************TEST DEMI-FIFO********************************************************************************
---    MemIn : APB_FIFO
---        generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
---   
---    Pont : Bridge
---        port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
---
---    MemOut : APB_FIFO
---        generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
---*************************************************************************************************************************************
-
---- UART -------------------------------------------------------------
-
-    COM0 : APB_UART
-        generic map (pindex => 4, paddr => 4)
-        port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
-
---- DELAY ------------------------------------------------------------
-
---    Delay0 : APB_Delay
---        generic map (pindex => 4, paddr => 4)
---        port map (clkm,rstn,apbi,apbo(4));
-
---- IIR Filter -------------------------------------------------------
---Test(0) <= sample_clk_out;
--- 
---
---    IIR1: APB_IIR_Filter
---        generic map(
---            tech           => CFG_MEMTECH,
---            pindex         => 8,
---            paddr          => 8,
---            Sample_SZ      => Sample_SZ,
---            ChanelsCount   => ChanelsCount,
---            Coef_SZ        => Coef_SZ,
---            CoefCntPerCel  => CoefCntPerCel,
---            Cels_count     => Cels_count,
---            virgPos        => virgPos
---            )
---        port map(
---            rst             => rstn,
---            clk             => clkm,
---            apbi            => apbi,
---            apbo            => apbo(8),
---            sample_clk_out  => sample_clk_out,
---            GOtest => Test(1),
---            CoefsInitVal    => (others => '1')
---            );
-----------------------------------------------------------------------
-
-----------------------------------------------------------------------
----  Reset and Clock generation  -------------------------------------
-----------------------------------------------------------------------
-  
-  vcc <= (others => '1'); gnd <= (others => '0');
-  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
-	
-  rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
-
-  
-  clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); 
-
-  clkgen0 : clkgen  		-- clock generator
-    generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, 
-	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
-    port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
-    
-    ramclk  <=  clkm;
-process(lclk2x)
-begin
-    if lclk2x'event and lclk2x = '1' then
-        lclk <= not lclk;
-    end if;
-end process;
-
-----------------------------------------------------------------------
----  LEON3 processor / DSU / IRQ  ------------------------------------
-----------------------------------------------------------------------
-
-  l3 : if CFG_LEON3 = 1 generate
-    cpu : for i in 0 to CFG_NCPU-1 generate
-      u0 : leon3s			-- LEON3 processor      
-      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 
-  	0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, 
-  	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
-  	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
-          CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, 
-          CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
-      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, 
-      		irqi(i), irqo(i), dbgi(i), dbgo(i));
-    end generate;
-    errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-    
-    dsugen : if CFG_DSU = 1 generate
-      dsu0 : dsu3			-- LEON3 Debug Support Unit
-      generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, 
-         ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
-      port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
---      dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); 
-	dsui.enable <= '1';
-      dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); 
-      dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
-    end generate;
-  end generate;
-
-  nodsu : if CFG_DSU = 0 generate 
-    ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
-  end generate;
-
-   irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
-    irqctrl0 : irqmp			-- interrupt controller
-    generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
-    port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
-  end generate;
-  irq3 : if CFG_IRQ3_ENABLE = 0 generate
-    x : for i in 0 to CFG_NCPU-1 generate
-      irqi(i).irl <= "0000";
-    end generate;
-    apbo(2) <= apb_none;
-  end generate;
-
-----------------------------------------------------------------------
----  Memory controllers  ---------------------------------------------
-----------------------------------------------------------------------
-
-    memctrlr : mctrl generic map (hindex => 0,pindex   => 0, paddr    => 0)
-        port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
-
-    memi.brdyn <= '1'; memi.bexcn <= '1';
-    memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
-
-    bdr : for i in 0 to 3 generate
-      data_pad : iopadv generic map (tech => padtech, width => 8)
-      port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
-    memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
-    end generate;
-
-
-    addr_pad : outpadv generic map (width => 19, tech => padtech) 
-    	port map (address, memo.address(20 downto 2));
-
-
-    SSRAM_0:entity ssram_plugin
-        generic map (tech => padtech)
-        port map
-        (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
-
-----------------------------------------------------------------------
----  AHB CONTROLLER  -------------------------------------------------
-----------------------------------------------------------------------
-
-  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
-  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, 
-	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
-	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
-  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
-
-----------------------------------------------------------------------
----  AHB UART  -------------------------------------------------------
-----------------------------------------------------------------------
-
-  dcomgen : if CFG_AHB_UART = 1 generate
-    dcom0: ahbuart		-- Debug UART
-    generic map (hindex => 2, pindex => 7, paddr => 7)
-    port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(2));
-    dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); 
-    dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
---    led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
-  end generate;
-  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
-
-----------------------------------------------------------------------
----  APB Bridge  -----------------------------------------------------
-----------------------------------------------------------------------
-
-  apb0 : apbctrl				-- AHB/APB bridge
-  generic map (hindex => 1, haddr => CFG_APBADDR)
-  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
-
-----------------------------------------------------------------------
----  GPT Timer  ------------------------------------------------------
-----------------------------------------------------------------------
-
-  gpt : if CFG_GPT_ENABLE /= 0 generate
-    timer0 : gptimer 			-- timer unit
-    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
-	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, 
-	nbits => CFG_GPT_TW)
-    port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
-    gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
---    led(4) <= gpto.wdog;
-  end generate;
-  notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-
-
-----------------------------------------------------------------------
----  APB UART  -------------------------------------------------------
-----------------------------------------------------------------------
-
-  ua1 : if CFG_UART1_ENABLE /= 0 generate
-    uart1 : apbuart			-- UART 1
-    generic map (pindex => 1, paddr => 1,  pirq => 2, console => dbguart,
-	fifosize => CFG_UART1_FIFO)
-    port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
-    apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
-    apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
---   led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
-  end generate;
-  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-
-----------------------------------------------------------------------
----  GPIO  -----------------------------------------------------------
-----------------------------------------------------------------------
-
-  gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GR GPIO unit
-    grgpio0: grgpio
-      generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
-      port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
-
-      pio_pads : for i in 0 to 6 generate
-        pio_pad : iopad generic map (tech => padtech)
-            port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-      end generate;
-   end generate;
-
-
-end Behavioral;
\ No newline at end of file
diff --git a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt
--- a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt
+++ b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt
@@ -1,13 +1,19 @@
+AD7688_drvr_sync.vhd
 AD7688_drvr.vhd
-AD7688_drvr_sync.vhd
+AD7688_drvr.vhd.orig
 AD7688_spi_if.vhd
 ADS1274_drvr.vhd
+ADS1274_drvr.vhd~
 ADS1278_drvr.vhd
+ADS1278_drvr.vhd~
 ADS7886_drvr.vhd
-RHF1401.vhd
-WriteGen_ADC.vhd
 dual_ADS1278_drvr.vhd
+dual_ADS1278_drvr.vhd~
 lpp_ad_Conv.vhd
+lpp_ad_Conv.vhd~
+lpp_ad_Conv.vhd.orig
 lpp_apb_ad_conv.vhd
+RHF1401.vhd
+top_ad_conv_RHF1401.vhd
 top_ad_conv.vhd
-top_ad_conv_RHF1401.vhd
+WriteGen_ADC.vhd
diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt
--- a/lib/lpp/lpp_amba/vhdlsyn.txt
+++ b/lib/lpp/lpp_amba/vhdlsyn.txt
@@ -1,4 +1,4 @@
+apb_devices_list.vhd
 APB_MULTI_DIODE.vhd
 APB_SIMPLE_DIODE.vhd
-apb_devices_list.vhd
 lpp_amba.vhd
diff --git a/lib/lpp/lpp_bootloader/vhdlsyn.txt b/lib/lpp/lpp_bootloader/vhdlsyn.txt
--- a/lib/lpp/lpp_bootloader/vhdlsyn.txt
+++ b/lib/lpp/lpp_bootloader/vhdlsyn.txt
@@ -1,3 +1,3 @@
 bootrom.vhd
+lpp_bootloader_pkg.vhd
 lpp_bootloader.vhd
-lpp_bootloader_pkg.vhd
diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt
--- a/lib/lpp/lpp_dma/vhdlsyn.txt
+++ b/lib/lpp/lpp_dma/vhdlsyn.txt
@@ -1,8 +1,8 @@
 fifo_latency_correction.vhd
-lpp_dma.vhd
 lpp_dma_apbreg.vhd
 lpp_dma_fsm.vhd
 lpp_dma_ip.vhd
 lpp_dma_pkg.vhd
 lpp_dma_send_16word.vhd
 lpp_dma_send_1word.vhd
+lpp_dma.vhd
diff --git a/lib/lpp/lpp_matrix/vhdlsyn.txt b/lib/lpp/lpp_matrix/vhdlsyn.txt
--- a/lib/lpp/lpp_matrix/vhdlsyn.txt
+++ b/lib/lpp/lpp_matrix/vhdlsyn.txt
@@ -4,6 +4,7 @@ APB_Matrix.vhd
 Dispatch.vhd
 DriveInputs.vhd
 GetResult.vhd
+lpp_matrix.vhd
 MatriceSpectrale.vhd
 MatriceSpectrale.vhd.bak
 Matrix.vhd
@@ -12,6 +13,5 @@ SpectralMatrix.vhd
 SpectralMatrix.vhd.bak
 Starter.vhd
 TopMatrix_PDR.vhd
+Top_MatrixSpec.vhd
 TopSpecMatrix.vhd
-Top_MatrixSpec.vhd
-lpp_matrix.vhd
diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt
--- a/lib/lpp/lpp_memory/vhdlsyn.txt
+++ b/lib/lpp/lpp_memory/vhdlsyn.txt
@@ -2,10 +2,10 @@ APB_FIFO.vhd
 APB_FIFO.vhd.bak
 FIFO_pipeline.vhd
 FillFifo.vhd
-SSRAM_plugin.vhd
-SSRAM_plugin_vsim.vhd
+lpp_FIFO.vhd
 lppFIFOxN.vhd
 lppFIFOxN.vhd.bak
-lpp_FIFO.vhd
 lpp_memory.vhd
 lpp_memory.vhd.bak
+SSRAM_plugin.vhd
+SSRAM_plugin_vsim.vhd
diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt
--- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt
+++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt
@@ -1,15 +1,15 @@
-lpp_lfr.vhd
 lpp_lfr_apbreg.vhd
 lpp_lfr_filter.vhd
 lpp_lfr_ms.vhd
 lpp_lfr_pkg.vhd
+lpp_lfr.vhd
 lpp_top_acq.vhd
 lpp_top_acq.vhd.bak
 lpp_top_apbreg.vhd
-lpp_top_lfr.vhd
 lpp_top_lfr_pkg.vhd
 lpp_top_lfr_pkg.vhd.bak
-lpp_top_lfr_wf_picker.vhd
+lpp_top_lfr.vhd
 lpp_top_lfr_wf_picker_ip.vhd
 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
+lpp_top_lfr_wf_picker.vhd
 top_wf_picker.vhd
diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt
--- a/lib/lpp/lpp_waveform/vhdlsyn.txt
+++ b/lib/lpp/lpp_waveform/vhdlsyn.txt
@@ -1,13 +1,13 @@
-lpp_waveform.vhd
 lpp_waveform_burst.vhd
-lpp_waveform_dma.vhd
 lpp_waveform_dma_genvalid.vhd
 lpp_waveform_dma_selectaddress.vhd
 lpp_waveform_dma_send_Nword.vhd
-lpp_waveform_fifo.vhd
+lpp_waveform_dma.vhd
 lpp_waveform_fifo_arbiter.vhd
 lpp_waveform_fifo_ctrl.vhd
+lpp_waveform_fifo.vhd
 lpp_waveform_pkg.vhd
+lpp_waveform_snapshot_controler.vhd
 lpp_waveform_snapshot.vhd
-lpp_waveform_snapshot_controler.vhd
 lpp_waveform_valid_ack.vhd
+lpp_waveform.vhd