Makefile
49 lines
| 1.3 KiB
| text/x-makefile
|
MakefileLexer
Jeandet Alexis
|
r255 | include .config | ||
| #GRLIB=$(GRLIB) | ||||
| TOP=BeagleSynth | ||||
| BOARD=BeagleSynth | ||||
| #BOARD=SP601 | ||||
| include ../../boards/$(BOARD)/Makefile.inc | ||||
| DEVICE=$(PART)-$(PACKAGE)$(SPEED) | ||||
| #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf | ||||
| UCF=../../boards/$(BOARD)/default.ucf | ||||
| QSF=../../boards/$(BOARD)/$(TOP).qsf | ||||
| EFFORT=high | ||||
| ISEMAPOPT="-timing" | ||||
| XSTOPT="" | ||||
| SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0" | ||||
| VHDLOPTSYNFILES= | ||||
| VHDLSYNFILES= \ | ||||
|
Jeandet Alexis
|
r269 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd | ||
|
Jeandet Alexis
|
r255 | #VHDLSIMFILES=testbench.vhd | ||
| #SIMTOP=testbench | ||||
| #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc | ||||
| SDCFILE=default.sdc | ||||
| BITGEN=../../boards/$(BOARD)/default.ut | ||||
| CLEAN=soft-clean | ||||
| VCOMOPT=-explicit | ||||
| TECHLIBS = secureip unisim | ||||
| LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | ||||
| tmtc openchip cypress ihp gleichmann gsi fmf spansion | ||||
| DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \ | ||||
| leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \ | ||||
| ac97 hcan usb | ||||
| DIRADD = | ||||
| FILEADD = | ||||
| FILESKIP = grcan.vhd ddr2.v mobile_ddr.v | ||||
| include $(GRLIB)/bin/Makefile | ||||
| include $(GRLIB)/software/leon3/Makefile | ||||
| ################## project specific targets ########################## | ||||
| flash: | ||||
|
Jeandet Alexis
|
r263 | xc3sprog -c ftdi -p 1 BeagleSynth.bit | ||
|
Jeandet Alexis
|
r265 | |||
| ram: | ||||
| xc3sprog -c ftdi -p 0 BeagleSynth.bit | ||||