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add TestBench designs
add TestBench designs
pellion - - Load All Authors

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r543:cacd7252f42c JC
r543:cacd7252f42c JC
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run.do
20 lines | 792 B | text/x-stata | StataLexer
/ designs / Validation_IIR_LFR / run.do
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pellion
add TestBench designs
 r543 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd
vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd
vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd
vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd
vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd
vcom -quiet -93 -work work IIR_CEL_TEST.vhd
vcom -quiet -93 -work work IIR_CEL_TEST_v3.vhd
vcom -quiet -93 -work work tb.vhd
vsim work.testbench
log -r *
do wave.do
run -all