##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen. Solved in place design developpment problem on Windows, look at EGSE_ICI makefile.
Alexis Jeandet - - Load All Authors

File last commit:

r220:9cd9574d2765 alexis
r220:9cd9574d2765 alexis
Show More
Makefile
36 lines | 1.3 KiB | text/x-makefile | MakefileLexer
/ designs / EGSE_ICI / Makefile
History | Source | Raw |Copy content |Copy permalink
Alexis Jeandet
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
 r220 #GRLIB=../..
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 VHDLIB=../..
Alexis Jeandet
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
 r220 SCRIPTSDIR=$(VHDLIB)/scripts/
GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
Alexis Jeandet
Cleaned EGSE_ICI design.
 r218 TOP=TOP_EGSE2
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 BOARD=GSE_ICI
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=high
XSTOPT=
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
Alexis Jeandet
ICI4 EGSE now working, need some more cleaning.
 r219 VHDLSYNFILES=config.vhd EGSE_ICI.vhd DC_GATE_GEN.vhd LF_GATE_GEN.vhd MajF_Gen.vhd MinF_Gen.vhd Serial_driver.vhd ICI_EGSE_PROTOCOL.vhd
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
SDC=$(GRLIB)/boards/$(BOARD)/default.sdc
PDC=$(GRLIB)/boards/$(BOARD)/GSE_ICI.pdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
TECHLIBS = proasic3
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
Alexis Jeandet
Cleaned EGSE_ICI design.
 r218 tmtc openchip hynix ihp gleichmann micron usbhc spw fmf gsi eth spansion esa
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
Alexis Jeandet
ICI4 EGSE now working, need some more cleaning.
 r219 pci grusbhc haps slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft can greth net gr1553b ./amba_lcd_16x2_ctrlr ./lpp_waveform \
./lpp_dma
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217
FILESKIP = i2cmst.vhd
include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile
################## project specific targets ##########################