HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/ICI4-3DCAM-Integ1/Makefile

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

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        jeandet
    
ICI rockets designs added

              r168
            
      include .config

      #GRLIB=$(GRLIB)

      TOP=ici4

      BOARD=ICI4-3DCAM

      #BOARD=SP601

      include $(GRLIB)/boards/$(BOARD)/Makefile.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf

      UCF=$(GRLIB)/boards/$(BOARD)/ICI4-Main-BD.ucf

      QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf

      EFFORT=high

      ISEMAPOPT="-timing"

      XSTOPT=""

      SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"

      VHDLOPTSYNFILES= \

                       ICI4HDL/Convertisseur_config.vhd \

                       ICI4HDL/ICI4_3DCAM_FRAM_PLACER.vhd \

                       ICI4HDL/LF_FRAME_PLACER.vhd 

      VHDLSYNFILES= \

      	config.vhd  ici4.vhd

      VHDLSIMFILES=testbench.vhd

      SIMTOP=testbench

      #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc

      SDCFILE=default.sdc

      BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut

      CLEAN=soft-clean

      VCOMOPT=-explicit

      TECHLIBS = secureip unisim 

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip cypress ihp gleichmann gsi fmf spansion 

      DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \

      	leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \

      	ac97 hcan usb

      DIRADD = 

      FILEADD =

      FILESKIP = grcan.vhd ddr2.v mobile_ddr.v

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

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jeandet ICI rockets designs added	r168	include .config

		#GRLIB=$(GRLIB)
		TOP=ici4
		BOARD=ICI4-3DCAM
		#BOARD=SP601
		include $(GRLIB)/boards/$(BOARD)/Makefile.inc
		DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		#UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
		UCF=$(GRLIB)/boards/$(BOARD)/ICI4-Main-BD.ucf
		QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
		EFFORT=high
		ISEMAPOPT="-timing"
		XSTOPT=""
		SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
		VHDLOPTSYNFILES= \
		ICI4HDL/Convertisseur_config.vhd \
		ICI4HDL/ICI4_3DCAM_FRAM_PLACER.vhd \
		ICI4HDL/LF_FRAME_PLACER.vhd

		VHDLSYNFILES= \
		config.vhd ici4.vhd
		VHDLSIMFILES=testbench.vhd
		SIMTOP=testbench
		#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
		SDCFILE=default.sdc
		BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
		CLEAN=soft-clean
		VCOMOPT=-explicit
		TECHLIBS = secureip unisim

		LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		tmtc openchip cypress ihp gleichmann gsi fmf spansion
		DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
		leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
		ac97 hcan usb
		DIRADD =
		FILEADD =
		FILESKIP = grcan.vhd ddr2.v mobile_ddr.v

		include $(GRLIB)/bin/Makefile
		include $(GRLIB)/software/leon3/Makefile


		################## project specific targets ##########################