/*------------------------------------------------------------------------------
--  This file is a part of the VHDL Tools Software
--  Copyright (C) 2014, Plasma Physics Laboratory - CNRS
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-------------------------------------------------------------------------------*/
/*--                  Author : Alexis Jeandet
--                     Mail : alexis.jeandet@member.fsf.org
----------------------------------------------------------------------------*/
#ifndef VHDL_AST_NODE_H
#define VHDL_AST_NODE_H
#include <QString>
#include <QList>

namespace VHDL_Tools{

#define closedByEnd (0x100)
#define closedBySemicolon (0x200)
#define closedByRightParen (0x300)

#define IS_CLOSED_BY_END(type) (((type)&0xF00)==closedByEnd)
#define IS_CLOSED_BY_SEMICOLON(type) (((type)&0xF00)==closedBySemicolon)
#define IS_CLOSED_BY_RIGHTPAREN(type) (((type)&0xF00)==closedByRightParen)

#define IS_CLOSED_BY(openType,type) ((type)==ExpectedCloseTypeLookUp[((openType)&0xF00)>>8])

#define FORCE_CLOSETYPE(node,closetype)  (node)->type = static_cast<VHDL_Tools::VHDL_AST_Node_type>(((node)->type & 0x0FF) | (closetype))

enum VHDL_AST_Node_type {
    none=0xF00000, //to force to at least 32 bits
    rootNode=1,
    separator=2,
    keyword=3,
    leftParen=4|closedByRightParen,
    rightParen=5,
    semicolon=6,
    colon=7,
    generic=8|closedBySemicolon,
    port=9|closedBySemicolon,
    map=10,
    endKw=11,
    virtualGroup=112,
    identifier=13,
    literal=14,
    comment=15,
    block=16|closedByEnd,
    units=17|closedByEnd,
    entity=18|closedByEnd,
    record=19|closedByEnd,
    clause=20|closedBySemicolon,
    signal=21|closedBySemicolon,
    variable=22|closedBySemicolon,
    shared=23|closedBySemicolon,
    type=24|closedBySemicolon,
    attribute=25|closedBySemicolon,
    constant=26|closedBySemicolon,
    function=27,
    procedure=28,
    is=29,
    return_t=30,
    begin=31,
    loop=32,
    architecture=33|closedByEnd,
    package=34|closedByEnd,
    subtype=35|closedBySemicolon,
    component=36|closedByEnd,
    range=37,
    comma=38,
    box=39,
    direction=40,
    array=41,
    access=42,
    file=43|closedBySemicolon,
    alias=44|closedBySemicolon,
    report=45|closedBySemicolon,
    body=46|closedByEnd,
    of=47,
    process=48|closedByEnd,
    arrow=49,
    varAsgn=50,
    wait=51|closedBySemicolon,
    leSym=52,
    caseKw=53|closedByEnd,
    when=54
};

const VHDL_AST_Node_type ExpectedCloseTypeLookUp[]={none,endKw,semicolon,rightParen,none,none,none,none,none,none,none,none,none,none,none,none};

class VHDL_AST_Node
{
public:
    VHDL_AST_Node(const QString& value,VHDL_Tools::VHDL_AST_Node_type type,int line=0, int column=0);
    ~VHDL_AST_Node();
    QString a_value;
    VHDL_Tools::VHDL_AST_Node_type type;
    int line;
    int column;
    QList<VHDL_Tools::VHDL_AST_Node*> childs;
    void move(VHDL_Tools::VHDL_AST_Node* parentNode);
    void moveWithoutChilds(VHDL_Tools::VHDL_AST_Node* parentNode);
    VHDL_Tools::VHDL_AST_Node* parent(){return p_parent;}
    void setParent(VHDL_Tools::VHDL_AST_Node* parent){this->p_parent=parent;}
private:
    VHDL_Tools::VHDL_AST_Node* p_parent;

};
}

#endif // VHDL_AST_NODE_H