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%{
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/* C++ string header, for string ops below */
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#include <string>
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#include <QString>
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/* Implementation of yyFlexScanner */
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#include "vhdl_scanner.h"
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#include <QDebug>
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/* define to keep from re-typing the same code over and over */
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#define STOKEN( x ) ( new QString( x ) )
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/* define yyterminate as this instead of NULL */
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//#define yyterminate() return( token::END )
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/* msvc2010 requires that we exclude this header file. */
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#define YY_NO_UNISTD_H
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#define YY_USER_ACTION yycolumn += yyleng;
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%}
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%option debug
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%option nodefault
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%option yyclass="vhdl_Scanner"
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%option case-insensitive yylineno
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%option noyywrap
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%option c++
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%%
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/*-----------------------------------------------------------*/
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/*Separators*/
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[ \t]+ { } //skip new lines, blanc spaces and tabulations
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/*-----------------------------------------------------------*/
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\n {yycolumn=1;}
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\x0d\x0a {yycolumn=1;}
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/*comment*/
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--.* {
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this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::comment,yylineno, yycolumn-yyleng));
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}
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/*-----------------------------------------------------------*/
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/*Reserved words*/
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abs |
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after |
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all |
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and |
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assert |
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buffer |
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bus |
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disconnect |
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else |
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elsif |
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exit |
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generate | /* don't parse generate as block! just look for "if" or "for" */
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group |
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guarded |
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impure |
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in |
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inertial |
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inout |
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label |
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linkage |
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literal |
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mod |
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nand |
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new |
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next |
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nor |
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not |
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null |
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on |
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open |
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or |
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others |
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out |
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postponed |
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pure |
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register |
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reject |
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rem |
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rol |
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ror |
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select |
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severity |
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sla |
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sll |
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sra |
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srl |
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then |
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transport |
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unaffected |
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until |
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when |
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with |
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xnor |
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xor |
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(true|false) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::keyword,yylineno, yycolumn-yyleng));}
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return {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::return_t,yylineno, yycolumn-yyleng));}
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when {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::when,yylineno, yycolumn-yyleng));}
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begin {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::begin,yylineno, yycolumn-yyleng));}
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is {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::is,yylineno, yycolumn-yyleng));}
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port {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::port,yylineno, yycolumn-yyleng));}
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generic {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::generic,yylineno, yycolumn-yyleng));}
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map {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::map,yylineno, yycolumn-yyleng));}
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loop {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::loop,yylineno, yycolumn-yyleng));}
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range {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::range,yylineno, yycolumn-yyleng));}
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array {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::array,yylineno, yycolumn-yyleng));}
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access {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::access,yylineno, yycolumn-yyleng));}
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file {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::file,yylineno, yycolumn-yyleng));}
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alias {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::alias,yylineno, yycolumn-yyleng));}
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report {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::report,yylineno, yycolumn-yyleng));}
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body {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::body,yylineno, yycolumn-yyleng));}
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of {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::of,yylineno, yycolumn-yyleng));}
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to |
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downto {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::direction,yylineno, yycolumn-yyleng));}
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block |
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configuration |
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for |
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if |
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while |
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protected {
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this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::block,yylineno, yycolumn-yyleng));
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}
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case {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::caseKw,yylineno, yycolumn-yyleng));}
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wait {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::wait,yylineno, yycolumn-yyleng));}
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process {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::process,yylineno, yycolumn-yyleng));}
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component {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::component,yylineno, yycolumn-yyleng));}
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package {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::package,yylineno, yycolumn-yyleng));}
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architecture {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::architecture,yylineno, yycolumn-yyleng));}
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record {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::record,yylineno, yycolumn-yyleng));}
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entity {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::entity,yylineno, yycolumn-yyleng));}
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procedure {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::procedure,yylineno, yycolumn-yyleng));}
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function {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::function,yylineno, yycolumn-yyleng));}
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units { this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::units,yylineno, yycolumn-yyleng));}
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library |
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use {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::clause,yylineno, yycolumn-yyleng));}
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constant {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::constant,yylineno, yycolumn-yyleng));}
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subtype {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::subtype,yylineno, yycolumn-yyleng));}
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type {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::type,yylineno, yycolumn-yyleng));}
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attribute {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::attribute,yylineno, yycolumn-yyleng));}
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variable {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::variable,yylineno, yycolumn-yyleng));}
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signal {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::signal,yylineno, yycolumn-yyleng));}
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shared {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::shared,yylineno, yycolumn-yyleng));}
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end {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::endKw,yylineno, yycolumn-yyleng));}
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/*-----------------------------------------------------------*/
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/*identifier (may be a reserved word)*/
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[a-z][a-z0-9\_\.]*[a-z0-9]+ |
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[a-z]+ |
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\\.*\\ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::identifier,yylineno, yycolumn-yyleng));}
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/*-----------------------------------------------------------*/
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/*abstract literal (integer or floating point type)*/
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/*Numerical literals*/
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[0-9]+\#[a-f0-9]+\# {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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(\+|\-)?([0-9\_]+)|(\+|\-)?([0-9\_]+E[0-9\_]+)|((2|3|4|5|6|7|8|9|10|11|12|13|14|15|16)\#[0-9\_]\#) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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(\+|\-)?[0-9\_]+\.[0-9\_]+|[0-9\_]+\.[0-9\_]+E[0-9\_]+ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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\'(0|1)\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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\'.\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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(\+|\-)?([0-9\_]+)(fs|ps|ns|us|ms|sec|min|hr) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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/*Bit string literals*/
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[\"\”][0-1\_\-]+[\"\”] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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x[\"\”][0-9A-F\_]+[\"\”] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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o[\"\”][0-7\_]+[\"\”] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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/*String literals*/
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[\"\”][^\"\n]*[\"\”] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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/*The NULL literal*/
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\[NULL\] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));}
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/*-----------------------------------------------------------*/
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/*character literal (a graphical character surrounded by ‘, e.g.: ‘H’)*/
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/*-----------------------------------------------------------*/
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/*string literal (a sequence of graphical characters surrounded by ”, e.g.: ”HAR-DI”)*/
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/*-----------------------------------------------------------*/
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/* bit string literal (a sequence of extended digits * surrounded by ”, e.g.: ”011”)*/
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/*-----------------------------------------------------------*/
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/* delimiter*/
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\. |
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\| |
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\[ |
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\] |
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\>\= |
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\/\= |
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\= |
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\> |
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\< |
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\& |
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\‘ |
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\' |
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\’ |
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\* |
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\+ |
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\- |
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\/ |
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\*\* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::separator,yylineno, yycolumn-yyleng)); }
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\<\= {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::leSym,yylineno, yycolumn-yyleng)); }
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\=\> {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::arrow,yylineno, yycolumn-yyleng)); }
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\:= {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::varAsgn,yylineno, yycolumn-yyleng)); }
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\<\> {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::box,yylineno, yycolumn-yyleng)); }
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\, {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::comma,yylineno, yycolumn-yyleng)); }
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\: {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::colon,yylineno, yycolumn-yyleng)); }
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\( {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::leftParen,yylineno, yycolumn-yyleng));}
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\) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::rightParen,yylineno, yycolumn-yyleng));}
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\; {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::semicolon,yylineno, yycolumn-yyleng)); }
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. printf("bad input character '%s' at line %d column %d\n ", yytext, yylineno,yycolumn-yyleng);
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%%
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