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package test is
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component ramb4_s16
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port (
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do : out std_logic_vector (15 downto 0)
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);
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end component;
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component ramb4_s16
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port (
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do : out std_logic_vector (15 downto 0)
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);
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end component;
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end package;
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package test is
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component cmp1
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port (
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do : out std_logic_vector (15 downto 0)
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);
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end component;
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component cmp2
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port (
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do : out std_logic_vector (15 downto 0)
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);
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end component;
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end package;
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Package: vcomponents
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-- File: vcomponents.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: Component declartions of some XILINX primitives
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package vcomponents is
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-- synopsys translate_off
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-----------------------------------------
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----------- FPGA Globals --------------
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-----------------------------------------
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signal GSR : std_logic := '0';
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signal GTS : std_logic := '0';
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signal GWE : std_logic := '0';
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signal PLL_LOCKG : std_logic := 'H';
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signal PROGB_GLBL : std_logic := '0';
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signal CCLKO_GLBL : std_logic := 'H';
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-----------------------------------------
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----------- CPLD Globals --------------
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-----------------------------------------
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signal PRLD : std_logic := '0';
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-----------------------------------------
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----------- JTAG Globals --------------
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-----------------------------------------
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signal JTAG_TDO_GLBL : std_logic;
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signal JTAG_TDI_GLBL : std_logic := '0';
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signal JTAG_TMS_GLBL : std_logic := '0';
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signal JTAG_TCK_GLBL : std_logic := '0';
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signal JTAG_TRST_GLBL : std_logic := '0';
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signal JTAG_CAPTURE_GLBL : std_logic := '0';
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signal JTAG_RESET_GLBL : std_logic := '1';
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signal JTAG_SHIFT_GLBL : std_logic := '1';
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signal JTAG_UPDATE_GLBL : std_logic := '0';
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signal JTAG_RUNTEST_GLBL : std_logic := '0';
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signal JTAG_SEL1_GLBL : std_logic := '0';
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signal JTAG_SEL2_GLBL : std_logic := '0';
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signal JTAG_SEL3_GLBL : std_logic := '0';
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signal JTAG_SEL4_GLBL : std_logic := '0';
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signal JTAG_USER_TDO1_GLBL : std_logic := 'Z';
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signal JTAG_USER_TDO2_GLBL : std_logic := 'Z';
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signal JTAG_USER_TDO3_GLBL : std_logic := 'Z';
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signal JTAG_USER_TDO4_GLBL : std_logic := 'Z';
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-- synopsys translate_on
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component ramb4_s16 port (
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do : out std_logic_vector (15 downto 0);
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addr : in std_logic_vector (7 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (15 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S8
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port (do : out std_logic_vector (7 downto 0);
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addr : in std_logic_vector (8 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (7 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S4
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port (do : out std_logic_vector (3 downto 0);
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addr : in std_logic_vector (9 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (3 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S2
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port (do : out std_logic_vector (1 downto 0);
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addr : in std_logic_vector (10 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (1 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S1
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port (do : out std_logic_vector (0 downto 0);
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addr : in std_logic_vector (11 downto 0);
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clk : in std_ulogic;
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di : in std_logic_vector (0 downto 0);
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en, rst, we : in std_ulogic);
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end component;
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component RAMB4_S1_S1
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port (
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doa : out std_logic_vector (0 downto 0);
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dob : out std_logic_vector (0 downto 0);
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addra : in std_logic_vector (11 downto 0);
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addrb : in std_logic_vector (11 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (0 downto 0);
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dib : in std_logic_vector (0 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S2_S2
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port (
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doa : out std_logic_vector (1 downto 0);
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dob : out std_logic_vector (1 downto 0);
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addra : in std_logic_vector (10 downto 0);
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addrb : in std_logic_vector (10 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (1 downto 0);
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dib : in std_logic_vector (1 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S4_S4
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port (
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doa : out std_logic_vector (3 downto 0);
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dob : out std_logic_vector (3 downto 0);
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addra : in std_logic_vector (9 downto 0);
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addrb : in std_logic_vector (9 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (3 downto 0);
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dib : in std_logic_vector (3 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S8_S8
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port (
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doa : out std_logic_vector (7 downto 0);
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dob : out std_logic_vector (7 downto 0);
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addra : in std_logic_vector (8 downto 0);
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addrb : in std_logic_vector (8 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (7 downto 0);
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dib : in std_logic_vector (7 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB4_S16_S16
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port (
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doa : out std_logic_vector (15 downto 0);
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dob : out std_logic_vector (15 downto 0);
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addra : in std_logic_vector (7 downto 0);
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addrb : in std_logic_vector (7 downto 0);
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clka : in std_ulogic;
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clkb : in std_ulogic;
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dia : in std_logic_vector (15 downto 0);
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dib : in std_logic_vector (15 downto 0);
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ena : in std_ulogic;
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enb : in std_ulogic;
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rsta : in std_ulogic;
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rstb : in std_ulogic;
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wea : in std_ulogic;
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web : in std_ulogic
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);
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end component;
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component RAMB16_S1
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-- pragma translate_off
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generic
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(
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INIT : bit_vector := X"0";
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SRVAL : bit_vector := X"0";
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WRITE_MODE : string := "WRITE_FIRST";
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INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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279
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INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
251
|
280
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
252
|
281
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
253
|
282
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
254
|
283
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
255
|
284
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
256
|
285
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
257
|
286
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
258
|
287
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
259
|
288
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
260
|
289
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
261
|
290
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
262
|
291
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
263
|
292
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
264
|
293
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
265
|
294
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
266
|
295
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
267
|
296
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
268
|
297
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
269
|
298
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
270
|
299
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
271
|
300
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
272
|
301
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
273
|
302
|
);
|
|
274
|
303
|
-- pragma translate_on
|
|
275
|
304
|
port (
|
|
276
|
305
|
DO : out std_logic_vector (0 downto 0);
|
|
277
|
306
|
ADDR : in std_logic_vector (13 downto 0);
|
|
278
|
307
|
CLK : in std_ulogic;
|
|
279
|
308
|
DI : in std_logic_vector (0 downto 0);
|
|
280
|
309
|
EN : in std_ulogic;
|
|
281
|
310
|
SSR : in std_ulogic;
|
|
282
|
311
|
WE : in std_ulogic
|
|
283
|
312
|
);
|
|
284
|
313
|
end component;
|
|
285
|
314
|
|
|
286
|
315
|
component RAMB16_S2
|
|
287
|
316
|
-- pragma translate_off
|
|
288
|
317
|
generic
|
|
289
|
318
|
(
|
|
290
|
319
|
INIT : bit_vector := X"0";
|
|
291
|
320
|
SRVAL : bit_vector := X"0";
|
|
292
|
321
|
WRITE_MODE : string := "WRITE_FIRST";
|
|
293
|
322
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
294
|
323
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
295
|
324
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
296
|
325
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
297
|
326
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
298
|
327
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
299
|
328
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
300
|
329
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
301
|
330
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
302
|
331
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
303
|
332
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
304
|
333
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
305
|
334
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
306
|
335
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
307
|
336
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
308
|
337
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
309
|
338
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
310
|
339
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
311
|
340
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
312
|
341
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
313
|
342
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
314
|
343
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
315
|
344
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
316
|
345
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
317
|
346
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
318
|
347
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
319
|
348
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
320
|
349
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
321
|
350
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
322
|
351
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
323
|
352
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
324
|
353
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
325
|
354
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
326
|
355
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
327
|
356
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
328
|
357
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
329
|
358
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
330
|
359
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
331
|
360
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
332
|
361
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
333
|
362
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
334
|
363
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
335
|
364
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
336
|
365
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
337
|
366
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
338
|
367
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
339
|
368
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
340
|
369
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
341
|
370
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
342
|
371
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
343
|
372
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
344
|
373
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
345
|
374
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
346
|
375
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
347
|
376
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
348
|
377
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
349
|
378
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
350
|
379
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
351
|
380
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
352
|
381
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
353
|
382
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
354
|
383
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
355
|
384
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
356
|
385
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
357
|
386
|
);
|
|
358
|
387
|
-- pragma translate_on
|
|
359
|
388
|
port (
|
|
360
|
389
|
DO : out std_logic_vector (1 downto 0);
|
|
361
|
390
|
ADDR : in std_logic_vector (12 downto 0);
|
|
362
|
391
|
CLK : in std_ulogic;
|
|
363
|
392
|
DI : in std_logic_vector (1 downto 0);
|
|
364
|
393
|
EN : in std_ulogic;
|
|
365
|
394
|
SSR : in std_ulogic;
|
|
366
|
395
|
WE : in std_ulogic
|
|
367
|
396
|
);
|
|
368
|
397
|
end component;
|
|
369
|
398
|
|
|
370
|
399
|
component RAMB16_S4
|
|
371
|
400
|
-- pragma translate_off
|
|
372
|
401
|
generic
|
|
373
|
402
|
(
|
|
374
|
403
|
INIT : bit_vector := X"0";
|
|
375
|
404
|
SRVAL : bit_vector := X"0";
|
|
376
|
405
|
WRITE_MODE : string := "WRITE_FIRST";
|
|
377
|
406
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
378
|
407
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
379
|
408
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
380
|
409
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
381
|
410
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
382
|
411
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
383
|
412
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
384
|
413
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
385
|
414
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
386
|
415
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
387
|
416
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
388
|
417
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
389
|
418
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
390
|
419
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
391
|
420
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
392
|
421
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
393
|
422
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
394
|
423
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
395
|
424
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
396
|
425
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
397
|
426
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
398
|
427
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
399
|
428
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
400
|
429
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
401
|
430
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
402
|
431
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
403
|
432
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
404
|
433
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
405
|
434
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
406
|
435
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
407
|
436
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
408
|
437
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
409
|
438
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
410
|
439
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
411
|
440
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
412
|
441
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
413
|
442
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
414
|
443
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
415
|
444
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
416
|
445
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
417
|
446
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
418
|
447
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
419
|
448
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
420
|
449
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
421
|
450
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
422
|
451
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
423
|
452
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
424
|
453
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
425
|
454
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
426
|
455
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
427
|
456
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
428
|
457
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
429
|
458
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
430
|
459
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
431
|
460
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
432
|
461
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
433
|
462
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
434
|
463
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
435
|
464
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
436
|
465
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
437
|
466
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
438
|
467
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
439
|
468
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
440
|
469
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
441
|
470
|
);
|
|
442
|
471
|
-- pragma translate_on
|
|
443
|
472
|
port (
|
|
444
|
473
|
DO : out std_logic_vector (3 downto 0);
|
|
445
|
474
|
ADDR : in std_logic_vector (11 downto 0);
|
|
446
|
475
|
CLK : in std_ulogic;
|
|
447
|
476
|
DI : in std_logic_vector (3 downto 0);
|
|
448
|
477
|
EN : in std_ulogic;
|
|
449
|
478
|
SSR : in std_ulogic;
|
|
450
|
479
|
WE : in std_ulogic
|
|
451
|
480
|
);
|
|
452
|
481
|
end component;
|
|
453
|
482
|
|
|
454
|
483
|
component RAMB16_S9
|
|
455
|
484
|
-- pragma translate_off
|
|
456
|
485
|
generic
|
|
457
|
486
|
(
|
|
458
|
487
|
INIT : bit_vector := X"000";
|
|
459
|
488
|
SRVAL : bit_vector := X"000";
|
|
460
|
489
|
WRITE_MODE : string := "WRITE_FIRST";
|
|
461
|
490
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
462
|
491
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
463
|
492
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
464
|
493
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
465
|
494
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
466
|
495
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
467
|
496
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
468
|
497
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
469
|
498
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
470
|
499
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
471
|
500
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
472
|
501
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
473
|
502
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
474
|
503
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
475
|
504
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
476
|
505
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
477
|
506
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
478
|
507
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
479
|
508
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
480
|
509
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
481
|
510
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
482
|
511
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
483
|
512
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
484
|
513
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
485
|
514
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
486
|
515
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
487
|
516
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
488
|
517
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
489
|
518
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
490
|
519
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
491
|
520
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
492
|
521
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
493
|
522
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
494
|
523
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
495
|
524
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
496
|
525
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
497
|
526
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
498
|
527
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
499
|
528
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
500
|
529
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
501
|
530
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
502
|
531
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
503
|
532
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
504
|
533
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
505
|
534
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
506
|
535
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
507
|
536
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
508
|
537
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
509
|
538
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
510
|
539
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
511
|
540
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
512
|
541
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
513
|
542
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
514
|
543
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
515
|
544
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
516
|
545
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
517
|
546
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
518
|
547
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
519
|
548
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
520
|
549
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
521
|
550
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
522
|
551
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
523
|
552
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
524
|
553
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
525
|
554
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
526
|
555
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
527
|
556
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
528
|
557
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
529
|
558
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
530
|
559
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
531
|
560
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
532
|
561
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
533
|
562
|
);
|
|
534
|
563
|
-- pragma translate_on
|
|
535
|
564
|
port (
|
|
536
|
565
|
DO : out std_logic_vector (7 downto 0);
|
|
537
|
566
|
DOP : out std_logic_vector (0 downto 0);
|
|
538
|
567
|
ADDR : in std_logic_vector (10 downto 0);
|
|
539
|
568
|
CLK : in std_ulogic;
|
|
540
|
569
|
DI : in std_logic_vector (7 downto 0);
|
|
541
|
570
|
DIP : in std_logic_vector (0 downto 0);
|
|
542
|
571
|
EN : in std_ulogic;
|
|
543
|
572
|
SSR : in std_ulogic;
|
|
544
|
573
|
WE : in std_ulogic
|
|
545
|
574
|
);
|
|
546
|
575
|
end component;
|
|
547
|
576
|
|
|
548
|
577
|
component RAMB16_S18
|
|
549
|
578
|
-- pragma translate_off
|
|
550
|
579
|
generic
|
|
551
|
580
|
(
|
|
552
|
581
|
INIT : bit_vector := X"00000";
|
|
553
|
582
|
SRVAL : bit_vector := X"00000";
|
|
554
|
583
|
write_mode : string := "WRITE_FIRST";
|
|
555
|
584
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
556
|
585
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
557
|
586
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
558
|
587
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
559
|
588
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
560
|
589
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
561
|
590
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
562
|
591
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
563
|
592
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
564
|
593
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
565
|
594
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
566
|
595
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
567
|
596
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
568
|
597
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
569
|
598
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
570
|
599
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
571
|
600
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
572
|
601
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
573
|
602
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
574
|
603
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
575
|
604
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
576
|
605
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
577
|
606
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
578
|
607
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
579
|
608
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
580
|
609
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
581
|
610
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
582
|
611
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
583
|
612
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
584
|
613
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
585
|
614
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
586
|
615
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
587
|
616
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
588
|
617
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
589
|
618
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
590
|
619
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
591
|
620
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
592
|
621
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
593
|
622
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
594
|
623
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
595
|
624
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
596
|
625
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
597
|
626
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
598
|
627
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
599
|
628
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
600
|
629
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
601
|
630
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
602
|
631
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
603
|
632
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
604
|
633
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
605
|
634
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
606
|
635
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
607
|
636
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
608
|
637
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
609
|
638
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
610
|
639
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
611
|
640
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
612
|
641
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
613
|
642
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
614
|
643
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
615
|
644
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
616
|
645
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
617
|
646
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
618
|
647
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
619
|
648
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
620
|
649
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
621
|
650
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
622
|
651
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
623
|
652
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
624
|
653
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
625
|
654
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
626
|
655
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
627
|
656
|
);
|
|
628
|
657
|
-- pragma translate_on
|
|
629
|
658
|
port (
|
|
630
|
659
|
DO : out std_logic_vector (15 downto 0);
|
|
631
|
660
|
DOP : out std_logic_vector (1 downto 0);
|
|
632
|
661
|
ADDR : in std_logic_vector (9 downto 0);
|
|
633
|
662
|
CLK : in std_ulogic;
|
|
634
|
663
|
DI : in std_logic_vector (15 downto 0);
|
|
635
|
664
|
DIP : in std_logic_vector (1 downto 0);
|
|
636
|
665
|
EN : in std_ulogic;
|
|
637
|
666
|
SSR : in std_ulogic;
|
|
638
|
667
|
WE : in std_ulogic
|
|
639
|
668
|
);
|
|
640
|
669
|
end component;
|
|
641
|
670
|
|
|
642
|
671
|
component RAMB16_S36
|
|
643
|
672
|
-- pragma translate_off
|
|
644
|
673
|
generic
|
|
645
|
674
|
(
|
|
646
|
675
|
INIT : bit_vector := X"000000000";
|
|
647
|
676
|
SRVAL : bit_vector := X"000000000";
|
|
648
|
677
|
WRITE_MODE : string := "WRITE_FIRST";
|
|
649
|
678
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
650
|
679
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
651
|
680
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
652
|
681
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
653
|
682
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
654
|
683
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
655
|
684
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
656
|
685
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
657
|
686
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
658
|
687
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
659
|
688
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
660
|
689
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
661
|
690
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
662
|
691
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
663
|
692
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
664
|
693
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
665
|
694
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
666
|
695
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
667
|
696
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
668
|
697
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
669
|
698
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
670
|
699
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
671
|
700
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
672
|
701
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
673
|
702
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
674
|
703
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
675
|
704
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
676
|
705
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
677
|
706
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
678
|
707
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
679
|
708
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
680
|
709
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
681
|
710
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
682
|
711
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
683
|
712
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
684
|
713
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
685
|
714
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
686
|
715
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
687
|
716
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
688
|
717
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
689
|
718
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
690
|
719
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
691
|
720
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
692
|
721
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
693
|
722
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
694
|
723
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
695
|
724
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
696
|
725
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
697
|
726
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
698
|
727
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
699
|
728
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
700
|
729
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
701
|
730
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
702
|
731
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
703
|
732
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
704
|
733
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
705
|
734
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
706
|
735
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
707
|
736
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
708
|
737
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
709
|
738
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
710
|
739
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
711
|
740
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
712
|
741
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
713
|
742
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
714
|
743
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
715
|
744
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
716
|
745
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
717
|
746
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
718
|
747
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
719
|
748
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
720
|
749
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
721
|
750
|
);
|
|
722
|
751
|
-- pragma translate_on
|
|
723
|
752
|
port (
|
|
724
|
753
|
DO : out std_logic_vector (31 downto 0);
|
|
725
|
754
|
DOP : out std_logic_vector (3 downto 0);
|
|
726
|
755
|
ADDR : in std_logic_vector (8 downto 0);
|
|
727
|
756
|
CLK : in std_ulogic;
|
|
728
|
757
|
DI : in std_logic_vector (31 downto 0);
|
|
729
|
758
|
DIP : in std_logic_vector (3 downto 0);
|
|
730
|
759
|
EN : in std_ulogic;
|
|
731
|
760
|
SSR : in std_ulogic;
|
|
732
|
761
|
WE : in std_ulogic
|
|
733
|
762
|
);
|
|
734
|
763
|
end component;
|
|
735
|
764
|
|
|
736
|
765
|
component RAMB16_S4_S4
|
|
737
|
766
|
-- pragma translate_off
|
|
738
|
767
|
generic
|
|
739
|
768
|
(
|
|
740
|
769
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
741
|
770
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
742
|
771
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
743
|
772
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
744
|
773
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
745
|
774
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
746
|
775
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
747
|
776
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
748
|
777
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
749
|
778
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
750
|
779
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
751
|
780
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
752
|
781
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
753
|
782
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
754
|
783
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
755
|
784
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
756
|
785
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
757
|
786
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
758
|
787
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
759
|
788
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
760
|
789
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
761
|
790
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
762
|
791
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
763
|
792
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
764
|
793
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
765
|
794
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
766
|
795
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
767
|
796
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
768
|
797
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
769
|
798
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
770
|
799
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
771
|
800
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
772
|
801
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
773
|
802
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
774
|
803
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
775
|
804
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
776
|
805
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
777
|
806
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
778
|
807
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
779
|
808
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
780
|
809
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
781
|
810
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
782
|
811
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
783
|
812
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
784
|
813
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
785
|
814
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
786
|
815
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
787
|
816
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
788
|
817
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
789
|
818
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
790
|
819
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
791
|
820
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
792
|
821
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
793
|
822
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
794
|
823
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
795
|
824
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
796
|
825
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
797
|
826
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
798
|
827
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
799
|
828
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
800
|
829
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
801
|
830
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
802
|
831
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
803
|
832
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
804
|
833
|
INIT_A : bit_vector := X"0";
|
|
805
|
834
|
INIT_B : bit_vector := X"0";
|
|
806
|
835
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
807
|
836
|
SRVAL_A : bit_vector := X"0";
|
|
808
|
837
|
SRVAL_B : bit_vector := X"0";
|
|
809
|
838
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
810
|
839
|
WRITE_MODE_B : string := "WRITE_FIRST"
|
|
811
|
840
|
);
|
|
812
|
841
|
-- pragma translate_on
|
|
813
|
842
|
port (
|
|
814
|
843
|
DOA : out std_logic_vector (3 downto 0);
|
|
815
|
844
|
DOB : out std_logic_vector (3 downto 0);
|
|
816
|
845
|
ADDRA : in std_logic_vector (11 downto 0);
|
|
817
|
846
|
ADDRB : in std_logic_vector (11 downto 0);
|
|
818
|
847
|
CLKA : in std_ulogic;
|
|
819
|
848
|
CLKB : in std_ulogic;
|
|
820
|
849
|
DIA : in std_logic_vector (3 downto 0);
|
|
821
|
850
|
DIB : in std_logic_vector (3 downto 0);
|
|
822
|
851
|
ENA : in std_ulogic;
|
|
823
|
852
|
ENB : in std_ulogic;
|
|
824
|
853
|
SSRA : in std_ulogic;
|
|
825
|
854
|
SSRB : in std_ulogic;
|
|
826
|
855
|
WEA : in std_ulogic;
|
|
827
|
856
|
WEB : in std_ulogic
|
|
828
|
857
|
);
|
|
829
|
858
|
end component;
|
|
830
|
859
|
|
|
831
|
860
|
component RAMB16_S1_S1
|
|
832
|
861
|
-- pragma translate_off
|
|
833
|
862
|
generic
|
|
834
|
863
|
(
|
|
835
|
864
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
836
|
865
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
837
|
866
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
838
|
867
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
839
|
868
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
840
|
869
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
841
|
870
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
842
|
871
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
843
|
872
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
844
|
873
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
845
|
874
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
846
|
875
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
847
|
876
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
848
|
877
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
849
|
878
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
850
|
879
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
851
|
880
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
852
|
881
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
853
|
882
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
854
|
883
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
855
|
884
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
856
|
885
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
857
|
886
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
858
|
887
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
859
|
888
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
860
|
889
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
861
|
890
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
862
|
891
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
863
|
892
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
864
|
893
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
865
|
894
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
866
|
895
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
867
|
896
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
868
|
897
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
869
|
898
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
870
|
899
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
871
|
900
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
872
|
901
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
873
|
902
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
874
|
903
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
875
|
904
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
876
|
905
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
877
|
906
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
878
|
907
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
879
|
908
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
880
|
909
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
881
|
910
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
882
|
911
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
883
|
912
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
884
|
913
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
885
|
914
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
886
|
915
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
887
|
916
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
888
|
917
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
889
|
918
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
890
|
919
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
891
|
920
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
892
|
921
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
893
|
922
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
894
|
923
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
895
|
924
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
896
|
925
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
897
|
926
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
898
|
927
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
899
|
928
|
INIT_A : bit_vector := X"0";
|
|
900
|
929
|
INIT_B : bit_vector := X"0";
|
|
901
|
930
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
902
|
931
|
SRVAL_A : bit_vector := X"0";
|
|
903
|
932
|
SRVAL_B : bit_vector := X"0";
|
|
904
|
933
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
905
|
934
|
WRITE_MODE_B : string := "WRITE_FIRST"
|
|
906
|
935
|
);
|
|
907
|
936
|
-- pragma translate_on
|
|
908
|
937
|
port (
|
|
909
|
938
|
DOA : out std_logic_vector (0 downto 0);
|
|
910
|
939
|
DOB : out std_logic_vector (0 downto 0);
|
|
911
|
940
|
ADDRA : in std_logic_vector (13 downto 0);
|
|
912
|
941
|
ADDRB : in std_logic_vector (13 downto 0);
|
|
913
|
942
|
CLKA : in std_ulogic;
|
|
914
|
943
|
CLKB : in std_ulogic;
|
|
915
|
944
|
DIA : in std_logic_vector (0 downto 0);
|
|
916
|
945
|
DIB : in std_logic_vector (0 downto 0);
|
|
917
|
946
|
ENA : in std_ulogic;
|
|
918
|
947
|
ENB : in std_ulogic;
|
|
919
|
948
|
SSRA : in std_ulogic;
|
|
920
|
949
|
SSRB : in std_ulogic;
|
|
921
|
950
|
WEA : in std_ulogic;
|
|
922
|
951
|
WEB : in std_ulogic
|
|
923
|
952
|
);
|
|
924
|
953
|
end component;
|
|
925
|
954
|
|
|
926
|
955
|
component RAMB16_S2_S2
|
|
927
|
956
|
-- pragma translate_off
|
|
928
|
957
|
generic
|
|
929
|
958
|
(
|
|
930
|
959
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
931
|
960
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
932
|
961
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
933
|
962
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
934
|
963
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
935
|
964
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
936
|
965
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
937
|
966
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
938
|
967
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
939
|
968
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
940
|
969
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
941
|
970
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
942
|
971
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
943
|
972
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
944
|
973
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
945
|
974
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
946
|
975
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
947
|
976
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
948
|
977
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
949
|
978
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
950
|
979
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
951
|
980
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
952
|
981
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
953
|
982
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
954
|
983
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
955
|
984
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
956
|
985
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
957
|
986
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
958
|
987
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
959
|
988
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
960
|
989
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
961
|
990
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
962
|
991
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
963
|
992
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
964
|
993
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
965
|
994
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
966
|
995
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
967
|
996
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
968
|
997
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
969
|
998
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
970
|
999
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
971
|
1000
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
972
|
1001
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
973
|
1002
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
974
|
1003
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
975
|
1004
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
976
|
1005
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
977
|
1006
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
978
|
1007
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
979
|
1008
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
980
|
1009
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
981
|
1010
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
982
|
1011
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
983
|
1012
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
984
|
1013
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
985
|
1014
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
986
|
1015
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
987
|
1016
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
988
|
1017
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
989
|
1018
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
990
|
1019
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
991
|
1020
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
992
|
1021
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
993
|
1022
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
994
|
1023
|
INIT_A : bit_vector := X"0";
|
|
995
|
1024
|
INIT_B : bit_vector := X"0";
|
|
996
|
1025
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
997
|
1026
|
SRVAL_A : bit_vector := X"0";
|
|
998
|
1027
|
SRVAL_B : bit_vector := X"0";
|
|
999
|
1028
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
1000
|
1029
|
WRITE_MODE_B : string := "WRITE_FIRST"
|
|
1001
|
1030
|
);
|
|
1002
|
1031
|
-- pragma translate_on
|
|
1003
|
1032
|
port (
|
|
1004
|
1033
|
DOA : out std_logic_vector (1 downto 0);
|
|
1005
|
1034
|
DOB : out std_logic_vector (1 downto 0);
|
|
1006
|
1035
|
ADDRA : in std_logic_vector (12 downto 0);
|
|
1007
|
1036
|
ADDRB : in std_logic_vector (12 downto 0);
|
|
1008
|
1037
|
CLKA : in std_ulogic;
|
|
1009
|
1038
|
CLKB : in std_ulogic;
|
|
1010
|
1039
|
DIA : in std_logic_vector (1 downto 0);
|
|
1011
|
1040
|
DIB : in std_logic_vector (1 downto 0);
|
|
1012
|
1041
|
ENA : in std_ulogic;
|
|
1013
|
1042
|
ENB : in std_ulogic;
|
|
1014
|
1043
|
SSRA : in std_ulogic;
|
|
1015
|
1044
|
SSRB : in std_ulogic;
|
|
1016
|
1045
|
WEA : in std_ulogic;
|
|
1017
|
1046
|
WEB : in std_ulogic
|
|
1018
|
1047
|
);
|
|
1019
|
1048
|
end component;
|
|
1020
|
1049
|
|
|
1021
|
1050
|
component RAMB16_S9_S9
|
|
1022
|
1051
|
-- pragma translate_off
|
|
1023
|
1052
|
generic
|
|
1024
|
1053
|
(
|
|
1025
|
1054
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1026
|
1055
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1027
|
1056
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1028
|
1057
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1029
|
1058
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1030
|
1059
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1031
|
1060
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1032
|
1061
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1033
|
1062
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1034
|
1063
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1035
|
1064
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1036
|
1065
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1037
|
1066
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1038
|
1067
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1039
|
1068
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1040
|
1069
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1041
|
1070
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1042
|
1071
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1043
|
1072
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1044
|
1073
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1045
|
1074
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1046
|
1075
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1047
|
1076
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1048
|
1077
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1049
|
1078
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1050
|
1079
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1051
|
1080
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1052
|
1081
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1053
|
1082
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1054
|
1083
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1055
|
1084
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1056
|
1085
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1057
|
1086
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1058
|
1087
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1059
|
1088
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1060
|
1089
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1061
|
1090
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1062
|
1091
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1063
|
1092
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1064
|
1093
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1065
|
1094
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1066
|
1095
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1067
|
1096
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1068
|
1097
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1069
|
1098
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1070
|
1099
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1071
|
1100
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1072
|
1101
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1073
|
1102
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1074
|
1103
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1075
|
1104
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1076
|
1105
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1077
|
1106
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1078
|
1107
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1079
|
1108
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1080
|
1109
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1081
|
1110
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1082
|
1111
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1083
|
1112
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1084
|
1113
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1085
|
1114
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1086
|
1115
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1087
|
1116
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1088
|
1117
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1089
|
1118
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1090
|
1119
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1091
|
1120
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1092
|
1121
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1093
|
1122
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1094
|
1123
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1095
|
1124
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1096
|
1125
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1097
|
1126
|
INIT_A : bit_vector := X"000";
|
|
1098
|
1127
|
INIT_B : bit_vector := X"000";
|
|
1099
|
1128
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
1100
|
1129
|
SRVAL_A : bit_vector := X"000";
|
|
1101
|
1130
|
SRVAL_B : bit_vector := X"000";
|
|
1102
|
1131
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
1103
|
1132
|
WRITE_MODE_B : string := "WRITE_FIRST"
|
|
1104
|
1133
|
);
|
|
1105
|
1134
|
-- pragma translate_on
|
|
1106
|
1135
|
port (
|
|
1107
|
1136
|
DOA : out std_logic_vector (7 downto 0);
|
|
1108
|
1137
|
DOB : out std_logic_vector (7 downto 0);
|
|
1109
|
1138
|
DOPA : out std_logic_vector (0 downto 0);
|
|
1110
|
1139
|
DOPB : out std_logic_vector (0 downto 0);
|
|
1111
|
1140
|
ADDRA : in std_logic_vector (10 downto 0);
|
|
1112
|
1141
|
ADDRB : in std_logic_vector (10 downto 0);
|
|
1113
|
1142
|
CLKA : in std_ulogic;
|
|
1114
|
1143
|
CLKB : in std_ulogic;
|
|
1115
|
1144
|
DIA : in std_logic_vector (7 downto 0);
|
|
1116
|
1145
|
DIB : in std_logic_vector (7 downto 0);
|
|
1117
|
1146
|
DIPA : in std_logic_vector (0 downto 0);
|
|
1118
|
1147
|
DIPB : in std_logic_vector (0 downto 0);
|
|
1119
|
1148
|
ENA : in std_ulogic;
|
|
1120
|
1149
|
ENB : in std_ulogic;
|
|
1121
|
1150
|
SSRA : in std_ulogic;
|
|
1122
|
1151
|
SSRB : in std_ulogic;
|
|
1123
|
1152
|
WEA : in std_ulogic;
|
|
1124
|
1153
|
WEB : in std_ulogic
|
|
1125
|
1154
|
);
|
|
1126
|
1155
|
end component;
|
|
1127
|
1156
|
|
|
1128
|
1157
|
component RAMB16_S18_S18
|
|
1129
|
1158
|
-- pragma translate_off
|
|
1130
|
1159
|
generic
|
|
1131
|
1160
|
(
|
|
1132
|
1161
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1133
|
1162
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1134
|
1163
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1135
|
1164
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1136
|
1165
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1137
|
1166
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1138
|
1167
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1139
|
1168
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1140
|
1169
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1141
|
1170
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1142
|
1171
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1143
|
1172
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1144
|
1173
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1145
|
1174
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1146
|
1175
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1147
|
1176
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1148
|
1177
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1149
|
1178
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1150
|
1179
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1151
|
1180
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1152
|
1181
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1153
|
1182
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1154
|
1183
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1155
|
1184
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1156
|
1185
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1157
|
1186
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1158
|
1187
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1159
|
1188
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1160
|
1189
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1161
|
1190
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1162
|
1191
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1163
|
1192
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1164
|
1193
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1165
|
1194
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1166
|
1195
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1167
|
1196
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1168
|
1197
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1169
|
1198
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1170
|
1199
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1171
|
1200
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1172
|
1201
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1173
|
1202
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1174
|
1203
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1175
|
1204
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1176
|
1205
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1177
|
1206
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1178
|
1207
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1179
|
1208
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1180
|
1209
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1181
|
1210
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1182
|
1211
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1183
|
1212
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1184
|
1213
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1185
|
1214
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1186
|
1215
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1187
|
1216
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1188
|
1217
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1189
|
1218
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1190
|
1219
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1191
|
1220
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1192
|
1221
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1193
|
1222
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1194
|
1223
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1195
|
1224
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1196
|
1225
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1197
|
1226
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1198
|
1227
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1199
|
1228
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1200
|
1229
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1201
|
1230
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1202
|
1231
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1203
|
1232
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1204
|
1233
|
INIT_A : bit_vector := X"00000";
|
|
1205
|
1234
|
INIT_B : bit_vector := X"00000";
|
|
1206
|
1235
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
1207
|
1236
|
SRVAL_A : bit_vector := X"00000";
|
|
1208
|
1237
|
SRVAL_B : bit_vector := X"00000";
|
|
1209
|
1238
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
1210
|
1239
|
WRITE_MODE_B : string := "WRITE_FIRST"
|
|
1211
|
1240
|
);
|
|
1212
|
1241
|
-- pragma translate_on
|
|
1213
|
1242
|
port (
|
|
1214
|
1243
|
DOA : out std_logic_vector (15 downto 0);
|
|
1215
|
1244
|
DOB : out std_logic_vector (15 downto 0);
|
|
1216
|
1245
|
DOPA : out std_logic_vector (1 downto 0);
|
|
1217
|
1246
|
DOPB : out std_logic_vector (1 downto 0);
|
|
1218
|
1247
|
ADDRA : in std_logic_vector (9 downto 0);
|
|
1219
|
1248
|
ADDRB : in std_logic_vector (9 downto 0);
|
|
1220
|
1249
|
CLKA : in std_ulogic;
|
|
1221
|
1250
|
CLKB : in std_ulogic;
|
|
1222
|
1251
|
DIA : in std_logic_vector (15 downto 0);
|
|
1223
|
1252
|
DIB : in std_logic_vector (15 downto 0);
|
|
1224
|
1253
|
DIPA : in std_logic_vector (1 downto 0);
|
|
1225
|
1254
|
DIPB : in std_logic_vector (1 downto 0);
|
|
1226
|
1255
|
ENA : in std_ulogic;
|
|
1227
|
1256
|
ENB : in std_ulogic;
|
|
1228
|
1257
|
SSRA : in std_ulogic;
|
|
1229
|
1258
|
SSRB : in std_ulogic;
|
|
1230
|
1259
|
WEA : in std_ulogic;
|
|
1231
|
1260
|
WEB : in std_ulogic);
|
|
1232
|
1261
|
end component;
|
|
1233
|
1262
|
|
|
1234
|
1263
|
component RAMB16_S36_S36
|
|
1235
|
1264
|
-- pragma translate_off
|
|
1236
|
1265
|
generic
|
|
1237
|
1266
|
(
|
|
1238
|
1267
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1239
|
1268
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1240
|
1269
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1241
|
1270
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1242
|
1271
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1243
|
1272
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1244
|
1273
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1245
|
1274
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1246
|
1275
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1247
|
1276
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1248
|
1277
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1249
|
1278
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1250
|
1279
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1251
|
1280
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1252
|
1281
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1253
|
1282
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1254
|
1283
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1255
|
1284
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1256
|
1285
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1257
|
1286
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1258
|
1287
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1259
|
1288
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1260
|
1289
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1261
|
1290
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1262
|
1291
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1263
|
1292
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1264
|
1293
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1265
|
1294
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1266
|
1295
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1267
|
1296
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1268
|
1297
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1269
|
1298
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1270
|
1299
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1271
|
1300
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1272
|
1301
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1273
|
1302
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1274
|
1303
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1275
|
1304
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1276
|
1305
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1277
|
1306
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1278
|
1307
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1279
|
1308
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1280
|
1309
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1281
|
1310
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1282
|
1311
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1283
|
1312
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1284
|
1313
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1285
|
1314
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1286
|
1315
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1287
|
1316
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1288
|
1317
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1289
|
1318
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1290
|
1319
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1291
|
1320
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1292
|
1321
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1293
|
1322
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1294
|
1323
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1295
|
1324
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1296
|
1325
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1297
|
1326
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1298
|
1327
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1299
|
1328
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1300
|
1329
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1301
|
1330
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1302
|
1331
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1303
|
1332
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1304
|
1333
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1305
|
1334
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1306
|
1335
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1307
|
1336
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1308
|
1337
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1309
|
1338
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
1310
|
1339
|
INIT_A : bit_vector := X"000000000";
|
|
1311
|
1340
|
INIT_B : bit_vector := X"000000000";
|
|
1312
|
1341
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
1313
|
1342
|
SRVAL_A : bit_vector := X"000000000";
|
|
1314
|
1343
|
SRVAL_B : bit_vector := X"000000000";
|
|
1315
|
1344
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
1316
|
1345
|
WRITE_MODE_B : string := "WRITE_FIRST"
|
|
1317
|
1346
|
);
|
|
1318
|
1347
|
-- pragma translate_on
|
|
1319
|
1348
|
port (
|
|
1320
|
1349
|
DOA : out std_logic_vector (31 downto 0);
|
|
1321
|
1350
|
DOB : out std_logic_vector (31 downto 0);
|
|
1322
|
1351
|
DOPA : out std_logic_vector (3 downto 0);
|
|
1323
|
1352
|
DOPB : out std_logic_vector (3 downto 0);
|
|
1324
|
1353
|
ADDRA : in std_logic_vector (8 downto 0);
|
|
1325
|
1354
|
ADDRB : in std_logic_vector (8 downto 0);
|
|
1326
|
1355
|
CLKA : in std_ulogic;
|
|
1327
|
1356
|
CLKB : in std_ulogic;
|
|
1328
|
1357
|
DIA : in std_logic_vector (31 downto 0);
|
|
1329
|
1358
|
DIB : in std_logic_vector (31 downto 0);
|
|
1330
|
1359
|
DIPA : in std_logic_vector (3 downto 0);
|
|
1331
|
1360
|
DIPB : in std_logic_vector (3 downto 0);
|
|
1332
|
1361
|
ENA : in std_ulogic;
|
|
1333
|
1362
|
ENB : in std_ulogic;
|
|
1334
|
1363
|
SSRA : in std_ulogic;
|
|
1335
|
1364
|
SSRB : in std_ulogic;
|
|
1336
|
1365
|
WEA : in std_ulogic;
|
|
1337
|
1366
|
WEB : in std_ulogic);
|
|
1338
|
1367
|
end component;
|
|
1339
|
1368
|
|
|
1340
|
1369
|
component DCM
|
|
1341
|
1370
|
generic (
|
|
1342
|
1371
|
CLKDV_DIVIDE : real := 2.0;
|
|
1343
|
1372
|
CLKFX_DIVIDE : integer := 1;
|
|
1344
|
1373
|
CLKFX_MULTIPLY : integer := 4;
|
|
1345
|
1374
|
CLKIN_DIVIDE_BY_2 : boolean := false;
|
|
1346
|
1375
|
CLKIN_PERIOD : real := 10.0;
|
|
1347
|
1376
|
CLKOUT_PHASE_SHIFT : string := "NONE";
|
|
1348
|
1377
|
CLK_FEEDBACK : string := "1X";
|
|
1349
|
1378
|
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
|
|
1350
|
1379
|
DFS_FREQUENCY_MODE : string := "LOW";
|
|
1351
|
1380
|
DLL_FREQUENCY_MODE : string := "LOW";
|
|
1352
|
1381
|
DSS_MODE : string := "NONE";
|
|
1353
|
1382
|
DUTY_CYCLE_CORRECTION : boolean := true;
|
|
1354
|
1383
|
FACTORY_JF : bit_vector := X"C080";
|
|
1355
|
1384
|
PHASE_SHIFT : integer := 0;
|
|
1356
|
1385
|
STARTUP_WAIT : boolean := false
|
|
1357
|
1386
|
);
|
|
1358
|
1387
|
port (
|
|
1359
|
1388
|
CLKFB : in std_logic;
|
|
1360
|
1389
|
CLKIN : in std_logic;
|
|
1361
|
1390
|
DSSEN : in std_logic;
|
|
1362
|
1391
|
PSCLK : in std_logic;
|
|
1363
|
1392
|
PSEN : in std_logic;
|
|
1364
|
1393
|
PSINCDEC : in std_logic;
|
|
1365
|
1394
|
RST : in std_logic;
|
|
1366
|
1395
|
CLK0 : out std_logic;
|
|
1367
|
1396
|
CLK90 : out std_logic;
|
|
1368
|
1397
|
CLK180 : out std_logic;
|
|
1369
|
1398
|
CLK270 : out std_logic;
|
|
1370
|
1399
|
CLK2X : out std_logic;
|
|
1371
|
1400
|
CLK2X180 : out std_logic;
|
|
1372
|
1401
|
CLKDV : out std_logic;
|
|
1373
|
1402
|
CLKFX : out std_logic;
|
|
1374
|
1403
|
CLKFX180 : out std_logic;
|
|
1375
|
1404
|
LOCKED : out std_logic;
|
|
1376
|
1405
|
PSDONE : out std_logic;
|
|
1377
|
1406
|
STATUS : out std_logic_vector (7 downto 0));
|
|
1378
|
1407
|
end component;
|
|
1379
|
1408
|
|
|
1380
|
1409
|
component DCM_SP
|
|
1381
|
1410
|
generic (
|
|
1382
|
1411
|
TimingChecksOn : boolean := true;
|
|
1383
|
1412
|
InstancePath : string := "*";
|
|
1384
|
1413
|
Xon : boolean := true;
|
|
1385
|
1414
|
MsgOn : boolean := false;
|
|
1386
|
1415
|
CLKDV_DIVIDE : real := 2.0;
|
|
1387
|
1416
|
CLKFX_DIVIDE : integer := 1;
|
|
1388
|
1417
|
CLKFX_MULTIPLY : integer := 4;
|
|
1389
|
1418
|
CLKIN_DIVIDE_BY_2 : boolean := false;
|
|
1390
|
1419
|
CLKIN_PERIOD : real := 10.0; --non-simulatable
|
|
1391
|
1420
|
CLKOUT_PHASE_SHIFT : string := "NONE";
|
|
1392
|
1421
|
CLK_FEEDBACK : string := "1X";
|
|
1393
|
1422
|
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
|
|
1394
|
1423
|
DFS_FREQUENCY_MODE : string := "LOW";
|
|
1395
|
1424
|
DLL_FREQUENCY_MODE : string := "LOW";
|
|
1396
|
1425
|
DSS_MODE : string := "NONE"; --non-simulatable
|
|
1397
|
1426
|
DUTY_CYCLE_CORRECTION : boolean := true;
|
|
1398
|
1427
|
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
|
|
1399
|
1428
|
PHASE_SHIFT : integer := 0;
|
|
1400
|
1429
|
STARTUP_WAIT : boolean := false --non-simulatable
|
|
1401
|
1430
|
);
|
|
1402
|
1431
|
|
|
1403
|
1432
|
port (
|
|
1404
|
1433
|
CLK0 : out std_ulogic := '0';
|
|
1405
|
1434
|
CLK180 : out std_ulogic := '0';
|
|
1406
|
1435
|
CLK270 : out std_ulogic := '0';
|
|
1407
|
1436
|
CLK2X : out std_ulogic := '0';
|
|
1408
|
1437
|
CLK2X180 : out std_ulogic := '0';
|
|
1409
|
1438
|
CLK90 : out std_ulogic := '0';
|
|
1410
|
1439
|
CLKDV : out std_ulogic := '0';
|
|
1411
|
1440
|
CLKFX : out std_ulogic := '0';
|
|
1412
|
1441
|
CLKFX180 : out std_ulogic := '0';
|
|
1413
|
1442
|
LOCKED : out std_ulogic := '0';
|
|
1414
|
1443
|
PSDONE : out std_ulogic := '0';
|
|
1415
|
1444
|
STATUS : out std_logic_vector(7 downto 0) := "00000000";
|
|
1416
|
1445
|
|
|
1417
|
1446
|
CLKFB : in std_ulogic := '0';
|
|
1418
|
1447
|
CLKIN : in std_ulogic := '0';
|
|
1419
|
1448
|
DSSEN : in std_ulogic := '0';
|
|
1420
|
1449
|
PSCLK : in std_ulogic := '0';
|
|
1421
|
1450
|
PSEN : in std_ulogic := '0';
|
|
1422
|
1451
|
PSINCDEC : in std_ulogic := '0';
|
|
1423
|
1452
|
RST : in std_ulogic := '0'
|
|
1424
|
1453
|
);
|
|
1425
|
1454
|
end component;
|
|
1426
|
1455
|
|
|
1427
|
1456
|
----- component PLLE2_ADV -----
|
|
1428
|
1457
|
component PLLE2_ADV
|
|
1429
|
1458
|
generic (
|
|
1430
|
1459
|
BANDWIDTH : string := "OPTIMIZED";
|
|
1431
|
1460
|
CLKFBOUT_MULT : integer := 5;
|
|
1432
|
1461
|
CLKFBOUT_PHASE : real := 0.0;
|
|
1433
|
1462
|
CLKIN1_PERIOD : real := 0.0;
|
|
1434
|
1463
|
CLKIN2_PERIOD : real := 0.0;
|
|
1435
|
1464
|
CLKOUT0_DIVIDE : integer := 1;
|
|
1436
|
1465
|
CLKOUT0_DUTY_CYCLE : real := 0.5;
|
|
1437
|
1466
|
CLKOUT0_PHASE : real := 0.0;
|
|
1438
|
1467
|
CLKOUT1_DIVIDE : integer := 1;
|
|
1439
|
1468
|
CLKOUT1_DUTY_CYCLE : real := 0.5;
|
|
1440
|
1469
|
CLKOUT1_PHASE : real := 0.0;
|
|
1441
|
1470
|
CLKOUT2_DIVIDE : integer := 1;
|
|
1442
|
1471
|
CLKOUT2_DUTY_CYCLE : real := 0.5;
|
|
1443
|
1472
|
CLKOUT2_PHASE : real := 0.0;
|
|
1444
|
1473
|
CLKOUT3_DIVIDE : integer := 1;
|
|
1445
|
1474
|
CLKOUT3_DUTY_CYCLE : real := 0.5;
|
|
1446
|
1475
|
CLKOUT3_PHASE : real := 0.0;
|
|
1447
|
1476
|
CLKOUT4_DIVIDE : integer := 1;
|
|
1448
|
1477
|
CLKOUT4_DUTY_CYCLE : real := 0.5;
|
|
1449
|
1478
|
CLKOUT4_PHASE : real := 0.0;
|
|
1450
|
1479
|
CLKOUT5_DIVIDE : integer := 1;
|
|
1451
|
1480
|
CLKOUT5_DUTY_CYCLE : real := 0.5;
|
|
1452
|
1481
|
CLKOUT5_PHASE : real := 0.0;
|
|
1453
|
1482
|
COMPENSATION : string := "ZHOLD";
|
|
1454
|
1483
|
DIVCLK_DIVIDE : integer := 1;
|
|
1455
|
1484
|
REF_JITTER1 : real := 0.0;
|
|
1456
|
1485
|
REF_JITTER2 : real := 0.0;
|
|
1457
|
1486
|
STARTUP_WAIT : string := "FALSE"
|
|
1458
|
1487
|
);
|
|
1459
|
1488
|
port (
|
|
1460
|
1489
|
CLKFBOUT : out std_ulogic := '0';
|
|
1461
|
1490
|
CLKOUT0 : out std_ulogic := '0';
|
|
1462
|
1491
|
CLKOUT1 : out std_ulogic := '0';
|
|
1463
|
1492
|
CLKOUT2 : out std_ulogic := '0';
|
|
1464
|
1493
|
CLKOUT3 : out std_ulogic := '0';
|
|
1465
|
1494
|
CLKOUT4 : out std_ulogic := '0';
|
|
1466
|
1495
|
CLKOUT5 : out std_ulogic := '0';
|
|
1467
|
1496
|
DO : out std_logic_vector (15 downto 0);
|
|
1468
|
1497
|
DRDY : out std_ulogic := '0';
|
|
1469
|
1498
|
LOCKED : out std_ulogic := '0';
|
|
1470
|
1499
|
CLKFBIN : in std_ulogic;
|
|
1471
|
1500
|
CLKIN1 : in std_ulogic;
|
|
1472
|
1501
|
CLKIN2 : in std_ulogic;
|
|
1473
|
1502
|
CLKINSEL : in std_ulogic;
|
|
1474
|
1503
|
DADDR : in std_logic_vector(6 downto 0);
|
|
1475
|
1504
|
DCLK : in std_ulogic;
|
|
1476
|
1505
|
DEN : in std_ulogic;
|
|
1477
|
1506
|
DI : in std_logic_vector(15 downto 0);
|
|
1478
|
1507
|
DWE : in std_ulogic;
|
|
1479
|
1508
|
PWRDWN : in std_ulogic;
|
|
1480
|
1509
|
RST : in std_ulogic
|
|
1481
|
1510
|
);
|
|
1482
|
1511
|
end component;
|
|
1483
|
1512
|
|
|
1484
|
1513
|
component PLL_ADV
|
|
1485
|
1514
|
generic (
|
|
1486
|
1515
|
BANDWIDTH : string := "OPTIMIZED";
|
|
1487
|
1516
|
CLKFBOUT_DESKEW_ADJUST : string := "NONE";
|
|
1488
|
1517
|
CLKFBOUT_MULT : integer := 1;
|
|
1489
|
1518
|
CLKFBOUT_PHASE : real := 0.0;
|
|
1490
|
1519
|
CLKIN1_PERIOD : real := 0.000;
|
|
1491
|
1520
|
CLKIN2_PERIOD : real := 0.000;
|
|
1492
|
1521
|
CLKOUT0_DESKEW_ADJUST : string := "NONE";
|
|
1493
|
1522
|
CLKOUT0_DIVIDE : integer := 1;
|
|
1494
|
1523
|
CLKOUT0_DUTY_CYCLE : real := 0.5;
|
|
1495
|
1524
|
CLKOUT0_PHASE : real := 0.0;
|
|
1496
|
1525
|
CLKOUT1_DESKEW_ADJUST : string := "NONE";
|
|
1497
|
1526
|
CLKOUT1_DIVIDE : integer := 1;
|
|
1498
|
1527
|
CLKOUT1_DUTY_CYCLE : real := 0.5;
|
|
1499
|
1528
|
CLKOUT1_PHASE : real := 0.0;
|
|
1500
|
1529
|
CLKOUT2_DESKEW_ADJUST : string := "NONE";
|
|
1501
|
1530
|
CLKOUT2_DIVIDE : integer := 1;
|
|
1502
|
1531
|
CLKOUT2_DUTY_CYCLE : real := 0.5;
|
|
1503
|
1532
|
CLKOUT2_PHASE : real := 0.0;
|
|
1504
|
1533
|
CLKOUT3_DESKEW_ADJUST : string := "NONE";
|
|
1505
|
1534
|
CLKOUT3_DIVIDE : integer := 1;
|
|
1506
|
1535
|
CLKOUT3_DUTY_CYCLE : real := 0.5;
|
|
1507
|
1536
|
CLKOUT3_PHASE : real := 0.0;
|
|
1508
|
1537
|
CLKOUT4_DESKEW_ADJUST : string := "NONE";
|
|
1509
|
1538
|
CLKOUT4_DIVIDE : integer := 1;
|
|
1510
|
1539
|
CLKOUT4_DUTY_CYCLE : real := 0.5;
|
|
1511
|
1540
|
CLKOUT4_PHASE : real := 0.0;
|
|
1512
|
1541
|
CLKOUT5_DESKEW_ADJUST : string := "NONE";
|
|
1513
|
1542
|
CLKOUT5_DIVIDE : integer := 1;
|
|
1514
|
1543
|
CLKOUT5_DUTY_CYCLE : real := 0.5;
|
|
1515
|
1544
|
CLKOUT5_PHASE : real := 0.0;
|
|
1516
|
1545
|
CLK_FEEDBACK : string := "CLKFBOUT";
|
|
1517
|
1546
|
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
|
|
1518
|
1547
|
DIVCLK_DIVIDE : integer := 1;
|
|
1519
|
1548
|
EN_REL : boolean := FALSE;
|
|
1520
|
1549
|
PLL_PMCD_MODE : boolean := FALSE;
|
|
1521
|
1550
|
REF_JITTER : real := 0.100;
|
|
1522
|
1551
|
RESET_ON_LOSS_OF_LOCK : boolean := FALSE;
|
|
1523
|
1552
|
RST_DEASSERT_CLK : string := "CLKIN1";
|
|
1524
|
1553
|
SIM_DEVICE : string := "VIRTEX5"
|
|
1525
|
1554
|
);
|
|
1526
|
1555
|
port (
|
|
1527
|
1556
|
CLKFBDCM : out std_ulogic := '0';
|
|
1528
|
1557
|
CLKFBOUT : out std_ulogic := '0';
|
|
1529
|
1558
|
CLKOUT0 : out std_ulogic := '0';
|
|
1530
|
1559
|
CLKOUT1 : out std_ulogic := '0';
|
|
1531
|
1560
|
CLKOUT2 : out std_ulogic := '0';
|
|
1532
|
1561
|
CLKOUT3 : out std_ulogic := '0';
|
|
1533
|
1562
|
CLKOUT4 : out std_ulogic := '0';
|
|
1534
|
1563
|
CLKOUT5 : out std_ulogic := '0';
|
|
1535
|
1564
|
CLKOUTDCM0 : out std_ulogic := '0';
|
|
1536
|
1565
|
CLKOUTDCM1 : out std_ulogic := '0';
|
|
1537
|
1566
|
CLKOUTDCM2 : out std_ulogic := '0';
|
|
1538
|
1567
|
CLKOUTDCM3 : out std_ulogic := '0';
|
|
1539
|
1568
|
CLKOUTDCM4 : out std_ulogic := '0';
|
|
1540
|
1569
|
CLKOUTDCM5 : out std_ulogic := '0';
|
|
1541
|
1570
|
DO : out std_logic_vector(15 downto 0);
|
|
1542
|
1571
|
DRDY : out std_ulogic := '0';
|
|
1543
|
1572
|
LOCKED : out std_ulogic := '0';
|
|
1544
|
1573
|
CLKFBIN : in std_ulogic;
|
|
1545
|
1574
|
CLKIN1 : in std_ulogic;
|
|
1546
|
1575
|
CLKIN2 : in std_ulogic;
|
|
1547
|
1576
|
CLKINSEL : in std_ulogic;
|
|
1548
|
1577
|
DADDR : in std_logic_vector(4 downto 0);
|
|
1549
|
1578
|
DCLK : in std_ulogic;
|
|
1550
|
1579
|
DEN : in std_ulogic;
|
|
1551
|
1580
|
DI : in std_logic_vector(15 downto 0);
|
|
1552
|
1581
|
DWE : in std_ulogic;
|
|
1553
|
1582
|
REL : in std_ulogic;
|
|
1554
|
1583
|
RST : in std_ulogic
|
|
1555
|
1584
|
);
|
|
1556
|
1585
|
end component;
|
|
1557
|
1586
|
|
|
1558
|
1587
|
component PLL_BASE
|
|
1559
|
1588
|
generic (
|
|
1560
|
1589
|
BANDWIDTH : string := "OPTIMIZED";
|
|
1561
|
1590
|
CLKFBOUT_MULT : integer := 1;
|
|
1562
|
1591
|
CLKFBOUT_PHASE : real := 0.0;
|
|
1563
|
1592
|
CLKIN_PERIOD : real := 0.000;
|
|
1564
|
1593
|
CLKOUT0_DIVIDE : integer := 1;
|
|
1565
|
1594
|
CLKOUT0_DUTY_CYCLE : real := 0.5;
|
|
1566
|
1595
|
CLKOUT0_PHASE : real := 0.0;
|
|
1567
|
1596
|
CLKOUT1_DIVIDE : integer := 1;
|
|
1568
|
1597
|
CLKOUT1_DUTY_CYCLE : real := 0.5;
|
|
1569
|
1598
|
CLKOUT1_PHASE : real := 0.0;
|
|
1570
|
1599
|
CLKOUT2_DIVIDE : integer := 1;
|
|
1571
|
1600
|
CLKOUT2_DUTY_CYCLE : real := 0.5;
|
|
1572
|
1601
|
CLKOUT2_PHASE : real := 0.0;
|
|
1573
|
1602
|
CLKOUT3_DIVIDE : integer := 1;
|
|
1574
|
1603
|
CLKOUT3_DUTY_CYCLE : real := 0.5;
|
|
1575
|
1604
|
CLKOUT3_PHASE : real := 0.0;
|
|
1576
|
1605
|
CLKOUT4_DIVIDE : integer := 1;
|
|
1577
|
1606
|
CLKOUT4_DUTY_CYCLE : real := 0.5;
|
|
1578
|
1607
|
CLKOUT4_PHASE : real := 0.0;
|
|
1579
|
1608
|
CLKOUT5_DIVIDE : integer := 1;
|
|
1580
|
1609
|
CLKOUT5_DUTY_CYCLE : real := 0.5;
|
|
1581
|
1610
|
CLKOUT5_PHASE : real := 0.0;
|
|
1582
|
1611
|
CLK_FEEDBACK : string := "CLKFBOUT";
|
|
1583
|
1612
|
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
|
|
1584
|
1613
|
DIVCLK_DIVIDE : integer := 1;
|
|
1585
|
1614
|
REF_JITTER : real := 0.100;
|
|
1586
|
1615
|
RESET_ON_LOSS_OF_LOCK : boolean := FALSE
|
|
1587
|
1616
|
);
|
|
1588
|
1617
|
port (
|
|
1589
|
1618
|
CLKFBOUT : out std_ulogic;
|
|
1590
|
1619
|
CLKOUT0 : out std_ulogic;
|
|
1591
|
1620
|
CLKOUT1 : out std_ulogic;
|
|
1592
|
1621
|
CLKOUT2 : out std_ulogic;
|
|
1593
|
1622
|
CLKOUT3 : out std_ulogic;
|
|
1594
|
1623
|
CLKOUT4 : out std_ulogic;
|
|
1595
|
1624
|
CLKOUT5 : out std_ulogic;
|
|
1596
|
1625
|
LOCKED : out std_ulogic;
|
|
1597
|
1626
|
CLKFBIN : in std_ulogic;
|
|
1598
|
1627
|
CLKIN : in std_ulogic;
|
|
1599
|
1628
|
RST : in std_ulogic
|
|
1600
|
1629
|
);
|
|
1601
|
1630
|
end component;
|
|
1602
|
1631
|
|
|
1603
|
1632
|
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
|
|
1604
|
1633
|
component BUFG port (O : out std_logic; I : in std_logic); end component;
|
|
1605
|
1634
|
component BUFGP port (O : out std_logic; I : in std_logic); end component;
|
|
1606
|
1635
|
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
|
|
1607
|
1636
|
|
|
1608
|
1637
|
component IBUFG generic(
|
|
1609
|
1638
|
CAPACITANCE : string := "DONT_CARE";
|
|
1610
|
1639
|
IBUF_LOW_PWR : boolean := TRUE;
|
|
1611
|
1640
|
IOSTANDARD : string := "LVCMOS25");
|
|
1612
|
1641
|
port (O : out std_logic; I : in std_logic); end component;
|
|
1613
|
1642
|
component IBUF generic(
|
|
1614
|
1643
|
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
|
|
1615
|
1644
|
port (O : out std_ulogic; I : in std_ulogic); end component;
|
|
1616
|
1645
|
component IOBUF generic (
|
|
1617
|
1646
|
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
|
|
1618
|
1647
|
IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE;
|
|
1619
|
1648
|
IFD_DELAY_VALUE : string := "AUTO";
|
|
1620
|
1649
|
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
|
|
1621
|
1650
|
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
|
|
1622
|
1651
|
component OBUF generic (
|
|
1623
|
1652
|
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
|
|
1624
|
1653
|
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
|
|
1625
|
1654
|
port (O : out std_ulogic; I : in std_ulogic); end component;
|
|
1626
|
1655
|
component OBUFT generic (
|
|
1627
|
1656
|
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
|
|
1628
|
1657
|
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
|
|
1629
|
1658
|
port (O : out std_ulogic; I, T : in std_ulogic); end component;
|
|
1630
|
1659
|
|
|
1631
|
1660
|
component CLKDLL
|
|
1632
|
1661
|
port (
|
|
1633
|
1662
|
CLK0 : out std_ulogic;
|
|
1634
|
1663
|
CLK180 : out std_ulogic;
|
|
1635
|
1664
|
CLK270 : out std_ulogic;
|
|
1636
|
1665
|
CLK2X : out std_ulogic;
|
|
1637
|
1666
|
CLK90 : out std_ulogic;
|
|
1638
|
1667
|
CLKDV : out std_ulogic;
|
|
1639
|
1668
|
LOCKED : out std_ulogic;
|
|
1640
|
1669
|
CLKFB : in std_ulogic;
|
|
1641
|
1670
|
CLKIN : in std_ulogic;
|
|
1642
|
1671
|
RST : in std_ulogic);
|
|
1643
|
1672
|
end component;
|
|
1644
|
1673
|
|
|
1645
|
1674
|
component CLKDLLHF
|
|
1646
|
1675
|
port (
|
|
1647
|
1676
|
CLK0 : out std_ulogic := '0';
|
|
1648
|
1677
|
CLK180 : out std_ulogic := '0';
|
|
1649
|
1678
|
CLKDV : out std_ulogic := '0';
|
|
1650
|
1679
|
LOCKED : out std_ulogic := '0';
|
|
1651
|
1680
|
CLKFB : in std_ulogic := '0';
|
|
1652
|
1681
|
CLKIN : in std_ulogic := '0';
|
|
1653
|
1682
|
RST : in std_ulogic := '0');
|
|
1654
|
1683
|
end component;
|
|
1655
|
1684
|
|
|
1656
|
1685
|
component BSCAN_VIRTEX
|
|
1657
|
1686
|
port (CAPTURE : out STD_ULOGIC;
|
|
1658
|
1687
|
DRCK1 : out STD_ULOGIC;
|
|
1659
|
1688
|
DRCK2 : out STD_ULOGIC;
|
|
1660
|
1689
|
RESET : out STD_ULOGIC;
|
|
1661
|
1690
|
SEL1 : out STD_ULOGIC;
|
|
1662
|
1691
|
SEL2 : out STD_ULOGIC;
|
|
1663
|
1692
|
SHIFT : out STD_ULOGIC;
|
|
1664
|
1693
|
TDI : out STD_ULOGIC;
|
|
1665
|
1694
|
UPDATE : out STD_ULOGIC;
|
|
1666
|
1695
|
TDO1 : in STD_ULOGIC;
|
|
1667
|
1696
|
TDO2 : in STD_ULOGIC);
|
|
1668
|
1697
|
end component;
|
|
1669
|
1698
|
|
|
1670
|
1699
|
component BSCAN_VIRTEX2
|
|
1671
|
1700
|
port (CAPTURE : out STD_ULOGIC;
|
|
1672
|
1701
|
DRCK1 : out STD_ULOGIC;
|
|
1673
|
1702
|
DRCK2 : out STD_ULOGIC;
|
|
1674
|
1703
|
RESET : out STD_ULOGIC;
|
|
1675
|
1704
|
SEL1 : out STD_ULOGIC;
|
|
1676
|
1705
|
SEL2 : out STD_ULOGIC;
|
|
1677
|
1706
|
SHIFT : out STD_ULOGIC;
|
|
1678
|
1707
|
TDI : out STD_ULOGIC;
|
|
1679
|
1708
|
UPDATE : out STD_ULOGIC;
|
|
1680
|
1709
|
TDO1 : in STD_ULOGIC;
|
|
1681
|
1710
|
TDO2 : in STD_ULOGIC);
|
|
1682
|
1711
|
end component;
|
|
1683
|
1712
|
|
|
1684
|
1713
|
component BSCAN_SPARTAN3
|
|
1685
|
1714
|
port (CAPTURE : out STD_ULOGIC;
|
|
1686
|
1715
|
DRCK1 : out STD_ULOGIC;
|
|
1687
|
1716
|
DRCK2 : out STD_ULOGIC;
|
|
1688
|
1717
|
RESET : out STD_ULOGIC;
|
|
1689
|
1718
|
SEL1 : out STD_ULOGIC;
|
|
1690
|
1719
|
SEL2 : out STD_ULOGIC;
|
|
1691
|
1720
|
SHIFT : out STD_ULOGIC;
|
|
1692
|
1721
|
TDI : out STD_ULOGIC;
|
|
1693
|
1722
|
UPDATE : out STD_ULOGIC;
|
|
1694
|
1723
|
TDO1 : in STD_ULOGIC;
|
|
1695
|
1724
|
TDO2 : in STD_ULOGIC);
|
|
1696
|
1725
|
end component;
|
|
1697
|
1726
|
|
|
1698
|
1727
|
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
|
|
1699
|
1728
|
port ( CAPTURE : out std_ulogic;
|
|
1700
|
1729
|
DRCK : out std_ulogic;
|
|
1701
|
1730
|
RESET : out std_ulogic;
|
|
1702
|
1731
|
SEL : out std_ulogic;
|
|
1703
|
1732
|
SHIFT : out std_ulogic;
|
|
1704
|
1733
|
TDI : out std_ulogic;
|
|
1705
|
1734
|
UPDATE : out std_ulogic;
|
|
1706
|
1735
|
TDO : in std_ulogic);
|
|
1707
|
1736
|
end component;
|
|
1708
|
1737
|
|
|
1709
|
1738
|
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
|
|
1710
|
1739
|
port ( CAPTURE : out std_ulogic;
|
|
1711
|
1740
|
DRCK : out std_ulogic;
|
|
1712
|
1741
|
RESET : out std_ulogic;
|
|
1713
|
1742
|
SEL : out std_ulogic;
|
|
1714
|
1743
|
SHIFT : out std_ulogic;
|
|
1715
|
1744
|
TDI : out std_ulogic;
|
|
1716
|
1745
|
UPDATE : out std_ulogic;
|
|
1717
|
1746
|
TDO : in std_ulogic);
|
|
1718
|
1747
|
end component;
|
|
1719
|
1748
|
|
|
1720
|
1749
|
component IBUFDS
|
|
1721
|
1750
|
generic (
|
|
1722
|
1751
|
CAPACITANCE : string := "DONT_CARE";
|
|
1723
|
1752
|
DIFF_TERM : boolean := FALSE;
|
|
1724
|
1753
|
IBUF_DELAY_VALUE : string := "0";
|
|
1725
|
1754
|
IFD_DELAY_VALUE : string := "AUTO";
|
|
1726
|
1755
|
IOSTANDARD : string := "DEFAULT");
|
|
1727
|
1756
|
port (
|
|
1728
|
1757
|
O : out std_ulogic;
|
|
1729
|
1758
|
I : in std_ulogic;
|
|
1730
|
1759
|
IB : in std_ulogic
|
|
1731
|
1760
|
);
|
|
1732
|
1761
|
end component;
|
|
1733
|
1762
|
|
|
1734
|
1763
|
|
|
1735
|
1764
|
component IBUFDS_LVDS_25
|
|
1736
|
1765
|
port ( O : out std_ulogic;
|
|
1737
|
1766
|
I : in std_ulogic;
|
|
1738
|
1767
|
IB : in std_ulogic);
|
|
1739
|
1768
|
end component;
|
|
1740
|
1769
|
|
|
1741
|
1770
|
component IBUFGDS_LVDS_25
|
|
1742
|
1771
|
port ( O : out std_ulogic;
|
|
1743
|
1772
|
I : in std_ulogic;
|
|
1744
|
1773
|
IB : in std_ulogic);
|
|
1745
|
1774
|
end component;
|
|
1746
|
1775
|
|
|
1747
|
1776
|
component IOBUFDS
|
|
1748
|
1777
|
generic(
|
|
1749
|
1778
|
CAPACITANCE : string := "DONT_CARE";
|
|
1750
|
1779
|
IBUF_DELAY_VALUE : string := "0";
|
|
1751
|
1780
|
IFD_DELAY_VALUE : string := "AUTO";
|
|
1752
|
1781
|
IOSTANDARD : string := "DEFAULT");
|
|
1753
|
1782
|
port (
|
|
1754
|
1783
|
O : out std_ulogic;
|
|
1755
|
1784
|
IO : inout std_ulogic;
|
|
1756
|
1785
|
IOB : inout std_ulogic;
|
|
1757
|
1786
|
I : in std_ulogic;
|
|
1758
|
1787
|
T : in std_ulogic
|
|
1759
|
1788
|
);
|
|
1760
|
1789
|
end component;
|
|
1761
|
1790
|
|
|
1762
|
1791
|
component OBUFDS
|
|
1763
|
1792
|
generic(
|
|
1764
|
1793
|
CAPACITANCE : string := "DONT_CARE";
|
|
1765
|
1794
|
IOSTANDARD : string := "DEFAULT";
|
|
1766
|
1795
|
SLEW : string := "SLOW"
|
|
1767
|
1796
|
);
|
|
1768
|
1797
|
port(
|
|
1769
|
1798
|
O : out std_ulogic;
|
|
1770
|
1799
|
OB : out std_ulogic;
|
|
1771
|
1800
|
I : in std_ulogic
|
|
1772
|
1801
|
);
|
|
1773
|
1802
|
end component;
|
|
1774
|
1803
|
|
|
1775
|
1804
|
component OBUFDS_LVDS_25
|
|
1776
|
1805
|
port ( O : out std_ulogic;
|
|
1777
|
1806
|
OB : out std_ulogic;
|
|
1778
|
1807
|
I : in std_ulogic);
|
|
1779
|
1808
|
end component;
|
|
1780
|
1809
|
|
|
1781
|
1810
|
component OBUFTDS_LVDS_25
|
|
1782
|
1811
|
port ( O : out std_ulogic;
|
|
1783
|
1812
|
OB : out std_ulogic;
|
|
1784
|
1813
|
I : in std_ulogic;
|
|
1785
|
1814
|
T : in std_ulogic);
|
|
1786
|
1815
|
end component;
|
|
1787
|
1816
|
|
|
1788
|
1817
|
component IBUFGDS is
|
|
1789
|
1818
|
generic( CAPACITANCE : string := "DONT_CARE";
|
|
1790
|
1819
|
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
|
|
1791
|
1820
|
IBUF_LOW_PWR : boolean := TRUE;
|
|
1792
|
1821
|
IOSTANDARD : string := "DEFAULT");
|
|
1793
|
1822
|
port (O : out std_logic; I, IB : in std_logic);
|
|
1794
|
1823
|
end component;
|
|
1795
|
1824
|
|
|
1796
|
1825
|
component IBUFDS_LVDS_33
|
|
1797
|
1826
|
port ( O : out std_ulogic;
|
|
1798
|
1827
|
I : in std_ulogic;
|
|
1799
|
1828
|
IB : in std_ulogic);
|
|
1800
|
1829
|
end component;
|
|
1801
|
1830
|
|
|
1802
|
1831
|
component IBUFGDS_LVDS_33
|
|
1803
|
1832
|
port ( O : out std_ulogic;
|
|
1804
|
1833
|
I : in std_ulogic;
|
|
1805
|
1834
|
IB : in std_ulogic);
|
|
1806
|
1835
|
end component;
|
|
1807
|
1836
|
|
|
1808
|
1837
|
component OBUFDS_LVDS_33
|
|
1809
|
1838
|
port ( O : out std_ulogic;
|
|
1810
|
1839
|
OB : out std_ulogic;
|
|
1811
|
1840
|
I : in std_ulogic);
|
|
1812
|
1841
|
end component;
|
|
1813
|
1842
|
|
|
1814
|
1843
|
component OBUFTDS_LVDS_33
|
|
1815
|
1844
|
port ( O : out std_ulogic;
|
|
1816
|
1845
|
OB : out std_ulogic;
|
|
1817
|
1846
|
I : in std_ulogic;
|
|
1818
|
1847
|
T : in std_ulogic);
|
|
1819
|
1848
|
end component;
|
|
1820
|
1849
|
|
|
1821
|
1850
|
component FDCPE
|
|
1822
|
1851
|
generic ( INIT : bit := '0');
|
|
1823
|
1852
|
port (
|
|
1824
|
1853
|
Q : out std_ulogic;
|
|
1825
|
1854
|
C : in std_ulogic;
|
|
1826
|
1855
|
CE : in std_ulogic;
|
|
1827
|
1856
|
CLR : in std_ulogic;
|
|
1828
|
1857
|
D : in std_ulogic;
|
|
1829
|
1858
|
PRE : in std_ulogic);
|
|
1830
|
1859
|
end component;
|
|
1831
|
1860
|
|
|
1832
|
1861
|
component IDDR
|
|
1833
|
1862
|
generic (
|
|
1834
|
1863
|
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
|
|
1835
|
1864
|
INIT_Q1 : bit := '0';
|
|
1836
|
1865
|
INIT_Q2 : bit := '0';
|
|
1837
|
1866
|
SRTYPE : string := "SYNC");
|
|
1838
|
1867
|
port
|
|
1839
|
1868
|
(
|
|
1840
|
1869
|
Q1 : out std_ulogic;
|
|
1841
|
1870
|
Q2 : out std_ulogic;
|
|
1842
|
1871
|
C : in std_ulogic;
|
|
1843
|
1872
|
CE : in std_ulogic;
|
|
1844
|
1873
|
D : in std_ulogic;
|
|
1845
|
1874
|
R : in std_ulogic;
|
|
1846
|
1875
|
S : in std_ulogic);
|
|
1847
|
1876
|
end component;
|
|
1848
|
1877
|
|
|
1849
|
1878
|
component ODDR
|
|
1850
|
1879
|
generic (
|
|
1851
|
1880
|
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
|
|
1852
|
1881
|
INIT : bit := '0';
|
|
1853
|
1882
|
SRTYPE : string := "SYNC");
|
|
1854
|
1883
|
port (
|
|
1855
|
1884
|
Q : out std_ulogic;
|
|
1856
|
1885
|
C : in std_ulogic;
|
|
1857
|
1886
|
CE : in std_ulogic;
|
|
1858
|
1887
|
D1 : in std_ulogic;
|
|
1859
|
1888
|
D2 : in std_ulogic;
|
|
1860
|
1889
|
R : in std_ulogic;
|
|
1861
|
1890
|
S : in std_ulogic);
|
|
1862
|
1891
|
end component;
|
|
1863
|
1892
|
|
|
1864
|
1893
|
component IFDDRRSE
|
|
1865
|
1894
|
port (
|
|
1866
|
1895
|
Q0 : out std_ulogic;
|
|
1867
|
1896
|
Q1 : out std_ulogic;
|
|
1868
|
1897
|
C0 : in std_ulogic;
|
|
1869
|
1898
|
C1 : in std_ulogic;
|
|
1870
|
1899
|
CE : in std_ulogic;
|
|
1871
|
1900
|
D : in std_ulogic;
|
|
1872
|
1901
|
R : in std_ulogic;
|
|
1873
|
1902
|
S : in std_ulogic);
|
|
1874
|
1903
|
end component;
|
|
1875
|
1904
|
|
|
1876
|
1905
|
component OFDDRRSE
|
|
1877
|
1906
|
port (
|
|
1878
|
1907
|
Q : out std_ulogic;
|
|
1879
|
1908
|
C0 : in std_ulogic;
|
|
1880
|
1909
|
C1 : in std_ulogic;
|
|
1881
|
1910
|
CE : in std_ulogic;
|
|
1882
|
1911
|
D0 : in std_ulogic;
|
|
1883
|
1912
|
D1 : in std_ulogic;
|
|
1884
|
1913
|
R : in std_ulogic;
|
|
1885
|
1914
|
S : in std_ulogic);
|
|
1886
|
1915
|
end component;
|
|
1887
|
1916
|
|
|
1888
|
1917
|
component FDDRRSE
|
|
1889
|
1918
|
generic ( INIT : bit := '0');
|
|
1890
|
1919
|
port ( Q : out std_ulogic;
|
|
1891
|
1920
|
C0 : in std_ulogic;
|
|
1892
|
1921
|
C1 : in std_ulogic;
|
|
1893
|
1922
|
CE : in std_ulogic;
|
|
1894
|
1923
|
D0 : in std_ulogic;
|
|
1895
|
1924
|
D1 : in std_ulogic;
|
|
1896
|
1925
|
R : in std_ulogic;
|
|
1897
|
1926
|
S : in std_ulogic);
|
|
1898
|
1927
|
end component;
|
|
1899
|
1928
|
|
|
1900
|
1929
|
|
|
1901
|
1930
|
component IDELAY
|
|
1902
|
1931
|
generic ( IOBDELAY_TYPE : string := "DEFAULT";
|
|
1903
|
1932
|
IOBDELAY_VALUE : integer := 0);
|
|
1904
|
1933
|
port ( O : out std_ulogic;
|
|
1905
|
1934
|
C : in std_ulogic;
|
|
1906
|
1935
|
CE : in std_ulogic;
|
|
1907
|
1936
|
I : in std_ulogic;
|
|
1908
|
1937
|
INC : in std_ulogic;
|
|
1909
|
1938
|
RST : in std_ulogic);
|
|
1910
|
1939
|
end component;
|
|
1911
|
1940
|
|
|
1912
|
1941
|
component IDELAYCTRL
|
|
1913
|
1942
|
port ( RDY : out std_ulogic;
|
|
1914
|
1943
|
REFCLK : in std_ulogic;
|
|
1915
|
1944
|
RST : in std_ulogic);
|
|
1916
|
1945
|
end component;
|
|
1917
|
1946
|
|
|
1918
|
1947
|
component BUFIO
|
|
1919
|
1948
|
port ( O : out std_ulogic;
|
|
1920
|
1949
|
I : in std_ulogic);
|
|
1921
|
1950
|
end component;
|
|
1922
|
1951
|
|
|
1923
|
1952
|
component BUFR
|
|
1924
|
1953
|
generic ( BUFR_DIVIDE : string := "BYPASS";
|
|
1925
|
1954
|
SIM_DEVICE : string := "VIRTEX4");
|
|
1926
|
1955
|
port ( O : out std_ulogic;
|
|
1927
|
1956
|
CE : in std_ulogic;
|
|
1928
|
1957
|
CLR : in std_ulogic;
|
|
1929
|
1958
|
I : in std_ulogic);
|
|
1930
|
1959
|
end component;
|
|
1931
|
1960
|
|
|
1932
|
1961
|
component ODDR2
|
|
1933
|
1962
|
generic
|
|
1934
|
1963
|
(
|
|
1935
|
1964
|
DDR_ALIGNMENT : string := "NONE";
|
|
1936
|
1965
|
INIT : bit := '0';
|
|
1937
|
1966
|
SRTYPE : string := "SYNC"
|
|
1938
|
1967
|
);
|
|
1939
|
1968
|
port
|
|
1940
|
1969
|
(
|
|
1941
|
1970
|
Q : out std_ulogic;
|
|
1942
|
1971
|
C0 : in std_ulogic;
|
|
1943
|
1972
|
C1 : in std_ulogic;
|
|
1944
|
1973
|
CE : in std_ulogic;
|
|
1945
|
1974
|
D0 : in std_ulogic;
|
|
1946
|
1975
|
D1 : in std_ulogic;
|
|
1947
|
1976
|
R : in std_ulogic;
|
|
1948
|
1977
|
S : in std_ulogic
|
|
1949
|
1978
|
);
|
|
1950
|
1979
|
end component;
|
|
1951
|
1980
|
|
|
1952
|
1981
|
component IDDR2
|
|
1953
|
1982
|
generic
|
|
1954
|
1983
|
(
|
|
1955
|
1984
|
DDR_ALIGNMENT : string := "NONE";
|
|
1956
|
1985
|
INIT_Q0 : bit := '0';
|
|
1957
|
1986
|
INIT_Q1 : bit := '0';
|
|
1958
|
1987
|
SRTYPE : string := "SYNC"
|
|
1959
|
1988
|
);
|
|
1960
|
1989
|
port
|
|
1961
|
1990
|
(
|
|
1962
|
1991
|
Q0 : out std_ulogic;
|
|
1963
|
1992
|
Q1 : out std_ulogic;
|
|
1964
|
1993
|
C0 : in std_ulogic;
|
|
1965
|
1994
|
C1 : in std_ulogic;
|
|
1966
|
1995
|
CE : in std_ulogic;
|
|
1967
|
1996
|
D : in std_ulogic;
|
|
1968
|
1997
|
R : in std_ulogic;
|
|
1969
|
1998
|
S : in std_ulogic
|
|
1970
|
1999
|
);
|
|
1971
|
2000
|
end component;
|
|
1972
|
2001
|
|
|
1973
|
2002
|
component SYSMON
|
|
1974
|
2003
|
generic
|
|
1975
|
2004
|
(
|
|
1976
|
2005
|
INIT_40 : bit_vector := X"0000";
|
|
1977
|
2006
|
INIT_41 : bit_vector := X"0000";
|
|
1978
|
2007
|
INIT_42 : bit_vector := X"0800";
|
|
1979
|
2008
|
INIT_43 : bit_vector := X"0000";
|
|
1980
|
2009
|
INIT_44 : bit_vector := X"0000";
|
|
1981
|
2010
|
INIT_45 : bit_vector := X"0000";
|
|
1982
|
2011
|
INIT_46 : bit_vector := X"0000";
|
|
1983
|
2012
|
INIT_47 : bit_vector := X"0000";
|
|
1984
|
2013
|
INIT_48 : bit_vector := X"0000";
|
|
1985
|
2014
|
INIT_49 : bit_vector := X"0000";
|
|
1986
|
2015
|
INIT_4A : bit_vector := X"0000";
|
|
1987
|
2016
|
INIT_4B : bit_vector := X"0000";
|
|
1988
|
2017
|
INIT_4C : bit_vector := X"0000";
|
|
1989
|
2018
|
INIT_4D : bit_vector := X"0000";
|
|
1990
|
2019
|
INIT_4E : bit_vector := X"0000";
|
|
1991
|
2020
|
INIT_4F : bit_vector := X"0000";
|
|
1992
|
2021
|
INIT_50 : bit_vector := X"0000";
|
|
1993
|
2022
|
INIT_51 : bit_vector := X"0000";
|
|
1994
|
2023
|
INIT_52 : bit_vector := X"0000";
|
|
1995
|
2024
|
INIT_53 : bit_vector := X"0000";
|
|
1996
|
2025
|
INIT_54 : bit_vector := X"0000";
|
|
1997
|
2026
|
INIT_55 : bit_vector := X"0000";
|
|
1998
|
2027
|
INIT_56 : bit_vector := X"0000";
|
|
1999
|
2028
|
INIT_57 : bit_vector := X"0000";
|
|
2000
|
2029
|
SIM_MONITOR_FILE : string := "design.txt"
|
|
2001
|
2030
|
);
|
|
2002
|
2031
|
port
|
|
2003
|
2032
|
(
|
|
2004
|
2033
|
ALM : out std_logic_vector(2 downto 0);
|
|
2005
|
2034
|
BUSY : out std_ulogic;
|
|
2006
|
2035
|
CHANNEL : out std_logic_vector(4 downto 0);
|
|
2007
|
2036
|
DO : out std_logic_vector(15 downto 0);
|
|
2008
|
2037
|
DRDY : out std_ulogic;
|
|
2009
|
2038
|
EOC : out std_ulogic;
|
|
2010
|
2039
|
EOS : out std_ulogic;
|
|
2011
|
2040
|
JTAGBUSY : out std_ulogic;
|
|
2012
|
2041
|
JTAGLOCKED : out std_ulogic;
|
|
2013
|
2042
|
JTAGMODIFIED : out std_ulogic;
|
|
2014
|
2043
|
OT : out std_ulogic;
|
|
2015
|
2044
|
CONVST : in std_ulogic;
|
|
2016
|
2045
|
CONVSTCLK : in std_ulogic;
|
|
2017
|
2046
|
DADDR : in std_logic_vector(6 downto 0);
|
|
2018
|
2047
|
DCLK : in std_ulogic;
|
|
2019
|
2048
|
DEN : in std_ulogic;
|
|
2020
|
2049
|
DI : in std_logic_vector(15 downto 0);
|
|
2021
|
2050
|
DWE : in std_ulogic;
|
|
2022
|
2051
|
RESET : in std_ulogic;
|
|
2023
|
2052
|
VAUXN : in std_logic_vector(15 downto 0);
|
|
2024
|
2053
|
VAUXP : in std_logic_vector(15 downto 0);
|
|
2025
|
2054
|
VN : in std_ulogic;
|
|
2026
|
2055
|
VP : in std_ulogic
|
|
2027
|
2056
|
);
|
|
2028
|
2057
|
end component;
|
|
2029
|
2058
|
|
|
2030
|
2059
|
component FDRSE
|
|
2031
|
2060
|
generic ( INIT : bit := '0');
|
|
2032
|
2061
|
port ( Q : out std_ulogic;
|
|
2033
|
2062
|
C : in std_ulogic;
|
|
2034
|
2063
|
CE : in std_ulogic;
|
|
2035
|
2064
|
D : in std_ulogic;
|
|
2036
|
2065
|
R : in std_ulogic;
|
|
2037
|
2066
|
S : in std_ulogic);
|
|
2038
|
2067
|
end component;
|
|
2039
|
2068
|
|
|
2040
|
2069
|
component FDR
|
|
2041
|
2070
|
generic ( INIT : bit := '0');
|
|
2042
|
2071
|
port ( Q : out std_ulogic;
|
|
2043
|
2072
|
C : in std_ulogic;
|
|
2044
|
2073
|
D : in std_ulogic;
|
|
2045
|
2074
|
R : in std_ulogic);
|
|
2046
|
2075
|
end component;
|
|
2047
|
2076
|
|
|
2048
|
2077
|
component FDRE
|
|
2049
|
2078
|
generic ( INIT : bit := '0');
|
|
2050
|
2079
|
port ( Q : out std_ulogic;
|
|
2051
|
2080
|
C : in std_ulogic;
|
|
2052
|
2081
|
CE : in std_ulogic;
|
|
2053
|
2082
|
D : in std_ulogic;
|
|
2054
|
2083
|
R : in std_ulogic);
|
|
2055
|
2084
|
end component;
|
|
2056
|
2085
|
|
|
2057
|
2086
|
component FD
|
|
2058
|
2087
|
generic ( INIT : bit := '0');
|
|
2059
|
2088
|
port ( Q : out std_ulogic;
|
|
2060
|
2089
|
C : in std_ulogic;
|
|
2061
|
2090
|
D : in std_ulogic);
|
|
2062
|
2091
|
end component;
|
|
2063
|
2092
|
|
|
2064
|
2093
|
component FDRS
|
|
2065
|
2094
|
generic ( INIT : bit := '0');
|
|
2066
|
2095
|
port ( Q : out std_ulogic;
|
|
2067
|
2096
|
C : in std_ulogic;
|
|
2068
|
2097
|
D : in std_ulogic;
|
|
2069
|
2098
|
R : in std_ulogic;
|
|
2070
|
2099
|
S : in std_ulogic);
|
|
2071
|
2100
|
end component;
|
|
2072
|
2101
|
|
|
2073
|
2102
|
component FDE
|
|
2074
|
2103
|
generic ( INIT : bit := '0');
|
|
2075
|
2104
|
port ( Q : out std_ulogic;
|
|
2076
|
2105
|
C : in std_ulogic;
|
|
2077
|
2106
|
CE : in std_ulogic;
|
|
2078
|
2107
|
D : in std_ulogic);
|
|
2079
|
2108
|
end component;
|
|
2080
|
2109
|
|
|
2081
|
2110
|
component MUXF5
|
|
2082
|
2111
|
port ( O : out std_ulogic;
|
|
2083
|
2112
|
I0 : in std_ulogic;
|
|
2084
|
2113
|
I1 : in std_ulogic;
|
|
2085
|
2114
|
S : in std_ulogic);
|
|
2086
|
2115
|
end component;
|
|
2087
|
2116
|
|
|
2088
|
2117
|
component VCC
|
|
2089
|
2118
|
port ( P : out std_ulogic := '1');
|
|
2090
|
2119
|
end component;
|
|
2091
|
2120
|
|
|
2092
|
2121
|
component GND
|
|
2093
|
2122
|
port ( G : out std_ulogic := '0');
|
|
2094
|
2123
|
end component;
|
|
2095
|
2124
|
|
|
2096
|
2125
|
component INV
|
|
2097
|
2126
|
port
|
|
2098
|
2127
|
(
|
|
2099
|
2128
|
O : out std_ulogic;
|
|
2100
|
2129
|
I : in std_ulogic
|
|
2101
|
2130
|
);
|
|
2102
|
2131
|
end component;
|
|
2103
|
2132
|
component LUT2_L
|
|
2104
|
2133
|
generic
|
|
2105
|
2134
|
(
|
|
2106
|
2135
|
INIT : bit_vector := X"0"
|
|
2107
|
2136
|
);
|
|
2108
|
2137
|
port
|
|
2109
|
2138
|
(
|
|
2110
|
2139
|
LO : out std_ulogic;
|
|
2111
|
2140
|
I0 : in std_ulogic;
|
|
2112
|
2141
|
I1 : in std_ulogic
|
|
2113
|
2142
|
);
|
|
2114
|
2143
|
end component;
|
|
2115
|
2144
|
component LUT4
|
|
2116
|
2145
|
generic
|
|
2117
|
2146
|
(
|
|
2118
|
2147
|
INIT : bit_vector := X"0000"
|
|
2119
|
2148
|
);
|
|
2120
|
2149
|
port
|
|
2121
|
2150
|
(
|
|
2122
|
2151
|
O : out std_ulogic;
|
|
2123
|
2152
|
I0 : in std_ulogic;
|
|
2124
|
2153
|
I1 : in std_ulogic;
|
|
2125
|
2154
|
I2 : in std_ulogic;
|
|
2126
|
2155
|
I3 : in std_ulogic
|
|
2127
|
2156
|
);
|
|
2128
|
2157
|
end component;
|
|
2129
|
2158
|
component LUT3
|
|
2130
|
2159
|
generic
|
|
2131
|
2160
|
(
|
|
2132
|
2161
|
INIT : bit_vector := X"00"
|
|
2133
|
2162
|
);
|
|
2134
|
2163
|
port
|
|
2135
|
2164
|
(
|
|
2136
|
2165
|
O : out std_ulogic;
|
|
2137
|
2166
|
I0 : in std_ulogic;
|
|
2138
|
2167
|
I1 : in std_ulogic;
|
|
2139
|
2168
|
I2 : in std_ulogic
|
|
2140
|
2169
|
);
|
|
2141
|
2170
|
end component;
|
|
2142
|
2171
|
component LUT2
|
|
2143
|
2172
|
generic
|
|
2144
|
2173
|
(
|
|
2145
|
2174
|
INIT : bit_vector := X"0"
|
|
2146
|
2175
|
);
|
|
2147
|
2176
|
port
|
|
2148
|
2177
|
(
|
|
2149
|
2178
|
O : out std_ulogic;
|
|
2150
|
2179
|
I0 : in std_ulogic;
|
|
2151
|
2180
|
I1 : in std_ulogic
|
|
2152
|
2181
|
);
|
|
2153
|
2182
|
end component;
|
|
2154
|
2183
|
component FDC
|
|
2155
|
2184
|
generic
|
|
2156
|
2185
|
(
|
|
2157
|
2186
|
INIT : bit := '0'
|
|
2158
|
2187
|
);
|
|
2159
|
2188
|
port
|
|
2160
|
2189
|
(
|
|
2161
|
2190
|
Q : out std_ulogic;
|
|
2162
|
2191
|
C : in std_ulogic;
|
|
2163
|
2192
|
CLR : in std_ulogic;
|
|
2164
|
2193
|
D : in std_ulogic
|
|
2165
|
2194
|
);
|
|
2166
|
2195
|
end component;
|
|
2167
|
2196
|
component LUT3_L
|
|
2168
|
2197
|
generic
|
|
2169
|
2198
|
(
|
|
2170
|
2199
|
INIT : bit_vector := X"00"
|
|
2171
|
2200
|
);
|
|
2172
|
2201
|
port
|
|
2173
|
2202
|
(
|
|
2174
|
2203
|
LO : out std_ulogic;
|
|
2175
|
2204
|
I0 : in std_ulogic;
|
|
2176
|
2205
|
I1 : in std_ulogic;
|
|
2177
|
2206
|
I2 : in std_ulogic
|
|
2178
|
2207
|
);
|
|
2179
|
2208
|
end component;
|
|
2180
|
2209
|
component LUT1
|
|
2181
|
2210
|
generic
|
|
2182
|
2211
|
(
|
|
2183
|
2212
|
INIT : bit_vector := X"0"
|
|
2184
|
2213
|
);
|
|
2185
|
2214
|
port
|
|
2186
|
2215
|
(
|
|
2187
|
2216
|
O : out std_ulogic;
|
|
2188
|
2217
|
I0 : in std_ulogic
|
|
2189
|
2218
|
);
|
|
2190
|
2219
|
end component;
|
|
2191
|
2220
|
component LUT4_L
|
|
2192
|
2221
|
generic
|
|
2193
|
2222
|
(
|
|
2194
|
2223
|
INIT : bit_vector := X"0000"
|
|
2195
|
2224
|
);
|
|
2196
|
2225
|
port
|
|
2197
|
2226
|
(
|
|
2198
|
2227
|
LO : out std_ulogic;
|
|
2199
|
2228
|
I0 : in std_ulogic;
|
|
2200
|
2229
|
I1 : in std_ulogic;
|
|
2201
|
2230
|
I2 : in std_ulogic;
|
|
2202
|
2231
|
I3 : in std_ulogic
|
|
2203
|
2232
|
);
|
|
2204
|
2233
|
end component;
|
|
2205
|
2234
|
component FDCE
|
|
2206
|
2235
|
generic
|
|
2207
|
2236
|
(
|
|
2208
|
2237
|
INIT : bit := '0'
|
|
2209
|
2238
|
);
|
|
2210
|
2239
|
port
|
|
2211
|
2240
|
(
|
|
2212
|
2241
|
Q : out std_ulogic;
|
|
2213
|
2242
|
C : in std_ulogic;
|
|
2214
|
2243
|
CE : in std_ulogic;
|
|
2215
|
2244
|
CLR : in std_ulogic;
|
|
2216
|
2245
|
D : in std_ulogic
|
|
2217
|
2246
|
);
|
|
2218
|
2247
|
end component;
|
|
2219
|
2248
|
component FDC_1
|
|
2220
|
2249
|
generic
|
|
2221
|
2250
|
(
|
|
2222
|
2251
|
INIT : bit := '0'
|
|
2223
|
2252
|
);
|
|
2224
|
2253
|
port
|
|
2225
|
2254
|
(
|
|
2226
|
2255
|
Q : out std_ulogic;
|
|
2227
|
2256
|
C : in std_ulogic;
|
|
2228
|
2257
|
CLR : in std_ulogic;
|
|
2229
|
2258
|
D : in std_ulogic
|
|
2230
|
2259
|
);
|
|
2231
|
2260
|
end component;
|
|
2232
|
2261
|
component FDP
|
|
2233
|
2262
|
generic
|
|
2234
|
2263
|
(
|
|
2235
|
2264
|
INIT : bit := '1'
|
|
2236
|
2265
|
);
|
|
2237
|
2266
|
port
|
|
2238
|
2267
|
(
|
|
2239
|
2268
|
Q : out std_ulogic;
|
|
2240
|
2269
|
C : in std_ulogic;
|
|
2241
|
2270
|
D : in std_ulogic;
|
|
2242
|
2271
|
PRE : in std_ulogic
|
|
2243
|
2272
|
);
|
|
2244
|
2273
|
end component;
|
|
2245
|
2274
|
component FDS
|
|
2246
|
2275
|
generic
|
|
2247
|
2276
|
(
|
|
2248
|
2277
|
INIT : bit := '1'
|
|
2249
|
2278
|
);
|
|
2250
|
2279
|
port
|
|
2251
|
2280
|
(
|
|
2252
|
2281
|
Q : out std_ulogic;
|
|
2253
|
2282
|
C : in std_ulogic;
|
|
2254
|
2283
|
D : in std_ulogic;
|
|
2255
|
2284
|
S : in std_ulogic
|
|
2256
|
2285
|
);
|
|
2257
|
2286
|
end component;
|
|
2258
|
2287
|
component MUXCY
|
|
2259
|
2288
|
port
|
|
2260
|
2289
|
(
|
|
2261
|
2290
|
O : out std_ulogic;
|
|
2262
|
2291
|
CI : in std_ulogic;
|
|
2263
|
2292
|
DI : in std_ulogic;
|
|
2264
|
2293
|
S : in std_ulogic
|
|
2265
|
2294
|
);
|
|
2266
|
2295
|
end component;
|
|
2267
|
2296
|
component LUT1_L
|
|
2268
|
2297
|
generic
|
|
2269
|
2298
|
(
|
|
2270
|
2299
|
INIT : bit_vector := X"0"
|
|
2271
|
2300
|
);
|
|
2272
|
2301
|
port
|
|
2273
|
2302
|
(
|
|
2274
|
2303
|
LO : out std_ulogic;
|
|
2275
|
2304
|
I0 : in std_ulogic
|
|
2276
|
2305
|
);
|
|
2277
|
2306
|
end component;
|
|
2278
|
2307
|
component MUXF6
|
|
2279
|
2308
|
port
|
|
2280
|
2309
|
(
|
|
2281
|
2310
|
O : out std_ulogic;
|
|
2282
|
2311
|
I0 : in std_ulogic;
|
|
2283
|
2312
|
I1 : in std_ulogic;
|
|
2284
|
2313
|
S : in std_ulogic
|
|
2285
|
2314
|
);
|
|
2286
|
2315
|
end component;
|
|
2287
|
2316
|
component MUXF5_D
|
|
2288
|
2317
|
port
|
|
2289
|
2318
|
(
|
|
2290
|
2319
|
LO : out std_ulogic;
|
|
2291
|
2320
|
O : out std_ulogic;
|
|
2292
|
2321
|
I0 : in std_ulogic;
|
|
2293
|
2322
|
I1 : in std_ulogic;
|
|
2294
|
2323
|
S : in std_ulogic
|
|
2295
|
2324
|
);
|
|
2296
|
2325
|
end component;
|
|
2297
|
2326
|
component XORCY
|
|
2298
|
2327
|
port
|
|
2299
|
2328
|
(
|
|
2300
|
2329
|
O : out std_ulogic;
|
|
2301
|
2330
|
CI : in std_ulogic;
|
|
2302
|
2331
|
LI : in std_ulogic
|
|
2303
|
2332
|
);
|
|
2304
|
2333
|
end component;
|
|
2305
|
2334
|
component MUXCY_L
|
|
2306
|
2335
|
port
|
|
2307
|
2336
|
(
|
|
2308
|
2337
|
LO : out std_ulogic;
|
|
2309
|
2338
|
CI : in std_ulogic;
|
|
2310
|
2339
|
DI : in std_ulogic;
|
|
2311
|
2340
|
S : in std_ulogic
|
|
2312
|
2341
|
);
|
|
2313
|
2342
|
end component;
|
|
2314
|
2343
|
component FDSE
|
|
2315
|
2344
|
generic
|
|
2316
|
2345
|
(
|
|
2317
|
2346
|
INIT : bit := '1'
|
|
2318
|
2347
|
);
|
|
2319
|
2348
|
port
|
|
2320
|
2349
|
(
|
|
2321
|
2350
|
Q : out std_ulogic;
|
|
2322
|
2351
|
C : in std_ulogic;
|
|
2323
|
2352
|
CE : in std_ulogic;
|
|
2324
|
2353
|
D : in std_ulogic;
|
|
2325
|
2354
|
S : in std_ulogic
|
|
2326
|
2355
|
);
|
|
2327
|
2356
|
end component;
|
|
2328
|
2357
|
component MULT_AND
|
|
2329
|
2358
|
port
|
|
2330
|
2359
|
(
|
|
2331
|
2360
|
LO : out std_ulogic;
|
|
2332
|
2361
|
I0 : in std_ulogic;
|
|
2333
|
2362
|
I1 : in std_ulogic
|
|
2334
|
2363
|
);
|
|
2335
|
2364
|
end component;
|
|
2336
|
2365
|
|
|
2337
|
2366
|
component SRL16E
|
|
2338
|
2367
|
generic
|
|
2339
|
2368
|
(
|
|
2340
|
2369
|
INIT : bit_vector := X"0000"
|
|
2341
|
2370
|
);
|
|
2342
|
2371
|
port
|
|
2343
|
2372
|
(
|
|
2344
|
2373
|
Q : out STD_ULOGIC;
|
|
2345
|
2374
|
A0 : in STD_ULOGIC;
|
|
2346
|
2375
|
A1 : in STD_ULOGIC;
|
|
2347
|
2376
|
A2 : in STD_ULOGIC;
|
|
2348
|
2377
|
A3 : in STD_ULOGIC;
|
|
2349
|
2378
|
CE : in STD_ULOGIC;
|
|
2350
|
2379
|
CLK : in STD_ULOGIC;
|
|
2351
|
2380
|
D : in STD_ULOGIC
|
|
2352
|
2381
|
);
|
|
2353
|
2382
|
end component;
|
|
2354
|
2383
|
|
|
2355
|
2384
|
component ROM256X1
|
|
2356
|
2385
|
generic
|
|
2357
|
2386
|
(
|
|
2358
|
2387
|
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
2359
|
2388
|
);
|
|
2360
|
2389
|
port
|
|
2361
|
2390
|
(
|
|
2362
|
2391
|
O : out std_ulogic;
|
|
2363
|
2392
|
A0 : in std_ulogic;
|
|
2364
|
2393
|
A1 : in std_ulogic;
|
|
2365
|
2394
|
A2 : in std_ulogic;
|
|
2366
|
2395
|
A3 : in std_ulogic;
|
|
2367
|
2396
|
A4 : in std_ulogic;
|
|
2368
|
2397
|
A5 : in std_ulogic;
|
|
2369
|
2398
|
A6 : in std_ulogic;
|
|
2370
|
2399
|
A7 : in std_ulogic
|
|
2371
|
2400
|
);
|
|
2372
|
2401
|
end component;
|
|
2373
|
2402
|
|
|
2374
|
2403
|
component FDPE
|
|
2375
|
2404
|
generic
|
|
2376
|
2405
|
(
|
|
2377
|
2406
|
INIT : bit := '1'
|
|
2378
|
2407
|
);
|
|
2379
|
2408
|
port
|
|
2380
|
2409
|
(
|
|
2381
|
2410
|
Q : out std_ulogic;
|
|
2382
|
2411
|
C : in std_ulogic;
|
|
2383
|
2412
|
CE : in std_ulogic;
|
|
2384
|
2413
|
D : in std_ulogic;
|
|
2385
|
2414
|
PRE : in std_ulogic
|
|
2386
|
2415
|
);
|
|
2387
|
2416
|
end component;
|
|
2388
|
2417
|
|
|
2389
|
2418
|
component MULT18X18
|
|
2390
|
2419
|
port
|
|
2391
|
2420
|
(
|
|
2392
|
2421
|
P : out std_logic_vector (35 downto 0);
|
|
2393
|
2422
|
A : in std_logic_vector (17 downto 0);
|
|
2394
|
2423
|
B : in std_logic_vector (17 downto 0)
|
|
2395
|
2424
|
);
|
|
2396
|
2425
|
end component;
|
|
2397
|
2426
|
|
|
2398
|
2427
|
component MULT18X18S
|
|
2399
|
2428
|
port
|
|
2400
|
2429
|
(
|
|
2401
|
2430
|
P : out std_logic_vector (35 downto 0);
|
|
2402
|
2431
|
A : in std_logic_vector (17 downto 0);
|
|
2403
|
2432
|
B : in std_logic_vector (17 downto 0);
|
|
2404
|
2433
|
C : in std_ulogic;
|
|
2405
|
2434
|
CE : in std_ulogic;
|
|
2406
|
2435
|
R : in std_ulogic
|
|
2407
|
2436
|
);
|
|
2408
|
2437
|
end component;
|
|
2409
|
2438
|
|
|
2410
|
2439
|
component MUXF7
|
|
2411
|
2440
|
port
|
|
2412
|
2441
|
(
|
|
2413
|
2442
|
O : out std_ulogic;
|
|
2414
|
2443
|
I0 : in std_ulogic;
|
|
2415
|
2444
|
I1 : in std_ulogic;
|
|
2416
|
2445
|
S : in std_ulogic
|
|
2417
|
2446
|
);
|
|
2418
|
2447
|
end component;
|
|
2419
|
2448
|
|
|
2420
|
2449
|
component IODELAY
|
|
2421
|
2450
|
generic
|
|
2422
|
2451
|
(
|
|
2423
|
2452
|
DELAY_SRC : string := "I";
|
|
2424
|
2453
|
HIGH_PERFORMANCE_MODE : boolean := true;
|
|
2425
|
2454
|
IDELAY_TYPE : string := "DEFAULT";
|
|
2426
|
2455
|
IDELAY_VALUE : integer := 0;
|
|
2427
|
2456
|
ODELAY_VALUE : integer := 0;
|
|
2428
|
2457
|
REFCLK_FREQUENCY : real := 200.0;
|
|
2429
|
2458
|
SIGNAL_PATTERN : string := "DATA"
|
|
2430
|
2459
|
);
|
|
2431
|
2460
|
port
|
|
2432
|
2461
|
(
|
|
2433
|
2462
|
DATAOUT : out std_ulogic;
|
|
2434
|
2463
|
C : in std_ulogic;
|
|
2435
|
2464
|
CE : in std_ulogic;
|
|
2436
|
2465
|
DATAIN : in std_ulogic;
|
|
2437
|
2466
|
IDATAIN : in std_ulogic;
|
|
2438
|
2467
|
INC : in std_ulogic;
|
|
2439
|
2468
|
ODATAIN : in std_ulogic;
|
|
2440
|
2469
|
RST : in std_ulogic;
|
|
2441
|
2470
|
T : in std_ulogic
|
|
2442
|
2471
|
);
|
|
2443
|
2472
|
end component;
|
|
2444
|
2473
|
|
|
2445
|
2474
|
component IODELAY2
|
|
2446
|
2475
|
generic (
|
|
2447
|
2476
|
COUNTER_WRAPAROUND : string := "WRAPAROUND";
|
|
2448
|
2477
|
DATA_RATE : string := "SDR";
|
|
2449
|
2478
|
DELAY_SRC : string := "IO";
|
|
2450
|
2479
|
IDELAY2_VALUE : integer := 0;
|
|
2451
|
2480
|
IDELAY_MODE : string := "NORMAL";
|
|
2452
|
2481
|
IDELAY_TYPE : string := "DEFAULT";
|
|
2453
|
2482
|
IDELAY_VALUE : integer := 0;
|
|
2454
|
2483
|
ODELAY_VALUE : integer := 0;
|
|
2455
|
2484
|
SERDES_MODE : string := "NONE";
|
|
2456
|
2485
|
SIM_TAPDELAY_VALUE : integer := 75
|
|
2457
|
2486
|
);
|
|
2458
|
2487
|
port (
|
|
2459
|
2488
|
BUSY : out std_ulogic;
|
|
2460
|
2489
|
DATAOUT : out std_ulogic;
|
|
2461
|
2490
|
DATAOUT2 : out std_ulogic;
|
|
2462
|
2491
|
DOUT : out std_ulogic;
|
|
2463
|
2492
|
TOUT : out std_ulogic;
|
|
2464
|
2493
|
CAL : in std_ulogic;
|
|
2465
|
2494
|
CE : in std_ulogic;
|
|
2466
|
2495
|
CLK : in std_ulogic;
|
|
2467
|
2496
|
IDATAIN : in std_ulogic;
|
|
2468
|
2497
|
INC : in std_ulogic;
|
|
2469
|
2498
|
IOCLK0 : in std_ulogic;
|
|
2470
|
2499
|
IOCLK1 : in std_ulogic;
|
|
2471
|
2500
|
ODATAIN : in std_ulogic;
|
|
2472
|
2501
|
RST : in std_ulogic;
|
|
2473
|
2502
|
T : in std_ulogic
|
|
2474
|
2503
|
);
|
|
2475
|
2504
|
end component;
|
|
2476
|
2505
|
|
|
2477
|
2506
|
component ISERDES
|
|
2478
|
2507
|
generic
|
|
2479
|
2508
|
(
|
|
2480
|
2509
|
BITSLIP_ENABLE : boolean := false;
|
|
2481
|
2510
|
DATA_RATE : string := "DDR";
|
|
2482
|
2511
|
DATA_WIDTH : integer := 4;
|
|
2483
|
2512
|
INIT_Q1 : bit := '0';
|
|
2484
|
2513
|
INIT_Q2 : bit := '0';
|
|
2485
|
2514
|
INIT_Q3 : bit := '0';
|
|
2486
|
2515
|
INIT_Q4 : bit := '0';
|
|
2487
|
2516
|
INTERFACE_TYPE : string := "MEMORY";
|
|
2488
|
2517
|
IOBDELAY : string := "NONE";
|
|
2489
|
2518
|
IOBDELAY_TYPE : string := "DEFAULT";
|
|
2490
|
2519
|
IOBDELAY_VALUE : integer := 0;
|
|
2491
|
2520
|
NUM_CE : integer := 2;
|
|
2492
|
2521
|
SERDES_MODE : string := "MASTER";
|
|
2493
|
2522
|
SRVAL_Q1 : bit := '0';
|
|
2494
|
2523
|
SRVAL_Q2 : bit := '0';
|
|
2495
|
2524
|
SRVAL_Q3 : bit := '0';
|
|
2496
|
2525
|
SRVAL_Q4 : bit := '0'
|
|
2497
|
2526
|
);
|
|
2498
|
2527
|
port
|
|
2499
|
2528
|
(
|
|
2500
|
2529
|
O : out std_ulogic;
|
|
2501
|
2530
|
Q1 : out std_ulogic;
|
|
2502
|
2531
|
Q2 : out std_ulogic;
|
|
2503
|
2532
|
Q3 : out std_ulogic;
|
|
2504
|
2533
|
Q4 : out std_ulogic;
|
|
2505
|
2534
|
Q5 : out std_ulogic;
|
|
2506
|
2535
|
Q6 : out std_ulogic;
|
|
2507
|
2536
|
SHIFTOUT1 : out std_ulogic;
|
|
2508
|
2537
|
SHIFTOUT2 : out std_ulogic;
|
|
2509
|
2538
|
BITSLIP : in std_ulogic;
|
|
2510
|
2539
|
CE1 : in std_ulogic;
|
|
2511
|
2540
|
CE2 : in std_ulogic;
|
|
2512
|
2541
|
CLK : in std_ulogic;
|
|
2513
|
2542
|
CLKDIV : in std_ulogic;
|
|
2514
|
2543
|
D : in std_ulogic;
|
|
2515
|
2544
|
DLYCE : in std_ulogic;
|
|
2516
|
2545
|
DLYINC : in std_ulogic;
|
|
2517
|
2546
|
DLYRST : in std_ulogic;
|
|
2518
|
2547
|
OCLK : in std_ulogic;
|
|
2519
|
2548
|
REV : in std_ulogic;
|
|
2520
|
2549
|
SHIFTIN1 : in std_ulogic;
|
|
2521
|
2550
|
SHIFTIN2 : in std_ulogic;
|
|
2522
|
2551
|
SR : in std_ulogic
|
|
2523
|
2552
|
);
|
|
2524
|
2553
|
end component;
|
|
2525
|
2554
|
|
|
2526
|
2555
|
component RAM16X1S
|
|
2527
|
2556
|
generic
|
|
2528
|
2557
|
(
|
|
2529
|
2558
|
INIT : bit_vector(15 downto 0) := X"0000"
|
|
2530
|
2559
|
);
|
|
2531
|
2560
|
port
|
|
2532
|
2561
|
(
|
|
2533
|
2562
|
O : out std_ulogic;
|
|
2534
|
2563
|
A0 : in std_ulogic;
|
|
2535
|
2564
|
A1 : in std_ulogic;
|
|
2536
|
2565
|
A2 : in std_ulogic;
|
|
2537
|
2566
|
A3 : in std_ulogic;
|
|
2538
|
2567
|
D : in std_ulogic;
|
|
2539
|
2568
|
WCLK : in std_ulogic;
|
|
2540
|
2569
|
WE : in std_ulogic
|
|
2541
|
2570
|
);
|
|
2542
|
2571
|
end component;
|
|
2543
|
2572
|
|
|
2544
|
2573
|
component RAM16X1D
|
|
2545
|
2574
|
generic
|
|
2546
|
2575
|
(
|
|
2547
|
2576
|
INIT : bit_vector(15 downto 0) := X"0000"
|
|
2548
|
2577
|
);
|
|
2549
|
2578
|
port
|
|
2550
|
2579
|
(
|
|
2551
|
2580
|
DPO : out std_ulogic;
|
|
2552
|
2581
|
SPO : out std_ulogic;
|
|
2553
|
2582
|
A0 : in std_ulogic;
|
|
2554
|
2583
|
A1 : in std_ulogic;
|
|
2555
|
2584
|
A2 : in std_ulogic;
|
|
2556
|
2585
|
A3 : in std_ulogic;
|
|
2557
|
2586
|
D : in std_ulogic;
|
|
2558
|
2587
|
DPRA0 : in std_ulogic;
|
|
2559
|
2588
|
DPRA1 : in std_ulogic;
|
|
2560
|
2589
|
DPRA2 : in std_ulogic;
|
|
2561
|
2590
|
DPRA3 : in std_ulogic;
|
|
2562
|
2591
|
WCLK : in std_ulogic;
|
|
2563
|
2592
|
WE : in std_ulogic
|
|
2564
|
2593
|
);
|
|
2565
|
2594
|
end component;
|
|
2566
|
2595
|
|
|
2567
|
2596
|
component ROM32X1
|
|
2568
|
2597
|
generic
|
|
2569
|
2598
|
(
|
|
2570
|
2599
|
INIT : bit_vector := X"00000000"
|
|
2571
|
2600
|
);
|
|
2572
|
2601
|
port
|
|
2573
|
2602
|
(
|
|
2574
|
2603
|
O : out std_ulogic;
|
|
2575
|
2604
|
A0 : in std_ulogic;
|
|
2576
|
2605
|
A1 : in std_ulogic;
|
|
2577
|
2606
|
A2 : in std_ulogic;
|
|
2578
|
2607
|
A3 : in std_ulogic;
|
|
2579
|
2608
|
A4 : in std_ulogic
|
|
2580
|
2609
|
);
|
|
2581
|
2610
|
end component;
|
|
2582
|
2611
|
|
|
2583
|
2612
|
component DSP48
|
|
2584
|
2613
|
generic
|
|
2585
|
2614
|
(
|
|
2586
|
2615
|
AREG : integer := 1;
|
|
2587
|
2616
|
B_INPUT : string := "DIRECT";
|
|
2588
|
2617
|
BREG : integer := 1;
|
|
2589
|
2618
|
CARRYINREG : integer := 1;
|
|
2590
|
2619
|
CARRYINSELREG : integer := 1;
|
|
2591
|
2620
|
CREG : integer := 1;
|
|
2592
|
2621
|
LEGACY_MODE : string := "MULT18X18S";
|
|
2593
|
2622
|
MREG : integer := 1;
|
|
2594
|
2623
|
OPMODEREG : integer := 1;
|
|
2595
|
2624
|
PREG : integer := 1;
|
|
2596
|
2625
|
SUBTRACTREG : integer := 1
|
|
2597
|
2626
|
);
|
|
2598
|
2627
|
port
|
|
2599
|
2628
|
(
|
|
2600
|
2629
|
BCOUT : out std_logic_vector(17 downto 0);
|
|
2601
|
2630
|
P : out std_logic_vector(47 downto 0);
|
|
2602
|
2631
|
PCOUT : out std_logic_vector(47 downto 0);
|
|
2603
|
2632
|
A : in std_logic_vector(17 downto 0);
|
|
2604
|
2633
|
B : in std_logic_vector(17 downto 0);
|
|
2605
|
2634
|
BCIN : in std_logic_vector(17 downto 0);
|
|
2606
|
2635
|
C : in std_logic_vector(47 downto 0);
|
|
2607
|
2636
|
CARRYIN : in std_ulogic;
|
|
2608
|
2637
|
CARRYINSEL : in std_logic_vector(1 downto 0);
|
|
2609
|
2638
|
CEA : in std_ulogic;
|
|
2610
|
2639
|
CEB : in std_ulogic;
|
|
2611
|
2640
|
CEC : in std_ulogic;
|
|
2612
|
2641
|
CECARRYIN : in std_ulogic;
|
|
2613
|
2642
|
CECINSUB : in std_ulogic;
|
|
2614
|
2643
|
CECTRL : in std_ulogic;
|
|
2615
|
2644
|
CEM : in std_ulogic;
|
|
2616
|
2645
|
CEP : in std_ulogic;
|
|
2617
|
2646
|
CLK : in std_ulogic;
|
|
2618
|
2647
|
OPMODE : in std_logic_vector(6 downto 0);
|
|
2619
|
2648
|
PCIN : in std_logic_vector(47 downto 0);
|
|
2620
|
2649
|
RSTA : in std_ulogic;
|
|
2621
|
2650
|
RSTB : in std_ulogic;
|
|
2622
|
2651
|
RSTC : in std_ulogic;
|
|
2623
|
2652
|
RSTCARRYIN : in std_ulogic;
|
|
2624
|
2653
|
RSTCTRL : in std_ulogic;
|
|
2625
|
2654
|
RSTM : in std_ulogic;
|
|
2626
|
2655
|
RSTP : in std_ulogic;
|
|
2627
|
2656
|
SUBTRACT : in std_ulogic
|
|
2628
|
2657
|
);
|
|
2629
|
2658
|
end component;
|
|
2630
|
2659
|
|
|
2631
|
2660
|
component RAMB16
|
|
2632
|
2661
|
generic
|
|
2633
|
2662
|
(
|
|
2634
|
2663
|
DOA_REG : integer := 0;
|
|
2635
|
2664
|
DOB_REG : integer := 0;
|
|
2636
|
2665
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2637
|
2666
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2638
|
2667
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2639
|
2668
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2640
|
2669
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2641
|
2670
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2642
|
2671
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2643
|
2672
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2644
|
2673
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2645
|
2674
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2646
|
2675
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2647
|
2676
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2648
|
2677
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2649
|
2678
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2650
|
2679
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2651
|
2680
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2652
|
2681
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2653
|
2682
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2654
|
2683
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2655
|
2684
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2656
|
2685
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2657
|
2686
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2658
|
2687
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2659
|
2688
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2660
|
2689
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2661
|
2690
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2662
|
2691
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2663
|
2692
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2664
|
2693
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2665
|
2694
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2666
|
2695
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2667
|
2696
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2668
|
2697
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2669
|
2698
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2670
|
2699
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2671
|
2700
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2672
|
2701
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2673
|
2702
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2674
|
2703
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2675
|
2704
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2676
|
2705
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2677
|
2706
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2678
|
2707
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2679
|
2708
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2680
|
2709
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2681
|
2710
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2682
|
2711
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2683
|
2712
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2684
|
2713
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2685
|
2714
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2686
|
2715
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2687
|
2716
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2688
|
2717
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2689
|
2718
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2690
|
2719
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2691
|
2720
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2692
|
2721
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2693
|
2722
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2694
|
2723
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2695
|
2724
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2696
|
2725
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2697
|
2726
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2698
|
2727
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2699
|
2728
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2700
|
2729
|
INIT_A : bit_vector := X"000000000";
|
|
2701
|
2730
|
INIT_B : bit_vector := X"000000000";
|
|
2702
|
2731
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2703
|
2732
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2704
|
2733
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2705
|
2734
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2706
|
2735
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2707
|
2736
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2708
|
2737
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2709
|
2738
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
2710
|
2739
|
INVERT_CLK_DOA_REG : boolean := false;
|
|
2711
|
2740
|
INVERT_CLK_DOB_REG : boolean := false;
|
|
2712
|
2741
|
RAM_EXTENSION_A : string := "NONE";
|
|
2713
|
2742
|
RAM_EXTENSION_B : string := "NONE";
|
|
2714
|
2743
|
READ_WIDTH_A : integer := 0;
|
|
2715
|
2744
|
READ_WIDTH_B : integer := 0;
|
|
2716
|
2745
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
2717
|
2746
|
SRVAL_A : bit_vector := X"000000000";
|
|
2718
|
2747
|
SRVAL_B : bit_vector := X"000000000";
|
|
2719
|
2748
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
2720
|
2749
|
WRITE_MODE_B : string := "WRITE_FIRST";
|
|
2721
|
2750
|
WRITE_WIDTH_A : integer := 0;
|
|
2722
|
2751
|
WRITE_WIDTH_B : integer := 0
|
|
2723
|
2752
|
);
|
|
2724
|
2753
|
port
|
|
2725
|
2754
|
(
|
|
2726
|
2755
|
CASCADEOUTA : out std_ulogic;
|
|
2727
|
2756
|
CASCADEOUTB : out std_ulogic;
|
|
2728
|
2757
|
DOA : out std_logic_vector (31 downto 0);
|
|
2729
|
2758
|
DOB : out std_logic_vector (31 downto 0);
|
|
2730
|
2759
|
DOPA : out std_logic_vector (3 downto 0);
|
|
2731
|
2760
|
DOPB : out std_logic_vector (3 downto 0);
|
|
2732
|
2761
|
ADDRA : in std_logic_vector (14 downto 0);
|
|
2733
|
2762
|
ADDRB : in std_logic_vector (14 downto 0);
|
|
2734
|
2763
|
CASCADEINA : in std_ulogic;
|
|
2735
|
2764
|
CASCADEINB : in std_ulogic;
|
|
2736
|
2765
|
CLKA : in std_ulogic;
|
|
2737
|
2766
|
CLKB : in std_ulogic;
|
|
2738
|
2767
|
DIA : in std_logic_vector (31 downto 0);
|
|
2739
|
2768
|
DIB : in std_logic_vector (31 downto 0);
|
|
2740
|
2769
|
DIPA : in std_logic_vector (3 downto 0);
|
|
2741
|
2770
|
DIPB : in std_logic_vector (3 downto 0);
|
|
2742
|
2771
|
ENA : in std_ulogic;
|
|
2743
|
2772
|
ENB : in std_ulogic;
|
|
2744
|
2773
|
REGCEA : in std_ulogic;
|
|
2745
|
2774
|
REGCEB : in std_ulogic;
|
|
2746
|
2775
|
SSRA : in std_ulogic;
|
|
2747
|
2776
|
SSRB : in std_ulogic;
|
|
2748
|
2777
|
WEA : in std_logic_vector (3 downto 0);
|
|
2749
|
2778
|
WEB : in std_logic_vector (3 downto 0)
|
|
2750
|
2779
|
);
|
|
2751
|
2780
|
end component;
|
|
2752
|
2781
|
|
|
2753
|
2782
|
component MUXF8
|
|
2754
|
2783
|
port
|
|
2755
|
2784
|
(
|
|
2756
|
2785
|
O : out std_ulogic;
|
|
2757
|
2786
|
I0 : in std_ulogic;
|
|
2758
|
2787
|
I1 : in std_ulogic;
|
|
2759
|
2788
|
S : in std_ulogic
|
|
2760
|
2789
|
);
|
|
2761
|
2790
|
end component;
|
|
2762
|
2791
|
|
|
2763
|
2792
|
component RAM64X1D
|
|
2764
|
2793
|
generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
|
|
2765
|
2794
|
port
|
|
2766
|
2795
|
(
|
|
2767
|
2796
|
DPO : out std_ulogic;
|
|
2768
|
2797
|
SPO : out std_ulogic;
|
|
2769
|
2798
|
A0 : in std_ulogic;
|
|
2770
|
2799
|
A1 : in std_ulogic;
|
|
2771
|
2800
|
A2 : in std_ulogic;
|
|
2772
|
2801
|
A3 : in std_ulogic;
|
|
2773
|
2802
|
A4 : in std_ulogic;
|
|
2774
|
2803
|
A5 : in std_ulogic;
|
|
2775
|
2804
|
D : in std_ulogic;
|
|
2776
|
2805
|
DPRA0 : in std_ulogic;
|
|
2777
|
2806
|
DPRA1 : in std_ulogic;
|
|
2778
|
2807
|
DPRA2 : in std_ulogic;
|
|
2779
|
2808
|
DPRA3 : in std_ulogic;
|
|
2780
|
2809
|
DPRA4 : in std_ulogic;
|
|
2781
|
2810
|
DPRA5 : in std_ulogic;
|
|
2782
|
2811
|
WCLK : in std_ulogic;
|
|
2783
|
2812
|
WE : in std_ulogic
|
|
2784
|
2813
|
);
|
|
2785
|
2814
|
end component;
|
|
2786
|
2815
|
|
|
2787
|
2816
|
|
|
2788
|
2817
|
component BUF
|
|
2789
|
2818
|
port
|
|
2790
|
2819
|
(
|
|
2791
|
2820
|
O : out std_ulogic;
|
|
2792
|
2821
|
I : in std_ulogic
|
|
2793
|
2822
|
);
|
|
2794
|
2823
|
end component;
|
|
2795
|
2824
|
component LUT5
|
|
2796
|
2825
|
generic
|
|
2797
|
2826
|
(
|
|
2798
|
2827
|
INIT : bit_vector := X"00000000"
|
|
2799
|
2828
|
);
|
|
2800
|
2829
|
port
|
|
2801
|
2830
|
(
|
|
2802
|
2831
|
O : out std_ulogic;
|
|
2803
|
2832
|
I0 : in std_ulogic;
|
|
2804
|
2833
|
I1 : in std_ulogic;
|
|
2805
|
2834
|
I2 : in std_ulogic;
|
|
2806
|
2835
|
I3 : in std_ulogic;
|
|
2807
|
2836
|
I4 : in std_ulogic
|
|
2808
|
2837
|
);
|
|
2809
|
2838
|
end component;
|
|
2810
|
2839
|
component LUT5_L
|
|
2811
|
2840
|
generic
|
|
2812
|
2841
|
(
|
|
2813
|
2842
|
INIT : bit_vector := X"00000000"
|
|
2814
|
2843
|
);
|
|
2815
|
2844
|
port
|
|
2816
|
2845
|
(
|
|
2817
|
2846
|
LO : out std_ulogic;
|
|
2818
|
2847
|
I0 : in std_ulogic;
|
|
2819
|
2848
|
I1 : in std_ulogic;
|
|
2820
|
2849
|
I2 : in std_ulogic;
|
|
2821
|
2850
|
I3 : in std_ulogic;
|
|
2822
|
2851
|
I4 : in std_ulogic
|
|
2823
|
2852
|
);
|
|
2824
|
2853
|
end component;
|
|
2825
|
2854
|
component LUT6
|
|
2826
|
2855
|
generic
|
|
2827
|
2856
|
(
|
|
2828
|
2857
|
INIT : bit_vector := X"0000000000000000"
|
|
2829
|
2858
|
);
|
|
2830
|
2859
|
port
|
|
2831
|
2860
|
(
|
|
2832
|
2861
|
O : out std_ulogic;
|
|
2833
|
2862
|
I0 : in std_ulogic;
|
|
2834
|
2863
|
I1 : in std_ulogic;
|
|
2835
|
2864
|
I2 : in std_ulogic;
|
|
2836
|
2865
|
I3 : in std_ulogic;
|
|
2837
|
2866
|
I4 : in std_ulogic;
|
|
2838
|
2867
|
I5 : in std_ulogic
|
|
2839
|
2868
|
);
|
|
2840
|
2869
|
end component;
|
|
2841
|
2870
|
component LUT6_L
|
|
2842
|
2871
|
generic
|
|
2843
|
2872
|
(
|
|
2844
|
2873
|
INIT : bit_vector := X"0000000000000000"
|
|
2845
|
2874
|
);
|
|
2846
|
2875
|
port
|
|
2847
|
2876
|
(
|
|
2848
|
2877
|
LO : out std_ulogic;
|
|
2849
|
2878
|
I0 : in std_ulogic;
|
|
2850
|
2879
|
I1 : in std_ulogic;
|
|
2851
|
2880
|
I2 : in std_ulogic;
|
|
2852
|
2881
|
I3 : in std_ulogic;
|
|
2853
|
2882
|
I4 : in std_ulogic;
|
|
2854
|
2883
|
I5 : in std_ulogic
|
|
2855
|
2884
|
);
|
|
2856
|
2885
|
end component;
|
|
2857
|
2886
|
|
|
2858
|
2887
|
component RAM128X1S
|
|
2859
|
2888
|
|
|
2860
|
2889
|
generic (
|
|
2861
|
2890
|
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
|
|
2862
|
2891
|
);
|
|
2863
|
2892
|
|
|
2864
|
2893
|
port (
|
|
2865
|
2894
|
O : out std_ulogic;
|
|
2866
|
2895
|
|
|
2867
|
2896
|
A0 : in std_ulogic;
|
|
2868
|
2897
|
A1 : in std_ulogic;
|
|
2869
|
2898
|
A2 : in std_ulogic;
|
|
2870
|
2899
|
A3 : in std_ulogic;
|
|
2871
|
2900
|
A4 : in std_ulogic;
|
|
2872
|
2901
|
A5 : in std_ulogic;
|
|
2873
|
2902
|
A6 : in std_ulogic;
|
|
2874
|
2903
|
D : in std_ulogic;
|
|
2875
|
2904
|
WCLK : in std_ulogic;
|
|
2876
|
2905
|
WE : in std_ulogic
|
|
2877
|
2906
|
);
|
|
2878
|
2907
|
end component;
|
|
2879
|
2908
|
|
|
2880
|
2909
|
component SRLC16E
|
|
2881
|
2910
|
|
|
2882
|
2911
|
generic (
|
|
2883
|
2912
|
INIT : bit_vector := X"0000"
|
|
2884
|
2913
|
);
|
|
2885
|
2914
|
|
|
2886
|
2915
|
port (
|
|
2887
|
2916
|
Q : out STD_ULOGIC;
|
|
2888
|
2917
|
Q15 : out STD_ULOGIC;
|
|
2889
|
2918
|
|
|
2890
|
2919
|
A0 : in STD_ULOGIC;
|
|
2891
|
2920
|
A1 : in STD_ULOGIC;
|
|
2892
|
2921
|
A2 : in STD_ULOGIC;
|
|
2893
|
2922
|
A3 : in STD_ULOGIC;
|
|
2894
|
2923
|
CE : in STD_ULOGIC;
|
|
2895
|
2924
|
CLK : in STD_ULOGIC;
|
|
2896
|
2925
|
D : in STD_ULOGIC
|
|
2897
|
2926
|
);
|
|
2898
|
2927
|
end component;
|
|
2899
|
2928
|
|
|
2900
|
2929
|
component LD_1
|
|
2901
|
2930
|
generic(
|
|
2902
|
2931
|
INIT : bit := '0'
|
|
2903
|
2932
|
);
|
|
2904
|
2933
|
|
|
2905
|
2934
|
port(
|
|
2906
|
2935
|
Q : out std_ulogic := '0';
|
|
2907
|
2936
|
|
|
2908
|
2937
|
D : in std_ulogic;
|
|
2909
|
2938
|
G : in std_ulogic
|
|
2910
|
2939
|
);
|
|
2911
|
2940
|
end component;
|
|
2912
|
2941
|
|
|
2913
|
2942
|
component RAM32X1D
|
|
2914
|
2943
|
|
|
2915
|
2944
|
generic (
|
|
2916
|
2945
|
INIT : bit_vector(31 downto 0) := X"00000000"
|
|
2917
|
2946
|
);
|
|
2918
|
2947
|
|
|
2919
|
2948
|
port (
|
|
2920
|
2949
|
DPO : out std_ulogic;
|
|
2921
|
2950
|
SPO : out std_ulogic;
|
|
2922
|
2951
|
|
|
2923
|
2952
|
A0 : in std_ulogic;
|
|
2924
|
2953
|
A1 : in std_ulogic;
|
|
2925
|
2954
|
A2 : in std_ulogic;
|
|
2926
|
2955
|
A3 : in std_ulogic;
|
|
2927
|
2956
|
A4 : in std_ulogic;
|
|
2928
|
2957
|
D : in std_ulogic;
|
|
2929
|
2958
|
DPRA0 : in std_ulogic;
|
|
2930
|
2959
|
DPRA1 : in std_ulogic;
|
|
2931
|
2960
|
DPRA2 : in std_ulogic;
|
|
2932
|
2961
|
DPRA3 : in std_ulogic;
|
|
2933
|
2962
|
DPRA4 : in std_ulogic;
|
|
2934
|
2963
|
WCLK : in std_ulogic;
|
|
2935
|
2964
|
WE : in std_ulogic
|
|
2936
|
2965
|
);
|
|
2937
|
2966
|
end component;
|
|
2938
|
2967
|
|
|
2939
|
2968
|
component FD_1
|
|
2940
|
2969
|
generic(
|
|
2941
|
2970
|
INIT : bit := '0'
|
|
2942
|
2971
|
);
|
|
2943
|
2972
|
|
|
2944
|
2973
|
port(
|
|
2945
|
2974
|
Q : out std_ulogic;
|
|
2946
|
2975
|
|
|
2947
|
2976
|
C : in std_ulogic;
|
|
2948
|
2977
|
D : in std_ulogic
|
|
2949
|
2978
|
);
|
|
2950
|
2979
|
end component;
|
|
2951
|
2980
|
|
|
2952
|
2981
|
component XORCY_L
|
|
2953
|
2982
|
port(
|
|
2954
|
2983
|
LO : out std_ulogic;
|
|
2955
|
2984
|
|
|
2956
|
2985
|
CI : in std_ulogic;
|
|
2957
|
2986
|
LI : in std_ulogic
|
|
2958
|
2987
|
);
|
|
2959
|
2988
|
end component;
|
|
2960
|
2989
|
|
|
2961
|
2990
|
component RAM32M
|
|
2962
|
2991
|
generic (
|
|
2963
|
2992
|
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
|
|
2964
|
2993
|
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
|
|
2965
|
2994
|
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
|
|
2966
|
2995
|
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
|
|
2967
|
2996
|
);
|
|
2968
|
2997
|
|
|
2969
|
2998
|
port (
|
|
2970
|
2999
|
DOA : out std_logic_vector (1 downto 0);
|
|
2971
|
3000
|
DOB : out std_logic_vector (1 downto 0);
|
|
2972
|
3001
|
DOC : out std_logic_vector (1 downto 0);
|
|
2973
|
3002
|
DOD : out std_logic_vector (1 downto 0);
|
|
2974
|
3003
|
|
|
2975
|
3004
|
ADDRA : in std_logic_vector(4 downto 0);
|
|
2976
|
3005
|
ADDRB : in std_logic_vector(4 downto 0);
|
|
2977
|
3006
|
ADDRC : in std_logic_vector(4 downto 0);
|
|
2978
|
3007
|
ADDRD : in std_logic_vector(4 downto 0);
|
|
2979
|
3008
|
DIA : in std_logic_vector (1 downto 0);
|
|
2980
|
3009
|
DIB : in std_logic_vector (1 downto 0);
|
|
2981
|
3010
|
DIC : in std_logic_vector (1 downto 0);
|
|
2982
|
3011
|
DID : in std_logic_vector (1 downto 0);
|
|
2983
|
3012
|
WCLK : in std_ulogic;
|
|
2984
|
3013
|
WE : in std_ulogic
|
|
2985
|
3014
|
);
|
|
2986
|
3015
|
end component;
|
|
2987
|
3016
|
|
|
2988
|
3017
|
component RAM128X1D
|
|
2989
|
3018
|
generic
|
|
2990
|
3019
|
(
|
|
2991
|
3020
|
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
|
|
2992
|
3021
|
);
|
|
2993
|
3022
|
port
|
|
2994
|
3023
|
(
|
|
2995
|
3024
|
DPO : out std_ulogic;
|
|
2996
|
3025
|
SPO : out std_ulogic;
|
|
2997
|
3026
|
A : in std_logic_vector(6 downto 0);
|
|
2998
|
3027
|
D : in std_ulogic;
|
|
2999
|
3028
|
DPRA : in std_logic_vector(6 downto 0);
|
|
3000
|
3029
|
WCLK : in std_ulogic;
|
|
3001
|
3030
|
WE : in std_ulogic
|
|
3002
|
3031
|
);
|
|
3003
|
3032
|
end component;
|
|
3004
|
3033
|
|
|
3005
|
3034
|
component RAM64M
|
|
3006
|
3035
|
generic (
|
|
3007
|
3036
|
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
|
|
3008
|
3037
|
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
|
|
3009
|
3038
|
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
|
|
3010
|
3039
|
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
|
|
3011
|
3040
|
);
|
|
3012
|
3041
|
|
|
3013
|
3042
|
port (
|
|
3014
|
3043
|
DOA : out std_ulogic;
|
|
3015
|
3044
|
DOB : out std_ulogic;
|
|
3016
|
3045
|
DOC : out std_ulogic;
|
|
3017
|
3046
|
DOD : out std_ulogic;
|
|
3018
|
3047
|
|
|
3019
|
3048
|
ADDRA : in std_logic_vector(5 downto 0);
|
|
3020
|
3049
|
ADDRB : in std_logic_vector(5 downto 0);
|
|
3021
|
3050
|
ADDRC : in std_logic_vector(5 downto 0);
|
|
3022
|
3051
|
ADDRD : in std_logic_vector(5 downto 0);
|
|
3023
|
3052
|
DIA : in std_ulogic;
|
|
3024
|
3053
|
DIB : in std_ulogic;
|
|
3025
|
3054
|
DIC : in std_ulogic;
|
|
3026
|
3055
|
DID : in std_ulogic;
|
|
3027
|
3056
|
WCLK : in std_ulogic;
|
|
3028
|
3057
|
WE : in std_ulogic
|
|
3029
|
3058
|
);
|
|
3030
|
3059
|
end component;
|
|
3031
|
3060
|
|
|
3032
|
3061
|
component XOR2
|
|
3033
|
3062
|
port(
|
|
3034
|
3063
|
O : out std_ulogic;
|
|
3035
|
3064
|
|
|
3036
|
3065
|
I0 : in std_ulogic;
|
|
3037
|
3066
|
I1 : in std_ulogic
|
|
3038
|
3067
|
);
|
|
3039
|
3068
|
end component;
|
|
3040
|
3069
|
|
|
3041
|
3070
|
component BSCANE2
|
|
3042
|
3071
|
generic (
|
|
3043
|
3072
|
DISABLE_JTAG : string := "FALSE";
|
|
3044
|
3073
|
JTAG_CHAIN : integer := 1
|
|
3045
|
3074
|
);
|
|
3046
|
3075
|
port (
|
|
3047
|
3076
|
CAPTURE : out std_ulogic := 'H';
|
|
3048
|
3077
|
DRCK : out std_ulogic := 'H';
|
|
3049
|
3078
|
RESET : out std_ulogic := 'H';
|
|
3050
|
3079
|
RUNTEST : out std_ulogic := 'L';
|
|
3051
|
3080
|
SEL : out std_ulogic := 'L';
|
|
3052
|
3081
|
SHIFT : out std_ulogic := 'L';
|
|
3053
|
3082
|
TCK : out std_ulogic := 'L';
|
|
3054
|
3083
|
TDI : out std_ulogic := 'L';
|
|
3055
|
3084
|
TMS : out std_ulogic := 'L';
|
|
3056
|
3085
|
UPDATE : out std_ulogic := 'L';
|
|
3057
|
3086
|
TDO : in std_ulogic := 'X'
|
|
3058
|
3087
|
);
|
|
3059
|
3088
|
end component;
|
|
3060
|
3089
|
|
|
3061
|
3090
|
component BSCAN_SPARTAN6
|
|
3062
|
3091
|
generic (
|
|
3063
|
3092
|
JTAG_CHAIN : integer := 1
|
|
3064
|
3093
|
);
|
|
3065
|
3094
|
port (
|
|
3066
|
3095
|
CAPTURE : out std_ulogic := 'H';
|
|
3067
|
3096
|
DRCK : out std_ulogic := 'H';
|
|
3068
|
3097
|
RESET : out std_ulogic := 'H';
|
|
3069
|
3098
|
RUNTEST : out std_ulogic := 'L';
|
|
3070
|
3099
|
SEL : out std_ulogic := 'L';
|
|
3071
|
3100
|
SHIFT : out std_ulogic := 'L';
|
|
3072
|
3101
|
TCK : out std_ulogic := 'L';
|
|
3073
|
3102
|
TDI : out std_ulogic := 'L';
|
|
3074
|
3103
|
TMS : out std_ulogic := 'L';
|
|
3075
|
3104
|
UPDATE : out std_ulogic := 'L';
|
|
3076
|
3105
|
TDO : in std_ulogic := 'X'
|
|
3077
|
3106
|
);
|
|
3078
|
3107
|
end component;
|
|
3079
|
3108
|
|
|
3080
|
3109
|
component BSCAN_VIRTEX6
|
|
3081
|
3110
|
generic (
|
|
3082
|
3111
|
DISABLE_JTAG : boolean := FALSE;
|
|
3083
|
3112
|
JTAG_CHAIN : integer := 1
|
|
3084
|
3113
|
);
|
|
3085
|
3114
|
port (
|
|
3086
|
3115
|
CAPTURE : out std_ulogic := 'H';
|
|
3087
|
3116
|
DRCK : out std_ulogic := 'H';
|
|
3088
|
3117
|
RESET : out std_ulogic := 'H';
|
|
3089
|
3118
|
RUNTEST : out std_ulogic := 'L';
|
|
3090
|
3119
|
SEL : out std_ulogic := 'L';
|
|
3091
|
3120
|
SHIFT : out std_ulogic := 'L';
|
|
3092
|
3121
|
TCK : out std_ulogic := 'L';
|
|
3093
|
3122
|
TDI : out std_ulogic := 'L';
|
|
3094
|
3123
|
TMS : out std_ulogic := 'L';
|
|
3095
|
3124
|
UPDATE : out std_ulogic := 'L';
|
|
3096
|
3125
|
TDO : in std_ulogic := 'X'
|
|
3097
|
3126
|
);
|
|
3098
|
3127
|
end component;
|
|
3099
|
3128
|
|
|
3100
|
3129
|
component SRL16
|
|
3101
|
3130
|
generic ( INIT : bit_vector := X"0000");
|
|
3102
|
3131
|
port (
|
|
3103
|
3132
|
Q : out STD_ULOGIC;
|
|
3104
|
3133
|
A0 : in STD_ULOGIC;
|
|
3105
|
3134
|
A1 : in STD_ULOGIC;
|
|
3106
|
3135
|
A2 : in STD_ULOGIC;
|
|
3107
|
3136
|
A3 : in STD_ULOGIC;
|
|
3108
|
3137
|
CLK : in STD_ULOGIC;
|
|
3109
|
3138
|
D : in STD_ULOGIC);
|
|
3110
|
3139
|
end component;
|
|
3111
|
3140
|
|
|
3112
|
3141
|
component LUT6_2
|
|
3113
|
3142
|
generic(
|
|
3114
|
3143
|
INIT : bit_vector := X"0000000000000000"
|
|
3115
|
3144
|
);
|
|
3116
|
3145
|
|
|
3117
|
3146
|
port(
|
|
3118
|
3147
|
O5 : out std_ulogic;
|
|
3119
|
3148
|
O6 : out std_ulogic;
|
|
3120
|
3149
|
|
|
3121
|
3150
|
I0 : in std_ulogic;
|
|
3122
|
3151
|
I1 : in std_ulogic;
|
|
3123
|
3152
|
I2 : in std_ulogic;
|
|
3124
|
3153
|
I3 : in std_ulogic;
|
|
3125
|
3154
|
I4 : in std_ulogic;
|
|
3126
|
3155
|
I5 : in std_ulogic
|
|
3127
|
3156
|
);
|
|
3128
|
3157
|
end component;
|
|
3129
|
3158
|
|
|
3130
|
3159
|
component DSP48E
|
|
3131
|
3160
|
|
|
3132
|
3161
|
generic(
|
|
3133
|
3162
|
|
|
3134
|
3163
|
SIM_MODE : string := "SAFE";
|
|
3135
|
3164
|
|
|
3136
|
3165
|
ACASCREG : integer := 1;
|
|
3137
|
3166
|
ALUMODEREG : integer := 1;
|
|
3138
|
3167
|
AREG : integer := 1;
|
|
3139
|
3168
|
AUTORESET_PATTERN_DETECT : boolean := FALSE;
|
|
3140
|
3169
|
AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH";
|
|
3141
|
3170
|
A_INPUT : string := "DIRECT";
|
|
3142
|
3171
|
BCASCREG : integer := 1;
|
|
3143
|
3172
|
BREG : integer := 1;
|
|
3144
|
3173
|
B_INPUT : string := "DIRECT";
|
|
3145
|
3174
|
CARRYINREG : integer := 1;
|
|
3146
|
3175
|
CARRYINSELREG : integer := 1;
|
|
3147
|
3176
|
CREG : integer := 1;
|
|
3148
|
3177
|
MASK : bit_vector := X"3FFFFFFFFFFF";
|
|
3149
|
3178
|
MREG : integer := 1;
|
|
3150
|
3179
|
MULTCARRYINREG : integer := 1;
|
|
3151
|
3180
|
OPMODEREG : integer := 1;
|
|
3152
|
3181
|
PATTERN : bit_vector := X"000000000000";
|
|
3153
|
3182
|
PREG : integer := 1;
|
|
3154
|
3183
|
SEL_MASK : string := "MASK";
|
|
3155
|
3184
|
SEL_PATTERN : string := "PATTERN";
|
|
3156
|
3185
|
SEL_ROUNDING_MASK : string := "SEL_MASK";
|
|
3157
|
3186
|
USE_MULT : string := "MULT_S";
|
|
3158
|
3187
|
USE_PATTERN_DETECT : string := "NO_PATDET";
|
|
3159
|
3188
|
USE_SIMD : string := "ONE48"
|
|
3160
|
3189
|
);
|
|
3161
|
3190
|
|
|
3162
|
3191
|
port(
|
|
3163
|
3192
|
ACOUT : out std_logic_vector(29 downto 0);
|
|
3164
|
3193
|
BCOUT : out std_logic_vector(17 downto 0);
|
|
3165
|
3194
|
CARRYCASCOUT : out std_ulogic;
|
|
3166
|
3195
|
CARRYOUT : out std_logic_vector(3 downto 0);
|
|
3167
|
3196
|
MULTSIGNOUT : out std_ulogic;
|
|
3168
|
3197
|
OVERFLOW : out std_ulogic;
|
|
3169
|
3198
|
P : out std_logic_vector(47 downto 0);
|
|
3170
|
3199
|
PATTERNBDETECT : out std_ulogic;
|
|
3171
|
3200
|
PATTERNDETECT : out std_ulogic;
|
|
3172
|
3201
|
PCOUT : out std_logic_vector(47 downto 0);
|
|
3173
|
3202
|
UNDERFLOW : out std_ulogic;
|
|
3174
|
3203
|
|
|
3175
|
3204
|
A : in std_logic_vector(29 downto 0);
|
|
3176
|
3205
|
ACIN : in std_logic_vector(29 downto 0);
|
|
3177
|
3206
|
ALUMODE : in std_logic_vector(3 downto 0);
|
|
3178
|
3207
|
B : in std_logic_vector(17 downto 0);
|
|
3179
|
3208
|
BCIN : in std_logic_vector(17 downto 0);
|
|
3180
|
3209
|
C : in std_logic_vector(47 downto 0);
|
|
3181
|
3210
|
CARRYCASCIN : in std_ulogic;
|
|
3182
|
3211
|
CARRYIN : in std_ulogic;
|
|
3183
|
3212
|
CARRYINSEL : in std_logic_vector(2 downto 0);
|
|
3184
|
3213
|
CEA1 : in std_ulogic;
|
|
3185
|
3214
|
CEA2 : in std_ulogic;
|
|
3186
|
3215
|
CEALUMODE : in std_ulogic;
|
|
3187
|
3216
|
CEB1 : in std_ulogic;
|
|
3188
|
3217
|
CEB2 : in std_ulogic;
|
|
3189
|
3218
|
CEC : in std_ulogic;
|
|
3190
|
3219
|
CECARRYIN : in std_ulogic;
|
|
3191
|
3220
|
CECTRL : in std_ulogic;
|
|
3192
|
3221
|
CEM : in std_ulogic;
|
|
3193
|
3222
|
CEMULTCARRYIN : in std_ulogic;
|
|
3194
|
3223
|
CEP : in std_ulogic;
|
|
3195
|
3224
|
CLK : in std_ulogic;
|
|
3196
|
3225
|
MULTSIGNIN : in std_ulogic;
|
|
3197
|
3226
|
OPMODE : in std_logic_vector(6 downto 0);
|
|
3198
|
3227
|
PCIN : in std_logic_vector(47 downto 0);
|
|
3199
|
3228
|
RSTA : in std_ulogic;
|
|
3200
|
3229
|
RSTALLCARRYIN : in std_ulogic;
|
|
3201
|
3230
|
RSTALUMODE : in std_ulogic;
|
|
3202
|
3231
|
RSTB : in std_ulogic;
|
|
3203
|
3232
|
RSTC : in std_ulogic;
|
|
3204
|
3233
|
RSTCTRL : in std_ulogic;
|
|
3205
|
3234
|
RSTM : in std_ulogic;
|
|
3206
|
3235
|
RSTP : in std_ulogic
|
|
3207
|
3236
|
);
|
|
3208
|
3237
|
|
|
3209
|
3238
|
end component;
|
|
3210
|
3239
|
|
|
3211
|
3240
|
component RAMB18
|
|
3212
|
3241
|
generic (
|
|
3213
|
3242
|
|
|
3214
|
3243
|
DOA_REG : integer := 0;
|
|
3215
|
3244
|
DOB_REG : integer := 0;
|
|
3216
|
3245
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3217
|
3246
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3218
|
3247
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3219
|
3248
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3220
|
3249
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3221
|
3250
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3222
|
3251
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3223
|
3252
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3224
|
3253
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3225
|
3254
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3226
|
3255
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3227
|
3256
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3228
|
3257
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3229
|
3258
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3230
|
3259
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3231
|
3260
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3232
|
3261
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3233
|
3262
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3234
|
3263
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3235
|
3264
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3236
|
3265
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3237
|
3266
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3238
|
3267
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3239
|
3268
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3240
|
3269
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3241
|
3270
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3242
|
3271
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3243
|
3272
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3244
|
3273
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3245
|
3274
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3246
|
3275
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3247
|
3276
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3248
|
3277
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3249
|
3278
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3250
|
3279
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3251
|
3280
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3252
|
3281
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3253
|
3282
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3254
|
3283
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3255
|
3284
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3256
|
3285
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3257
|
3286
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3258
|
3287
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3259
|
3288
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3260
|
3289
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3261
|
3290
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3262
|
3291
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3263
|
3292
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3264
|
3293
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3265
|
3294
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3266
|
3295
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3267
|
3296
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3268
|
3297
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3269
|
3298
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3270
|
3299
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3271
|
3300
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3272
|
3301
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3273
|
3302
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3274
|
3303
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3275
|
3304
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3276
|
3305
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3277
|
3306
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3278
|
3307
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3279
|
3308
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3280
|
3309
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3281
|
3310
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3282
|
3311
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3283
|
3312
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3284
|
3313
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3285
|
3314
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3286
|
3315
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3287
|
3316
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3288
|
3317
|
INIT_A : bit_vector := X"00000";
|
|
3289
|
3318
|
INIT_B : bit_vector := X"00000";
|
|
3290
|
3319
|
INIT_FILE : string := "NONE";
|
|
3291
|
3320
|
READ_WIDTH_A : integer := 0;
|
|
3292
|
3321
|
READ_WIDTH_B : integer := 0;
|
|
3293
|
3322
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
3294
|
3323
|
SIM_MODE : string := "SAFE";
|
|
3295
|
3324
|
SRVAL_A : bit_vector := X"00000";
|
|
3296
|
3325
|
SRVAL_B : bit_vector := X"00000";
|
|
3297
|
3326
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
3298
|
3327
|
WRITE_MODE_B : string := "WRITE_FIRST";
|
|
3299
|
3328
|
WRITE_WIDTH_A : integer := 0;
|
|
3300
|
3329
|
WRITE_WIDTH_B : integer := 0
|
|
3301
|
3330
|
|
|
3302
|
3331
|
);
|
|
3303
|
3332
|
|
|
3304
|
3333
|
port (
|
|
3305
|
3334
|
|
|
3306
|
3335
|
DOA : out std_logic_vector(15 downto 0);
|
|
3307
|
3336
|
DOB : out std_logic_vector(15 downto 0);
|
|
3308
|
3337
|
DOPA : out std_logic_vector(1 downto 0);
|
|
3309
|
3338
|
DOPB : out std_logic_vector(1 downto 0);
|
|
3310
|
3339
|
|
|
3311
|
3340
|
ADDRA : in std_logic_vector(13 downto 0);
|
|
3312
|
3341
|
ADDRB : in std_logic_vector(13 downto 0);
|
|
3313
|
3342
|
CLKA : in std_ulogic;
|
|
3314
|
3343
|
CLKB : in std_ulogic;
|
|
3315
|
3344
|
DIA : in std_logic_vector(15 downto 0);
|
|
3316
|
3345
|
DIB : in std_logic_vector(15 downto 0);
|
|
3317
|
3346
|
DIPA : in std_logic_vector(1 downto 0);
|
|
3318
|
3347
|
DIPB : in std_logic_vector(1 downto 0);
|
|
3319
|
3348
|
ENA : in std_ulogic;
|
|
3320
|
3349
|
ENB : in std_ulogic;
|
|
3321
|
3350
|
REGCEA : in std_ulogic;
|
|
3322
|
3351
|
REGCEB : in std_ulogic;
|
|
3323
|
3352
|
SSRA : in std_ulogic;
|
|
3324
|
3353
|
SSRB : in std_ulogic;
|
|
3325
|
3354
|
WEA : in std_logic_vector(1 downto 0);
|
|
3326
|
3355
|
WEB : in std_logic_vector(1 downto 0)
|
|
3327
|
3356
|
|
|
3328
|
3357
|
);
|
|
3329
|
3358
|
end component;
|
|
3330
|
3359
|
|
|
3331
|
3360
|
component RAMB36
|
|
3332
|
3361
|
generic (
|
|
3333
|
3362
|
|
|
3334
|
3363
|
DOA_REG : integer := 0;
|
|
3335
|
3364
|
DOB_REG : integer := 0;
|
|
3336
|
3365
|
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3337
|
3366
|
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3338
|
3367
|
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3339
|
3368
|
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3340
|
3369
|
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3341
|
3370
|
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3342
|
3371
|
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3343
|
3372
|
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3344
|
3373
|
INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3345
|
3374
|
INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3346
|
3375
|
INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3347
|
3376
|
INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3348
|
3377
|
INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3349
|
3378
|
INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3350
|
3379
|
INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3351
|
3380
|
INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3352
|
3381
|
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3353
|
3382
|
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3354
|
3383
|
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3355
|
3384
|
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3356
|
3385
|
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3357
|
3386
|
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3358
|
3387
|
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3359
|
3388
|
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3360
|
3389
|
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3361
|
3390
|
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3362
|
3391
|
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3363
|
3392
|
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3364
|
3393
|
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3365
|
3394
|
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3366
|
3395
|
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3367
|
3396
|
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3368
|
3397
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3369
|
3398
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3370
|
3399
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3371
|
3400
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3372
|
3401
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3373
|
3402
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3374
|
3403
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3375
|
3404
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3376
|
3405
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3377
|
3406
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3378
|
3407
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3379
|
3408
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3380
|
3409
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3381
|
3410
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3382
|
3411
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3383
|
3412
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3384
|
3413
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3385
|
3414
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3386
|
3415
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3387
|
3416
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3388
|
3417
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3389
|
3418
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3390
|
3419
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3391
|
3420
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3392
|
3421
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3393
|
3422
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3394
|
3423
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3395
|
3424
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3396
|
3425
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3397
|
3426
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3398
|
3427
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3399
|
3428
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3400
|
3429
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3401
|
3430
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3402
|
3431
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3403
|
3432
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3404
|
3433
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3405
|
3434
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3406
|
3435
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3407
|
3436
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3408
|
3437
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3409
|
3438
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3410
|
3439
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3411
|
3440
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3412
|
3441
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3413
|
3442
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3414
|
3443
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3415
|
3444
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3416
|
3445
|
INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3417
|
3446
|
INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3418
|
3447
|
INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3419
|
3448
|
INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3420
|
3449
|
INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3421
|
3450
|
INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3422
|
3451
|
INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3423
|
3452
|
INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3424
|
3453
|
INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3425
|
3454
|
INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3426
|
3455
|
INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3427
|
3456
|
INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3428
|
3457
|
INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3429
|
3458
|
INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3430
|
3459
|
INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3431
|
3460
|
INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3432
|
3461
|
INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3433
|
3462
|
INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3434
|
3463
|
INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3435
|
3464
|
INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3436
|
3465
|
INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3437
|
3466
|
INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3438
|
3467
|
INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3439
|
3468
|
INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3440
|
3469
|
INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3441
|
3470
|
INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3442
|
3471
|
INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3443
|
3472
|
INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3444
|
3473
|
INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3445
|
3474
|
INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3446
|
3475
|
INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3447
|
3476
|
INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3448
|
3477
|
INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3449
|
3478
|
INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3450
|
3479
|
INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3451
|
3480
|
INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3452
|
3481
|
INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3453
|
3482
|
INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3454
|
3483
|
INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3455
|
3484
|
INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3456
|
3485
|
INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3457
|
3486
|
INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3458
|
3487
|
INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3459
|
3488
|
INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3460
|
3489
|
INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3461
|
3490
|
INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3462
|
3491
|
INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3463
|
3492
|
INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3464
|
3493
|
INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3465
|
3494
|
INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3466
|
3495
|
INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3467
|
3496
|
INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3468
|
3497
|
INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3469
|
3498
|
INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3470
|
3499
|
INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3471
|
3500
|
INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3472
|
3501
|
INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3473
|
3502
|
INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3474
|
3503
|
INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3475
|
3504
|
INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3476
|
3505
|
INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3477
|
3506
|
INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3478
|
3507
|
INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3479
|
3508
|
INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
|
3480
|
3509
|
INIT_A : bit_vector := X"000000000";
|
|
3481
|
3510
|
INIT_B : bit_vector := X"000000000";
|
|
3482
|
3511
|
INIT_FILE : string := "NONE";
|
|
3483
|
3512
|
RAM_EXTENSION_A : string := "NONE";
|
|
3484
|
3513
|
RAM_EXTENSION_B : string := "NONE";
|
|
3485
|
3514
|
READ_WIDTH_A : integer := 0;
|
|
3486
|
3515
|
READ_WIDTH_B : integer := 0;
|
|
3487
|
3516
|
SIM_COLLISION_CHECK : string := "ALL";
|
|
3488
|
3517
|
SIM_MODE : string := "SAFE";
|
|
3489
|
3518
|
SRVAL_A : bit_vector := X"000000000";
|
|
3490
|
3519
|
SRVAL_B : bit_vector := X"000000000";
|
|
3491
|
3520
|
WRITE_MODE_A : string := "WRITE_FIRST";
|
|
3492
|
3521
|
WRITE_MODE_B : string := "WRITE_FIRST";
|
|
3493
|
3522
|
WRITE_WIDTH_A : integer := 0;
|
|
3494
|
3523
|
WRITE_WIDTH_B : integer := 0
|
|
3495
|
3524
|
|
|
3496
|
3525
|
);
|
|
3497
|
3526
|
|
|
3498
|
3527
|
port (
|
|
3499
|
3528
|
|
|
3500
|
3529
|
CASCADEOUTLATA : out std_ulogic;
|
|
3501
|
3530
|
CASCADEOUTLATB : out std_ulogic;
|
|
3502
|
3531
|
CASCADEOUTREGA : out std_ulogic;
|
|
3503
|
3532
|
CASCADEOUTREGB : out std_ulogic;
|
|
3504
|
3533
|
DOA : out std_logic_vector(31 downto 0);
|
|
3505
|
3534
|
DOB : out std_logic_vector(31 downto 0);
|
|
3506
|
3535
|
DOPA : out std_logic_vector(3 downto 0);
|
|
3507
|
3536
|
DOPB : out std_logic_vector(3 downto 0);
|
|
3508
|
3537
|
|
|
3509
|
3538
|
ADDRA : in std_logic_vector(15 downto 0);
|
|
3510
|
3539
|
ADDRB : in std_logic_vector(15 downto 0);
|
|
3511
|
3540
|
CASCADEINLATA : in std_ulogic;
|
|
3512
|
3541
|
CASCADEINLATB : in std_ulogic;
|
|
3513
|
3542
|
CASCADEINREGA : in std_ulogic;
|
|
3514
|
3543
|
CASCADEINREGB : in std_ulogic;
|
|
3515
|
3544
|
CLKA : in std_ulogic;
|
|
3516
|
3545
|
CLKB : in std_ulogic;
|
|
3517
|
3546
|
DIA : in std_logic_vector(31 downto 0);
|
|
3518
|
3547
|
DIB : in std_logic_vector(31 downto 0);
|
|
3519
|
3548
|
DIPA : in std_logic_vector(3 downto 0);
|
|
3520
|
3549
|
DIPB : in std_logic_vector(3 downto 0);
|
|
3521
|
3550
|
ENA : in std_ulogic;
|
|
3522
|
3551
|
ENB : in std_ulogic;
|
|
3523
|
3552
|
REGCEA : in std_ulogic;
|
|
3524
|
3553
|
REGCEB : in std_ulogic;
|
|
3525
|
3554
|
SSRA : in std_ulogic;
|
|
3526
|
3555
|
SSRB : in std_ulogic;
|
|
3527
|
3556
|
WEA : in std_logic_vector(3 downto 0);
|
|
3528
|
3557
|
WEB : in std_logic_vector(3 downto 0)
|
|
3529
|
3558
|
|
|
3530
|
3559
|
);
|
|
3531
|
3560
|
end component;
|
|
3532
|
3561
|
|
|
3533
|
3562
|
component BUFGCE
|
|
3534
|
3563
|
port(
|
|
3535
|
3564
|
O : out STD_ULOGIC;
|
|
3536
|
3565
|
|
|
3537
|
3566
|
CE: in STD_ULOGIC;
|
|
3538
|
3567
|
I : in STD_ULOGIC
|
|
3539
|
3568
|
);
|
|
3540
|
3569
|
end component;
|
|
3541
|
3570
|
|
|
3542
|
3571
|
component RAM64X1S
|
|
3543
|
3572
|
generic (
|
|
3544
|
3573
|
INIT : bit_vector(63 downto 0) := X"0000000000000000"
|
|
3545
|
3574
|
);
|
|
3546
|
3575
|
|
|
3547
|
3576
|
port (
|
|
3548
|
3577
|
O : out std_ulogic;
|
|
3549
|
3578
|
|
|
3550
|
3579
|
A0 : in std_ulogic;
|
|
3551
|
3580
|
A1 : in std_ulogic;
|
|
3552
|
3581
|
A2 : in std_ulogic;
|
|
3553
|
3582
|
A3 : in std_ulogic;
|
|
3554
|
3583
|
A4 : in std_ulogic;
|
|
3555
|
3584
|
A5 : in std_ulogic;
|
|
3556
|
3585
|
D : in std_ulogic;
|
|
3557
|
3586
|
WCLK : in std_ulogic;
|
|
3558
|
3587
|
WE : in std_ulogic
|
|
3559
|
3588
|
);
|
|
3560
|
3589
|
end component;
|
|
3561
|
3590
|
|
|
3562
|
3591
|
component IBUFDS_GTXE1
|
|
3563
|
3592
|
generic (
|
|
3564
|
3593
|
CLKCM_CFG : boolean := TRUE;
|
|
3565
|
3594
|
CLKRCV_TRST : boolean := TRUE;
|
|
3566
|
3595
|
REFCLKOUT_DLY : bit_vector := b"0000000000"
|
|
3567
|
3596
|
);
|
|
3568
|
3597
|
port (
|
|
3569
|
3598
|
O : out std_ulogic;
|
|
3570
|
3599
|
ODIV2 : out std_ulogic;
|
|
3571
|
3600
|
CEB : in std_ulogic;
|
|
3572
|
3601
|
I : in std_ulogic;
|
|
3573
|
3602
|
IB : in std_ulogic
|
|
3574
|
3603
|
);
|
|
3575
|
3604
|
end component;
|
|
3576
|
3605
|
|
|
3577
|
3606
|
----- component MMCM_ADV -----
|
|
3578
|
3607
|
component MMCM_ADV
|
|
3579
|
3608
|
generic (
|
|
3580
|
3609
|
BANDWIDTH : string := "OPTIMIZED";
|
|
3581
|
3610
|
CLKFBOUT_MULT_F : real := 5.000;
|
|
3582
|
3611
|
CLKFBOUT_PHASE : real := 0.000;
|
|
3583
|
3612
|
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
|
|
3584
|
3613
|
CLKIN1_PERIOD : real := 0.000;
|
|
3585
|
3614
|
CLKIN2_PERIOD : real := 0.000;
|
|
3586
|
3615
|
CLKOUT0_DIVIDE_F : real := 1.000;
|
|
3587
|
3616
|
CLKOUT0_DUTY_CYCLE : real := 0.500;
|
|
3588
|
3617
|
CLKOUT0_PHASE : real := 0.000;
|
|
3589
|
3618
|
CLKOUT0_USE_FINE_PS : boolean := FALSE;
|
|
3590
|
3619
|
CLKOUT1_DIVIDE : integer := 1;
|
|
3591
|
3620
|
CLKOUT1_DUTY_CYCLE : real := 0.500;
|
|
3592
|
3621
|
CLKOUT1_PHASE : real := 0.000;
|
|
3593
|
3622
|
CLKOUT1_USE_FINE_PS : boolean := FALSE;
|
|
3594
|
3623
|
CLKOUT2_DIVIDE : integer := 1;
|
|
3595
|
3624
|
CLKOUT2_DUTY_CYCLE : real := 0.500;
|
|
3596
|
3625
|
CLKOUT2_PHASE : real := 0.000;
|
|
3597
|
3626
|
CLKOUT2_USE_FINE_PS : boolean := FALSE;
|
|
3598
|
3627
|
CLKOUT3_DIVIDE : integer := 1;
|
|
3599
|
3628
|
CLKOUT3_DUTY_CYCLE : real := 0.500;
|
|
3600
|
3629
|
CLKOUT3_PHASE : real := 0.000;
|
|
3601
|
3630
|
CLKOUT3_USE_FINE_PS : boolean := FALSE;
|
|
3602
|
3631
|
CLKOUT4_CASCADE : boolean := FALSE;
|
|
3603
|
3632
|
CLKOUT4_DIVIDE : integer := 1;
|
|
3604
|
3633
|
CLKOUT4_DUTY_CYCLE : real := 0.500;
|
|
3605
|
3634
|
CLKOUT4_PHASE : real := 0.000;
|
|
3606
|
3635
|
CLKOUT4_USE_FINE_PS : boolean := FALSE;
|
|
3607
|
3636
|
CLKOUT5_DIVIDE : integer := 1;
|
|
3608
|
3637
|
CLKOUT5_DUTY_CYCLE : real := 0.500;
|
|
3609
|
3638
|
CLKOUT5_PHASE : real := 0.000;
|
|
3610
|
3639
|
CLKOUT5_USE_FINE_PS : boolean := FALSE;
|
|
3611
|
3640
|
CLKOUT6_DIVIDE : integer := 1;
|
|
3612
|
3641
|
CLKOUT6_DUTY_CYCLE : real := 0.500;
|
|
3613
|
3642
|
CLKOUT6_PHASE : real := 0.000;
|
|
3614
|
3643
|
CLKOUT6_USE_FINE_PS : boolean := FALSE;
|
|
3615
|
3644
|
CLOCK_HOLD : boolean := FALSE;
|
|
3616
|
3645
|
COMPENSATION : string := "ZHOLD";
|
|
3617
|
3646
|
DIVCLK_DIVIDE : integer := 1;
|
|
3618
|
3647
|
REF_JITTER1 : real := 0.0;
|
|
3619
|
3648
|
REF_JITTER2 : real := 0.0;
|
|
3620
|
3649
|
STARTUP_WAIT : boolean := FALSE
|
|
3621
|
3650
|
);
|
|
3622
|
3651
|
port (
|
|
3623
|
3652
|
CLKFBOUT : out std_ulogic := '0';
|
|
3624
|
3653
|
CLKFBOUTB : out std_ulogic := '0';
|
|
3625
|
3654
|
CLKFBSTOPPED : out std_ulogic := '0';
|
|
3626
|
3655
|
CLKINSTOPPED : out std_ulogic := '0';
|
|
3627
|
3656
|
CLKOUT0 : out std_ulogic := '0';
|
|
3628
|
3657
|
CLKOUT0B : out std_ulogic := '0';
|
|
3629
|
3658
|
CLKOUT1 : out std_ulogic := '0';
|
|
3630
|
3659
|
CLKOUT1B : out std_ulogic := '0';
|
|
3631
|
3660
|
CLKOUT2 : out std_ulogic := '0';
|
|
3632
|
3661
|
CLKOUT2B : out std_ulogic := '0';
|
|
3633
|
3662
|
CLKOUT3 : out std_ulogic := '0';
|
|
3634
|
3663
|
CLKOUT3B : out std_ulogic := '0';
|
|
3635
|
3664
|
CLKOUT4 : out std_ulogic := '0';
|
|
3636
|
3665
|
CLKOUT5 : out std_ulogic := '0';
|
|
3637
|
3666
|
CLKOUT6 : out std_ulogic := '0';
|
|
3638
|
3667
|
DO : out std_logic_vector (15 downto 0);
|
|
3639
|
3668
|
DRDY : out std_ulogic := '0';
|
|
3640
|
3669
|
LOCKED : out std_ulogic := '0';
|
|
3641
|
3670
|
PSDONE : out std_ulogic := '0';
|
|
3642
|
3671
|
CLKFBIN : in std_ulogic;
|
|
3643
|
3672
|
CLKIN1 : in std_ulogic;
|
|
3644
|
3673
|
CLKIN2 : in std_ulogic;
|
|
3645
|
3674
|
CLKINSEL : in std_ulogic;
|
|
3646
|
3675
|
DADDR : in std_logic_vector(6 downto 0);
|
|
3647
|
3676
|
DCLK : in std_ulogic;
|
|
3648
|
3677
|
DEN : in std_ulogic;
|
|
3649
|
3678
|
DI : in std_logic_vector(15 downto 0);
|
|
3650
|
3679
|
DWE : in std_ulogic;
|
|
3651
|
3680
|
PSCLK : in std_ulogic;
|
|
3652
|
3681
|
PSEN : in std_ulogic;
|
|
3653
|
3682
|
PSINCDEC : in std_ulogic;
|
|
3654
|
3683
|
PWRDWN : in std_ulogic;
|
|
3655
|
3684
|
RST : in std_ulogic
|
|
3656
|
3685
|
);
|
|
3657
|
3686
|
end component;
|
|
3658
|
3687
|
|
|
3659
|
3688
|
component OSERDESE1
|
|
3660
|
3689
|
generic (
|
|
3661
|
3690
|
DATA_RATE_OQ : string := "DDR";
|
|
3662
|
3691
|
DATA_RATE_TQ : string := "DDR";
|
|
3663
|
3692
|
DATA_WIDTH : integer := 4;
|
|
3664
|
3693
|
DDR3_DATA : integer := 1;
|
|
3665
|
3694
|
INIT_OQ : bit := '0';
|
|
3666
|
3695
|
INIT_TQ : bit := '0';
|
|
3667
|
3696
|
INTERFACE_TYPE : string := "DEFAULT";
|
|
3668
|
3697
|
ODELAY_USED : integer := 0;
|
|
3669
|
3698
|
SERDES_MODE : string := "MASTER";
|
|
3670
|
3699
|
SRVAL_OQ : bit := '0';
|
|
3671
|
3700
|
SRVAL_TQ : bit := '0';
|
|
3672
|
3701
|
TRISTATE_WIDTH : integer := 4
|
|
3673
|
3702
|
);
|
|
3674
|
3703
|
port (
|
|
3675
|
3704
|
OCBEXTEND : out std_ulogic;
|
|
3676
|
3705
|
OFB : out std_ulogic;
|
|
3677
|
3706
|
OQ : out std_ulogic;
|
|
3678
|
3707
|
SHIFTOUT1 : out std_ulogic;
|
|
3679
|
3708
|
SHIFTOUT2 : out std_ulogic;
|
|
3680
|
3709
|
TFB : out std_ulogic;
|
|
3681
|
3710
|
TQ : out std_ulogic;
|
|
3682
|
3711
|
CLK : in std_ulogic;
|
|
3683
|
3712
|
CLKDIV : in std_ulogic;
|
|
3684
|
3713
|
CLKPERF : in std_ulogic;
|
|
3685
|
3714
|
CLKPERFDELAY : in std_ulogic;
|
|
3686
|
3715
|
D1 : in std_ulogic;
|
|
3687
|
3716
|
D2 : in std_ulogic;
|
|
3688
|
3717
|
D3 : in std_ulogic;
|
|
3689
|
3718
|
D4 : in std_ulogic;
|
|
3690
|
3719
|
D5 : in std_ulogic;
|
|
3691
|
3720
|
D6 : in std_ulogic;
|
|
3692
|
3721
|
OCE : in std_ulogic;
|
|
3693
|
3722
|
ODV : in std_ulogic;
|
|
3694
|
3723
|
RST : in std_ulogic;
|
|
3695
|
3724
|
SHIFTIN1 : in std_ulogic;
|
|
3696
|
3725
|
SHIFTIN2 : in std_ulogic;
|
|
3697
|
3726
|
T1 : in std_ulogic;
|
|
3698
|
3727
|
T2 : in std_ulogic;
|
|
3699
|
3728
|
T3 : in std_ulogic;
|
|
3700
|
3729
|
T4 : in std_ulogic;
|
|
3701
|
3730
|
TCE : in std_ulogic;
|
|
3702
|
3731
|
WC : in std_ulogic
|
|
3703
|
3732
|
);
|
|
3704
|
3733
|
end component;
|
|
3705
|
3734
|
|
|
3706
|
3735
|
component IODELAYE1
|
|
3707
|
3736
|
generic (
|
|
3708
|
3737
|
CINVCTRL_SEL : boolean := FALSE;
|
|
3709
|
3738
|
DELAY_SRC : string := "I";
|
|
3710
|
3739
|
HIGH_PERFORMANCE_MODE : boolean := FALSE;
|
|
3711
|
3740
|
IDELAY_TYPE : string := "DEFAULT";
|
|
3712
|
3741
|
IDELAY_VALUE : integer := 0;
|
|
3713
|
3742
|
ODELAY_TYPE : string := "FIXED";
|
|
3714
|
3743
|
ODELAY_VALUE : integer := 0;
|
|
3715
|
3744
|
REFCLK_FREQUENCY : real := 200.0;
|
|
3716
|
3745
|
SIGNAL_PATTERN : string := "DATA"
|
|
3717
|
3746
|
);
|
|
3718
|
3747
|
port (
|
|
3719
|
3748
|
CNTVALUEOUT : out std_logic_vector(4 downto 0);
|
|
3720
|
3749
|
DATAOUT : out std_ulogic;
|
|
3721
|
3750
|
C : in std_ulogic;
|
|
3722
|
3751
|
CE : in std_ulogic;
|
|
3723
|
3752
|
CINVCTRL : in std_ulogic;
|
|
3724
|
3753
|
CLKIN : in std_ulogic;
|
|
3725
|
3754
|
CNTVALUEIN : in std_logic_vector(4 downto 0);
|
|
3726
|
3755
|
DATAIN : in std_ulogic;
|
|
3727
|
3756
|
IDATAIN : in std_ulogic;
|
|
3728
|
3757
|
INC : in std_ulogic;
|
|
3729
|
3758
|
ODATAIN : in std_ulogic;
|
|
3730
|
3759
|
RST : in std_ulogic;
|
|
3731
|
3760
|
T : in std_ulogic
|
|
3732
|
3761
|
);
|
|
3733
|
3762
|
end component;
|
|
3734
|
3763
|
|
|
3735
|
3764
|
component ISERDESE1
|
|
3736
|
3765
|
generic (
|
|
3737
|
3766
|
DATA_RATE : string := "DDR";
|
|
3738
|
3767
|
DATA_WIDTH : integer := 4;
|
|
3739
|
3768
|
DYN_CLKDIV_INV_EN : boolean := FALSE;
|
|
3740
|
3769
|
DYN_CLK_INV_EN : boolean := FALSE;
|
|
3741
|
3770
|
INIT_Q1 : bit := '0';
|
|
3742
|
3771
|
INIT_Q2 : bit := '0';
|
|
3743
|
3772
|
INIT_Q3 : bit := '0';
|
|
3744
|
3773
|
INIT_Q4 : bit := '0';
|
|
3745
|
3774
|
INTERFACE_TYPE : string := "MEMORY";
|
|
3746
|
3775
|
IOBDELAY : string := "NONE";
|
|
3747
|
3776
|
NUM_CE : integer := 2;
|
|
3748
|
3777
|
OFB_USED : boolean := FALSE;
|
|
3749
|
3778
|
SERDES_MODE : string := "MASTER";
|
|
3750
|
3779
|
SRVAL_Q1 : bit := '0';
|
|
3751
|
3780
|
SRVAL_Q2 : bit := '0';
|
|
3752
|
3781
|
SRVAL_Q3 : bit := '0';
|
|
3753
|
3782
|
SRVAL_Q4 : bit := '0'
|
|
3754
|
3783
|
);
|
|
3755
|
3784
|
port (
|
|
3756
|
3785
|
O : out std_ulogic;
|
|
3757
|
3786
|
Q1 : out std_ulogic;
|
|
3758
|
3787
|
Q2 : out std_ulogic;
|
|
3759
|
3788
|
Q3 : out std_ulogic;
|
|
3760
|
3789
|
Q4 : out std_ulogic;
|
|
3761
|
3790
|
Q5 : out std_ulogic;
|
|
3762
|
3791
|
Q6 : out std_ulogic;
|
|
3763
|
3792
|
SHIFTOUT1 : out std_ulogic;
|
|
3764
|
3793
|
SHIFTOUT2 : out std_ulogic;
|
|
3765
|
3794
|
BITSLIP : in std_ulogic;
|
|
3766
|
3795
|
CE1 : in std_ulogic;
|
|
3767
|
3796
|
CE2 : in std_ulogic;
|
|
3768
|
3797
|
CLK : in std_ulogic;
|
|
3769
|
3798
|
CLKB : in std_ulogic;
|
|
3770
|
3799
|
CLKDIV : in std_ulogic;
|
|
3771
|
3800
|
D : in std_ulogic;
|
|
3772
|
3801
|
DDLY : in std_ulogic;
|
|
3773
|
3802
|
DYNCLKDIVSEL : in std_ulogic;
|
|
3774
|
3803
|
DYNCLKSEL : in std_ulogic;
|
|
3775
|
3804
|
OCLK : in std_ulogic;
|
|
3776
|
3805
|
OFB : in std_ulogic;
|
|
3777
|
3806
|
RST : in std_ulogic;
|
|
3778
|
3807
|
SHIFTIN1 : in std_ulogic;
|
|
3779
|
3808
|
SHIFTIN2 : in std_ulogic
|
|
3780
|
3809
|
);
|
|
3781
|
3810
|
end component;
|
|
3782
|
3811
|
|
|
3783
|
3812
|
component IOBUFDS_DIFF_OUT
|
|
3784
|
3813
|
generic (
|
|
3785
|
3814
|
DIFF_TERM : boolean := FALSE;
|
|
3786
|
3815
|
IBUF_LOW_PWR : boolean := TRUE;
|
|
3787
|
3816
|
IOSTANDARD : string := "DEFAULT"
|
|
3788
|
3817
|
);
|
|
3789
|
3818
|
port (
|
|
3790
|
3819
|
O : out std_ulogic;
|
|
3791
|
3820
|
OB : out std_ulogic;
|
|
3792
|
3821
|
IO : inout std_ulogic;
|
|
3793
|
3822
|
IOB : inout std_ulogic;
|
|
3794
|
3823
|
I : in std_ulogic;
|
|
3795
|
3824
|
TM : in std_ulogic;
|
|
3796
|
3825
|
TS : in std_ulogic
|
|
3797
|
3826
|
);
|
|
3798
|
3827
|
end component;
|
|
3799
|
3828
|
|
|
3800
|
3829
|
component SRLC32E
|
|
3801
|
3830
|
generic (
|
|
3802
|
3831
|
INIT : bit_vector := X"00000000"
|
|
3803
|
3832
|
);
|
|
3804
|
3833
|
port (
|
|
3805
|
3834
|
Q : out STD_ULOGIC;
|
|
3806
|
3835
|
Q31 : out STD_ULOGIC;
|
|
3807
|
3836
|
A : in STD_LOGIC_VECTOR (4 downto 0);
|
|
3808
|
3837
|
CE : in STD_ULOGIC;
|
|
3809
|
3838
|
CLK : in STD_ULOGIC;
|
|
3810
|
3839
|
D : in STD_ULOGIC
|
|
3811
|
3840
|
);
|
|
3812
|
3841
|
end component;
|
|
3813
|
3842
|
|
|
3814
|
3843
|
end;
|