----------------------------------------------------------------------------- -- LEON3 Xilinx SP605 Demonstration design -- Copyright (C) 2011 Jiri Gaisler, Aeroflex Gaisler ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2011, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; use grlib.amba.all; use grlib.stdlib.all; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.spi.all; use gaisler.i2c.all; use gaisler.can.all; use gaisler.net.all; use gaisler.jtag.all; use gaisler.spacewire.all; -- pragma translate_off use gaisler.sim.all; library unisim; use unisim.ODDR2; -- pragma translate_on library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW ); port ( reset : in std_ulogic; clk27 : in std_ulogic; -- 27 MHz clock clk200p : in std_ulogic; -- 200 MHz clock clk200n : in std_ulogic; -- 200 MHz clock clk33 : in std_ulogic; -- 32 MHz clock from sysace address : out std_logic_vector(23 downto 0); data : inout std_logic_vector(15 downto 0); oen : out std_ulogic; writen : out std_ulogic; romsn : out std_logic; txd1 : out std_ulogic; -- UART1 tx data rxd1 : in std_ulogic; -- UART1 rx data ctsn1 : in std_ulogic; -- UART1 ctsn rtsn1 : out std_ulogic; -- UART1 trsn button : inout std_logic_vector(3 downto 0); -- I/O port switch : inout std_logic_vector(3 downto 0); -- I/O port led : out std_logic_vector(3 downto 0) -- I/O port ); end; architecture rtl of leon3mp is --attribute syn_netlist_hierarchy : boolean; --attribute syn_netlist_hierarchy of rtl : architecture is false; component ODDR2 generic ( DDR_ALIGNMENT : string := "NONE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); port ( Q : out std_ulogic; C0 : in std_ulogic; C1 : in std_ulogic; CE : in std_ulogic := 'H'; D0 : in std_ulogic; D1 : in std_ulogic; R : in std_ulogic := 'L'; S : in std_ulogic := 'L' ); end component; constant blength : integer := 12; constant fifodepth : integer := 8; constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG; signal vcc, gnd : std_logic; signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdram_out_type; signal sdo2, sdo3 : sdctrl_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal vahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal vahbmo : ahb_mst_out_type; signal clkm, rstn, rstraw, sdclkl : std_ulogic; signal clk_200 : std_ulogic; signal clk25, clk40, clk65 : std_ulogic; signal cgi, cgi2 : clkgen_in_type; signal cgo, cgo2 : clkgen_out_type; signal u1i, u2i, dui : uart_in_type; signal u1o, u2o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal gpti : gptimer_in_type; signal gpto : gptimer_out_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal clklock, elock, ulock : std_ulogic; signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic; signal tck, tckn, tms, tdi, tdo : std_ulogic; constant BOARD_FREQ : integer := 33000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz constant IOAEN : integer := 0; constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz signal stati : ahbstat_in_type; signal fpi : grfpu_in_vector_type; signal fpo : grfpu_out_vector_type; signal clk_sel : std_logic_vector(1 downto 0); signal clkvga, clkvga_p, clkvga_n : std_ulogic; attribute keep : boolean; attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_preserve of clkm : signal is true; attribute keep of clkm : signal is true; begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= '1'; gnd <= '0'; cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; clk_pad : clkpad generic map (tech => padtech) port map (clk33, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ) port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, open, open); reset_pad : inpad generic map (tech => padtech) port map (reset, rst); rst0 : rstgen -- reset generator generic map (acthigh => 1) port map (rst, clkm, lock, rstn, rstraw); lock <= cgo.clklock and calib_done when CFG_MIG_DDR2 = 1 else cgo.clklock; ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => maxahbm, nahbs => 16) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- nosh : if CFG_GRFPUSH = 0 generate nocpu: if CFG_NCPU>0 generate cpu : for i in 0 to CFG_NCPU-1 generate l3s : if CFG_LEON3FT_EN = 0 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; end generate; led1_pad : odpad generic map (tech => padtech) port map (led(1), dbgo(0).error); end generate; end generate; dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsui.break <= button(3); dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact); ndsuact <= not dsuo.active; end generate; nodsu : if CFG_DSU = 0 generate dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none; end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01"; memi.brdyn <= '0'; memi.bexcn <= '1'; mctrl0 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN, invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS, pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); addr_pad : outpadv generic map (width => 24, tech => padtech) port map (address, memo.address(24 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); data_pad : iopadvv generic map (tech => padtech, width => 16) port map (data(15 downto 0), memo.data(31 downto 16), memo.vbdrive(31 downto 16), memi.data(31 downto 16)); ----------------------------------------------------------------------- --- Test report module ---------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off test0 : ahbrep generic map (hindex => 6, haddr => 16#200#) port map (rstn, clkm, ahbsi, ahbso(6)); -- pragma translate_on led(2) <= calib_done; led(3) <= lock; noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.extclk <= '0'; rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd); txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd); cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn); rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn); end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; nocpu: if CFG_NCPU>0 generate irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW, wdog => 0) port map (rstn, clkm, apbi, apbo(3), gpti, gpto); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; end generate; nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to 3 generate pio_pad : iopad generic map (tech => padtech) port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; pio_pads2 : for i in 4 to 6 generate pio_pad : iopad generic map (tech => padtech) port map (button(i-4), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7, nftslv => CFG_AHBSTATN) port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15)); end generate; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_version generic map ( msg1 => "LEON3 Xilinx SP605 Demonstration design", msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100) & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD), msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech), mdel => 1 ); -- pragma translate_on end;