KEY LIBERO "8.1"
KEY CAPTURE "8.1.0.32"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "PROASIC3"
KEY VendorTechnology_Die "IT14X14M4LDP"
KEY VendorTechnology_Package "fg324"
KEY ProjectLocation "."
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "top"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
grlib
proasic3
synplify
techmap
spw
eth
opencores
gaisler
esa
fmf
spansion
gsi
lpp
cypress
work
ENDLIST
LIST LIBRARIES_grlib
ALIAS=grlib
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_proasic3
ALIAS=proasic3
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_synplify
ALIAS=synplify
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_techmap
ALIAS=techmap
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spw
ALIAS=spw
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_eth
ALIAS=eth
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_opencores
ALIAS=opencores
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gaisler
ALIAS=gaisler
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_esa
ALIAS=esa
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_fmf
ALIAS=fmf
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_spansion
ALIAS=spansion
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_gsi
ALIAS=gsi
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_lpp
ALIAS=lpp
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_cypress
ALIAS=cypress
COMPILE_OPTION=COMPILE
ENDLIST
LIST LIBRARIES_work
ALIAS=work
COMPILE_OPTION=COMPILE
ENDLIST
LIST FileManager
VALUE "<project>/../..//lib/grlib/stdlib/version.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/stdlib/stdlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/stdlib/stdio.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/util/util.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/sparc/sparc.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/sparc/sparc_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/sparc/cpu_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/modgen/multlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/modgen/leaves.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/amba.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/devices.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/defmst.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/apbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/ahbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_pkg.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/dma2ahb.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_tp.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../..//lib/tech/proasic3/components/proasic3.vhd,hdl"
STATE="utd"
LIBRARY="proasic3"
ENDFILE
VALUE "<project>/../..//lib/synplify/sim/synplify.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../..//lib/synplify/sim/synattr.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../..//lib/techmap/gencomp/gencomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/gencomp/netcomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/inferred/memory_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/inferred/ddr_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/inferred/mul_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/memory_apa3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/buffer_apa3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/proasic3/tap_proasic3.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allclkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allmem.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/allpads.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/alltap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkmux.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkand.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ddr_ireg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ddr_oreg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ddrphy.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram64.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram_2p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncram_dp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/syncfifo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/regfile_3p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/tap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/techbuf.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/clkpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/inpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/inpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/iodpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/iopad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/iopad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/lvds_combo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/odpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/outpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/toutpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/skew_outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/grspwc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/grlfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/grfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/mul_61x61.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/cpu_disas_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/usbhc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ringosc.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/techmap/maps/ssrctrl_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../..//lib/spw/comp/spwcomp.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../..//lib/eth/comp/ethcomp.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/greth_pkg.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/eth_rstgen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/eth_ahb_mst.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/greth_tx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/greth_rx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/core/grethc.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/wrapper/greth_gen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/eth/wrapper/greth_gbit_gen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../..//lib/opencores/occomp/occomp.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../..//lib/opencores/can/cancomp.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../..//lib/opencores/can/can_top.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../..//lib/opencores/can/can_top_core_sync.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../..//lib/gaisler/arith/arith.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/arith/mul32.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/arith/div32.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/memctrl/memctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/memctrl/sdctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/memctrl/sdmctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/memctrl/srctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/leon3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmuconfig.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmuiface.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/libmmu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/libiu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/libcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/libproc3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/cachemem.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmu_icache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmu_dcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmu_acache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmutlbcam.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmulrue.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmulru.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmutlb.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmutw.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mmu_cache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/acache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/dcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/icache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/cache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/cpu_disasx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/iu3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/grfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/mfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/grlfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/tbufmem.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/dsu3x.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/dsu3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/proc3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/leon3s.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/leon3cg.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/irqmp.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/grfpwxsh.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/grfpushwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/leon3/leon3sh.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/can/can.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/can/can_mod.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/can/can_oc.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/can/can_mc.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/can/canmux.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/can/can_rd.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/misc.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/rstgen.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/gptimer.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/ahbram.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/ahbtrace.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/ahbmst.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/grgpio.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/ahbstat.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/logan.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/apbps2.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/charrom_package.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/charrom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/apbvga.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/ahbdma.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/svgactrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/spictrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/i2cslv.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/wild.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/misc/wild2ahb.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/ambatest/ambatest.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/ambatest/ahb_tbfunct.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/ambatest/ahbslv_em.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/ambatest/ahbmst_em.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/net/net.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/uart/uart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/uart/libdcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/uart/apbuart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/uart/dcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/uart/dcom_uart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/uart/ahbuart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/i2c_slave_model.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/sim.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/sram.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/ata_device.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/sram16.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/phy.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/sim/ahbrep.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/jtag/jtag.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/jtag/libjtagcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/jtag/jtagcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/jtag/jtagtst.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/greth/ethernet_mac.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/greth/greth.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/greth/greth_gbit.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/greth/grethm.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/spacewire/spacewire.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/spacewire/grspw.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/spacewire/grspw2.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/gaisler/spacewire/grspwm.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../..//lib/esa/memoryctrl/memoryctrl.vhd,hdl"
STATE="utd"
LIBRARY="esa"
ENDFILE
VALUE "<project>/../..//lib/esa/memoryctrl/mctrl.vhd,hdl"
STATE="utd"
LIBRARY="esa"
ENDFILE
VALUE "<project>/../..//lib/fmf/utilities/conversions.vhd,hdl"
STATE="utd"
LIBRARY="fmf"
ENDFILE
VALUE "<project>/../..//lib/fmf/utilities/gen_utils.vhd,hdl"
STATE="utd"
LIBRARY="fmf"
ENDFILE
VALUE "<project>/../..//lib/gsi/ssram/functions.vhd,hdl"
STATE="utd"
LIBRARY="gsi"
ENDFILE
VALUE "<project>/../..//lib/gsi/ssram/core_burst.vhd,hdl"
STATE="utd"
LIBRARY="gsi"
ENDFILE
VALUE "<project>/../..//lib/gsi/ssram/g880e18bt.vhd,hdl"
STATE="utd"
LIBRARY="gsi"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/CoreFFT.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/actar.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/actram.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fftDp.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fftSm.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fft_components.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/primitives.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/twiddle.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/ALU.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/Adder.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/Clk_divider.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_MUX.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_REG.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/MUX2.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/Multiplier.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/REG.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/Shifter.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./general_purpose/general_purpose.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/Serialize.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/Starter.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/ApbDriver.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_uart/UART.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_usb/APB_USB.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
STATE="utd"
LIBRARY="lpp"
ENDFILE
VALUE "<project>/../..//lib/cypress/ssram/components.vhd,hdl"
STATE="utd"
LIBRARY="cypress"
ENDFILE
VALUE "<project>/../..//lib/cypress/ssram/package_utility.vhd,hdl"
STATE="utd"
LIBRARY="cypress"
ENDFILE
VALUE "<project>/../..//lib/cypress/ssram/cy7c1354b.vhd,hdl"
STATE="utd"
LIBRARY="cypress"
ENDFILE
VALUE "<project>/../..//lib/cypress/ssram/cy7c1380d.vhd,hdl"
STATE="utd"
LIBRARY="cypress"
ENDFILE
VALUE "<project>/../..//lib/work/debug/debug.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/../..//lib/work/debug/grtestmod.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/../..//lib/work/debug/cpu_disas.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/config.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/ahbrom.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/leon3mp.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/testbench.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/../..//boards/TEST-LEON-M7-LPP/TEST-LEON-M7-LPP.pdc,pdc"
STATE="utd"
ENDFILE
ENDLIST
LIST SimulationOptions
ENDLIST
LIST ExcludePackageForSimulation
LIST top
ENDLIST
ENDLIST
LIST ExcludePackageForSynthesis
LIST top
VALUE "<project>/../..//lib/grlib/stdlib/stdio.vhd,hdl"
VALUE "<project>/../..//lib/grlib/util/util.vhd,hdl"
VALUE "<project>/../..//lib/grlib/sparc/sparc_disas.vhd,hdl"
VALUE "<project>/../..//lib/grlib/sparc/cpu_disas.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_tp.vhd,hdl"
VALUE "<project>/../..//lib/tech/proasic3/components/proasic3.vhd,hdl"
VALUE "<project>/../..//lib/synplify/sim/synplify.vhd,hdl"
VALUE "<project>/../..//lib/synplify/sim/synattr.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ambatest.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ahb_tbfunct.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ahbslv_em.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ahbmst_em.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/i2c_slave_model.v,hdl"
VALUE "<project>/../..//lib/gaisler/sim/sim.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/sram.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/ata_device.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/sram16.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/phy.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/ahbrep.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/jtagtst.vhd,hdl"
VALUE "<project>/../..//lib/fmf/utilities/conversions.vhd,hdl"
VALUE "<project>/../..//lib/fmf/utilities/gen_utils.vhd,hdl"
VALUE "<project>/../..//lib/gsi/ssram/functions.vhd,hdl"
VALUE "<project>/../..//lib/gsi/ssram/core_burst.vhd,hdl"
VALUE "<project>/../..//lib/gsi/ssram/g880e18bt.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/components.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/package_utility.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/cy7c1354b.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/cy7c1380d.vhd,hdl"
VALUE "<project>/../..//lib/work/debug/debug.vhd,hdl"
VALUE "<project>/../..//lib/work/debug/grtestmod.vhd,hdl"
VALUE "<project>/../..//lib/work/debug/cpu_disas.vhd,hdl"
VALUE "<project>/config.vhd,hdl"
VALUE "<project>/ahbrom.vhd,hdl"
VALUE "<project>/leon3mp.vhd,hdl"
VALUE "<project>/testbench.vhd,hdl"
VALUE "<project>/testbench.vhd,hdl"
ENDLIST
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST UserCustomizedFileList
LIST "top"
LIST "ideSYNTHESIS"
USE_LIST=TRUE
FILELIST
VALUE "<project>/../..//lib/grlib/stdlib/version.vhd,hdl"
VALUE "<project>/../..//lib/grlib/stdlib/stdlib.vhd,hdl"
VALUE "<project>/../..//lib/grlib/sparc/sparc.vhd,hdl"
VALUE "<project>/../..//lib/grlib/modgen/multlib.vhd,hdl"
VALUE "<project>/../..//lib/grlib/modgen/leaves.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/amba.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/devices.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/defmst.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/apbctrl.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/ahbctrl.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_pkg.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/dma2ahb.vhd,hdl"
VALUE "<project>/../..//lib/techmap/gencomp/gencomp.vhd,hdl"
VALUE "<project>/../..//lib/techmap/gencomp/netcomp.vhd,hdl"
VALUE "<project>/../..//lib/techmap/inferred/memory_inferred.vhd,hdl"
VALUE "<project>/../..//lib/techmap/inferred/ddr_inferred.vhd,hdl"
VALUE "<project>/../..//lib/techmap/inferred/mul_inferred.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/memory_apa3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/buffer_apa3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/tap_proasic3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allclkgen.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allddr.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allmem.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allpads.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/alltap.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkgen.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkmux.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkand.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ddr_ireg.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ddr_oreg.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ddrphy.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram64.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram_2p.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram_dp.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncfifo.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/regfile_3p.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/tap.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/techbuf.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkpad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/inpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/inpad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/iodpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/iopad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/iopad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/lvds_combo.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/odpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/outpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/outpad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/toutpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/skew_outpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/grspwc_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/grlfpw_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/grfpw_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/mul_61x61.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/cpu_disas_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/usbhc_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ringosc.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ssrctrl_net.vhd,hdl"
VALUE "<project>/../..//lib/spw/comp/spwcomp.vhd,hdl"
VALUE "<project>/../..//lib/eth/comp/ethcomp.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/greth_pkg.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/eth_rstgen.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/eth_ahb_mst.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/greth_tx.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/greth_rx.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/grethc.vhd,hdl"
VALUE "<project>/../..//lib/eth/wrapper/greth_gen.vhd,hdl"
VALUE "<project>/../..//lib/eth/wrapper/greth_gbit_gen.vhd,hdl"
VALUE "<project>/../..//lib/opencores/occomp/occomp.vhd,hdl"
VALUE "<project>/../..//lib/opencores/can/cancomp.vhd,hdl"
VALUE "<project>/../..//lib/opencores/can/can_top.vhd,hdl"
VALUE "<project>/../..//lib/opencores/can/can_top_core_sync.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/arith/arith.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/arith/mul32.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/arith/div32.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/memctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/sdctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/sdmctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/srctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmuconfig.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmuiface.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libmmu.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libiu.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libcache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libproc3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/cachemem.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_icache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_dcache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_acache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmutlbcam.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmulrue.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmulru.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmutlb.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmutw.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_cache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/acache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/dcache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/icache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/cache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/cpu_disasx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/iu3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grfpwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mfpwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grlfpwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/tbufmem.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/dsu3x.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/dsu3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/proc3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3s.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3cg.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/irqmp.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grfpwxsh.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grfpushwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3sh.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_mod.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_oc.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_mc.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/canmux.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_rd.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/misc.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/rstgen.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/gptimer.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbram.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbtrace.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbmst.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/grgpio.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbstat.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/logan.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/apbps2.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/charrom_package.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/charrom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/apbvga.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbdma.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/svgactrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/spictrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/i2cslv.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/wild.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/wild2ahb.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/net/net.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/uart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/libdcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/apbuart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/dcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/dcom_uart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/ahbuart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/jtag.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/libjtagcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/jtagcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/ethernet_mac.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/greth.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/greth_gbit.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/grethm.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/spacewire.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/grspw.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/grspw2.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/grspwm.vhd,hdl"
VALUE "<project>/../..//lib/esa/memoryctrl/memoryctrl.vhd,hdl"
VALUE "<project>/../..//lib/esa/memoryctrl/mctrl.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/CoreFFT.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/actar.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/actram.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fftDp.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fftSm.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fft_components.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/primitives.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/twiddle.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/ALU.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Adder.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Clk_divider.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_MUX.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_REG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MUX2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Multiplier.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/REG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Shifter.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/general_purpose.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Serialize.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/Starter.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/ApbDriver.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/UART.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_usb/APB_USB.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
VALUE "<project>/config.vhd,hdl"
VALUE "<project>/ahbrom.vhd,hdl"
VALUE "<project>/leon3mp.vhd,hdl"
ENDFILELIST
ENDLIST
LIST "ideSIMULATION"
USE_LIST=TRUE
FILELIST
VALUE "<project>/../..//lib/grlib/stdlib/version.vhd,hdl"
VALUE "<project>/../..//lib/grlib/stdlib/stdlib.vhd,hdl"
VALUE "<project>/../..//lib/grlib/stdlib/stdio.vhd,hdl"
VALUE "<project>/../..//lib/grlib/util/util.vhd,hdl"
VALUE "<project>/../..//lib/grlib/sparc/sparc.vhd,hdl"
VALUE "<project>/../..//lib/grlib/sparc/sparc_disas.vhd,hdl"
VALUE "<project>/../..//lib/grlib/sparc/cpu_disas.vhd,hdl"
VALUE "<project>/../..//lib/grlib/modgen/multlib.vhd,hdl"
VALUE "<project>/../..//lib/grlib/modgen/leaves.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/amba.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/devices.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/defmst.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/apbctrl.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/ahbctrl.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_pkg.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/dma2ahb.vhd,hdl"
VALUE "<project>/../..//lib/grlib/amba/dma2ahb_tp.vhd,hdl"
VALUE "<project>/../..//lib/tech/proasic3/components/proasic3.vhd,hdl"
VALUE "<project>/../..//lib/synplify/sim/synplify.vhd,hdl"
VALUE "<project>/../..//lib/synplify/sim/synattr.vhd,hdl"
VALUE "<project>/../..//lib/techmap/gencomp/gencomp.vhd,hdl"
VALUE "<project>/../..//lib/techmap/gencomp/netcomp.vhd,hdl"
VALUE "<project>/../..//lib/techmap/inferred/memory_inferred.vhd,hdl"
VALUE "<project>/../..//lib/techmap/inferred/ddr_inferred.vhd,hdl"
VALUE "<project>/../..//lib/techmap/inferred/mul_inferred.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/memory_apa3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/buffer_apa3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/proasic3/tap_proasic3.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allclkgen.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allddr.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allmem.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/allpads.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/alltap.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkgen.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkmux.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkand.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ddr_ireg.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ddr_oreg.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ddrphy.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram64.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram_2p.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncram_dp.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/syncfifo.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/regfile_3p.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/tap.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/techbuf.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/clkpad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/inpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/inpad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/iodpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/iopad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/iopad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/lvds_combo.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/odpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/outpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/outpad_ds.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/toutpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/skew_outpad.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/grspwc_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/grlfpw_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/grfpw_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/mul_61x61.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/cpu_disas_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/usbhc_net.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ringosc.vhd,hdl"
VALUE "<project>/../..//lib/techmap/maps/ssrctrl_net.vhd,hdl"
VALUE "<project>/../..//lib/spw/comp/spwcomp.vhd,hdl"
VALUE "<project>/../..//lib/eth/comp/ethcomp.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/greth_pkg.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/eth_rstgen.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/eth_ahb_mst.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/greth_tx.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/greth_rx.vhd,hdl"
VALUE "<project>/../..//lib/eth/core/grethc.vhd,hdl"
VALUE "<project>/../..//lib/eth/wrapper/greth_gen.vhd,hdl"
VALUE "<project>/../..//lib/eth/wrapper/greth_gbit_gen.vhd,hdl"
VALUE "<project>/../..//lib/opencores/occomp/occomp.vhd,hdl"
VALUE "<project>/../..//lib/opencores/can/cancomp.vhd,hdl"
VALUE "<project>/../..//lib/opencores/can/can_top.vhd,hdl"
VALUE "<project>/../..//lib/opencores/can/can_top_core_sync.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/arith/arith.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/arith/mul32.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/arith/div32.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/memctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/sdctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/sdmctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/memctrl/srctrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmuconfig.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmuiface.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libmmu.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libiu.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libcache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/libproc3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/cachemem.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_icache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_dcache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_acache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmutlbcam.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmulrue.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmulru.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmutlb.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmutw.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mmu_cache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/acache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/dcache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/icache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/cache.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/cpu_disasx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/iu3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grfpwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/mfpwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grlfpwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/tbufmem.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/dsu3x.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/dsu3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/proc3.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3s.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3cg.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/irqmp.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grfpwxsh.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/grfpushwx.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/leon3/leon3sh.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_mod.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_oc.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_mc.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/canmux.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/can/can_rd.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/misc.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/rstgen.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/gptimer.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbram.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbtrace.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbmst.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/grgpio.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbstat.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/logan.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/apbps2.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/charrom_package.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/charrom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/apbvga.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/ahbdma.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/svgactrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/spictrl.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/i2cslv.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/wild.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/misc/wild2ahb.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ambatest.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ahb_tbfunct.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ahbslv_em.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/ambatest/ahbmst_em.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/net/net.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/uart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/libdcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/apbuart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/dcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/dcom_uart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/uart/ahbuart.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/i2c_slave_model.v,hdl"
VALUE "<project>/../..//lib/gaisler/sim/sim.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/sram.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/ata_device.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/sram16.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/phy.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/sim/ahbrep.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/jtag.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/libjtagcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/jtagcom.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/jtag/jtagtst.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/ethernet_mac.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/greth.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/greth_gbit.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/greth/grethm.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/spacewire.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/grspw.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/grspw2.vhd,hdl"
VALUE "<project>/../..//lib/gaisler/spacewire/grspwm.vhd,hdl"
VALUE "<project>/../..//lib/esa/memoryctrl/memoryctrl.vhd,hdl"
VALUE "<project>/../..//lib/esa/memoryctrl/mctrl.vhd,hdl"
VALUE "<project>/../..//lib/fmf/utilities/conversions.vhd,hdl"
VALUE "<project>/../..//lib/fmf/utilities/gen_utils.vhd,hdl"
VALUE "<project>/../..//lib/gsi/ssram/functions.vhd,hdl"
VALUE "<project>/../..//lib/gsi/ssram/core_burst.vhd,hdl"
VALUE "<project>/../..//lib/gsi/ssram/g880e18bt.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/CoreFFT.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/actar.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/actram.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fftDp.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fftSm.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/fft_components.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/primitives.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./dsp/lpp_fft/twiddle.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/ALU.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Adder.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Clk_divider.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_CONTROLER.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_MUX.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_MUX2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MAC_REG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/MUX2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Multiplier.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/REG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/Shifter.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./general_purpose/general_purpose.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Gene_SYNC.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Serialize.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/Starter.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/ApbDriver.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/UART.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_usb/APB_USB.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
VALUE "<project>/../..//lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/components.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/package_utility.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/cy7c1354b.vhd,hdl"
VALUE "<project>/../..//lib/cypress/ssram/cy7c1380d.vhd,hdl"
VALUE "<project>/../..//lib/work/debug/debug.vhd,hdl"
VALUE "<project>/../..//lib/work/debug/grtestmod.vhd,hdl"
VALUE "<project>/../..//lib/work/debug/cpu_disas.vhd,hdl"
VALUE "<project>/config.vhd,hdl"
VALUE "<project>/ahbrom.vhd,hdl"
VALUE "<project>/leon3mp.vhd,hdl"
VALUE "<project>/testbench.vhd,hdl"
ENDFILELIST
ENDLIST
ENDLIST
ENDLIST