# Synopsys, Inc. constraint file
# E:\opt\tortoiseHG_vhdlib\boards\LFR-EQM\LFR_EQM_altran_syn.sdc
# Written on Fri Jun 12 10:24:30 2015
# by Synplify Pro, E-2010.09A-1 Scope Editor

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# Collections
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# Clocks
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define_clock   {clk50MHz}  -freq 50 -clockgroup default_clkgroup_0
define_clock   {n:clk_25}  -freq 25 -clockgroup default_clkgroup_1
define_clock   {n:clk_24}  -freq 24.576 -clockgroup default_clkgroup_2
define_clock   {n:spw_inputloop\.0\.spw_phy0.rxclki_1}  -freq 10 -clockgroup default_clkgroup_3
define_clock   {n:spw_inputloop\.1\.spw_phy0.rxclki_1}  -freq 10 -clockgroup default_clkgroup_4
define_clock   {clk49_152MHz}  -freq 49.152 -clockgroup default_clkgroup_5

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# Clock to Clock
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# Inputs/Outputs
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# Registers
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# Delay Paths
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# Attributes
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# I/O Standards
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# Compile Points
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# Other
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