----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:16:12 03/29/2011 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library grlib;
use grlib.amba.all;
use work.config.all;
library gaisler;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library lpp;
use lpp.general_purpose.all;
use lpp.lpp_uart.all;

entity top is
	generic (
		fabtech : integer := CFG_FABTECH;
		memtech : integer := CFG_MEMTECH;
		padtech : integer := CFG_PADTECH;
		clktech : integer := CFG_CLKTECH;
		disas   : integer := CFG_DISAS;     -- Enable disassembly to console
		dbguart : integer := CFG_DUART;     -- Print UART on console
		pclow   : integer := CFG_PCLOW);
	Port ( clk50MHz	: in  STD_LOGIC;
		reset		: in  STD_LOGIC;
		led		: out std_logic_vector(1 downto 0);
		--
		ahbrxd	: in std_ulogic;
		ahbtxd	: out std_ulogic;
		urxd1		: in std_ulogic;
		utxd1		: out std_ulogic
		);
end top;

architecture Behavioral of top is

--- AHB / APB
signal apbi		:	apb_slv_in_type;
signal apbo		:	apb_slv_out_vector := (others => apb_none);
signal ahbsi	:	ahb_slv_in_type;
signal ahbso	:	ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi	:	ahb_mst_in_type;
signal ahbmo	:	ahb_mst_out_vector := (others => ahbm_none);
-- AHBUART
signal ahbuarti:	uart_in_type;
signal ahbuarto:	uart_out_type;
signal apbuarti:	uart_in_type;
signal apbuarto:	uart_out_type;
signal rxd2		:	std_ulogic;
signal rxd1		:	std_ulogic;
signal txd1		:	std_ulogic;

signal vcc			: std_logic_vector(4 downto 0);
signal gnd   		: std_logic_vector(4 downto 0);
--signal LED_rotary	: std_logic_vector(7 downto 0);

signal clkm		: std_ulogic;
signal lclk		: std_ulogic;
signal rstn		: std_ulogic;
signal clk2x	: std_ulogic;
signal rstraw	: std_logic;
signal rstneg	: std_logic;
signal lock 	: std_logic;
signal cgi		: clkgen_in_type;
signal cgo		: clkgen_out_type;

constant BOARD_FREQ : integer := 50000;   -- input frequency in KHz

begin

----------------------------------------------------------------------
---  Reset and Clock generation  -------------------------------------
----------------------------------------------------------------------

  vcc <= (others => '1'); gnd <= (others => '0');
  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
  rstneg <=  reset;
	
  rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
  lock <= cgo.clklock;
  
  clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk); 

  clkgen0 : clkgen  		-- clock generator MUL 4, DIV 5
  generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
  port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
  
--------------------------------------
--- CLK_DIVIDER ----------------------
--------------------------------------
clk_divider0 : Clk_divider
	 generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)
    Port map( clkm, rstn, led(1));

-------------------------------
--- AHB CONTROLLER ------------
-------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
	generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
	nahbm => CFG_NCPU+CFG_AHB_UART,
	nahbs => 2)
	port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
	
-------------------------------	
--- AHBUART -------------------
-------------------------------
dcom0 : ahbuart -- AMBA AHB Serial Debug Interface
	generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
	port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech  => padtech) port map (ahbrxd, rxd2);
dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
ahbuarti.rxd <= rxd2;

----------------------------------------------------------------------
--- APB Bridge and various periherals --------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
	generic map (hindex => 1, haddr => CFG_APBADDR,nslaves => 1)
	port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);

uart1 : APB_UART 
  generic map(
    pindex   => 0,
    paddr    => 0)
  port map(
    clk     =>  clkm,          --! Horloge du composant
    rst     =>  rstn,           --! Reset general du composant
    apbi    =>  apbi,      --! Registre de gestion des entrées du bus
    apbo    =>  apbo(0),     --! Registre de gestion des sorties du bus
    TXD     =>  utxd1,         --! Transmission série, côté composant
    RXD     =>  urxd1           --! Reception série, côté composant
    );


----------------------------------
--- LED --------------------------
----------------------------------
led(0) <= not rxd1;

end Behavioral;