----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:16:12 03/29/2011 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
library lpp;
use lpp.lpp_amba.all;
use lpp.lpp_uart.all;
use lpp.lpp_memory.all;
use lpp.general_purpose.all;

entity miniamba is
	generic (
		fabtech : integer := CFG_FABTECH;
		memtech : integer := CFG_MEMTECH;
		padtech : integer := CFG_PADTECH;
		clktech : integer := CFG_CLKTECH;
		disas   : integer := CFG_DISAS;     -- Enable disassembly to console
		dbguart : integer := CFG_DUART;     -- Print UART on console
		pclow   : integer := CFG_PCLOW);
	Port ( 
        clk50MHz	: in  STD_LOGIC;
		reset		: in  STD_LOGIC;
		led		: out std_logic_vector(1 downto 0);
		ahbrxd	: in std_ulogic;
		ahbtxd	: out std_ulogic;
		urxd1		: in std_ulogic;
		utxd1		: out std_ulogic;
        data        : inout std_logic_vector(31 downto 0);
        address     : out std_logic_vector(18 downto 0);
        nBWa        : out std_logic;
        nBWb        : out std_logic;
        nBWc        : out std_logic;
        nBWd        : out std_logic;
        nBWE        : out std_logic;
        nADSC       : out std_logic;
        nADSP       : out std_logic;
        nADV        : out std_logic;
        nGW         : out std_logic;
        nCE1        : out std_logic;
        CE2         : out std_logic;
        nCE3        : out std_logic;
        nOE         : out std_logic;		
        MODE        : out std_logic;        
        SSRAM_CLK   : out std_logic;
        ZZ          : out std_logic
        );
end miniamba;

architecture Behavioral of miniamba is

--- AHB / APB
signal apbi		:	apb_slv_in_type;
signal apbo		:	apb_slv_out_vector := (others => apb_none);
signal ahbsi	:	ahb_slv_in_type;
signal ahbso	:	ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi	:	ahb_mst_in_type;
signal ahbmo	:	ahb_mst_out_vector := (others => ahbm_none);
-- AHBUART
signal ahbuarti:	uart_in_type;
signal ahbuarto:	uart_out_type;
signal apbuarti:	uart_in_type;
signal apbuarto:	uart_out_type;
signal rxd2		:	std_ulogic;
signal rxd1		:	std_ulogic;
signal txd1		:	std_ulogic;

signal vcc			: std_logic_vector(4 downto 0);
signal gnd   		: std_logic_vector(4 downto 0);

-- MEM CTRLR
signal memi  : memory_in_type;
signal memo  : memory_out_type;
signal sdo   : sdram_out_type;
signal sdo3 : sdctrl_out_type;
signal wpo   : wprot_out_type;

signal clkm		: std_ulogic;
signal resetnl	: std_ulogic;
signal sdclkl   : std_ulogic;
signal pciclk   : std_ulogic;
signal lclk		: std_ulogic;
signal rstn		: std_ulogic;
signal clk2x	: std_ulogic;
signal rstraw	: std_logic;
signal rstneg	: std_logic;
signal lock 	: std_logic;
signal cgi		: clkgen_in_type;
signal cgo		: clkgen_out_type;

-- LEON3
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);

signal dsui : dsu_in_type;
signal dsuo : dsu_out_type; 
signal dui : uart_in_type;
signal duo : uart_out_type;


constant boardfreq : integer := 50000;  -- input frequency in KHz

begin

----------------------------------------------------------------------
---  Reset and Clock generation  -------------------------------------
----------------------------------------------------------------------

--  vcc <= (others => '1'); gnd <= (others => '0');
--  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
--  rstneg <=  reset;
--	
--  rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw);
--  lock <= cgo.clklock;
--  
--  clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk); 
----
----  clkgen0 : clkgen  		-- clock generator MUL 4, DIV 5
----  generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
----  port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
--
--process(lclk)
--begin
--    if lclk'event and lclk = '1' then
--        clkm <= not clkm;
--    end if;
--end process;
  vcc <= (others => '1'); gnd <= (others => '0');
  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;

  clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk); 

  clkgen0 : clkgen  		-- clock generator
    generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, 
	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
    port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo);

  resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl);
  rst0 : rstgen			-- reset generator
  port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
  --led(5) <= cgo.clklock;

  
--------------------------------------
--- CLK_DIVIDER ----------------------
--------------------------------------
clk_divider0 : Clk_divider
	 generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)
    Port map( clkm, rstn, led(1));

-------------------------------
--- AHB CONTROLLER ------------
-------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
	generic map (defmast => 0, --AHB_UART default master
     split => CFG_SPLIT,
	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
	nahbm => 3,
	nahbs => 2)
	port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
	

-------------------------------
--- MEMORY CONTROLLER ---------
-------------------------------
memctrlr : mctrl generic map (hindex => 0,pindex   => 0, paddr    => 0)
    port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);


bdr : for i in 0 to 3 generate
  data_pad : iopadv generic map (tech => padtech, width => 8)
  port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;



addr_pad : outpadv generic map (width => 19, tech => padtech) 
	port map (address, memo.address(18 downto 0));



SSRAM_0:entity ssram_plugin 
generic map (tech => padtech)
port map
(clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);

-------------------------------	
--- AHBUART -------------------
-------------------------------
dcom0 : ahbuart -- AMBA AHB Serial Debug Interface
	generic map (hindex => 1, pindex => 2, paddr => 2)
	port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech  => padtech) port map (ahbrxd, rxd2);
dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
ahbuarti.rxd <= rxd2;

----------------------------------------------------------------------
--- APB Bridge and various periherals --------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
	generic map (hindex => 3, haddr => CFG_APBADDR)
	port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo);

uart1 : APB_UART 
  generic map(
    pindex   => 1,
    paddr    => 1)
  port map(
    clk     =>  clkm,      --! Horloge du composant
    rst     =>  rstn,      --! Reset general du composant
    apbi    =>  apbi,      --! Registre de gestion des entrées du bus
    apbo    =>  apbo(1),   --! Registre de gestion des sorties du bus
    TXD     =>  utxd1,     --! Transmission série, côté composant
    RXD     =>  urxd1      --! Reception série, côté composant
    );


----------------------------------
--- LED --------------------------
----------------------------------
led(0) <= not rxd1;

end Behavioral;