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------------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003 - 2008, Gaisler Research
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-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
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-- Copyright (C) 2015 - 2016, Cobham Gaisler
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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use work.debug.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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library grlib;
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use grlib.stdlib.all;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 20; -- system clock period
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romdepth : integer := 22 -- rom address depth (flash 4 MB)
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-- sramwidth : integer := 32; -- ram data width (8/16/32)
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-- sramdepth : integer := 20; -- ram address depth
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-- srambanks : integer := 2 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "ram.srec"; -- ram contents
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constant sdramfile : string := "ram.srec"; -- sdram contents
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signal SW : std_logic_vector(4 downto 1);
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signal clk : std_logic := '0';
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(21 downto 0);
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signal data : std_logic_vector(31 downto 24);
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signal romsn : std_logic;
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signal oen : std_logic;
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signal writen : std_logic;
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signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
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signal dsurst : std_logic;
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signal error : std_logic;
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signal sdcke : std_logic;
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signal sdcsn : std_logic;
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signal sdwen : std_logic; -- write en
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signal sdrasn : std_logic; -- row addr stb
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signal sdcasn : std_logic; -- col addr stb
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signal dram_ldqm : std_logic;
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signal dram_udqm : std_logic;
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signal sdclk : std_logic;
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signal dram_ba : std_logic_vector(1 downto 0);
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constant lresp : boolean := false;
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signal sa : std_logic_vector(12 downto 0);
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signal sd : std_logic_vector(15 downto 0);
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begin
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clk <= not clk after ct * 1 ns; --50 MHz clk
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rst <= dsurst; --reset
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dsuen <= '1';
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dsubre <= '1'; -- inverted on the board
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sw(1) <= rst;
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d3 : entity work.leon3mp
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generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
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port map (
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CLK50 => clk,
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LEDS => open,
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SW => SW,
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dram_addr => sa,
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dram_ba_0 => dram_ba(0),
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dram_ba_1 => dram_ba(1),
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dram_dq => sd(15 downto 0),
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dram_clk => sdclk,
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dram_cke => sdcke,
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dram_cs_n => sdcsn,
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dram_we_n => sdwen,
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dram_ras_n => sdrasn,
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dram_cas_n => sdcasn,
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dram_ldqm => dram_ldqm,
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dram_udqm => dram_udqm,
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uart_txd => dsutx,
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uart_rxd => dsurx);
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u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 9, index => 1024, fname => sdramfile)
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PORT MAP(
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Dq => sd(15 downto 0), Addr => sa(12 downto 0),
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Ba => dram_ba, Clk => sdclk, Cke => sdcke,
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Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
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Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
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error <= 'H'; -- ERROR pull-up
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iuerr : process
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begin
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wait for 2500 ns;
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if to_x01(error) = '1' then wait on error; end if;
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assert (to_x01(error) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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data <= buskeep(data) after 5 ns;
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sd <= buskeep(sd) after 5 ns;
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dsucom : process
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variable w32 : std_logic_vector(31 downto 0);
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constant txp : time := 160 * 1 ns;
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procedure writeReg(signal dsutx : out std_logic; address : integer; value : integer) is
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begin
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txc(dsutx, 16#c0#, txp); --control byte
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txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
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txa(dsutx, (value / (256*256*256)) , (value / (256*256)), (value / (256)), value, txp); --write data
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end;
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procedure readReg(signal dsurx : in std_logic; signal dsutx : out std_logic; address : integer; value: out std_logic_vector) is
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begin
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txc(dsutx, 16#a0#, txp); --control byte
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txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
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rxi(dsurx, value, txp, lresp); --write data
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end;
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procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
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variable c8 : std_logic_vector(7 downto 0);
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begin
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dsutx <= '1';
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dsurst <= '0'; --reset low
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wait for 500 ns;
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dsurst <= '1'; --reset high
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--wait; --evig w8
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wait for 5000 ns;
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txc(dsutx, 16#55#, txp);
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--dsucfg(dsutx, dsurx);
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writeReg(dsutx,16#40000000#,16#12345678#);
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writeReg(dsutx,16#40000004#,16#22222222#);
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writeReg(dsutx,16#40000008#,16#33333333#);
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writeReg(dsutx,16#4000000C#,16#44444444#);
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readReg(dsurx,dsutx,16#40000000#,w32);
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readReg(dsurx,dsutx,16#40000004#,w32);
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readReg(dsurx,dsutx,16#40000008#,w32);
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readReg(dsurx,dsutx,16#4000000C#,w32);
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end;
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begin
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dsucfg(dsutx, dsurx);
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wait;
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end process;
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end ;
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