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Update SOLO_LFR_LFR-EM timings constraints...
Update SOLO_LFR_LFR-EM timings constraints (due to the fact that we used a A3PE3000L FPGA on the LFR-EM board)

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r226:9c9d4ca3fdbf alexis
r674:b0efa9138022 default
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vhdlsyn.txt
3 lines | 54 B | text/plain | TextLexer
bootrom.vhd
lpp_bootloader_pkg.vhd
lpp_bootloader.vhd