HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc

EM Design : GRSPW 2 ports, WFP, FILTER, BW/SP/R OK...

EM Design : GRSPW 2 ports, WFP, FILTER, BW/SP/R OK (Redmine : 2013-07-22-leon3mp-grspw-wfrm.pdb)

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             Makefile.inc
        
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      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

      TECHNOLOGY=ProASIC3E

      LIBERO_DIE=IT14X14M4

      PART=A3PE3000

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

      MGCTECHNOLOGY=Proasic3

      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

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				PACKAGE=\"\"
				SPEED=Std
				SYNFREQ=50

				TECHNOLOGY=ProASIC3E
				LIBERO_DIE=IT14X14M4
				PART=A3PE3000

				DESIGNER_VOLTAGE=COM
				DESIGNER_TEMP=COM
				DESIGNER_PACKAGE=FBGA
				DESIGNER_PINS=324

				MANUFACTURER=Actel
				MGCTECHNOLOGY=Proasic3
				MGCPART=$(PART)
				MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
				LIBERO_PACKAGE=fg$(DESIGNER_PINS)