HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · boards/SP601/Makefile.inc

LFR-EQM 2.1.81...

LFR-EQM 2.1.81 > all is ok, the ADC data are sampled at 500M.sample.Hz

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             Makefile.inc
        
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      # Since synplify seems to cause a synthsis error involving

      # the DSP macro blocks the Spartan 3A technology 

      # without DSP is used for synthesis

      #

      TECHNOLOGY=Spartan6

      ISETECH="Spartan6"

      PART=XC6SLX16

      PACKAGE=csg324

      SPEED=-2

      SYNFREQ=220

      PROMGENPAR= -c FF -s 8192 -u 0 $(TOP).bit -p mcs -spi -w -o xilinx-sp601-xc6slx16

      MANUFACTURER=Xilinx

      MGCPART=XC6SLX16$(PACKAGE)

      MGCTECHNOLOGY=SPARTAN-6

      MGCPACKAGE=$(PACKAGE)

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				# Since synplify seems to cause a synthsis error involving
				# the DSP macro blocks the Spartan 3A technology
				# without DSP is used for synthesis
				#
				TECHNOLOGY=Spartan6
				ISETECH="Spartan6"
				PART=XC6SLX16
				PACKAGE=csg324
				SPEED=-2
				SYNFREQ=220
				PROMGENPAR= -c FF -s 8192 -u 0 $(TOP).bit -p mcs -spi -w -o xilinx-sp601-xc6slx16

				MANUFACTURER=Xilinx
				MGCPART=XC6SLX16$(PACKAGE)
				MGCTECHNOLOGY=SPARTAN-6
				MGCPACKAGE=$(PACKAGE)