|
|
KEY LIBERO "9.1"
|
|
|
KEY CAPTURE "9.1.0.18"
|
|
|
KEY DEFAULT_IMPORT_LOC "D:\Mission_Solar_Orbiteur\Prog_VHDL\Matrice Spec\MATRICE\hdl"
|
|
|
KEY DEFAULT_OPEN_LOC ""
|
|
|
KEY ProjectID "105b6a94-08a0-483a-9f39-345e43044ca5"
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|
|
KEY HDLTechnology "VHDL"
|
|
|
KEY VendorTechnology_Family "ProASIC3L"
|
|
|
KEY VendorTechnology_Die "IT14X14M4LDP"
|
|
|
KEY VendorTechnology_Package "fg896"
|
|
|
KEY ProjectLocation "D:\GRLIB_BusAMBA\VHD_Lib\designs\ProjetBlanc-LeonLPP-A3P3K"
|
|
|
KEY SimulationType "VHDL"
|
|
|
KEY Vendor "Actel"
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|
|
KEY ActiveRoot "leon3mp::work"
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|
|
LIST REVISIONS
|
|
|
VALUE="Impl1",NUM=1
|
|
|
VALUE="Impl2",NUM=2
|
|
|
CURREV=2
|
|
|
ENDLIST
|
|
|
LIST LIBRARIES
|
|
|
grlib
|
|
|
synplify
|
|
|
techmap
|
|
|
spw
|
|
|
eth
|
|
|
opencores
|
|
|
gaisler
|
|
|
esa
|
|
|
fmf
|
|
|
spansion
|
|
|
gsi
|
|
|
lpp
|
|
|
cypress
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_grlib
|
|
|
ALIAS=grlib
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_synplify
|
|
|
ALIAS=synplify
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_techmap
|
|
|
ALIAS=techmap
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_spw
|
|
|
ALIAS=spw
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_eth
|
|
|
ALIAS=eth
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_opencores
|
|
|
ALIAS=opencores
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_gaisler
|
|
|
ALIAS=gaisler
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_esa
|
|
|
ALIAS=esa
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_fmf
|
|
|
ALIAS=fmf
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_spansion
|
|
|
ALIAS=spansion
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_gsi
|
|
|
ALIAS=gsi
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_lpp
|
|
|
ALIAS=lpp
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST LIBRARY_cypress
|
|
|
ALIAS=cypress
|
|
|
COMPILE_OPTION=COMPILE
|
|
|
ENDLIST
|
|
|
LIST FileManager
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\amba_lcd_16x2_ctrlr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="4857"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\apb_lcd_ctrlr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="4684"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\FRAME_CLK.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2063"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_CFG.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2262"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_DRVR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="4068"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_16x2_ENGINE.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="5400"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_2x16_DRIVER.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="4608"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\LCD_CLK_GENERATOR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2035"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\amba_lcd_16x2_ctrlr\Top_LCD.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="3093"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\APB_IIR_CEL.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1328101750"
|
|
|
SIZE="8034"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\APB_IIR_Filter.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1347275095"
|
|
|
SIZE="9037"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTER.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1326707253"
|
|
|
SIZE="3402"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1349782083"
|
|
|
SIZE="7067"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FilterCTRLR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1326707253"
|
|
|
SIZE="8493"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\FILTER_RAM_CTRLR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1326707253"
|
|
|
SIZE="5164"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1346936328"
|
|
|
SIZE="10652"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\IIR_CEL_FILTER.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1346936328"
|
|
|
SIZE="2708"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1349782071"
|
|
|
SIZE="9041"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1348571754"
|
|
|
SIZE="2383"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1326707253"
|
|
|
SIZE="2276"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\RAM_CTRLR2.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1349786999"
|
|
|
SIZE="5122"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\Top_Filtre_IIR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1326707253"
|
|
|
SIZE="1005"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\iir_filter\Top_IIR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1349782055"
|
|
|
SIZE="2321"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746407"
|
|
|
SIZE="141869"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746407"
|
|
|
SIZE="4032"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\APB_FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1331642027"
|
|
|
SIZE="5929"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\APB_FFT_half.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1332429937"
|
|
|
SIZE="5590"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1295516964"
|
|
|
SIZE="12457"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1333012650"
|
|
|
SIZE="4721"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746408"
|
|
|
SIZE="25871"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746408"
|
|
|
SIZE="32249"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746408"
|
|
|
SIZE="5049"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Flag_Extremum.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1328875675"
|
|
|
SIZE="2574"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1333025894"
|
|
|
SIZE="4326"
|
|
|
LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1333024721"
|
|
|
SIZE="7485"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746408"
|
|
|
SIZE="3997"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1294746408"
|
|
|
SIZE="12080"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Adder.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2272"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="1930"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\ALU.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="2278"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="1958"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
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|
|
SIZE="5897"
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|
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LIBRARY="lpp"
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|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\APB_AMR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1313682702"
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|
|
SIZE="3577"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\bclk_reg.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1286437702"
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|
|
SIZE="685"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Clock_multi.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1286438714"
|
|
|
SIZE="1218"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Dephaseur.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1286455334"
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|
|
SIZE="1492"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\Gene_Rz.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1286438978"
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|
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SIZE="1011"
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|
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LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_AMR\lpp_AMR.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1313679648"
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|
|
SIZE="2523"
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|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_balise\APB_Balise.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1308741597"
|
|
|
SIZE="4392"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_balise\lpp_balise.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1308732390"
|
|
|
SIZE="1887"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\APB_Delay.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1319721765"
|
|
|
SIZE="5159"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\lpp_delay.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1319721794"
|
|
|
SIZE="2254"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\lpp_delay\TimerDelay.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1319721593"
|
|
|
SIZE="1726"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
|
|
VALUE "<project>\..\..\lib\lpp\.\general_purpose\MAC.vhd,hdl"
|
|
|
STATE="utd"
|
|
|
TIME="1292248642"
|
|
|
SIZE="7280"
|
|
|
LIBRARY="lpp"
|
|
|
ENDFILE
|
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ENDLIST
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ENDLIST
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EndProfile
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NAME="FlashPro"
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DESIGNFLOW:
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FILE:<project>\leon3mp.vhd,hdl
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FILE:<project>\..\..\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl
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ACTIVE_VIEW:1
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ENDLIST
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