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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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library lpp;
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use lpp.lpp_amba.all;
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use lpp.lpp_memory.all;
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use lpp.lpp_uart.all;
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use lpp.lpp_matrix.all;
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use lpp.lpp_delay.all;
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use lpp.lpp_fft.all;
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use lpp.fft_components.all;
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use lpp.lpp_ad_conv.all;
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use lpp.iir_filter.all;
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use lpp.general_purpose.all;
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use lpp.Filtercfg.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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clk50MHz : in std_ulogic;
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reset : in std_ulogic;
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ramclk : out std_logic;
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ahbrxd : in std_ulogic; -- DSU rx data
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ahbtxd : out std_ulogic; -- DSU tx data
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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urxd1 : in std_ulogic; -- UART1 rx data
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utxd1 : out std_ulogic; -- UART1 tx data
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errorn : out std_ulogic;
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address : out std_logic_vector(18 downto 0);
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data : inout std_logic_vector(31 downto 0);
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gpio : inout std_logic_vector(6 downto 0); -- I/O port
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nBWa : out std_logic;
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nBWb : out std_logic;
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nBWc : out std_logic;
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nBWd : out std_logic;
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nBWE : out std_logic;
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nADSC : out std_logic;
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nADSP : out std_logic;
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nADV : out std_logic;
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nGW : out std_logic;
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nCE1 : out std_logic;
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CE2 : out std_logic;
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nCE3 : out std_logic;
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nOE : out std_logic;
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MODE : out std_logic;
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SSRAM_CLK : out std_logic;
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ZZ : out std_logic;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------In/Out-----------------------
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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led : out std_logic_vector(1 downto 0)
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);
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end;
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architecture Behavioral of leon3mp is
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constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
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CFG_GRETH+CFG_AHB_JTAG;
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constant maxahbm : integer := maxahbmsp;
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--Clk & Rst g�n�
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signal vcc : std_logic_vector(4 downto 0);
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signal gnd : std_logic_vector(4 downto 0);
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signal resetnl : std_ulogic;
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signal clk2x : std_ulogic;
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signal lclk : std_ulogic;
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signal lclk2x : std_ulogic;
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signal clkm : std_ulogic;
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signal rstn : std_ulogic;
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signal rstraw : std_ulogic;
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signal pciclk : std_ulogic;
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signal sdclkl : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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--- AHB / APB
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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--UART
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signal ahbuarti : uart_in_type;
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signal ahbuarto : uart_out_type;
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signal apbuarti : uart_in_type;
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signal apbuarto : uart_out_type;
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--MEM CTRLR
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdo : sdram_out_type;
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--IRQ
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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--Timer
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signal gpti : gptimer_in_type;
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signal gpto : gptimer_out_type;
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--GPIO
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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--DSU
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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---------------------------------------------------------------------
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--- AJOUT TEST ------------------------Signaux----------------------
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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constant IOAEN : integer := CFG_CAN;
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constant boardfreq : integer := 50000;
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begin
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---------------------------------------------------------------------
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--- AJOUT TEST -------------------------------------IPs-------------
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---------------------------------------------------------------------
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
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clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
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port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
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ramclk <= clkm;
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process(lclk2x)
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begin
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if lclk2x'event and lclk2x = '1' then
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lclk <= not lclk;
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end if;
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end process;
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----------------------------------------------------------------------
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--- LEON3 processor / DSU / IRQ ------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
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dsui.enable <= '1';
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dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
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dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
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end generate;
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end generate;
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nodsu : if CFG_DSU = 0 generate
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ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
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end generate;
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irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
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irqctrl0 : irqmp -- interrupt controller
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generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
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end generate;
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irq3 : if CFG_IRQ3_ENABLE = 0 generate
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x : for i in 0 to CFG_NCPU-1 generate
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irqi(i).irl <= "0000";
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end generate;
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apbo(2) <= apb_none;
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end generate;
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----------------------------------------------------------------------
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--- Memory controllers ---------------------------------------------
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----------------------------------------------------------------------
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memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
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port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
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memi.brdyn <= '1'; memi.bexcn <= '1';
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memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
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bdr : for i in 0 to 3 generate
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data_pad : iopadv generic map (tech => padtech, width => 8)
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port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
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memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
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end generate;
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addr_pad : outpadv generic map (width => 19, tech => padtech)
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port map (address, memo.address(20 downto 2));
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SSRAM_0:entity ssram_plugin
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generic map (tech => padtech)
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port map
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(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
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----------------------------------------------------------------------
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--- AHB CONTROLLER -------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- AHB UART -------------------------------------------------------
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----------------------------------------------------------------------
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dcomgen : if CFG_AHB_UART = 1 generate
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dcom0: ahbuart -- Debug UART
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generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
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port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
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dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
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dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
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led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
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end generate;
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nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
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----------------------------------------------------------------------
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--- APB Bridge -----------------------------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 1, haddr => CFG_APBADDR)
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port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
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----------------------------------------------------------------------
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--- GPT Timer ------------------------------------------------------
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----------------------------------------------------------------------
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gpt : if CFG_GPT_ENABLE /= 0 generate
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timer0 : gptimer -- timer unit
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generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
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sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
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nbits => CFG_GPT_TW)
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port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
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gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
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-- led(4) <= gpto.wdog;
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end generate;
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notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
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----------------------------------------------------------------------
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--- APB UART -------------------------------------------------------
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----------------------------------------------------------------------
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ua1 : if CFG_UART1_ENABLE /= 0 generate
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uart1 : apbuart -- UART 1
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generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
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fifosize => CFG_UART1_FIFO)
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port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
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apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
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apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
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-- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
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end generate;
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noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
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----------------------------------------------------------------------
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--- GPIO -----------------------------------------------------------
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----------------------------------------------------------------------
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gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
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grgpio0: grgpio
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generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
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port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
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pio_pads : for i in 0 to 6 generate
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pio_pad : iopad generic map (tech => padtech)
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port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
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end generate;
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end generate;
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end Behavioral;
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