#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
#install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1
#OS:  6.1
#Hostname: PC-SOLAR2

#Implementation: synthesis

#Thu Oct 20 10:32:18 2011

$ Start of Compile
#Thu Oct 20 10:32:18 2011

Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : leon3mp.vhd(42) | Top entity is set to leon3mp.
@W:CD433 : sparc_disas.vhd(720) | No design units in file
VHDL syntax check successful!
Options changed - recompiling
@N:CD233 : mmuconfig.vhd(39) | Using sequential encoding for type mmu_idcache
@N:CD630 : leon3mp.vhd(42) | Synthesizing work.leon3mp.behavioral 
@W:CD326 : leon3mp.vhd(193) | Port clkc of entity techmap.clkgen is unconnected
@W:CD326 : leon3mp.vhd(193) | Port clkb of entity techmap.clkgen is unconnected
@W:CD326 : leon3mp.vhd(193) | Port clk2xu of entity techmap.clkgen is unconnected
@W:CD326 : leon3mp.vhd(193) | Port clk1xu of entity techmap.clkgen is unconnected
@W:CD326 : leon3mp.vhd(193) | Port clk4x of entity techmap.clkgen is unconnected
@W:CD638 : leon3mp.vhd(121) | Signal cgi.clksel is undriven 
@W:CD638 : leon3mp.vhd(121) | Signal cgi.pllref is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_4.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_4.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_4.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_4.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_4.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_5.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_5.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_5.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_5.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_5.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_6.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_6.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_6.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_6.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_6.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_8.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_8.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_8.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_8.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_8.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_9.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_9.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_9.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_9.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_9.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_10.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_10.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_10.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_10.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_10.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_12.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_12.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_12.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_12.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_12.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_13.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_13.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_13.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_13.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_13.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_14.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_14.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_14.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_14.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_14.prdata is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_15.pindex is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_15.pconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_15.pconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_15.pirq is undriven 
@W:CD638 : leon3mp.vhd(125) | Signal apbo_15.prdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_15.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_14.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_13.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_12.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_11.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_10.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_9.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_8.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_7.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_6.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_5.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_4.hready is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hindex is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hirq is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hcache is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hsplit is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hrdata is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hresp is undriven 
@W:CD638 : leon3mp.vhd(127) | Signal ahbso_3.hready is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_15.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_14.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_13.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_12.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_11.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_10.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_9.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_8.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_7.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_6.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_5.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_4.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_3.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hindex is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_0 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_1 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_2 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_3 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_4 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_5 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_6 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hconfig_7 is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hirq is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hwdata is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hprot is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hburst is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hsize is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hwrite is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.haddr is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.htrans is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hlock is undriven 
@W:CD638 : leon3mp.vhd(129) | Signal ahbmo_2.hbusreq is undriven 
@W:CD638 : leon3mp.vhd(131) | Signal ahbuarti.extclk is undriven 
@W:CD638 : leon3mp.vhd(131) | Signal ahbuarti.ctsn is undriven 
@W:CD638 : leon3mp.vhd(136) | Signal memi.edac is undriven 
@W:CD638 : leon3mp.vhd(136) | Signal memi.scb is undriven 
@W:CD638 : leon3mp.vhd(136) | Signal memi.cb is undriven 
@W:CD638 : leon3mp.vhd(136) | Signal memi.sd is undriven 
@W:CD638 : leon3mp.vhd(138) | Signal wpo.wprothit is undriven 
@W:CD638 : leon3mp.vhd(144) | Signal gpti.wdogen is undriven 
@W:CD638 : leon3mp.vhd(147) | Signal gpioi.sig_en is undriven 
@W:CD638 : leon3mp.vhd(147) | Signal gpioi.sig_in is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 7 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 8 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 9 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 10 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 11 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 12 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 13 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 14 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 15 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 16 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 17 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 18 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 19 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 20 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 21 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 22 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 23 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 24 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 25 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 26 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 27 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 28 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 29 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 30 of signal gpioi.din is undriven 
@W:CD796 : leon3mp.vhd(147) | Bit 31 of signal gpioi.din is undriven 
@N:CD630 : apbuart.vhd(47) | Synthesizing gaisler.apbuart.rtl 
@N:CD233 : apbuart.vhd(77) | Using sequential encoding for type txfsmtype
@N:CD231 : apbuart.vhd(76) | Using onehot encoding for type rxfsmtype (idle="10000")
Post processing for gaisler.apbuart.rtl
@W:CL189 : apbuart.vhd(537) | Register bit r.rwaddr(0) is always 0, optimizing ...
@W:CL189 : apbuart.vhd(537) | Register bit r.tshift(10) is always 1, optimizing ...
@W:CL189 : apbuart.vhd(537) | Register bit r.tcnt(1) is always 0, optimizing ...
@W:CL189 : apbuart.vhd(537) | Register bit r.rcnt(1) is always 0, optimizing ...
@W:CL260 : apbuart.vhd(537) | Pruning Register bit 1 of r.tcnt(1 downto 0)  
@W:CL260 : apbuart.vhd(537) | Pruning Register bit 10 of r.tshift(10 downto 0)  
@W:CL260 : apbuart.vhd(537) | Pruning Register bit 1 of r.rcnt(1 downto 0)  
@N:CD630 : iopad.vhd(32) | Synthesizing techmap.iopad.rtl 
Post processing for techmap.iopad.rtl
@N:CD630 : grgpio.vhd(45) | Synthesizing gaisler.grgpio.rtl 
Post processing for gaisler.grgpio.rtl
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_6(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_5(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_4(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_3(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_2(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_1(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.irqmap_0(0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.bypass(6 downto 0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.ilat(6 downto 0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.edge(6 downto 0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.level(6 downto 0)  
@W:CL169 : grgpio.vhd(320) | Pruning Register r.imask(6 downto 0)  
@N:CD630 : gptimer.vhd(47) | Synthesizing gaisler.gptimer.rtl 
Post processing for gaisler.gptimer.rtl
@N:CD630 : apbctrl.vhd(43) | Synthesizing grlib.apbctrl.rtl 
Post processing for grlib.apbctrl.rtl
@N:CD630 : outpad.vhd(32) | Synthesizing techmap.outpad.rtl 
@W:CD638 : outpad.vhd(39) | Signal padx is undriven 
Post processing for techmap.outpad.rtl
@N:CD630 : inpad.vhd(32) | Synthesizing techmap.inpad.rtl 
Post processing for techmap.inpad.rtl
@N:CD630 : ahbuart.vhd(45) | Synthesizing gaisler.ahbuart.struct 
@N:CD630 : dcom.vhd(35) | Synthesizing gaisler.dcom.struct 
@N:CD231 : dcom.vhd(49) | Using onehot encoding for type dcom_state_type (idle="100000")
Post processing for gaisler.dcom.struct
@W:CL169 : dcom.vhd(147) | Pruning Register r.hresp(1 downto 0)  
@N:CD630 : dcom_uart.vhd(39) | Synthesizing gaisler.dcom_uart.rtl 
@N:CD233 : dcom_uart.vhd(66) | Using sequential encoding for type txfsmtype
@N:CD233 : dcom_uart.vhd(65) | Using sequential encoding for type rxfsmtype
Post processing for gaisler.dcom_uart.rtl
@W:CL240 : dcom_uart.vhd(49) | uo.flow is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dcom_uart.vhd(49) | uo.txen is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL189 : dcom_uart.vhd(324) | Register bit r.tshift(10) is always 1, optimizing ...
@W:CL260 : dcom_uart.vhd(324) | Pruning Register bit 10 of r.tshift(10 downto 0)  
@N:CD630 : ahbmst.vhd(35) | Synthesizing gaisler.ahbmst.rtl 
Post processing for gaisler.ahbmst.rtl
Post processing for gaisler.ahbuart.struct
@N:CD630 : ahbctrl.vhd(37) | Synthesizing grlib.ahbctrl.rtl 
Post processing for grlib.ahbctrl.rtl
@W:CL169 : ahbctrl.vhd(664) | Pruning Register r.lsplmst(0)  
@W:CL169 : ahbctrl.vhd(664) | Pruning Register reg0.r.defmst_3  
@W:CL169 : ahbctrl.vhd(664) | Pruning Register r.beat(3 downto 0)  
@W:CL169 : ahbctrl.vhd(664) | Pruning Register r.hsize(2 downto 0)  
@W:CL189 : ahbctrl.vhd(664) | Register bit r.ldefmst is always 0, optimizing ...
@W:CL260 : ahbctrl.vhd(664) | Pruning Register bit 0 of r.htrans(1 downto 0)  
@W:CL260 : ahbctrl.vhd(664) | Pruning Register bit 15 of r.haddr(15 downto 2)  
@W:CL260 : ahbctrl.vhd(664) | Pruning Register bit 14 of r.haddr(15 downto 2)  
@W:CL260 : ahbctrl.vhd(664) | Pruning Register bit 13 of r.haddr(15 downto 2)  
@W:CL260 : ahbctrl.vhd(664) | Pruning Register bit 12 of r.haddr(15 downto 2)  
@W:CL260 : ahbctrl.vhd(664) | Pruning Register bit 11 of r.haddr(15 downto 2)  
@N:CD630 : iopad.vhd(137) | Synthesizing techmap.iopadv.rtl 
Post processing for techmap.iopadv.rtl
@N:CD630 : outpad.vhd(115) | Synthesizing techmap.outpadv.rtl 
Post processing for techmap.outpadv.rtl
@N:CD630 : mctrl.vhd(46) | Synthesizing esa.mctrl.rtl 
@N:CD231 : mctrl.vhd(120) | Using onehot encoding for type memcycletype (idle="10000000")
@W:CD604 : mctrl.vhd(740) | OTHERS clause is not synthesized 
@W:CD638 : mctrl.vhd(198) | Signal sdmo.vhready is undriven 
@W:CD638 : mctrl.vhd(198) | Signal sdmo.bsel is undriven 
@W:CD638 : mctrl.vhd(198) | Signal sdmo.hsel is undriven 
@W:CD638 : mctrl.vhd(199) | Signal sdi.merror is undriven 
@W:CD638 : mctrl.vhd(200) | Signal lsdo.dqm is undriven 
@W:CD638 : mctrl.vhd(200) | Signal lsdo.casn is undriven 
@W:CD638 : mctrl.vhd(200) | Signal lsdo.rasn is undriven 
@W:CD638 : mctrl.vhd(200) | Signal lsdo.sdwen is undriven 
@W:CD638 : mctrl.vhd(200) | Signal lsdo.sdcsn is undriven 
@W:CD638 : mctrl.vhd(200) | Signal lsdo.sdcke is undriven 
@W:CD638 : mctrl.vhd(204) | Signal rrsbdrive is undriven 
Post processing for esa.mctrl.rtl
@W:CL252 : mctrl.vhd(204) | Bit 0 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 1 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 2 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 3 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 4 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 5 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 6 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 7 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 8 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 9 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 10 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 11 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 12 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 13 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 14 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 15 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 16 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 17 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 18 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 19 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 20 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 21 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 22 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 23 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 24 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 25 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 26 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 27 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 28 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 29 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 30 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 31 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 32 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 33 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 34 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 35 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 36 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 37 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 38 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 39 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 40 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 41 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 42 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 43 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 44 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 45 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 46 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 47 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 48 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 49 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 50 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 51 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 52 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 53 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 54 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 55 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 56 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 57 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 58 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 59 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 60 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 61 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 62 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(204) | Bit 63 of signal rrsbdrive is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 0 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 1 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 2 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 3 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 4 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 5 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 6 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 7 of signal lsdo.dqm is floating - a simulation mismatch is possible
@W:CL240 : mctrl.vhd(200) | lsdo.casn is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(200) | lsdo.rasn is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(200) | lsdo.sdwen is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : mctrl.vhd(200) | Bit 0 of signal lsdo.sdcsn is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 1 of signal lsdo.sdcsn is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 0 of signal lsdo.sdcke is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(200) | Bit 1 of signal lsdo.sdcke is floating - a simulation mismatch is possible
@W:CL240 : mctrl.vhd(199) | sdi.merror is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(199) | sdi.idle is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(198) | sdmo.vhready is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(198) | sdmo.bsel is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(198) | sdmo.hsel is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(80) | memo.rs_edac_en is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(80) | memo.sdram_en is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mctrl.vhd(80) | memo.ce is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : mctrl.vhd(80) | Bit 0 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 1 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 2 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 3 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 4 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 5 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 6 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 7 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 8 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 9 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 10 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 11 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 12 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 13 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 14 of signal memo.sa is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 0 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 1 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 2 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 3 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 4 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 5 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 6 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 7 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 8 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 9 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 10 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 11 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 12 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 13 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 14 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 15 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 16 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 17 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 18 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 19 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 20 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 21 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 22 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 23 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 24 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 25 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 26 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 27 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 28 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 29 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 30 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 31 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 32 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 33 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 34 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 35 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 36 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 37 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 38 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 39 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 40 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 41 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 42 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 43 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 44 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 45 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 46 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 47 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 48 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 49 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 50 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 51 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 52 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 53 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 54 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 55 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 56 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 57 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 58 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 59 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 60 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 61 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 62 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL252 : mctrl.vhd(80) | Bit 63 of signal memo.sddata is floating - a simulation mismatch is possible
@W:CL169 : mctrl.vhd(1010) | Pruning Register stdregs.rsbdrive_3(63 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.sd(63 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.sa(14 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.htrans(1 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.sdhsel  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.hsel  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.haddr(31 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.mcfg2.sdren  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.mcfg2.srdis  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.mcfg2.brdyen  
@W:CL169 : mctrl.vhd(1010) | Pruning Register stdregs.r.nbdrive_3(3 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.ready8  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.readdata(31 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.sdwritedata(63 downto 0)  
@W:CL169 : mctrl.vhd(1010) | Pruning Register r.writedata8(15 downto 0)  
@W:CL190 : mctrl.vhd(1014) | Optimizing register bit r.ramsn(2) to a constant 1
@W:CL190 : mctrl.vhd(1014) | Optimizing register bit r.ramsn(3) to a constant 1
@W:CL190 : mctrl.vhd(1014) | Optimizing register bit r.ramsn(4) to a constant 1
@W:CL260 : mctrl.vhd(1014) | Pruning Register bit 4 of r.ramsn(4 downto 0)  
@W:CL260 : mctrl.vhd(1014) | Pruning Register bit 3 of r.ramsn(4 downto 0)  
@W:CL260 : mctrl.vhd(1014) | Pruning Register bit 2 of r.ramsn(4 downto 0)  
@N:CD630 : irqmp.vhd(43) | Synthesizing gaisler.irqmp.rtl 
Post processing for gaisler.irqmp.rtl
@W:CL169 : irqmp.vhd(316) | Pruning Register r.ibroadcast(15 downto 1)  
@N:CD630 : dsu3.vhd(44) | Synthesizing gaisler.dsu3.rtl 
@N:CD630 : dsu3x.vhd(37) | Synthesizing gaisler.dsu3x.rtl 
@W:CD434 : dsu3x.vhd(164) | Signal hrdata2x in the sensitivity list is not used in the process
@W:CD638 : dsu3x.vhd(153) | Signal tbo.data is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.break is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbwr is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg2.write is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg2.read is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg2.mask is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg2.addr is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg1.write is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg1.read is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg1.mask is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.tbreg1.addr is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.delaycnt is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.dcnten is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.bphit2 is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.bphit is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.enable is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.aindex is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.ahbactive is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hsel is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hmastlock is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hmaster is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hwdata is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hburst is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hsize is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.htrans is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.hwrite is undriven 
@W:CD638 : dsu3x.vhd(155) | Signal tr.haddr is undriven 
Post processing for gaisler.dsu3x.rtl
@W:CL240 : dsu3x.vhd(158) | rhin.irq is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.break is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.tbwr is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.tbreg2.write is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.tbreg2.read is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 6 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 7 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 8 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 9 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 10 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 11 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 12 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 13 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 14 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 15 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 16 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 17 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 18 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 19 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 20 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 21 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 22 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 23 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 24 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 25 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 26 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 27 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 28 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 29 of signal tr.tbreg2.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 6 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 7 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 8 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 9 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 10 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 11 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 12 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 13 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 14 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 15 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 16 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 17 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 18 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 19 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 20 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 21 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 22 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 23 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 24 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 25 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 26 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 27 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 28 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 29 of signal tr.tbreg2.addr is floating - a simulation mismatch is possible
@W:CL240 : dsu3x.vhd(155) | tr.tbreg1.write is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.tbreg1.read is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 6 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 7 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 8 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 9 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 10 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 11 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 12 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 13 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 14 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 15 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 16 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 17 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 18 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 19 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 20 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 21 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 22 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 23 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 24 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 25 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 26 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 27 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 28 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 29 of signal tr.tbreg1.mask is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 6 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 7 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 8 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 9 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 10 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 11 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 12 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 13 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 14 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 15 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 16 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 17 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 18 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 19 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 20 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 21 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 22 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 23 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 24 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 25 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 26 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 27 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 28 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 29 of signal tr.tbreg1.addr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.delaycnt is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.delaycnt is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.delaycnt is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.delaycnt is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.delaycnt is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.delaycnt is floating - a simulation mismatch is possible
@W:CL240 : dsu3x.vhd(155) | tr.dcnten is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.bphit2 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.bphit is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.enable is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.aindex is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.aindex is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.aindex is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.aindex is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.aindex is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.aindex is floating - a simulation mismatch is possible
@W:CL240 : dsu3x.vhd(155) | tr.ahbactive is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.hsel is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : dsu3x.vhd(155) | tr.hmastlock is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.hmaster is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.hmaster is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.hmaster is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.hmaster is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 6 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 7 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 8 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 9 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 10 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 11 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 12 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 13 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 14 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 15 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 16 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 17 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 18 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 19 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 20 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 21 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 22 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 23 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 24 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 25 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 26 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 27 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 28 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 29 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 30 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 31 of signal tr.hwdata is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.hburst is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.hburst is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.hburst is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.hsize is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.hsize is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.hsize is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.htrans is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.htrans is floating - a simulation mismatch is possible
@W:CL240 : dsu3x.vhd(155) | tr.hwrite is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : dsu3x.vhd(155) | Bit 0 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 1 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 2 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 3 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 4 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 5 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 6 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 7 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 8 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 9 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 10 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 11 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 12 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 13 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 14 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 15 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 16 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 17 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 18 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 19 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 20 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 21 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 22 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 23 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 24 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 25 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 26 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 27 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 28 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 29 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 30 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(155) | Bit 31 of signal tr.haddr is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 0 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 1 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 2 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 3 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 4 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 5 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 6 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 7 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 8 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 9 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 10 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 11 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 12 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 13 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 14 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 15 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 16 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 17 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 18 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 19 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 20 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 21 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 22 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 23 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 24 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 25 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 26 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 27 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 28 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 29 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 30 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 31 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 32 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 33 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 34 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 35 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 36 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 37 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 38 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 39 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 40 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 41 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 42 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 43 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 44 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 45 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 46 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 47 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 48 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 49 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 50 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 51 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 52 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 53 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 54 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 55 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 56 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 57 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 58 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 59 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 60 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 61 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 62 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 63 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 64 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 65 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 66 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 67 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 68 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 69 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 70 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 71 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 72 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 73 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 74 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 75 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 76 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 77 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 78 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 79 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 80 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 81 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 82 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 83 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 84 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 85 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 86 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 87 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 88 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 89 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 90 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 91 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 92 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 93 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 94 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 95 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 96 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 97 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 98 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 99 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 100 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 101 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 102 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 103 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 104 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 105 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 106 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 107 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 108 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 109 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 110 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 111 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 112 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 113 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 114 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 115 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 116 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 117 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 118 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 119 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 120 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 121 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 122 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 123 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 124 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 125 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 126 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : dsu3x.vhd(153) | Bit 127 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL260 : dsu3x.vhd(645) | Pruning Register bit 1 of r.slv.haddr(24 downto 0)  
@W:CL260 : dsu3x.vhd(645) | Pruning Register bit 0 of r.slv.haddr(24 downto 0)  
Post processing for gaisler.dsu3.rtl
@N:CD630 : leon3s.vhd(158) | Synthesizing gaisler.leon3s.rtl 
@W:CD638 : leon3s.vhd(233) | Signal tbo.data is undriven 
@W:CD638 : leon3s.vhd(241) | Signal rd1 is undriven 
@W:CD638 : leon3s.vhd(241) | Signal rd2 is undriven 
@W:CD638 : leon3s.vhd(241) | Signal wd is undriven 
@N:CD630 : cachemem.vhd(37) | Synthesizing gaisler.cachemem.rtl 
@W:CD638 : cachemem.vhd(127) | Signal ildataout is undriven 
@W:CD638 : cachemem.vhd(148) | Signal ldataout is undriven 
@N:CD630 : syncram.vhd(34) | Synthesizing techmap.syncram.rtl 
@W:CD638 : syncram.vhd(49) | Signal rena is undriven 
@W:CD638 : syncram.vhd(49) | Signal wena is undriven 
@W:CD638 : syncram.vhd(50) | Signal databp is undriven 
@W:CD638 : syncram.vhd(50) | Signal testdata is undriven 
@N:CD630 : memory_apa3.vhd(380) | Synthesizing techmap.proasic3_syncram.rtl 
@N:CD630 : memory_apa3.vhd(178) | Synthesizing techmap.proasic3_syncram_dp.rtl 
@N:CD630 : memory_apa3.vhd(33) | Synthesizing techmap.proasic3_ram4k9.rtl 
@W:CD796 : memory_apa3.vhd(77) | Bit 9 of signal qa is undriven 
@W:CD796 : memory_apa3.vhd(77) | Bit 9 of signal qb is undriven 
@N:CD630 : memory_apa3.vhd(46) | Synthesizing techmap.ram4k9.syn_black_box 
Post processing for techmap.ram4k9.syn_black_box
Post processing for techmap.proasic3_ram4k9.rtl
Post processing for techmap.proasic3_syncram_dp.rtl
Post processing for techmap.proasic3_syncram.rtl
Post processing for techmap.syncram.rtl
@N:CD630 : syncram.vhd(34) | Synthesizing techmap.syncram.rtl 
@W:CD638 : syncram.vhd(49) | Signal rena is undriven 
@W:CD638 : syncram.vhd(49) | Signal wena is undriven 
@W:CD638 : syncram.vhd(50) | Signal databp is undriven 
@W:CD638 : syncram.vhd(50) | Signal testdata is undriven 
@N:CD630 : memory_apa3.vhd(380) | Synthesizing techmap.proasic3_syncram.rtl 
@N:CD630 : memory_apa3.vhd(274) | Synthesizing techmap.proasic3_syncram_2p.rtl 
@N:CD630 : memory_apa3.vhd(120) | Synthesizing techmap.proasic3_ram512x18.rtl 
@N:CD630 : memory_apa3.vhd(132) | Synthesizing techmap.ram512x18.syn_black_box 
Post processing for techmap.ram512x18.syn_black_box
Post processing for techmap.proasic3_ram512x18.rtl
Post processing for techmap.proasic3_syncram_2p.rtl
Post processing for techmap.proasic3_syncram.rtl
Post processing for techmap.syncram.rtl
Post processing for gaisler.cachemem.rtl
@N:CD630 : regfile_3p.vhd(32) | Synthesizing techmap.regfile_3p.rtl 
@N:CD630 : syncram_2p.vhd(35) | Synthesizing techmap.syncram_2p.rtl 
@W:CD434 : syncram_2p.vhd(107) | Signal testin in the sensitivity list is not used in the process
@W:CD729 : syncram_2p.vhd(199) | Component declaration has 3 generics but entity declares only 2 generics
@W:CD638 : syncram_2p.vhd(58) | Signal databp is undriven 
@W:CD638 : syncram_2p.vhd(58) | Signal testdata is undriven 
@N:CD630 : memory_apa3.vhd(274) | Synthesizing techmap.proasic3_syncram_2p.rtl 
Post processing for techmap.proasic3_syncram_2p.rtl
Post processing for techmap.syncram_2p.rtl
Post processing for techmap.regfile_3p.rtl
@N:CD630 : proc3.vhd(43) | Synthesizing gaisler.proc3.rtl 
@N:CD630 : mmu_cache.vhd(39) | Synthesizing gaisler.mmu_cache.rtl 
@N:CD233 : mmuconfig.vhd(39) | Using sequential encoding for type mmu_idcache
@N:CD630 : mmu_acache.vhd(40) | Synthesizing gaisler.mmu_acache.rtl 
@W:CD434 : mmu_acache.vhd(100) | Signal hclken in the sensitivity list is not used in the process
@W:CD638 : mmu_acache.vhd(96) | Signal r2.hclken2 is undriven 
Post processing for gaisler.mmu_acache.rtl
@W:CL240 : mmu_acache.vhd(96) | r2.hclken2 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : mmu_acache.vhd(53) | Bit 0 of signal mcdo.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(53) | Bit 1 of signal mcdo.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(53) | Bit 2 of signal mcdo.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(53) | Bit 3 of signal mcdo.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(51) | Bit 0 of signal mcio.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(51) | Bit 1 of signal mcio.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(51) | Bit 2 of signal mcio.par is floating - a simulation mismatch is possible
@W:CL252 : mmu_acache.vhd(51) | Bit 3 of signal mcio.par is floating - a simulation mismatch is possible
@N:CD630 : mmu_dcache.vhd(41) | Synthesizing gaisler.mmu_dcache.rtl 
@N:CD233 : mmuconfig.vhd(39) | Using sequential encoding for type mmu_idcache
@N:CD231 : mmu_dcache.vhd(131) | Using onehot encoding for type dstatetype (idle="100000000")
@N:CD231 : mmu_dcache.vhd(118) | Using onehot encoding for type rdatatype (dtag="100000000")
@W:CD604 : mmu_dcache.vhd(1061) | OTHERS clause is not synthesized 
@W:CD638 : mmu_dcache.vhd(274) | Signal rh.snmiss is undriven 
@W:CD638 : mmu_dcache.vhd(274) | Signal rh.hitaddr is undriven 
Post processing for gaisler.mmu_dcache.rtl
@W:CL240 : mmu_dcache.vhd(274) | rh.snmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : mmu_dcache.vhd(274) | Bit 0 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 1 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 2 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 3 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 4 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 5 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 6 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(274) | Bit 7 of signal rh.hitaddr is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.sdiag is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.sdiag is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.sdiag is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.sdiag is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.dpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.dpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.dpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.dpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL240 : mmu_dcache.vhd(74) | dcrami.spar is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : mmu_dcache.vhd(74) | Bit 0 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 1 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 2 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 3 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 4 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 5 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 6 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 7 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 8 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 9 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 10 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 11 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 12 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 13 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 14 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 15 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 16 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 17 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 18 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(74) | Bit 19 of signal dcrami.faddress is floating - a simulation mismatch is possible
@W:CL240 : mmu_dcache.vhd(69) | dco.cache is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : mmu_dcache.vhd(69) | Bit 0 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(69) | Bit 1 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(69) | Bit 2 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible
@W:CL252 : mmu_dcache.vhd(69) | Bit 3 of signal dco.icdiag.ilock is floating - a simulation mismatch is possible
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.cache is always 1, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.cctrl.dsnoop is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.e is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.nf is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.pso is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.tlbdis is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.bar(0) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.bar(1) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.pagesize(0) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.pagesize(1) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(0) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(1) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(2) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(3) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(4) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(5) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(6) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctx(7) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(0) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(1) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(2) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(3) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(4) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(5) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(6) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(7) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(8) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(9) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(10) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(11) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(12) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(13) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(14) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(15) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(16) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(17) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(18) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(19) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(20) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(21) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(22) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(23) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(24) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(25) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(26) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(27) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(28) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.mmctrl1.ctxp(29) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.lock is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.flush_op is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.trans_op is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.dsuset(0) is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.lrr is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.ilramen is always 0, optimizing ...
@W:CL189 : mmu_dcache.vhd(1534) | Register bit r.ready is always 0, optimizing ...
@N:CD630 : mmu_icache.vhd(37) | Synthesizing gaisler.mmu_icache.rtl 
@N:CD233 : mmuconfig.vhd(39) | Using sequential encoding for type mmu_idcache
@N:CD233 : mmu_icache.vhd(162) | Using sequential encoding for type istatetype
@N:CD233 : mmu_icache.vhd(94) | Using sequential encoding for type rdatatype
@W:CD604 : mmu_icache.vhd(474) | OTHERS clause is not synthesized 
Post processing for gaisler.mmu_icache.rtl
@W:CL252 : mmu_icache.vhd(59) | Bit 0 of signal icrami.dpar is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 1 of signal icrami.dpar is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 2 of signal icrami.dpar is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 3 of signal icrami.dpar is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 0 of signal icrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 1 of signal icrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 2 of signal icrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 3 of signal icrami.tpar_0 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 0 of signal icrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 1 of signal icrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 2 of signal icrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 3 of signal icrami.tpar_1 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 0 of signal icrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 1 of signal icrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 2 of signal icrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 3 of signal icrami.tpar_2 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 0 of signal icrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 1 of signal icrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 2 of signal icrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL252 : mmu_icache.vhd(59) | Bit 3 of signal icrami.tpar_3 is floating - a simulation mismatch is possible
@W:CL240 : mmu_icache.vhd(54) | ico.cstat.mhold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mmu_icache.vhd(54) | ico.cstat.chold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mmu_icache.vhd(54) | ico.cstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : mmu_icache.vhd(54) | ico.cstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.pflushtyp  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.pflushaddr(31 downto 12)  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.pflushr  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.pflush  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.diagset(0)  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.setrepl(0)  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.rndcnt(0)  
@W:CL169 : mmu_icache.vhd(687) | Pruning Register r.flush3  
@W:CL189 : mmu_icache.vhd(687) | Register bit r.lock is always 0, optimizing ...
@W:CL189 : mmu_icache.vhd(687) | Register bit r.trans_op is always 0, optimizing ...
@W:CL189 : mmu_icache.vhd(687) | Register bit r.lrr is always 0, optimizing ...
@W:CL189 : mmu_icache.vhd(687) | Register bit r.cache is always 1, optimizing ...
Post processing for gaisler.mmu_cache.rtl
@N:CD630 : iu3.vhd(42) | Synthesizing gaisler.iu3.rtl 
@N:CD233 : iu3.vhd(242) | Using sequential encoding for type exception_state
@N:CD364 : iu3.vhd(2808) | Removed redundant assignment
@W:CD638 : iu3.vhd(2349) | Signal cpu_index is undriven 
@W:CD638 : iu3.vhd(2350) | Signal disasen is undriven 
Post processing for gaisler.iu3.rtl
@W:CL240 : iu3.vhd(80) | dbgo.su is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.wbhold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.dstat.mhold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.dstat.chold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.dstat.tmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.dstat.cmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.istat.mhold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.istat.chold is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.istat.tmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.istat.cmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(80) | dbgo.bpmiss is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : iu3.vhd(80) | Bit 0 of signal dbgo.optype is floating - a simulation mismatch is possible
@W:CL252 : iu3.vhd(80) | Bit 1 of signal dbgo.optype is floating - a simulation mismatch is possible
@W:CL252 : iu3.vhd(80) | Bit 2 of signal dbgo.optype is floating - a simulation mismatch is possible
@W:CL252 : iu3.vhd(80) | Bit 3 of signal dbgo.optype is floating - a simulation mismatch is possible
@W:CL252 : iu3.vhd(80) | Bit 4 of signal dbgo.optype is floating - a simulation mismatch is possible
@W:CL252 : iu3.vhd(80) | Bit 5 of signal dbgo.optype is floating - a simulation mismatch is possible
@W:CL240 : iu3.vhd(80) | dbgo.fcnt is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(78) | irqo.fpen is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(73) | dci.flushl is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : iu3.vhd(71) | ici.pnull is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL169 : iu3.vhd(3026) | Pruning Register dsur.tbufcnt(5 downto 0)  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.w.except  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.w.wreg  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.w.wa(6 downto 0)  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.mac  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.dci.asi(7 downto 0)  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.dci.dsuen  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.dci.lock  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.dci.write  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.dci.read  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.x.dci.enaddr  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.m.casaz  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.m.mul  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.m.divz  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.e.mul  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.a.ldchkex  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.a.ldchkra  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.a.ldcheck2  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.a.ldcheck1  
@W:CL169 : iu3.vhd(2997) | Pruning Register r.d.divrdy  
@W:CL189 : iu3.vhd(2997) | Register bit r.a.divstart is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.mulstart is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.w.s.ec is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.w.s.ef is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.ctrl.tt(0) is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.ctrl.tt(1) is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.ctrl.tt(2) is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.ctrl.tt(3) is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.ctrl.tt(4) is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.a.ctrl.tt(5) is always 0, optimizing ...
@W:CL189 : iu3.vhd(2997) | Register bit r.x.npc(2) is always 0, optimizing ...
@W:CL260 : iu3.vhd(2997) | Pruning Register bit 2 of r.x.npc(2 downto 0)  
Post processing for gaisler.proc3.rtl
Post processing for gaisler.leon3s.rtl
@W:CL252 : leon3s.vhd(233) | Bit 0 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 1 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 2 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 3 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 4 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 5 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 6 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 7 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 8 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 9 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 10 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 11 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 12 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 13 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 14 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 15 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 16 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 17 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 18 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 19 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 20 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 21 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 22 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 23 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 24 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 25 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 26 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 27 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 28 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 29 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 30 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 31 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 32 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 33 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 34 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 35 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 36 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 37 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 38 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 39 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 40 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 41 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 42 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 43 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 44 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 45 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 46 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 47 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 48 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 49 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 50 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 51 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 52 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 53 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 54 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 55 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 56 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 57 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 58 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 59 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 60 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 61 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 62 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 63 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 64 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 65 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 66 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 67 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 68 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 69 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 70 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 71 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 72 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 73 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 74 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 75 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 76 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 77 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 78 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 79 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 80 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 81 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 82 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 83 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 84 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 85 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 86 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 87 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 88 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 89 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 90 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 91 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 92 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 93 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 94 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 95 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 96 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 97 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 98 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 99 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 100 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 101 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 102 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 103 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 104 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 105 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 106 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 107 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 108 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 109 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 110 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 111 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 112 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 113 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 114 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 115 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 116 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 117 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 118 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 119 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 120 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 121 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 122 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 123 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 124 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 125 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 126 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL252 : leon3s.vhd(233) | Bit 127 of signal tbo.data is floating - a simulation mismatch is possible
@W:CL245 : leon3s.vhd(258) | Bit 0 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 1 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 2 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 3 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 4 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 5 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 6 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 7 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 8 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 9 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 10 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 11 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 12 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 13 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 14 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 15 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 16 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 17 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 18 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 19 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 20 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 21 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 22 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 23 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 24 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 25 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 26 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 27 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 28 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 29 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 30 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 31 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 32 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 33 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 34 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 35 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 36 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 37 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 38 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 39 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 40 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 41 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 42 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 43 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 44 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 45 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 46 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 47 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 48 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 49 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 50 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 51 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 52 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 53 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 54 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 55 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 56 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 57 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 58 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 59 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 60 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 61 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 62 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 63 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 64 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 65 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 66 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 67 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 68 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 69 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 70 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 71 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 72 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 73 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 74 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 75 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 76 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 77 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 78 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 79 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 80 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 81 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 82 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 83 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 84 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 85 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 86 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 87 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 88 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 89 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 90 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 91 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 92 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 93 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 94 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 95 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 96 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 97 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 98 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 99 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 100 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 101 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 102 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 103 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 104 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 105 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 106 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 107 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 108 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 109 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 110 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 111 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 112 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 113 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 114 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 115 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 116 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 117 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 118 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 119 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 120 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 121 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 122 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 123 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 124 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 125 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 126 of input tbo of instance p0 is floating
@W:CL245 : leon3s.vhd(258) | Bit 127 of input tbo of instance p0 is floating
@N:CD630 : rstgen.vhd(29) | Synthesizing gaisler.rstgen.rtl 
Post processing for gaisler.rstgen.rtl
@N:CD630 : clkgen.vhd(32) | Synthesizing techmap.clkgen.struct 
@W:CD279 : allclkgen.vhd(348) | Port clkb of component clkgen_proasic3 not found on corresponding entity
@W:CD279 : allclkgen.vhd(349) | Port clkc of component clkgen_proasic3 not found on corresponding entity
@W:CD729 : clkgen.vhd(157) | Component declaration has 8 generics but entity declares only 6 generics
@W:CD730 : clkgen.vhd(157) | Component declaration has 9 ports but entity declares 7 ports
@W:CD638 : clkgen.vhd(66) | Signal intclk is undriven 
@W:CD638 : clkgen.vhd(66) | Signal sdintclk is undriven 
@W:CD638 : clkgen.vhd(67) | Signal lock is undriven 
@N:CD630 : clkgen_proasic3.vhd(41) | Synthesizing techmap.clkgen_proasic3.struct 
@W:CD280 : clkgen_proasic3.vhd(83) | Unbound component PLLINT mapped to black box
@W:CD280 : clkgen_proasic3.vhd(64) | Unbound component PLL mapped to black box
@N:CD630 : clkgen_proasic3.vhd(64) | Synthesizing techmap.pll.syn_black_box 
Post processing for techmap.pll.syn_black_box
@N:CD630 : clkgen_proasic3.vhd(83) | Synthesizing techmap.pllint.syn_black_box 
Post processing for techmap.pllint.syn_black_box
Post processing for techmap.clkgen_proasic3.struct
@W:CL240 : clkgen_proasic3.vhd(53) | sdclk is not assigned a value (floating) - a simulation mismatch is possible 
Post processing for techmap.clkgen.struct
@W:CL240 : clkgen.vhd(62) | clkc is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : clkgen.vhd(61) | clkb is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : clkgen.vhd(60) | clk2xu is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : clkgen.vhd(59) | clk1xu is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : clkgen.vhd(58) | clk4x is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : clkgen.vhd(53) | clk2x is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : clkgen.vhd(52) | clkn is not assigned a value (floating) - a simulation mismatch is possible 
Post processing for work.leon3mp.behavioral
@W:CL252 : leon3mp.vhd(147) | Bit 0 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 1 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 2 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 3 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 4 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 5 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 6 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 7 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 8 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 9 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 10 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 11 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 12 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 13 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 14 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 15 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 16 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 17 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 18 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 19 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 20 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 21 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 22 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 23 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 24 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 25 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 26 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 27 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 28 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 29 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 30 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 31 of signal gpioi.sig_en is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 0 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 1 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 2 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 3 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 4 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 5 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 6 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 7 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 8 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 9 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 10 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 11 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 12 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 13 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 14 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 15 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 16 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 17 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 18 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 19 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 20 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 21 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 22 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 23 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 24 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 25 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 26 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 27 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 28 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 29 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 30 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(147) | Bit 31 of signal gpioi.sig_in is floating - a simulation mismatch is possible
@W:CL240 : leon3mp.vhd(144) | gpti.wdogen is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : leon3mp.vhd(138) | wpo.wprothit is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : leon3mp.vhd(136) | memi.edac is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : leon3mp.vhd(136) | Bit 0 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 1 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 2 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 3 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 4 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 5 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 6 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 7 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 8 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 9 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 10 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 11 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 12 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 13 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 14 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 15 of signal memi.scb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 0 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 1 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 2 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 3 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 4 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 5 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 6 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 7 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 8 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 9 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 10 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 11 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 12 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 13 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 14 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 15 of signal memi.cb is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 0 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 1 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 2 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 3 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 4 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 5 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 6 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 7 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 8 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 9 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 10 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 11 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 12 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 13 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 14 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 15 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 16 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 17 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 18 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 19 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 20 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 21 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 22 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 23 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 24 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 25 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 26 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 27 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 28 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 29 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 30 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 31 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 32 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 33 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 34 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 35 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 36 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 37 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 38 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 39 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 40 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 41 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 42 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 43 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 44 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 45 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 46 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 47 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 48 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 49 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 50 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 51 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 52 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 53 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 54 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 55 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 56 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 57 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 58 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 59 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 60 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 61 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 62 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(136) | Bit 63 of signal memi.sd is floating - a simulation mismatch is possible
@W:CL240 : leon3mp.vhd(131) | ahbuarti.extclk is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : leon3mp.vhd(131) | ahbuarti.ctsn is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL252 : leon3mp.vhd(121) | Bit 0 of signal cgi.clksel is floating - a simulation mismatch is possible
@W:CL252 : leon3mp.vhd(121) | Bit 1 of signal cgi.clksel is floating - a simulation mismatch is possible
@W:CL240 : leon3mp.vhd(121) | cgi.pllref is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL245 : leon3mp.vhd(362) | Bit 1 of input uarti of instance uart1 is floating
@W:CL245 : leon3mp.vhd(362) | Bit 2 of input uarti of instance uart1 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 32 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 33 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 34 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 35 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 36 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 37 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 38 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 39 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 40 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 41 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 42 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 43 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 44 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 45 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 46 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 47 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 48 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 49 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 50 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 51 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 52 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 53 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 54 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 55 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 56 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 57 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 58 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 59 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 60 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 61 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 62 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 63 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 64 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 65 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 66 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 67 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 68 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 69 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 70 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 71 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 72 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 73 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 74 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 75 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 76 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 77 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 78 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 79 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 80 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 81 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 82 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 83 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 84 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 85 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 86 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 87 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 88 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 89 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 90 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 91 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 92 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 93 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 94 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(347) | Bit 95 of input gpioi of instance grgpio0 is floating
@W:CL245 : leon3mp.vhd(332) | Bit 2 of input gpti of instance timer0 is floating
@W:CL245 : leon3mp.vhd(310) | Bit 1 of input uarti of instance dcom0 is floating
@W:CL245 : leon3mp.vhd(310) | Bit 2 of input uarti of instance dcom0 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 41 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 42 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 43 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 44 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 45 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 46 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 47 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 48 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 49 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 50 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 51 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 52 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 53 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 54 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 55 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 56 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 57 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 58 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 59 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 60 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 61 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 62 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 63 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 64 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 65 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 66 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 67 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 68 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 69 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 70 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 71 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 72 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 73 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 74 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 75 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 76 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 77 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 78 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 79 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 80 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 81 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 82 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 83 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 84 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 85 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 86 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 87 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 88 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 89 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 90 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 91 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 92 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 93 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 94 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 95 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 96 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 97 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 98 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 99 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 100 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 101 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 102 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 103 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 104 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 105 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 106 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 107 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 108 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 109 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 110 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 111 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 112 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 113 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 114 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 115 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 116 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 117 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 118 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 119 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 120 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 121 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 122 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 123 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 124 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 125 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 126 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 127 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 128 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 129 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 130 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 131 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 132 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 133 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 134 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 135 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 136 of input memi of instance sr1 is floating
@W:CL245 : leon3mp.vhd(254) | Bit 137 of input memi of instance sr1 is floating
@W:CL167 : leon3mp.vhd(254) | Input wpo of instance sr1 is floating
@W:CL245 : leon3mp.vhd(193) | Bit 0 of input cgi of instance clkgen0 is floating
@W:CL245 : leon3mp.vhd(193) | Bit 4 of input cgi of instance clkgen0 is floating
@W:CL245 : leon3mp.vhd(193) | Bit 5 of input cgi of instance clkgen0 is floating
@W:CL159 : clkgen_proasic3.vhd(51) | Input pciclkin is unused
@W:CL159 : clkgen_proasic3.vhd(55) | Input cgi is unused
@W:CL159 : rstgen.vhd(40) | Input testrst is unused
@W:CL159 : rstgen.vhd(41) | Input testen is unused
@N:CL201 : iu3.vhd(2997) | Trying to extract state machine for register r.d.cnt
@N:CL201 : iu3.vhd(2997) | Trying to extract state machine for register r.x.rstate
Extracted state machine for register r.x.rstate
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL246 : iu3.vhd(72) | Input port bits 203 to 200 of ico(203 downto 0) are unused 
@W:CL246 : iu3.vhd(72) | Input port bits 198 to 167 of ico(203 downto 0) are unused 
@W:CL246 : iu3.vhd(72) | Input port bits 165 to 134 of ico(203 downto 0) are unused 
@W:CL246 : iu3.vhd(72) | Input port bits 132 to 131 of ico(203 downto 0) are unused 
@W:CL246 : iu3.vhd(72) | Input port bits 129 to 128 of ico(203 downto 0) are unused 
@W:CL246 : iu3.vhd(72) | Input port bits 95 to 0 of ico(203 downto 0) are unused 
@W:CL246 : iu3.vhd(74) | Input port bits 207 to 134 of dco(210 downto 0) are unused 
@W:CL247 : iu3.vhd(74) | Input port bit 131 of dco(210 downto 0) is unused 
@W:CL246 : iu3.vhd(74) | Input port bits 129 to 128 of dco(210 downto 0) are unused 
@W:CL246 : iu3.vhd(74) | Input port bits 95 to 0 of dco(210 downto 0) are unused 
@W:CL246 : iu3.vhd(77) | Input port bits 30 to 4 of irqi(30 downto 0) are unused 
@W:CL246 : iu3.vhd(79) | Input port bits 97 to 66 of dbgi(97 downto 0) are unused 
@W:CL247 : iu3.vhd(85) | Input port bit 37 of fpo(69 downto 0) is unused 
@W:CL246 : iu3.vhd(85) | Input port bits 35 to 0 of fpo(69 downto 0) are unused 
@W:CL159 : iu3.vhd(82) | Input mulo is unused
@W:CL159 : iu3.vhd(84) | Input divo is unused
@W:CL159 : iu3.vhd(87) | Input cpo is unused
@W:CL159 : iu3.vhd(89) | Input tbo is unused
@N:CL201 : mmu_icache.vhd(687) | Trying to extract state machine for register r.istate
Extracted state machine for register r.istate
State machine has 3 reachable states with original encodings of:
   00
   10
   11
@W:CL246 : mmu_icache.vhd(53) | Input port bits 131 to 101 of ici(131 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(53) | Input port bits 95 to 64 of ici(131 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(53) | Input port bits 33 to 22 of ici(131 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(53) | Input port bits 1 to 0 of ici(131 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(55) | Input port bits 117 to 40 of dci(117 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(55) | Input port bits 7 to 0 of dci(117 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(56) | Input port bits 210 to 207 of dco(210 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(56) | Input port bits 205 to 180 of dco(210 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(56) | Input port bits 177 to 173 of dco(210 downto 0) are unused 
@W:CL247 : mmu_icache.vhd(56) | Input port bit 169 of dco(210 downto 0) is unused 
@W:CL246 : mmu_icache.vhd(56) | Input port bits 165 to 156 of dco(210 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(56) | Input port bits 135 to 132 of dco(210 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(56) | Input port bits 130 to 0 of dco(210 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(58) | Input port bits 41 to 37 of mcio(41 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(60) | Input port bits 319 to 256 of icramo(319 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(60) | Input port bits 95 to 0 of icramo(319 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(62) | Input port bits 117 to 85 of mmudci(117 downto 0) are unused 
@W:CL246 : mmu_icache.vhd(62) | Input port bits 76 to 0 of mmudci(117 downto 0) are unused 
@W:CL159 : mmu_icache.vhd(64) | Input mmuico is unused
@N:CL201 : mmu_dcache.vhd(1534) | Trying to extract state machine for register r.dstate
Extracted state machine for register r.dstate
State machine has 6 reachable states with original encodings of:
   000000001
   000000010
   000001000
   001000000
   010000000
   100000000
@W:CL247 : mmu_dcache.vhd(68) | Input port bit 116 of dci(117 downto 0) is unused 
@W:CL247 : mmu_dcache.vhd(68) | Input port bit 113 of dci(117 downto 0) is unused 
@W:CL246 : mmu_dcache.vhd(68) | Input port bits 71 to 52 of dci(117 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(68) | Input port bits 41 to 40 of dci(117 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(68) | Input port bits 7 to 5 of dci(117 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(70) | Input port bits 203 to 199 of ico(203 downto 0) are unused 
@W:CL247 : mmu_dcache.vhd(70) | Input port bit 166 of ico(203 downto 0) is unused 
@W:CL246 : mmu_dcache.vhd(70) | Input port bits 130 to 0 of ico(203 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(72) | Input port bits 43 to 38 of mcdo(45 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(73) | Input port bits 139 to 28 of ahbsi(139 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(73) | Input port bits 19 to 0 of ahbsi(139 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(75) | Input port bits 451 to 384 of dcramo(451 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(75) | Input port bits 363 to 256 of dcramo(451 downto 0) are unused 
@W:CL246 : mmu_dcache.vhd(78) | Input port bits 110 to 2 of mmudco(110 downto 0) are unused 
@W:CL159 : mmu_dcache.vhd(79) | Input sclk is unused
@N:CL201 : mmu_acache.vhd(355) | Trying to extract state machine for register r.bo
Extracted state machine for register r.bo
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL247 : mmu_acache.vhd(50) | Input port bit 35 of mcii(35 downto 0) is unused 
@W:CL247 : mmu_acache.vhd(54) | Input port bit 66 of mcmmi(69 downto 0) is unused 
@W:CL246 : mmu_acache.vhd(56) | Input port bits 87 to 85 of ahbi(87 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(56) | Input port bits 83 to 51 of ahbi(87 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(56) | Input port bits 14 to 0 of ahbi(87 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5503 to 5372 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5359 to 5357 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5343 to 5340 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5327 to 5325 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5311 to 5308 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5295 to 5293 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5279 to 5276 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5263 to 5261 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5247 to 5028 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 5015 to 5013 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4999 to 4996 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4983 to 4981 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4967 to 4964 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4951 to 4949 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4935 to 4932 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4919 to 4917 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4903 to 4684 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4671 to 4669 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4655 to 4652 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4639 to 4637 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4623 to 4620 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4607 to 4605 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4591 to 4588 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4575 to 4573 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4559 to 4340 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4327 to 4325 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4311 to 4308 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4295 to 4293 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4279 to 4276 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4263 to 4261 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4247 to 4244 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4231 to 4229 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 4215 to 3996 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3983 to 3981 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3967 to 3964 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3951 to 3949 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3935 to 3932 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3919 to 3917 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3903 to 3900 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3887 to 3885 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3871 to 3652 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3639 to 3637 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3623 to 3620 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3607 to 3605 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3591 to 3588 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3575 to 3573 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3559 to 3556 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3543 to 3541 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3527 to 3308 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3295 to 3293 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3279 to 3276 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3263 to 3261 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3247 to 3244 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3231 to 3229 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3215 to 3212 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3199 to 3197 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 3183 to 2964 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2951 to 2949 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2935 to 2932 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2919 to 2917 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2903 to 2900 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2887 to 2885 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2871 to 2868 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2855 to 2853 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2839 to 2620 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2607 to 2605 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2591 to 2588 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2575 to 2573 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2559 to 2556 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2543 to 2541 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2527 to 2524 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2511 to 2509 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2495 to 2276 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2263 to 2261 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2247 to 2244 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2231 to 2229 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2215 to 2212 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2199 to 2197 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2183 to 2180 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2167 to 2165 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 2151 to 1932 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1919 to 1917 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1903 to 1900 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1887 to 1885 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1871 to 1868 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1855 to 1853 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1839 to 1836 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1823 to 1821 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1807 to 1588 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1575 to 1573 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1559 to 1556 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1543 to 1541 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1527 to 1524 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1511 to 1509 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1495 to 1492 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1479 to 1477 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1463 to 1244 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1231 to 1229 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1215 to 1212 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1199 to 1197 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1183 to 1180 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1167 to 1165 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1151 to 1148 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1135 to 1133 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 1119 to 900 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 887 to 885 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 871 to 868 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 855 to 853 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 839 to 836 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 823 to 821 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 807 to 804 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 791 to 789 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 775 to 556 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 543 to 541 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 527 to 524 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 511 to 509 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 495 to 492 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 479 to 477 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 463 to 460 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 447 to 445 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 431 to 212 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 199 to 197 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 183 to 180 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 167 to 165 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 151 to 148 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 135 to 133 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 119 to 116 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 103 to 101 of ahbso(5503 downto 0) are unused 
@W:CL246 : mmu_acache.vhd(58) | Input port bits 87 to 0 of ahbso(5503 downto 0) are unused 
@W:CL159 : mmu_acache.vhd(59) | Input hclken is unused
@W:CL159 : mmu_cache.vhd(88) | Input hclk is unused
@W:CL159 : syncram_2p.vhd(48) | Input testin is unused
@W:CL159 : memory_apa3.vhd(127) | Input wea is unused
@W:CL159 : syncram.vhd(44) | Input testin is unused
@W:CL159 : memory_apa3.vhd(188) | Input address2 is unused
@W:CL159 : memory_apa3.vhd(189) | Input datain2 is unused
@W:CL159 : syncram.vhd(44) | Input testin is unused
@W:CL246 : cachemem.vhd(62) | Input port bits 796 to 647 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 645 to 643 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 641 to 639 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 606 to 511 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 508 to 502 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 500 to 370 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 349 to 342 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 337 to 232 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 221 to 191 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 189 to 187 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 150 to 148 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 127 to 120 of crami(796 downto 0) are unused 
@W:CL246 : cachemem.vhd(62) | Input port bits 115 to 10 of crami(796 downto 0) are unused 
@W:CL159 : cachemem.vhd(64) | Input sclk is unused
@W:CL246 : dsu3x.vhd(55) | Input port bits 139 to 94 of ahbsi(139 downto 0) are unused 
@W:CL246 : dsu3x.vhd(55) | Input port bits 92 to 89 of ahbsi(139 downto 0) are unused 
@W:CL246 : dsu3x.vhd(55) | Input port bits 56 to 51 of ahbsi(139 downto 0) are unused 
@W:CL247 : dsu3x.vhd(55) | Input port bit 49 of ahbsi(139 downto 0) is unused 
@W:CL246 : dsu3x.vhd(55) | Input port bits 47 to 41 of ahbsi(139 downto 0) are unused 
@W:CL246 : dsu3x.vhd(55) | Input port bits 17 to 14 of ahbsi(139 downto 0) are unused 
@W:CL246 : dsu3x.vhd(55) | Input port bits 12 to 0 of ahbsi(139 downto 0) are unused 
@W:CL246 : dsu3x.vhd(57) | Input port bits 0 to 18 of dbgi(0 to 58) are unused 
@W:CL159 : dsu3x.vhd(52) | Input hclk is unused
@W:CL159 : dsu3x.vhd(54) | Input ahbmi is unused
@W:CL246 : irqmp.vhd(54) | Input port bits 117 to 98 of apbi(117 downto 0) are unused 
@W:CL247 : irqmp.vhd(54) | Input port bit 82 of apbi(117 downto 0) is unused 
@W:CL247 : irqmp.vhd(54) | Input port bit 66 of apbi(117 downto 0) is unused 
@W:CL246 : irqmp.vhd(54) | Input port bits 48 to 25 of apbi(117 downto 0) are unused 
@W:CL246 : irqmp.vhd(54) | Input port bits 18 to 17 of apbi(117 downto 0) are unused 
@W:CL246 : irqmp.vhd(54) | Input port bits 15 to 14 of apbi(117 downto 0) are unused 
@W:CL246 : irqmp.vhd(54) | Input port bits 12 to 0 of apbi(117 downto 0) are unused 
@W:CL247 : irqmp.vhd(56) | Input port bit 0 of irqi(0 to 6) is unused 
@W:CL190 : mctrl.vhd(1014) | Optimizing register bit r.ramoen(2) to a constant 1
@W:CL190 : mctrl.vhd(1014) | Optimizing register bit r.ramoen(3) to a constant 1
@W:CL190 : mctrl.vhd(1014) | Optimizing register bit r.ramoen(4) to a constant 1
@W:CL260 : mctrl.vhd(1014) | Pruning Register bit 4 of r.ramoen(4 downto 0)  
@W:CL260 : mctrl.vhd(1014) | Pruning Register bit 3 of r.ramoen(4 downto 0)  
@W:CL260 : mctrl.vhd(1014) | Pruning Register bit 2 of r.ramoen(4 downto 0)  
@W:CL189 : mctrl.vhd(1010) | Register bit r.bstate(bwrite16) is always 0, optimizing ...
@W:CL189 : mctrl.vhd(1010) | Register bit r.bstate(bread16) is always 0, optimizing ...
@W:CL189 : mctrl.vhd(1010) | Register bit r.bstate(bwrite8) is always 0, optimizing ...
@W:CL189 : mctrl.vhd(1010) | Register bit r.bstate(bread8) is always 0, optimizing ...
@W:CL260 : mctrl.vhd(1010) | Pruning Register bit 0 of r.bstate(0 to 7)  
@W:CL260 : mctrl.vhd(1010) | Pruning Register bit 1 of r.bstate(0 to 7)  
@W:CL260 : mctrl.vhd(1010) | Pruning Register bit 2 of r.bstate(0 to 7)  
@W:CL260 : mctrl.vhd(1010) | Pruning Register bit 3 of r.bstate(0 to 7)  
@W:CL246 : mctrl.vhd(79) | Input port bits 137 to 41 of memi(137 downto 0) are unused 
@W:CL246 : mctrl.vhd(79) | Input port bits 38 to 34 of memi(137 downto 0) are unused 
@W:CL246 : mctrl.vhd(81) | Input port bits 139 to 103 of ahbsi(139 downto 0) are unused 
@W:CL246 : mctrl.vhd(81) | Input port bits 99 to 94 of ahbsi(139 downto 0) are unused 
@W:CL246 : mctrl.vhd(81) | Input port bits 92 to 89 of ahbsi(139 downto 0) are unused 
@W:CL247 : mctrl.vhd(81) | Input port bit 53 of ahbsi(139 downto 0) is unused 
@W:CL246 : mctrl.vhd(81) | Input port bits 14 to 0 of ahbsi(139 downto 0) are unused 
@W:CL246 : mctrl.vhd(83) | Input port bits 117 to 79 of apbi(117 downto 0) are unused 
@W:CL247 : mctrl.vhd(83) | Input port bit 74 of apbi(117 downto 0) is unused 
@W:CL246 : mctrl.vhd(83) | Input port bits 68 to 63 of apbi(117 downto 0) are unused 
@W:CL246 : mctrl.vhd(83) | Input port bits 48 to 23 of apbi(117 downto 0) are unused 
@W:CL246 : mctrl.vhd(83) | Input port bits 18 to 17 of apbi(117 downto 0) are unused 
@W:CL246 : mctrl.vhd(83) | Input port bits 14 to 0 of apbi(117 downto 0) are unused 
@W:CL159 : mctrl.vhd(85) | Input wpo is unused
@W:CL246 : ahbctrl.vhd(73) | Input port bits 5935 to 738 of msto(5935 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(73) | Input port bits 705 to 482 of msto(5935 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(73) | Input port bits 370 to 367 of msto(5935 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(73) | Input port bits 334 to 111 of msto(5935 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 5503 to 2748 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 2458 to 2443 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 2407 to 2404 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 2114 to 2099 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 2063 to 2060 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 1770 to 1755 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 1719 to 1716 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 1426 to 1411 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 1375 to 1372 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 1082 to 1067 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 1031 to 1028 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 738 to 723 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 687 to 684 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 394 to 379 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 343 to 340 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbctrl.vhd(75) | Input port bits 50 to 35 of slvo(5503 downto 0) are unused 
@W:CL246 : ahbmst.vhd(49) | Input port bits 87 to 51 of ahbi(87 downto 0) are unused 
@W:CL247 : ahbmst.vhd(49) | Input port bit 15 of ahbi(87 downto 0) is unused 
@W:CL246 : ahbmst.vhd(49) | Input port bits 13 to 0 of ahbi(87 downto 0) are unused 
@N:CL201 : dcom_uart.vhd(324) | Trying to extract state machine for register r.txstate
Extracted state machine for register r.txstate
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : dcom_uart.vhd(324) | Trying to extract state machine for register r.rxstate
Extracted state machine for register r.rxstate
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL246 : dcom_uart.vhd(48) | Input port bits 2 to 1 of ui(2 downto 0) are unused 
@W:CL246 : dcom_uart.vhd(50) | Input port bits 117 to 68 of apbi(117 downto 0) are unused 
@W:CL246 : dcom_uart.vhd(50) | Input port bits 48 to 21 of apbi(117 downto 0) are unused 
@W:CL246 : dcom_uart.vhd(50) | Input port bits 18 to 17 of apbi(117 downto 0) are unused 
@W:CL246 : dcom_uart.vhd(50) | Input port bits 15 to 9 of apbi(117 downto 0) are unused 
@W:CL246 : dcom_uart.vhd(50) | Input port bits 7 to 0 of apbi(117 downto 0) are unused 
@N:CL201 : dcom.vhd(147) | Trying to extract state machine for register r.state
Extracted state machine for register r.state
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
@W:CL246 : dcom.vhd(40) | Input port bits 14 to 3 of dmao(46 downto 0) are unused 
@W:CL247 : dcom.vhd(40) | Input port bit 0 of dmao(46 downto 0) is unused 
@W:CL247 : dcom.vhd(42) | Input port bit 4 of uarto(12 downto 0) is unused 
@W:CL247 : dcom.vhd(42) | Input port bit 1 of uarto(12 downto 0) is unused 
@W:CL159 : dcom.vhd(43) | Input ahbi is unused
@N:CL201 : apbctrl.vhd(222) | Trying to extract state machine for register r.state
Extracted state machine for register r.state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL246 : apbctrl.vhd(61) | Input port bits 103 to 94 of ahbi(139 downto 0) are unused 
@W:CL246 : apbctrl.vhd(61) | Input port bits 92 to 89 of ahbi(139 downto 0) are unused 
@W:CL246 : apbctrl.vhd(61) | Input port bits 56 to 51 of ahbi(139 downto 0) are unused 
@W:CL247 : apbctrl.vhd(61) | Input port bit 49 of ahbi(139 downto 0) is unused 
@W:CL246 : apbctrl.vhd(61) | Input port bits 47 to 36 of ahbi(139 downto 0) are unused 
@W:CL247 : apbctrl.vhd(61) | Input port bit 15 of ahbi(139 downto 0) is unused 
@W:CL246 : apbctrl.vhd(61) | Input port bits 13 to 0 of ahbi(139 downto 0) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 0 to 3 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 132 to 135 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 264 to 267 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 396 to 399 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 528 to 531 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 660 to 663 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 792 to 795 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 924 to 927 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1056 to 1059 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1188 to 1191 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1320 to 1323 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1452 to 1455 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1584 to 1587 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1716 to 1719 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1848 to 1851 of apbo(0 to 2111) are unused 
@W:CL246 : apbctrl.vhd(64) | Input port bits 1980 to 1983 of apbo(0 to 2111) are unused 
@W:CL246 : gptimer.vhd(63) | Input port bits 117 to 82 of apbi(117 downto 0) are unused 
@W:CL246 : gptimer.vhd(63) | Input port bits 48 to 24 of apbi(117 downto 0) are unused 
@W:CL246 : gptimer.vhd(63) | Input port bits 18 to 17 of apbi(117 downto 0) are unused 
@W:CL246 : gptimer.vhd(63) | Input port bits 15 to 13 of apbi(117 downto 0) are unused 
@W:CL246 : gptimer.vhd(63) | Input port bits 11 to 0 of apbi(117 downto 0) are unused 
@W:CL246 : gptimer.vhd(65) | Input port bits 2 to 1 of gpti(2 downto 0) are unused 
@W:CL246 : grgpio.vhd(63) | Input port bits 117 to 57 of apbi(117 downto 0) are unused 
@W:CL246 : grgpio.vhd(63) | Input port bits 48 to 23 of apbi(117 downto 0) are unused 
@W:CL246 : grgpio.vhd(63) | Input port bits 18 to 17 of apbi(117 downto 0) are unused 
@W:CL246 : grgpio.vhd(63) | Input port bits 15 to 5 of apbi(117 downto 0) are unused 
@W:CL246 : grgpio.vhd(63) | Input port bits 3 to 0 of apbi(117 downto 0) are unused 
@W:CL246 : grgpio.vhd(65) | Input port bits 95 to 7 of gpioi(95 downto 0) are unused 
@N:CL201 : apbuart.vhd(537) | Trying to extract state machine for register r.txstate
Extracted state machine for register r.txstate
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:CL201 : apbuart.vhd(537) | Trying to extract state machine for register r.rxstate
Extracted state machine for register r.rxstate
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL246 : apbuart.vhd(62) | Input port bits 117 to 65 of apbi(117 downto 0) are unused 
@W:CL246 : apbuart.vhd(62) | Input port bits 48 to 25 of apbi(117 downto 0) are unused 
@W:CL246 : apbuart.vhd(62) | Input port bits 18 to 17 of apbi(117 downto 0) are unused 
@W:CL247 : apbuart.vhd(62) | Input port bit 15 of apbi(117 downto 0) is unused 
@W:CL246 : apbuart.vhd(62) | Input port bits 13 to 0 of apbi(117 downto 0) are unused 
@END
Process took 0h:00m:32s realtime, 0h:00m:32s cputime
# Thu Oct 20 10:32:51 2011

###########################################################]