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LIBRARY="techmap" ENDFILE VALUE "\..\..\\lib\techmap\proasic3\buffer_apa3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="2154" LIBRARY="techmap" ENDFILE VALUE "\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="6738" LIBRARY="techmap" ENDFILE VALUE "\..\..\\lib\techmap\proasic3\memory_apa3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="17067" LIBRARY="techmap" ENDFILE VALUE "\..\..\\lib\techmap\proasic3\tap_proasic3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="3674" LIBRARY="techmap" ENDFILE VALUE "\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="115108" LIBRARY="proasic3" ENDFILE VALUE "\..\..\\lib\work\debug\cpu_disas.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="4162" ENDFILE VALUE "\..\..\\lib\work\debug\debug.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="1675" ENDFILE VALUE "\..\..\\lib\work\debug\grtestmod.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="4683" ENDFILE VALUE "\ahbrom.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="6729" ENDFILE VALUE "\config.vhd,hdl" STATE="utd" TIME="1309269161" SIZE="6110" ENDFILE VALUE "\leon3mp.pdc,pdc" STATE="utd" TIME="1309270090" SIZE="8981" ENDFILE VALUE "\leon3mp.sdc,sdc" STATE="utd" TIME="1190412216" SIZE="997" ENDFILE VALUE "\leon3mp.vhd,hdl" STATE="utd" TIME="1313657596" SIZE="24545" ENDFILE VALUE "\testbench.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="9095" ENDFILE ENDLIST LIST UsedFile ENDLIST LIST NewModulesInfo LIST "leon3mp::work" FILE "\leon3mp.vhd,hdl" LIST ExcludePackageForSynthesis VALUE "\..\..\\lib\grlib\stdlib\stdio.vhd,hdl" VALUE "\..\..\\lib\grlib\util\util.vhd,hdl" VALUE "\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl" VALUE "\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl" VALUE "\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl" VALUE "\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl" VALUE "\..\..\\lib\synplify\sim\synplify.vhd,hdl" VALUE "\..\..\\lib\synplify\sim\synattr.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl" VALUE "\..\..\\lib\gaisler\sim\sim.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\sram.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\ata_device.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\sram16.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\phy.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl" VALUE "\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl" VALUE "\..\..\\lib\fmf\utilities\conversions.vhd,hdl" VALUE "\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl" VALUE "\..\..\\lib\gsi\ssram\functions.vhd,hdl" VALUE "\..\..\\lib\gsi\ssram\core_burst.vhd,hdl" VALUE "\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\components.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\package_utility.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl" VALUE "\..\..\\lib\work\debug\debug.vhd,hdl" VALUE "\..\..\\lib\work\debug\grtestmod.vhd,hdl" VALUE "\..\..\\lib\work\debug\cpu_disas.vhd,hdl" VALUE "\config.vhd,hdl" VALUE "\ahbrom.vhd,hdl" VALUE "\leon3mp.vhd,hdl" VALUE "\testbench.vhd,hdl" ENDLIST LIST SynthesisConstraints VALUE "\leon3mp.sdc,sdc" ENDLIST LIST ProjectState5.1 LIST Impl1 ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateFailure LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST LIST Impl2 ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateFailure LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST ENDLIST ENDLIST ENDLIST LIST AssociatedStimulus ENDLIST LIST Other_Association ENDLIST LIST SimulationOptions UseAutomaticDoFile=true IncludeWaveDo=false Type=max RunTime=1000ns Resolution=1ps VsimOpt= EntityName=testbench TopInstanceName=_0 DoFileName= DoFileName2=wave.do DoFileParams= DisplayDUTWave=false LogAllSignals=false DumpVCD=false VCDFileName=power.vcd ENDLIST LIST ModelSimLibPath UseCustomPath=FALSE LibraryPath= ENDLIST LIST GlobalFlowOptions GenerateHDLAfterSynthesis=FALSE GenerateHDLAfterPhySynthesis=FALSE RunDRCAfterSynthesis=FALSE AutoCheckConstraints=TRUE UpdateViewDrawIni=TRUE UpdateModelSimIni=TRUE NoIOMode=FALSE GenerateHDLFromSchematic=TRUE FlashProInputFile=pdb SmartGenCompileReport=T ENDLIST LIST PhySynthesisOptions ENDLIST LIST Profiles NAME="Synplify AE" FUNCTION="Synthesis" TOOL="Synplify" LOCATION="C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\bin\synplify_pro.exe" PARAM="" BATCH=0 EndProfile NAME="ModelSim AE" FUNCTION="Simulation" TOOL="ModelSim" LOCATION="C:\Actel\Libero_v9.0\Model\win32acoem\modelsim.exe" PARAM="" BATCH=0 EndProfile NAME="WFL" FUNCTION="Stimulus" TOOL="WFL" LOCATION="syncad.exe" PARAM="-pwflite" BATCH=0 EndProfile NAME="FlashPro" FUNCTION="Program" TOOL="FlashPro" LOCATION="C:\Actel\Libero_v9.0\Designer\bin\FlashPro.exe" PARAM="" BATCH=0 EndProfile ENDLIST LIST ProjectState5.1 LIST "leon3mp::work" LIST Impl1 ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateFailure LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST LIST Impl2 ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateFailure LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST ENDLIST ENDLIST LIST ExcludePackageForSimulation ENDLIST LIST ExcludePackageForSynthesis LIST leon3mp VALUE "\..\..\\lib\grlib\stdlib\stdio.vhd,hdl" VALUE "\..\..\\lib\grlib\util\util.vhd,hdl" VALUE "\..\..\\lib\grlib\sparc\sparc_disas.vhd,hdl" VALUE "\..\..\\lib\grlib\sparc\cpu_disas.vhd,hdl" VALUE "\..\..\\lib\grlib\amba\dma2ahb_tp.vhd,hdl" VALUE "\..\..\\lib\tech\proasic3\components\proasic3.vhd,hdl" VALUE "\..\..\\lib\synplify\sim\synplify.vhd,hdl" VALUE "\..\..\\lib\synplify\sim\synattr.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ambatest.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ahb_tbfunct.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ahbslv_em.vhd,hdl" VALUE "\..\..\\lib\gaisler\ambatest\ahbmst_em.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\i2c_slave_model.v,hdl" VALUE "\..\..\\lib\gaisler\sim\sim.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\sram.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\ata_device.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\sram16.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\phy.vhd,hdl" VALUE "\..\..\\lib\gaisler\sim\ahbrep.vhd,hdl" VALUE "\..\..\\lib\gaisler\jtag\jtagtst.vhd,hdl" VALUE "\..\..\\lib\fmf\utilities\conversions.vhd,hdl" VALUE "\..\..\\lib\fmf\utilities\gen_utils.vhd,hdl" VALUE "\..\..\\lib\gsi\ssram\functions.vhd,hdl" VALUE "\..\..\\lib\gsi\ssram\core_burst.vhd,hdl" VALUE "\..\..\\lib\gsi\ssram\g880e18bt.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\components.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\package_utility.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\cy7c1354b.vhd,hdl" VALUE "\..\..\\lib\cypress\ssram\cy7c1380d.vhd,hdl" VALUE "\..\..\\lib\work\debug\debug.vhd,hdl" VALUE "\..\..\\lib\work\debug\grtestmod.vhd,hdl" VALUE "\..\..\\lib\work\debug\cpu_disas.vhd,hdl" VALUE "\config.vhd,hdl" VALUE "\ahbrom.vhd,hdl" VALUE "\leon3mp.vhd,hdl" VALUE "\testbench.vhd,hdl" ENDLIST ENDLIST LIST IncludeModuleForSimulation ENDLIST LIST CDBOrder ENDLIST LIST UserCustomizedFileList ENDLIST LIST OpenedFileList DESIGNFLOW: FILE:\leon3mp.vhd,hdl FILE:\ahbrom.vhd,hdl FILE:\config.vhd,hdl FILE:\..\..\\lib\lpp\.\lpp_usb\RWbuf.vhd,hdl FILE:\..\..\\lib\techmap\maps\techbuf.vhd,hdl FILE:\..\..\\lib\gaisler\greth\greth.vhd,hdl FILE:\..\..\\lib\grlib\amba\apbctrl.vhd,hdl FILE:\..\..\\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl FILE:\..\..\\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl FILE:\..\..\\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl ACTIVE_VIEW:10 ENDLIST