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LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\maps\tap.vhd,hdl" STATE="utd" TIME="1309254994" SIZE="6548" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\maps\techbuf.vhd,hdl" STATE="utd" TIME="1309254994" SIZE="4457" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\maps\techmult.vhd,hdl" STATE="utd" TIME="1309254994" SIZE="7034" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\maps\toutpad.vhd,hdl" STATE="utd" TIME="1309254994" SIZE="6172" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\proasic3\buffer_apa3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="2154" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\proasic3\clkgen_proasic3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="6738" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\proasic3\memory_apa3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="17067" LIBRARY="techmap" ENDFILE VALUE "\..\..\lib\techmap\proasic3\tap_proasic3.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="3674" LIBRARY="techmap" ENDFILE VALUE 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"\testbench.vhd,hdl" STATE="utd" TIME="1210769968" SIZE="9095" ENDFILE VALUE "C:\opt\GRLIB\grlib-gpl-1.1.0-b4108\boards\Projet-Blanc-LPP-M7A3P1000\Projet-Blanc-LPP-M7A3P1000.pdc,pdc" STATE="utd" TIME="1319032451" SIZE="5393" IS_READONLY="TRUE" ENDFILE ENDLIST LIST UsedFile ENDLIST LIST NewModulesInfo LIST "leon3mp::work" FILE "\leon3mp.vhd,hdl" LIST ExcludePackageForSynthesis VALUE "\..\..\lib\grlib\stdlib\stdio.vhd,hdl" VALUE "\..\..\lib\grlib\stdlib\testlib.vhd,hdl" VALUE "\..\..\lib\grlib\util\util.vhd,hdl" VALUE "\..\..\lib\grlib\sparc\sparc_disas.vhd,hdl" VALUE "\..\..\lib\grlib\sparc\cpu_disas.vhd,hdl" VALUE "\..\..\lib\grlib\amba\dma2ahb_tp.vhd,hdl" VALUE "\..\..\lib\grlib\amba\amba_tp.vhd,hdl" VALUE "\..\..\lib\synplify\sim\synplify.vhd,hdl" VALUE "\..\..\lib\synplify\sim\synattr.vhd,hdl" VALUE "\..\..\lib\gaisler\ambatest\ahbtbp.vhd,hdl" VALUE "\..\..\lib\gaisler\ambatest\ahbtbm.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\i2c_slave_model.v,hdl" VALUE "\..\..\lib\gaisler\sim\sim.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\sram.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\ata_device.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\sram16.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\phy.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\ahbrep.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\delay_wire.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\spi_flash.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\pwm_check.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\usbsim.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\grusbdcsim.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\grusb_dclsim.vhd,hdl" VALUE "\..\..\lib\gaisler\jtag\jtagtst.vhd,hdl" VALUE "\..\..\lib\fmf\utilities\conversions.vhd,hdl" VALUE "\..\..\lib\fmf\utilities\gen_utils.vhd,hdl" VALUE "\..\..\lib\fmf\flash\flash.vhd,hdl" VALUE "\..\..\lib\fmf\flash\s25fl064a.vhd,hdl" VALUE "\..\..\lib\fmf\flash\m25p80.vhd,hdl" VALUE "\..\..\lib\fmf\fifo\idt7202.vhd,hdl" VALUE "\..\..\lib\gsi\ssram\functions.vhd,hdl" VALUE "\..\..\lib\gsi\ssram\core_burst.vhd,hdl" VALUE "\..\..\lib\gsi\ssram\g880e18bt.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\components.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\package_utility.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\cy7c1354b.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\cy7c1380d.vhd,hdl" VALUE "\..\..\lib\work\debug\debug.vhd,hdl" VALUE "\..\..\lib\work\debug\grtestmod.vhd,hdl" VALUE "\..\..\lib\work\debug\cpu_disas.vhd,hdl" VALUE "\config.vhd,hdl" VALUE "\ahbrom.vhd,hdl" VALUE "\leon3mp.vhd,hdl" VALUE "\testbench.vhd,hdl" ENDLIST LIST ProjectState5.1 LIST Impl1 LiberoState=Post_Synthesis ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST LIST Impl2 LiberoState=Post_Layout ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateSuccess ideDESIGNER(\designer\impl2\leon3mp.adb,adb)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST ENDLIST ENDLIST ENDLIST LIST AssociatedStimulus ENDLIST LIST Other_Association ENDLIST LIST SimulationOptions UseAutomaticDoFile=true IncludeWaveDo=false Type=max RunTime=1000ns Resolution=1ps VsimOpt= EntityName=testbench TopInstanceName=_0 DoFileName= DoFileName2=wave.do DoFileParams= DisplayDUTWave=false LogAllSignals=false DumpVCD=false VCDFileName=power.vcd ENDLIST LIST ModelSimLibPath UseCustomPath=FALSE LibraryPath= ENDLIST LIST GlobalFlowOptions GenerateHDLAfterSynthesis=FALSE GenerateHDLAfterPhySynthesis=FALSE RunDRCAfterSynthesis=FALSE AutoCheckConstraints=TRUE UpdateViewDrawIni=TRUE UpdateModelSimIni=TRUE NoIOMode=FALSE GenerateHDLFromSchematic=TRUE FlashProInputFile=pdb SmartGenCompileReport=T ENDLIST LIST PhySynthesisOptions ENDLIST LIST Profiles NAME="Synplify AE" FUNCTION="Synthesis" TOOL="Synplify" LOCATION="C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\bin\synplify_pro.exe" PARAM="" BATCH=0 EndProfile NAME="ModelSim AE" FUNCTION="Simulation" TOOL="ModelSim" LOCATION="C:\Actel\Libero_v9.1\Model\win32acoem\modelsim.exe" PARAM="" BATCH=0 EndProfile NAME="WFL" FUNCTION="Stimulus" TOOL="WFL" LOCATION="syncad.exe" PARAM="-pwflite" BATCH=0 EndProfile NAME="FlashPro" FUNCTION="Program" TOOL="FlashPro" LOCATION="C:\Actel\Libero_v9.1\Designer\bin\FlashPro.exe" PARAM="" BATCH=0 EndProfile ENDLIST LIST ProjectState5.1 LIST "leon3mp::work" LIST Impl1 LiberoState=Post_Synthesis ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST LIST Impl2 LiberoState=Post_Layout ideSYNTHESIS(\synthesis\leon3mp.edn,syn_edn)=StateSuccess ideDESIGNER(\designer\impl2\leon3mp.adb,adb)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE ENDLIST Used_File_List ENDUsed_File_List ENDLIST ENDLIST ENDLIST LIST ExcludePackageForSimulation ENDLIST LIST ExcludePackageForSynthesis LIST leon3mp VALUE "\..\..\lib\grlib\stdlib\stdio.vhd,hdl" VALUE "\..\..\lib\grlib\stdlib\testlib.vhd,hdl" VALUE "\..\..\lib\grlib\util\util.vhd,hdl" VALUE "\..\..\lib\grlib\sparc\sparc_disas.vhd,hdl" VALUE "\..\..\lib\grlib\sparc\cpu_disas.vhd,hdl" VALUE "\..\..\lib\grlib\amba\dma2ahb_tp.vhd,hdl" VALUE "\..\..\lib\grlib\amba\amba_tp.vhd,hdl" VALUE "\..\..\lib\synplify\sim\synplify.vhd,hdl" VALUE "\..\..\lib\synplify\sim\synattr.vhd,hdl" VALUE "\..\..\lib\gaisler\ambatest\ahbtbp.vhd,hdl" VALUE "\..\..\lib\gaisler\ambatest\ahbtbm.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\i2c_slave_model.v,hdl" VALUE "\..\..\lib\gaisler\sim\sim.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\sram.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\ata_device.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\sram16.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\phy.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\ahbrep.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\delay_wire.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\spi_flash.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\pwm_check.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\usbsim.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\grusbdcsim.vhd,hdl" VALUE "\..\..\lib\gaisler\sim\grusb_dclsim.vhd,hdl" VALUE "\..\..\lib\gaisler\jtag\jtagtst.vhd,hdl" VALUE "\..\..\lib\fmf\utilities\conversions.vhd,hdl" VALUE "\..\..\lib\fmf\utilities\gen_utils.vhd,hdl" VALUE "\..\..\lib\fmf\flash\flash.vhd,hdl" VALUE "\..\..\lib\fmf\flash\s25fl064a.vhd,hdl" VALUE "\..\..\lib\fmf\flash\m25p80.vhd,hdl" VALUE "\..\..\lib\fmf\fifo\idt7202.vhd,hdl" VALUE "\..\..\lib\gsi\ssram\functions.vhd,hdl" VALUE "\..\..\lib\gsi\ssram\core_burst.vhd,hdl" VALUE "\..\..\lib\gsi\ssram\g880e18bt.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\components.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\package_utility.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\cy7c1354b.vhd,hdl" VALUE "\..\..\lib\cypress\ssram\cy7c1380d.vhd,hdl" VALUE "\..\..\lib\work\debug\debug.vhd,hdl" VALUE "\..\..\lib\work\debug\grtestmod.vhd,hdl" VALUE "\..\..\lib\work\debug\cpu_disas.vhd,hdl" VALUE "\config.vhd,hdl" VALUE "\ahbrom.vhd,hdl" VALUE "\leon3mp.vhd,hdl" VALUE "\testbench.vhd,hdl" ENDLIST ENDLIST LIST IncludeModuleForSimulation ENDLIST LIST CDBOrder ENDLIST LIST UserCustomizedFileList ENDLIST LIST OpenedFileList DESIGNFLOW: FILE:\leon3mp.vhd,hdl FILE:\config.vhd,hdl ACTIVE_VIEW:1 ENDLIST