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Updated SOLO_LFR_LFR-FM designs...
Alexis Jeandet -
r668:f6e57cae6ba0 SOLO_LFR_01-5B (LFR-FM) default draft
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@@ -450,14 +450,11 BEGIN -- beh
450 pirq_ms => 6,
450 pirq_ms => 6,
451 pirq_wfp => 14,
451 pirq_wfp => 14,
452 hindex => 2,
452 hindex => 2,
453 top_lfr_version => X"030159", -- aa.bb.cc version
453 top_lfr_version => LPP_LFR_BOARD_LFR_FM & X"015B",
454 -- AA : BOARD NUMBER
455 -- 0 => MINI_LFR
456 -- 1 => EM
457 -- 2 => EQM (with A3PE3000)
458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
454 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
459 RTL_DESIGN_LIGHT =>0,
455 RTL_DESIGN_LIGHT =>0,
460 WINDOWS_HAANNING_PARAM_SIZE => 15)
456 WINDOWS_HAANNING_PARAM_SIZE => 15,
457 DATA_SHAPING_SATURATION => 1)
461 PORT MAP (
458 PORT MAP (
462 clk => clk_25,
459 clk => clk_25,
463 rstn => LFR_rstn,
460 rstn => LFR_rstn,
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@@ -17,7 +17,7 VHDLSYNFILES=LFR-FM.vhd
17 VHDLSIMFILES=
17 VHDLSIMFILES=
18
18
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_FM_RTAX.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_FM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_FM_RTAX_layout.sdc
21
21
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
23 CLEAN=soft-clean
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