HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r1:d63cd96dab77

aded GRLIB Automated patcher

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.hgignore created 644 +15 0

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	1	# use glob syntax.
	2	syntax: glob
	3
	4	*.tex
	5	*.html
	6	log
	7	*.png
	8	*.dot
	9	*.css
	10	*.md5
	11	*.eps
	12	*.pdf
	13	*.toc
	14	*~
	15

Makefile created 644 +36 0

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	1	all: help
	2
	3	help:
	4	@echo
	5	@echo " batch targets:"
	6	@echo
	7	@echo " make Patch-GRLIB : install library into $(GRLIB)"
	8	@echo " make dist : create a tar file for using into an other computer"
	9	@echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer"
	10	@echo " make allGPL : add a GPL HEADER in all vhdl Files"
	11	@echo " make init : add a GPL HEADER in all vhdl Files, init all files"
	12	@echo " make doc : make documentation for VHDL IPs"
	13	@echo
	14
	15	allGPL:
	16	sh lib/GPL_Patcher.sh -R
	17
	18	init: allGPL
	19	sh lib/lpp/vhdlsynPatcher.sh
	20	sh lib/lpp/makeDirs.sh lib/lpp
	21
	22
	23	Patch-GRLIB: init doc
	24	sh patch.sh $(GRLIB)
	25
	26
	27	dist: init
	28	tar -cvzf ./../lpp-lib.tgz ./../lib_lpp/*
	29
	30	Patched-dist: Patch-GRLIB
	31	tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
	32
	33
	34	doc:
	35	doxygen lib/lpp/Doxyfile
	36	make lib/lpp/doc/latex

TODO created 644 +4 0

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	1	patch VENDOR Ids
	2	Write a README
	3	add app_simple_diode
	4	add LCD_16x2_DRIVER.vhd

boards/patchboards.sh created 644 +48 0

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	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP's GRLIB Boards PATCHER "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '----------------------------------------------------------------------------------------
	7	This file is a part of the LPP VHDL IP LIBRARY
	8	Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	----------------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28
	29	LPP_LIBPATH=`pwd -L`
	30
	31	echo "Patching boards..."
	32	echo
	33	echo
	34
	35	#COPY
	36	echo "Copy boards Files..."
	37	cp -R -v $LPP_LIBPATH/boards $1
	38	echo
	39	echo
	40	echo
	41
	42
	43	#CLEAN
	44	echo "CLEANING .."
	45	rm -v $1/boards/*.sh
	46	echo
	47	echo
	48	echo

designs/patchdesigns.sh created 644 +49 0

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	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP's GRLIB Designs PATCHER "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '----------------------------------------------------------------------------------------
	7	This file is a part of the LPP VHDL IP LIBRARY
	8	Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	----------------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28
	29	LPP_LIBPATH=`pwd -L`
	30
	31	echo "Patching designs..."
	32	echo
	33	echo
	34
	35	#COPY
	36	echo "Copy designs Files..."
	37	cp -R -v $LPP_LIBPATH/designs $1
	38	echo
	39	echo
	40	echo
	41
	42
	43	#CLEAN
	44	echo "CLEANING .."
	45	rm -v $1/designs/*.sh
	46	echo
	47	echo
	48	echo
	49

lib/GPL_HEADER created 644 +18 0

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	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------

lib/GPL_Patcher.sh created 644 +72 0

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	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP GPL PATCHER "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '----------------------------------------------------------------------------------------
	7	This file is a part of the LPP VHDL IP LIBRARY
	8	Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	----------------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28	# Absolute path to this script. /home/user/bin/foo.sh
	29	#SCRIPT=$(readlink -f $0)
	30	# Absolute path this script is in. /home/user/bin
	31
	32	#LPP_PATCHPATH=`dirname $SCRIPT`
	33	LPP_PATCHPATH=`pwd -L`
	34
	35
	36	case $1 in
	37	-R \| --recursive )
	38	for file in $(find . -name '*.vhd')
	39	do
	40	if(grep -q "This program is free software" $file); then
	41	echo "$file already contains GPL HEADER"
	42	else
	43	echo "Modifying file : $file"
	44	more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
	45	cat $file >> $file.tmp
	46	mv $file.tmp $file
	47	fi
	48	done
	49	;;
	50	-h \| --help \| --h \| -help)
	51	echo 'Help:
	52	This script add a GPL HEADER in all vhdl files.
	53
	54	-R or --recurcive:
	55	Analyse recurcively folders starting from $LPP_PATCHPATH'
	56	;;
	57	* )
	58	for file in $(ls *.vhd)
	59	do
	60	if(grep -q "This program is free software" $file); then
	61	echo "$file already contains GPL HEADER"
	62	else
	63	echo "Modifying file : $file"
	64	more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
	65	cat $file >> $file.tmp
	66	mv $file.tmp $file
	67	fi
	68	done
	69	;;
	70
	71	esac
	72

lib/lpp/COPYING created 644 +674 0

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		1	GNU GENERAL PUBLIC LICENSE
		2	Version 3, 29 June 2007
		3
		4	Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
		5	Everyone is permitted to copy and distribute verbatim copies
		6	of this license document, but changing it is not allowed.
		7
		8	Preamble
		9
		10	The GNU General Public License is a free, copyleft license for
		11	software and other kinds of works.
		12
		13	The licenses for most software and other practical works are designed
		14	to take away your freedom to share and change the works. By contrast,
		15	the GNU General Public License is intended to guarantee your freedom to
		16	share and change all versions of a program--to make sure it remains free
		17	software for all its users. We, the Free Software Foundation, use the
		18	GNU General Public License for most of our software; it applies also to
		19	any other work released this way by its authors. You can apply it to
		20	your programs, too.
		21
		22	When we speak of free software, we are referring to freedom, not
		23	price. Our General Public Licenses are designed to make sure that you
		24	have the freedom to distribute copies of free software (and charge for
		25	them if you wish), that you receive source code or can get it if you
		26	want it, that you can change the software or use pieces of it in new
		27	free programs, and that you know you can do these things.
		28
		29	To protect your rights, we need to prevent others from denying you
		30	these rights or asking you to surrender the rights. Therefore, you have
		31	certain responsibilities if you distribute copies of the software, or if
		32	you modify it: responsibilities to respect the freedom of others.
		33
		34	For example, if you distribute copies of such a program, whether
		35	gratis or for a fee, you must pass on to the recipients the same
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		38	know their rights.
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		40	Developers that use the GNU GPL protect your rights with two steps:
		41	(1) assert copyright on the software, and (2) offer you this License
		42	giving you legal permission to copy, distribute and/or modify it.
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		44	For the developers' and authors' protection, the GPL clearly explains
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		46	authors' sake, the GPL requires that modified versions be marked as
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		61	Finally, every program is threatened constantly by software patents.
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		68	The precise terms and conditions for copying, distribution and
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		70
		71	TERMS AND CONDITIONS
		72
		73	0. Definitions.
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		75	"This License" refers to version 3 of the GNU General Public License.
		76
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		321	User Product is transferred to the recipient in perpetuity or for a
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		323	Corresponding Source conveyed under this section must be accompanied
		324	by the Installation Information. But this requirement does not apply
		325	if neither you nor any third party retains the ability to install
		326	modified object code on the User Product (for example, the work has
		327	been installed in ROM).
		328
		329	The requirement to provide Installation Information does not include a
		330	requirement to continue to provide support service, warranty, or updates
		331	for a work that has been modified or installed by the recipient, or for
		332	the User Product in which it has been modified or installed. Access to a
		333	network may be denied when the modification itself materially and
		334	adversely affects the operation of the network or violates the rules and
		335	protocols for communication across the network.
		336
		337	Corresponding Source conveyed, and Installation Information provided,
		338	in accord with this section must be in a format that is publicly
		339	documented (and with an implementation available to the public in
		340	source code form), and must require no special password or key for
		341	unpacking, reading or copying.
		342
		343	7. Additional Terms.
		344
		345	"Additional permissions" are terms that supplement the terms of this
		346	License by making exceptions from one or more of its conditions.
		347	Additional permissions that are applicable to the entire Program shall
		348	be treated as though they were included in this License, to the extent
		349	that they are valid under applicable law. If additional permissions
		350	apply only to part of the Program, that part may be used separately
		351	under those permissions, but the entire Program remains governed by
		352	this License without regard to the additional permissions.
		353
		354	When you convey a copy of a covered work, you may at your option
		355	remove any additional permissions from that copy, or from any part of
		356	it. (Additional permissions may be written to require their own
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		358	additional permissions on material, added by you to a covered work,
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		361	Notwithstanding any other provision of this License, for material you
		362	add to a covered work, you may (if authorized by the copyright holders of
		363	that material) supplement the terms of this License with terms:
		364
		365	a) Disclaiming warranty or limiting liability differently from the
		366	terms of sections 15 and 16 of this License; or
		367
		368	b) Requiring preservation of specified reasonable legal notices or
		369	author attributions in that material or in the Appropriate Legal
		370	Notices displayed by works containing it; or
		371
		372	c) Prohibiting misrepresentation of the origin of that material, or
		373	requiring that modified versions of such material be marked in
		374	reasonable ways as different from the original version; or
		375
		376	d) Limiting the use for publicity purposes of names of licensors or
		377	authors of the material; or
		378
		379	e) Declining to grant rights under trademark law for use of some
		380	trade names, trademarks, or service marks; or
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		382	f) Requiring indemnification of licensors and authors of that
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		388	All other non-permissive additional terms are considered "further
		389	restrictions" within the meaning of section 10. If the Program as you
		390	received it, or any part of it, contains a notice stating that it is
		391	governed by this License along with a term that is a further
		392	restriction, you may remove that term. If a license document contains
		393	a further restriction but permits relicensing or conveying under this
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		398	If you add terms to a covered work in accord with this section, you
		399	must place, in the relevant source files, a statement of the
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		401	where to find the applicable terms.
		402
		403	Additional terms, permissive or non-permissive, may be stated in the
		404	form of a separately written license, or stated as exceptions;
		405	the above requirements apply either way.
		406
		407	8. Termination.
		408
		409	You may not propagate or modify a covered work except as expressly
		410	provided under this License. Any attempt otherwise to propagate or
		411	modify it is void, and will automatically terminate your rights under
		412	this License (including any patent licenses granted under the third
		413	paragraph of section 11).
		414
		415	However, if you cease all violation of this License, then your
		416	license from a particular copyright holder is reinstated (a)
		417	provisionally, unless and until the copyright holder explicitly and
		418	finally terminates your license, and (b) permanently, if the copyright
		419	holder fails to notify you of the violation by some reasonable means
		420	prior to 60 days after the cessation.
		421
		422	Moreover, your license from a particular copyright holder is
		423	reinstated permanently if the copyright holder notifies you of the
		424	violation by some reasonable means, this is the first time you have
		425	received notice of violation of this License (for any work) from that
		426	copyright holder, and you cure the violation prior to 30 days after
		427	your receipt of the notice.
		428
		429	Termination of your rights under this section does not terminate the
		430	licenses of parties who have received copies or rights from you under
		431	this License. If your rights have been terminated and not permanently
		432	reinstated, you do not qualify to receive new licenses for the same
		433	material under section 10.
		434
		435	9. Acceptance Not Required for Having Copies.
		436
		437	You are not required to accept this License in order to receive or
		438	run a copy of the Program. Ancillary propagation of a covered work
		439	occurring solely as a consequence of using peer-to-peer transmission
		440	to receive a copy likewise does not require acceptance. However,
		441	nothing other than this License grants you permission to propagate or
		442	modify any covered work. These actions infringe copyright if you do
		443	not accept this License. Therefore, by modifying or propagating a
		444	covered work, you indicate your acceptance of this License to do so.
		445
		446	10. Automatic Licensing of Downstream Recipients.
		447
		448	Each time you convey a covered work, the recipient automatically
		449	receives a license from the original licensors, to run, modify and
		450	propagate that work, subject to this License. You are not responsible
		451	for enforcing compliance by third parties with this License.
		452
		453	An "entity transaction" is a transaction transferring control of an
		454	organization, or substantially all assets of one, or subdividing an
		455	organization, or merging organizations. If propagation of a covered
		456	work results from an entity transaction, each party to that
		457	transaction who receives a copy of the work also receives whatever
		458	licenses to the work the party's predecessor in interest had or could
		459	give under the previous paragraph, plus a right to possession of the
		460	Corresponding Source of the work from the predecessor in interest, if
		461	the predecessor has it or can get it with reasonable efforts.
		462
		463	You may not impose any further restrictions on the exercise of the
		464	rights granted or affirmed under this License. For example, you may
		465	not impose a license fee, royalty, or other charge for exercise of
		466	rights granted under this License, and you may not initiate litigation
		467	(including a cross-claim or counterclaim in a lawsuit) alleging that
		468	any patent claim is infringed by making, using, selling, offering for
		469	sale, or importing the Program or any portion of it.
		470
		471	11. Patents.
		472
		473	A "contributor" is a copyright holder who authorizes use under this
		474	License of the Program or a work on which the Program is based. The
		475	work thus licensed is called the contributor's "contributor version".
		476
		477	A contributor's "essential patent claims" are all patent claims
		478	owned or controlled by the contributor, whether already acquired or
		479	hereafter acquired, that would be infringed by some manner, permitted
		480	by this License, of making, using, or selling its contributor version,
		481	but do not include claims that would be infringed only as a
		482	consequence of further modification of the contributor version. For
		483	purposes of this definition, "control" includes the right to grant
		484	patent sublicenses in a manner consistent with the requirements of
		485	this License.
		486
		487	Each contributor grants you a non-exclusive, worldwide, royalty-free
		488	patent license under the contributor's essential patent claims, to
		489	make, use, sell, offer for sale, import and otherwise run, modify and
		490	propagate the contents of its contributor version.
		491
		492	In the following three paragraphs, a "patent license" is any express
		493	agreement or commitment, however denominated, not to enforce a patent
		494	(such as an express permission to practice a patent or covenant not to
		495	sue for patent infringement). To "grant" such a patent license to a
		496	party means to make such an agreement or commitment not to enforce a
		497	patent against the party.
		498
		499	If you convey a covered work, knowingly relying on a patent license,
		500	and the Corresponding Source of the work is not available for anyone
		501	to copy, free of charge and under the terms of this License, through a
		502	publicly available network server or other readily accessible means,
		503	then you must either (1) cause the Corresponding Source to be so
		504	available, or (2) arrange to deprive yourself of the benefit of the
		505	patent license for this particular work, or (3) arrange, in a manner
		506	consistent with the requirements of this License, to extend the patent
		507	license to downstream recipients. "Knowingly relying" means you have
		508	actual knowledge that, but for the patent license, your conveying the
		509	covered work in a country, or your recipient's use of the covered work
		510	in a country, would infringe one or more identifiable patents in that
		511	country that you have reason to believe are valid.
		512
		513	If, pursuant to or in connection with a single transaction or
		514	arrangement, you convey, or propagate by procuring conveyance of, a
		515	covered work, and grant a patent license to some of the parties
		516	receiving the covered work authorizing them to use, propagate, modify
		517	or convey a specific copy of the covered work, then the patent license
		518	you grant is automatically extended to all recipients of the covered
		519	work and works based on it.
		520
		521	A patent license is "discriminatory" if it does not include within
		522	the scope of its coverage, prohibits the exercise of, or is
		523	conditioned on the non-exercise of one or more of the rights that are
		524	specifically granted under this License. You may not convey a covered
		525	work if you are a party to an arrangement with a third party that is
		526	in the business of distributing software, under which you make payment
		527	to the third party based on the extent of your activity of conveying
		528	the work, and under which the third party grants, to any of the
		529	parties who would receive the covered work from you, a discriminatory
		530	patent license (a) in connection with copies of the covered work
		531	conveyed by you (or copies made from those copies), or (b) primarily
		532	for and in connection with specific products or compilations that
		533	contain the covered work, unless you entered into that arrangement,
		534	or that patent license was granted, prior to 28 March 2007.
		535
		536	Nothing in this License shall be construed as excluding or limiting
		537	any implied license or other defenses to infringement that may
		538	otherwise be available to you under applicable patent law.
		539
		540	12. No Surrender of Others' Freedom.
		541
		542	If conditions are imposed on you (whether by court order, agreement or
		543	otherwise) that contradict the conditions of this License, they do not
		544	excuse you from the conditions of this License. If you cannot convey a
		545	covered work so as to satisfy simultaneously your obligations under this
		546	License and any other pertinent obligations, then as a consequence you may
		547	not convey it at all. For example, if you agree to terms that obligate you
		548	to collect a royalty for further conveying from those to whom you convey
		549	the Program, the only way you could satisfy both those terms and this
		550	License would be to refrain entirely from conveying the Program.
		551
		552	13. Use with the GNU Affero General Public License.
		553
		554	Notwithstanding any other provision of this License, you have
		555	permission to link or combine any covered work with a work licensed
		556	under version 3 of the GNU Affero General Public License into a single
		557	combined work, and to convey the resulting work. The terms of this
		558	License will continue to apply to the part which is the covered work,
		559	but the special requirements of the GNU Affero General Public License,
		560	section 13, concerning interaction through a network will apply to the
		561	combination as such.
		562
		563	14. Revised Versions of this License.
		564
		565	The Free Software Foundation may publish revised and/or new versions of
		566	the GNU General Public License from time to time. Such new versions will
		567	be similar in spirit to the present version, but may differ in detail to
		568	address new problems or concerns.
		569
		570	Each version is given a distinguishing version number. If the
		571	Program specifies that a certain numbered version of the GNU General
		572	Public License "or any later version" applies to it, you have the
		573	option of following the terms and conditions either of that numbered
		574	version or of any later version published by the Free Software
		575	Foundation. If the Program does not specify a version number of the
		576	GNU General Public License, you may choose any version ever published
		577	by the Free Software Foundation.
		578
		579	If the Program specifies that a proxy can decide which future
		580	versions of the GNU General Public License can be used, that proxy's
		581	public statement of acceptance of a version permanently authorizes you
		582	to choose that version for the Program.
		583
		584	Later license versions may give you additional or different
		585	permissions. However, no additional obligations are imposed on any
		586	author or copyright holder as a result of your choosing to follow a
		587	later version.
		588
		589	15. Disclaimer of Warranty.
		590
		591	THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
		592	APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
		593	HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
		594	OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
		595	THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
		596	PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
		597	IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
		598	ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
		599
		600	16. Limitation of Liability.
		601
		602	IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
		603	WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
		604	THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
		605	GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
		606	USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
		607	DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
		608	PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
		609	EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
		610	SUCH DAMAGES.
		611
		612	17. Interpretation of Sections 15 and 16.
		613
		614	If the disclaimer of warranty and limitation of liability provided
		615	above cannot be given local legal effect according to their terms,
		616	reviewing courts shall apply local law that most closely approximates
		617	an absolute waiver of all civil liability in connection with the
		618	Program, unless a warranty or assumption of liability accompanies a
		619	copy of the Program in return for a fee.
		620
		621	END OF TERMS AND CONDITIONS
		622
		623	How to Apply These Terms to Your New Programs
		624
		625	If you develop a new program, and you want it to be of the greatest
		626	possible use to the public, the best way to achieve this is to make it
		627	free software which everyone can redistribute and change under these terms.
		628
		629	To do so, attach the following notices to the program. It is safest
		630	to attach them to the start of each source file to most effectively
		631	state the exclusion of warranty; and each file should have at least
		632	the "copyright" line and a pointer to where the full notice is found.
		633
		634	<one line to give the program's name and a brief idea of what it does.>
		635	Copyright (C) <year> <name of author>
		636
		637	This program is free software: you can redistribute it and/or modify
		638	it under the terms of the GNU General Public License as published by
		639	the Free Software Foundation, either version 3 of the License, or
		640	(at your option) any later version.
		641
		642	This program is distributed in the hope that it will be useful,
		643	but WITHOUT ANY WARRANTY; without even the implied warranty of
		644	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		645	GNU General Public License for more details.
		646
		647	You should have received a copy of the GNU General Public License
		648	along with this program. If not, see <http://www.gnu.org/licenses/>.
		649
		650	Also add information on how to contact you by electronic and paper mail.
		651
		652	If the program does terminal interaction, make it output a short
		653	notice like this when it starts in an interactive mode:
		654
		655	<program> Copyright (C) <year> <name of author>
		656	This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
		657	This is free software, and you are welcome to redistribute it
		658	under certain conditions; type `show c' for details.
		659
		660	The hypothetical commands `show w' and `show c' should show the appropriate
		661	parts of the General Public License. Of course, your program's commands
		662	might be different; for a GUI interface, you would use an "about box".
		663
		664	You should also get your employer (if you work as a programmer) or school,
		665	if any, to sign a "copyright disclaimer" for the program, if necessary.
		666	For more information on this, and how to apply and follow the GNU GPL, see
		667	<http://www.gnu.org/licenses/>.
		668
		669	The GNU General Public License does not permit incorporating your program
		670	into proprietary programs. If your program is a subroutine library, you
		671	may consider it more useful to permit linking proprietary applications with
		672	the library. If this is what you want to do, use the GNU Lesser General
		673	Public License instead of this License. But first, please read
		674	<http://www.gnu.org/philosophy/why-not-lgpl.html>.

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		1	# Doxyfile 1.7.1
		2
		3	# This file describes the settings to be used by the documentation system
		4	# doxygen (www.doxygen.org) for a project
		5	#
		6	# All text after a hash (#) is considered a comment and will be ignored
		7	# The format is:
		8	# TAG = value [value, ...]
		9	# For lists items can also be appended using:
		10	# TAG += value [value, ...]
		11	# Values that contain spaces should be placed between quotes (" ")
		12
		13	#---------------------------------------------------------------------------
		14	# Project related configuration options
		15	#---------------------------------------------------------------------------
		16
		17	# This tag specifies the encoding used for all characters in the config file
		18	# that follow. The default is UTF-8 which is also the encoding used for all
		19	# text before the first occurrence of this tag. Doxygen uses libiconv (or the
		20	# iconv built into libc) for the transcoding. See
		21	# http://www.gnu.org/software/libiconv for the list of possible encodings.
		22
		23	DOXYFILE_ENCODING = UTF-8
		24
		25	# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
		26	# by quotes) that should identify the project.
		27
		28	PROJECT_NAME = lib-lpp
		29
		30	# The PROJECT_NUMBER tag can be used to enter a project or revision number.
		31	# This could be handy for archiving the generated documentation or
		32	# if some version control system is used.
		33
		34	PROJECT_NUMBER = 1.0
		35
		36	# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
		37	# base path where the generated documentation will be put.
		38	# If a relative path is entered, it will be relative to the location
		39	# where doxygen was started. If left blank the current directory will be used.
		40
		41	OUTPUT_DIRECTORY = /opt/GRLIB/lib_lpp/lib/lpp/doc
		42
		43	# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
		44	# 4096 sub-directories (in 2 levels) under the output directory of each output
		45	# format and will distribute the generated files over these directories.
		46	# Enabling this option can be useful when feeding doxygen a huge amount of
		47	# source files, where putting all generated files in the same directory would
		48	# otherwise cause performance problems for the file system.
		49
		50	CREATE_SUBDIRS = NO
		51
		52	# The OUTPUT_LANGUAGE tag is used to specify the language in which all
		53	# documentation generated by doxygen is written. Doxygen will use this
		54	# information to generate all constant output in the proper language.
		55	# The default language is English, other supported languages are:
		56	# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
		57	# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
		58	# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
		59	# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
		60	# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
		61	# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
		62
		63	OUTPUT_LANGUAGE = English
		64
		65	# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
		66	# include brief member descriptions after the members that are listed in
		67	# the file and class documentation (similar to JavaDoc).
		68	# Set to NO to disable this.
		69
		70	BRIEF_MEMBER_DESC = YES
		71
		72	# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
		73	# the brief description of a member or function before the detailed description.
		74	# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
		75	# brief descriptions will be completely suppressed.
		76
		77	REPEAT_BRIEF = YES
		78
		79	# This tag implements a quasi-intelligent brief description abbreviator
		80	# that is used to form the text in various listings. Each string
		81	# in this list, if found as the leading text of the brief description, will be
		82	# stripped from the text and the result after processing the whole list, is
		83	# used as the annotated text. Otherwise, the brief description is used as-is.
		84	# If left blank, the following values are used ("$name" is automatically
		85	# replaced with the name of the entity): "The $name class" "The $name widget"
		86	# "The $name file" "is" "provides" "specifies" "contains"
		87	# "represents" "a" "an" "the"
		88
		89	ABBREVIATE_BRIEF = "The $name class" \
		90	"The $name widget" \
		91	"The $name file" \
		92	is \
		93	provides \
		94	specifies \
		95	contains \
		96	represents \
		97	a \
		98	an \
		99	the
		100
		101	# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
		102	# Doxygen will generate a detailed section even if there is only a brief
		103	# description.
		104
		105	ALWAYS_DETAILED_SEC = NO
		106
		107	# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
		108	# inherited members of a class in the documentation of that class as if those
		109	# members were ordinary class members. Constructors, destructors and assignment
		110	# operators of the base classes will not be shown.
		111
		112	INLINE_INHERITED_MEMB = NO
		113
		114	# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
		115	# path before files name in the file list and in the header files. If set
		116	# to NO the shortest path that makes the file name unique will be used.
		117
		118	FULL_PATH_NAMES = YES
		119
		120	# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
		121	# can be used to strip a user-defined part of the path. Stripping is
		122	# only done if one of the specified strings matches the left-hand part of
		123	# the path. The tag can be used to show relative paths in the file list.
		124	# If left blank the directory from which doxygen is run is used as the
		125	# path to strip.
		126
		127	STRIP_FROM_PATH =
		128
		129	# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
		130	# the path mentioned in the documentation of a class, which tells
		131	# the reader which header file to include in order to use a class.
		132	# If left blank only the name of the header file containing the class
		133	# definition is used. Otherwise one should specify the include paths that
		134	# are normally passed to the compiler using the -I flag.
		135
		136	STRIP_FROM_INC_PATH =
		137
		138	# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
		139	# (but less readable) file names. This can be useful is your file systems
		140	# doesn't support long names like on DOS, Mac, or CD-ROM.
		141
		142	SHORT_NAMES = NO
		143
		144	# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
		145	# will interpret the first line (until the first dot) of a JavaDoc-style
		146	# comment as the brief description. If set to NO, the JavaDoc
		147	# comments will behave just like regular Qt-style comments
		148	# (thus requiring an explicit @brief command for a brief description.)
		149
		150	JAVADOC_AUTOBRIEF = NO
		151
		152	# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
		153	# interpret the first line (until the first dot) of a Qt-style
		154	# comment as the brief description. If set to NO, the comments
		155	# will behave just like regular Qt-style comments (thus requiring
		156	# an explicit \brief command for a brief description.)
		157
		158	QT_AUTOBRIEF = NO
		159
		160	# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
		161	# treat a multi-line C++ special comment block (i.e. a block of //! or ///
		162	# comments) as a brief description. This used to be the default behaviour.
		163	# The new default is to treat a multi-line C++ comment block as a detailed
		164	# description. Set this tag to YES if you prefer the old behaviour instead.
		165
		166	MULTILINE_CPP_IS_BRIEF = NO
		167
		168	# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
		169	# member inherits the documentation from any documented member that it
		170	# re-implements.
		171
		172	INHERIT_DOCS = YES
		173
		174	# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
		175	# a new page for each member. If set to NO, the documentation of a member will
		176	# be part of the file/class/namespace that contains it.
		177
		178	SEPARATE_MEMBER_PAGES = NO
		179
		180	# The TAB_SIZE tag can be used to set the number of spaces in a tab.
		181	# Doxygen uses this value to replace tabs by spaces in code fragments.
		182
		183	TAB_SIZE = 8
		184
		185	# This tag can be used to specify a number of aliases that acts
		186	# as commands in the documentation. An alias has the form "name=value".
		187	# For example adding "sideeffect=\par Side Effects:\n" will allow you to
		188	# put the command \sideeffect (or @sideeffect) in the documentation, which
		189	# will result in a user-defined paragraph with heading "Side Effects:".
		190	# You can put \n's in the value part of an alias to insert newlines.
		191
		192	ALIASES =
		193
		194	# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
		195	# sources only. Doxygen will then generate output that is more tailored for C.
		196	# For instance, some of the names that are used will be different. The list
		197	# of all members will be omitted, etc.
		198
		199	OPTIMIZE_OUTPUT_FOR_C = NO
		200
		201	# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
		202	# sources only. Doxygen will then generate output that is more tailored for
		203	# Java. For instance, namespaces will be presented as packages, qualified
		204	# scopes will look different, etc.
		205
		206	OPTIMIZE_OUTPUT_JAVA = NO
		207
		208	# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
		209	# sources only. Doxygen will then generate output that is more tailored for
		210	# Fortran.
		211
		212	OPTIMIZE_FOR_FORTRAN = NO
		213
		214	# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
		215	# sources. Doxygen will then generate output that is tailored for
		216	# VHDL.
		217
		218	OPTIMIZE_OUTPUT_VHDL = YES
		219
		220	# Doxygen selects the parser to use depending on the extension of the files it
		221	# parses. With this tag you can assign which parser to use for a given extension.
		222	# Doxygen has a built-in mapping, but you can override or extend it using this
		223	# tag. The format is ext=language, where ext is a file extension, and language
		224	# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
		225	# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
		226	# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
		227	# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
		228	# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
		229
		230	EXTENSION_MAPPING =
		231
		232	# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
		233	# to include (a tag file for) the STL sources as input, then you should
		234	# set this tag to YES in order to let doxygen match functions declarations and
		235	# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
		236	# func(std::string) {}). This also make the inheritance and collaboration
		237	# diagrams that involve STL classes more complete and accurate.
		238
		239	BUILTIN_STL_SUPPORT = NO
		240
		241	# If you use Microsoft's C++/CLI language, you should set this option to YES to
		242	# enable parsing support.
		243
		244	CPP_CLI_SUPPORT = NO
		245
		246	# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
		247	# Doxygen will parse them like normal C++ but will assume all classes use public
		248	# instead of private inheritance when no explicit protection keyword is present.
		249
		250	SIP_SUPPORT = NO
		251
		252	# For Microsoft's IDL there are propget and propput attributes to indicate getter
		253	# and setter methods for a property. Setting this option to YES (the default)
		254	# will make doxygen to replace the get and set methods by a property in the
		255	# documentation. This will only work if the methods are indeed getting or
		256	# setting a simple type. If this is not the case, or you want to show the
		257	# methods anyway, you should set this option to NO.
		258
		259	IDL_PROPERTY_SUPPORT = YES
		260
		261	# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
		262	# tag is set to YES, then doxygen will reuse the documentation of the first
		263	# member in the group (if any) for the other members of the group. By default
		264	# all members of a group must be documented explicitly.
		265
		266	DISTRIBUTE_GROUP_DOC = NO
		267
		268	# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
		269	# the same type (for instance a group of public functions) to be put as a
		270	# subgroup of that type (e.g. under the Public Functions section). Set it to
		271	# NO to prevent subgrouping. Alternatively, this can be done per class using
		272	# the \nosubgrouping command.
		273
		274	SUBGROUPING = YES
		275
		276	# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
		277	# is documented as struct, union, or enum with the name of the typedef. So
		278	# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
		279	# with name TypeT. When disabled the typedef will appear as a member of a file,
		280	# namespace, or class. And the struct will be named TypeS. This can typically
		281	# be useful for C code in case the coding convention dictates that all compound
		282	# types are typedef'ed and only the typedef is referenced, never the tag name.
		283
		284	TYPEDEF_HIDES_STRUCT = NO
		285
		286	# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
		287	# determine which symbols to keep in memory and which to flush to disk.
		288	# When the cache is full, less often used symbols will be written to disk.
		289	# For small to medium size projects (<1000 input files) the default value is
		290	# probably good enough. For larger projects a too small cache size can cause
		291	# doxygen to be busy swapping symbols to and from disk most of the time
		292	# causing a significant performance penality.
		293	# If the system has enough physical memory increasing the cache will improve the
		294	# performance by keeping more symbols in memory. Note that the value works on
		295	# a logarithmic scale so increasing the size by one will rougly double the
		296	# memory usage. The cache size is given by this formula:
		297	# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
		298	# corresponding to a cache size of 2^16 = 65536 symbols
		299
		300	SYMBOL_CACHE_SIZE = 0
		301
		302	#---------------------------------------------------------------------------
		303	# Build related configuration options
		304	#---------------------------------------------------------------------------
		305
		306	# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
		307	# documentation are documented, even if no documentation was available.
		308	# Private class members and static file members will be hidden unless
		309	# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
		310
		311	EXTRACT_ALL = YES
		312
		313	# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
		314	# will be included in the documentation.
		315
		316	EXTRACT_PRIVATE = NO
		317
		318	# If the EXTRACT_STATIC tag is set to YES all static members of a file
		319	# will be included in the documentation.
		320
		321	EXTRACT_STATIC = NO
		322
		323	# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
		324	# defined locally in source files will be included in the documentation.
		325	# If set to NO only classes defined in header files are included.
		326
		327	EXTRACT_LOCAL_CLASSES = YES
		328
		329	# This flag is only useful for Objective-C code. When set to YES local
		330	# methods, which are defined in the implementation section but not in
		331	# the interface are included in the documentation.
		332	# If set to NO (the default) only methods in the interface are included.
		333
		334	EXTRACT_LOCAL_METHODS = NO
		335
		336	# If this flag is set to YES, the members of anonymous namespaces will be
		337	# extracted and appear in the documentation as a namespace called
		338	# 'anonymous_namespace{file}', where file will be replaced with the base
		339	# name of the file that contains the anonymous namespace. By default
		340	# anonymous namespace are hidden.
		341
		342	EXTRACT_ANON_NSPACES = NO
		343
		344	# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
		345	# undocumented members of documented classes, files or namespaces.
		346	# If set to NO (the default) these members will be included in the
		347	# various overviews, but no documentation section is generated.
		348	# This option has no effect if EXTRACT_ALL is enabled.
		349
		350	HIDE_UNDOC_MEMBERS = NO
		351
		352	# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
		353	# undocumented classes that are normally visible in the class hierarchy.
		354	# If set to NO (the default) these classes will be included in the various
		355	# overviews. This option has no effect if EXTRACT_ALL is enabled.
		356
		357	HIDE_UNDOC_CLASSES = NO
		358
		359	# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
		360	# friend (class\|struct\|union) declarations.
		361	# If set to NO (the default) these declarations will be included in the
		362	# documentation.
		363
		364	HIDE_FRIEND_COMPOUNDS = NO
		365
		366	# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
		367	# documentation blocks found inside the body of a function.
		368	# If set to NO (the default) these blocks will be appended to the
		369	# function's detailed documentation block.
		370
		371	HIDE_IN_BODY_DOCS = NO
		372
		373	# The INTERNAL_DOCS tag determines if documentation
		374	# that is typed after a \internal command is included. If the tag is set
		375	# to NO (the default) then the documentation will be excluded.
		376	# Set it to YES to include the internal documentation.
		377
		378	INTERNAL_DOCS = NO
		379
		380	# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
		381	# file names in lower-case letters. If set to YES upper-case letters are also
		382	# allowed. This is useful if you have classes or files whose names only differ
		383	# in case and if your file system supports case sensitive file names. Windows
		384	# and Mac users are advised to set this option to NO.
		385
		386	CASE_SENSE_NAMES = NO
		387
		388	# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
		389	# will show members with their full class and namespace scopes in the
		390	# documentation. If set to YES the scope will be hidden.
		391
		392	HIDE_SCOPE_NAMES = NO
		393
		394	# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
		395	# will put a list of the files that are included by a file in the documentation
		396	# of that file.
		397
		398	SHOW_INCLUDE_FILES = YES
		399
		400	# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
		401	# will list include files with double quotes in the documentation
		402	# rather than with sharp brackets.
		403
		404	FORCE_LOCAL_INCLUDES = NO
		405
		406	# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
		407	# is inserted in the documentation for inline members.
		408
		409	INLINE_INFO = YES
		410
		411	# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
		412	# will sort the (detailed) documentation of file and class members
		413	# alphabetically by member name. If set to NO the members will appear in
		414	# declaration order.
		415
		416	SORT_MEMBER_DOCS = YES
		417
		418	# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
		419	# brief documentation of file, namespace and class members alphabetically
		420	# by member name. If set to NO (the default) the members will appear in
		421	# declaration order.
		422
		423	SORT_BRIEF_DOCS = NO
		424
		425	# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
		426	# will sort the (brief and detailed) documentation of class members so that
		427	# constructors and destructors are listed first. If set to NO (the default)
		428	# the constructors will appear in the respective orders defined by
		429	# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
		430	# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
		431	# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
		432
		433	SORT_MEMBERS_CTORS_1ST = NO
		434
		435	# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
		436	# hierarchy of group names into alphabetical order. If set to NO (the default)
		437	# the group names will appear in their defined order.
		438
		439	SORT_GROUP_NAMES = NO
		440
		441	# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
		442	# sorted by fully-qualified names, including namespaces. If set to
		443	# NO (the default), the class list will be sorted only by class name,
		444	# not including the namespace part.
		445	# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
		446	# Note: This option applies only to the class list, not to the
		447	# alphabetical list.
		448
		449	SORT_BY_SCOPE_NAME = NO
		450
		451	# The GENERATE_TODOLIST tag can be used to enable (YES) or
		452	# disable (NO) the todo list. This list is created by putting \todo
		453	# commands in the documentation.
		454
		455	GENERATE_TODOLIST = YES
		456
		457	# The GENERATE_TESTLIST tag can be used to enable (YES) or
		458	# disable (NO) the test list. This list is created by putting \test
		459	# commands in the documentation.
		460
		461	GENERATE_TESTLIST = YES
		462
		463	# The GENERATE_BUGLIST tag can be used to enable (YES) or
		464	# disable (NO) the bug list. This list is created by putting \bug
		465	# commands in the documentation.
		466
		467	GENERATE_BUGLIST = YES
		468
		469	# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
		470	# disable (NO) the deprecated list. This list is created by putting
		471	# \deprecated commands in the documentation.
		472
		473	GENERATE_DEPRECATEDLIST= YES
		474
		475	# The ENABLED_SECTIONS tag can be used to enable conditional
		476	# documentation sections, marked by \if sectionname ... \endif.
		477
		478	ENABLED_SECTIONS =
		479
		480	# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
		481	# the initial value of a variable or define consists of for it to appear in
		482	# the documentation. If the initializer consists of more lines than specified
		483	# here it will be hidden. Use a value of 0 to hide initializers completely.
		484	# The appearance of the initializer of individual variables and defines in the
		485	# documentation can be controlled using \showinitializer or \hideinitializer
		486	# command in the documentation regardless of this setting.
		487
		488	MAX_INITIALIZER_LINES = 30
		489
		490	# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
		491	# at the bottom of the documentation of classes and structs. If set to YES the
		492	# list will mention the files that were used to generate the documentation.
		493
		494	SHOW_USED_FILES = YES
		495
		496	# If the sources in your project are distributed over multiple directories
		497	# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
		498	# in the documentation. The default is NO.
		499
		500	SHOW_DIRECTORIES = NO
		501
		502	# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
		503	# This will remove the Files entry from the Quick Index and from the
		504	# Folder Tree View (if specified). The default is YES.
		505
		506	SHOW_FILES = YES
		507
		508	# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
		509	# Namespaces page. This will remove the Namespaces entry from the Quick Index
		510	# and from the Folder Tree View (if specified). The default is YES.
		511
		512	SHOW_NAMESPACES = YES
		513
		514	# The FILE_VERSION_FILTER tag can be used to specify a program or script that
		515	# doxygen should invoke to get the current version for each file (typically from
		516	# the version control system). Doxygen will invoke the program by executing (via
		517	# popen()) the command <command> <input-file>, where <command> is the value of
		518	# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file
		519	# provided by doxygen. Whatever the program writes to standard output
		520	# is used as the file version. See the manual for examples.
		521
		522	FILE_VERSION_FILTER =
		523
		524	# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
		525	# by doxygen. The layout file controls the global structure of the generated
		526	# output files in an output format independent way. The create the layout file
		527	# that represents doxygen's defaults, run doxygen with the -l option.
		528	# You can optionally specify a file name after the option, if omitted
		529	# DoxygenLayout.xml will be used as the name of the layout file.
		530
		531	LAYOUT_FILE =
		532
		533	#---------------------------------------------------------------------------
		534	# configuration options related to warning and progress messages
		535	#---------------------------------------------------------------------------
		536
		537	# The QUIET tag can be used to turn on/off the messages that are generated
		538	# by doxygen. Possible values are YES and NO. If left blank NO is used.
		539
		540	QUIET = NO
		541
		542	# The WARNINGS tag can be used to turn on/off the warning messages that are
		543	# generated by doxygen. Possible values are YES and NO. If left blank
		544	# NO is used.
		545
		546	WARNINGS = YES
		547
		548	# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
		549	# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
		550	# automatically be disabled.
		551
		552	WARN_IF_UNDOCUMENTED = YES
		553
		554	# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
		555	# potential errors in the documentation, such as not documenting some
		556	# parameters in a documented function, or documenting parameters that
		557	# don't exist or using markup commands wrongly.
		558
		559	WARN_IF_DOC_ERROR = YES
		560
		561	# This WARN_NO_PARAMDOC option can be abled to get warnings for
		562	# functions that are documented, but have no documentation for their parameters
		563	# or return value. If set to NO (the default) doxygen will only warn about
		564	# wrong or incomplete parameter documentation, but not about the absence of
		565	# documentation.
		566
		567	WARN_NO_PARAMDOC = NO
		568
		569	# The WARN_FORMAT tag determines the format of the warning messages that
		570	# doxygen can produce. The string should contain the $file, $line, and $text
		571	# tags, which will be replaced by the file and line number from which the
		572	# warning originated and the warning text. Optionally the format may contain
		573	# $version, which will be replaced by the version of the file (if it could
		574	# be obtained via FILE_VERSION_FILTER)
		575
		576	WARN_FORMAT = "$file:$line: $text"
		577
		578	# The WARN_LOGFILE tag can be used to specify a file to which warning
		579	# and error messages should be written. If left blank the output is written
		580	# to stderr.
		581
		582	WARN_LOGFILE =
		583
		584	#---------------------------------------------------------------------------
		585	# configuration options related to the input files
		586	#---------------------------------------------------------------------------
		587
		588	# The INPUT tag can be used to specify the files and/or directories that contain
		589	# documented source files. You may enter file names like "myfile.cpp" or
		590	# directories like "/usr/src/myproject". Separate the files or directories
		591	# with spaces.
		592
		593	INPUT = /opt/GRLIB/lib_lpp/lib/lpp
		594
		595	# This tag can be used to specify the character encoding of the source files
		596	# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
		597	# also the default input encoding. Doxygen uses libiconv (or the iconv built
		598	# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
		599	# the list of possible encodings.
		600
		601	INPUT_ENCODING = UTF-8
		602
		603	# If the value of the INPUT tag contains directories, you can use the
		604	# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
		605	# and *.h) to filter out the source-files in the directories. If left
		606	# blank the following patterns are tested:
		607	# .c .cc .cxx .cpp .c++ .java .ii .ixx .ipp .i++ .inl .h .hh .hxx
		608	# .hpp .h++ .idl .odl .cs .php .php3 .inc .m .mm .py .f90
		609
		610	FILE_PATTERNS = *.c \
		611	*.cc \
		612	*.cxx \
		613	*.cpp \
		614	*.c++ \
		615	*.d \
		616	*.java \
		617	*.ii \
		618	*.ixx \
		619	*.ipp \
		620	*.i++ \
		621	*.inl \
		622	*.h \
		623	*.hh \
		624	*.hxx \
		625	*.hpp \
		626	*.h++ \
		627	*.idl \
		628	*.odl \
		629	*.cs \
		630	*.php \
		631	*.php3 \
		632	*.inc \
		633	*.m \
		634	*.mm \
		635	*.dox \
		636	*.py \
		637	*.f90 \
		638	*.f \
		639	*.vhd \
		640	*.vhdl
		641
		642	# The RECURSIVE tag can be used to turn specify whether or not subdirectories
		643	# should be searched for input files as well. Possible values are YES and NO.
		644	# If left blank NO is used.
		645
		646	RECURSIVE = YES
		647
		648	# The EXCLUDE tag can be used to specify files and/or directories that should
		649	# excluded from the INPUT source files. This way you can easily exclude a
		650	# subdirectory from a directory tree whose root is specified with the INPUT tag.
		651
		652	EXCLUDE =
		653
		654	# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
		655	# directories that are symbolic links (a Unix filesystem feature) are excluded
		656	# from the input.
		657
		658	EXCLUDE_SYMLINKS = NO
		659
		660	# If the value of the INPUT tag contains directories, you can use the
		661	# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
		662	# certain files from those directories. Note that the wildcards are matched
		663	# against the file with absolute path, so to exclude all test directories
		664	# for example use the pattern /test/
		665
		666	EXCLUDE_PATTERNS =
		667
		668	# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
		669	# (namespaces, classes, functions, etc.) that should be excluded from the
		670	# output. The symbol name can be a fully qualified name, a word, or if the
		671	# wildcard * is used, a substring. Examples: ANamespace, AClass,
		672	# AClass::ANamespace, ANamespace::*Test
		673
		674	EXCLUDE_SYMBOLS =
		675
		676	# The EXAMPLE_PATH tag can be used to specify one or more files or
		677	# directories that contain example code fragments that are included (see
		678	# the \include command).
		679
		680	EXAMPLE_PATH =
		681
		682	# If the value of the EXAMPLE_PATH tag contains directories, you can use the
		683	# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
		684	# and *.h) to filter out the source-files in the directories. If left
		685	# blank all files are included.
		686
		687	EXAMPLE_PATTERNS = *
		688
		689	# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
		690	# searched for input files to be used with the \include or \dontinclude
		691	# commands irrespective of the value of the RECURSIVE tag.
		692	# Possible values are YES and NO. If left blank NO is used.
		693
		694	EXAMPLE_RECURSIVE = NO
		695
		696	# The IMAGE_PATH tag can be used to specify one or more files or
		697	# directories that contain image that are included in the documentation (see
		698	# the \image command).
		699
		700	IMAGE_PATH =
		701
		702	# The INPUT_FILTER tag can be used to specify a program that doxygen should
		703	# invoke to filter for each input file. Doxygen will invoke the filter program
		704	# by executing (via popen()) the command <filter> <input-file>, where <filter>
		705	# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
		706	# input file. Doxygen will then use the output that the filter program writes
		707	# to standard output. If FILTER_PATTERNS is specified, this tag will be
		708	# ignored.
		709
		710	INPUT_FILTER =
		711
		712	# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
		713	# basis. Doxygen will compare the file name with each pattern and apply the
		714	# filter if there is a match. The filters are a list of the form:
		715	# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
		716	# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
		717	# is applied to all files.
		718
		719	FILTER_PATTERNS =
		720
		721	# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
		722	# INPUT_FILTER) will be used to filter the input files when producing source
		723	# files to browse (i.e. when SOURCE_BROWSER is set to YES).
		724
		725	FILTER_SOURCE_FILES = NO
		726
		727	#---------------------------------------------------------------------------
		728	# configuration options related to source browsing
		729	#---------------------------------------------------------------------------
		730
		731	# If the SOURCE_BROWSER tag is set to YES then a list of source files will
		732	# be generated. Documented entities will be cross-referenced with these sources.
		733	# Note: To get rid of all source code in the generated output, make sure also
		734	# VERBATIM_HEADERS is set to NO.
		735
		736	SOURCE_BROWSER = NO
		737
		738	# Setting the INLINE_SOURCES tag to YES will include the body
		739	# of functions and classes directly in the documentation.
		740
		741	INLINE_SOURCES = NO
		742
		743	# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
		744	# doxygen to hide any special comment blocks from generated source code
		745	# fragments. Normal C and C++ comments will always remain visible.
		746
		747	STRIP_CODE_COMMENTS = YES
		748
		749	# If the REFERENCED_BY_RELATION tag is set to YES
		750	# then for each documented function all documented
		751	# functions referencing it will be listed.
		752
		753	REFERENCED_BY_RELATION = NO
		754
		755	# If the REFERENCES_RELATION tag is set to YES
		756	# then for each documented function all documented entities
		757	# called/used by that function will be listed.
		758
		759	REFERENCES_RELATION = NO
		760
		761	# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
		762	# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
		763	# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
		764	# link to the source code. Otherwise they will link to the documentation.
		765
		766	REFERENCES_LINK_SOURCE = YES
		767
		768	# If the USE_HTAGS tag is set to YES then the references to source code
		769	# will point to the HTML generated by the htags(1) tool instead of doxygen
		770	# built-in source browser. The htags tool is part of GNU's global source
		771	# tagging system (see http://www.gnu.org/software/global/global.html). You
		772	# will need version 4.8.6 or higher.
		773
		774	USE_HTAGS = NO
		775
		776	# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
		777	# will generate a verbatim copy of the header file for each class for
		778	# which an include is specified. Set to NO to disable this.
		779
		780	VERBATIM_HEADERS = YES
		781
		782	#---------------------------------------------------------------------------
		783	# configuration options related to the alphabetical class index
		784	#---------------------------------------------------------------------------
		785
		786	# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
		787	# of all compounds will be generated. Enable this if the project
		788	# contains a lot of classes, structs, unions or interfaces.
		789
		790	ALPHABETICAL_INDEX = YES
		791
		792	# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
		793	# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
		794	# in which this list will be split (can be a number in the range [1..20])
		795
		796	COLS_IN_ALPHA_INDEX = 5
		797
		798	# In case all classes in a project start with a common prefix, all
		799	# classes will be put under the same header in the alphabetical index.
		800	# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
		801	# should be ignored while generating the index headers.
		802
		803	IGNORE_PREFIX =
		804
		805	#---------------------------------------------------------------------------
		806	# configuration options related to the HTML output
		807	#---------------------------------------------------------------------------
		808
		809	# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
		810	# generate HTML output.
		811
		812	GENERATE_HTML = YES
		813
		814	# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
		815	# If a relative path is entered the value of OUTPUT_DIRECTORY will be
		816	# put in front of it. If left blank `html' will be used as the default path.
		817
		818	HTML_OUTPUT = html
		819
		820	# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
		821	# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
		822	# doxygen will generate files with .html extension.
		823
		824	HTML_FILE_EXTENSION = .html
		825
		826	# The HTML_HEADER tag can be used to specify a personal HTML header for
		827	# each generated HTML page. If it is left blank doxygen will generate a
		828	# standard header.
		829
		830	HTML_HEADER =
		831
		832	# The HTML_FOOTER tag can be used to specify a personal HTML footer for
		833	# each generated HTML page. If it is left blank doxygen will generate a
		834	# standard footer.
		835
		836	HTML_FOOTER =
		837
		838	# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
		839	# style sheet that is used by each HTML page. It can be used to
		840	# fine-tune the look of the HTML output. If the tag is left blank doxygen
		841	# will generate a default style sheet. Note that doxygen will try to copy
		842	# the style sheet file to the HTML output directory, so don't put your own
		843	# stylesheet in the HTML output directory as well, or it will be erased!
		844
		845	HTML_STYLESHEET =
		846
		847	# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
		848	# Doxygen will adjust the colors in the stylesheet and background images
		849	# according to this color. Hue is specified as an angle on a colorwheel,
		850	# see http://en.wikipedia.org/wiki/Hue for more information.
		851	# For instance the value 0 represents red, 60 is yellow, 120 is green,
		852	# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
		853	# The allowed range is 0 to 359.
		854
		855	HTML_COLORSTYLE_HUE = 220
		856
		857	# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
		858	# the colors in the HTML output. For a value of 0 the output will use
		859	# grayscales only. A value of 255 will produce the most vivid colors.
		860
		861	HTML_COLORSTYLE_SAT = 100
		862
		863	# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
		864	# the luminance component of the colors in the HTML output. Values below
		865	# 100 gradually make the output lighter, whereas values above 100 make
		866	# the output darker. The value divided by 100 is the actual gamma applied,
		867	# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
		868	# and 100 does not change the gamma.
		869
		870	HTML_COLORSTYLE_GAMMA = 80
		871
		872	# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
		873	# page will contain the date and time when the page was generated. Setting
		874	# this to NO can help when comparing the output of multiple runs.
		875
		876	HTML_TIMESTAMP = YES
		877
		878	# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
		879	# files or namespaces will be aligned in HTML using tables. If set to
		880	# NO a bullet list will be used.
		881
		882	HTML_ALIGN_MEMBERS = YES
		883
		884	# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
		885	# documentation will contain sections that can be hidden and shown after the
		886	# page has loaded. For this to work a browser that supports
		887	# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
		888	# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
		889
		890	HTML_DYNAMIC_SECTIONS = NO
		891
		892	# If the GENERATE_DOCSET tag is set to YES, additional index files
		893	# will be generated that can be used as input for Apple's Xcode 3
		894	# integrated development environment, introduced with OSX 10.5 (Leopard).
		895	# To create a documentation set, doxygen will generate a Makefile in the
		896	# HTML output directory. Running make will produce the docset in that
		897	# directory and running "make install" will install the docset in
		898	# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
		899	# it at startup.
		900	# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
		901	# for more information.
		902
		903	GENERATE_DOCSET = NO
		904
		905	# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
		906	# feed. A documentation feed provides an umbrella under which multiple
		907	# documentation sets from a single provider (such as a company or product suite)
		908	# can be grouped.
		909
		910	DOCSET_FEEDNAME = "Doxygen generated docs"
		911
		912	# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
		913	# should uniquely identify the documentation set bundle. This should be a
		914	# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
		915	# will append .docset to the name.
		916
		917	DOCSET_BUNDLE_ID = org.doxygen.Project
		918
		919	# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
		920	# the documentation publisher. This should be a reverse domain-name style
		921	# string, e.g. com.mycompany.MyDocSet.documentation.
		922
		923	DOCSET_PUBLISHER_ID = org.doxygen.Publisher
		924
		925	# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
		926
		927	DOCSET_PUBLISHER_NAME = Publisher
		928
		929	# If the GENERATE_HTMLHELP tag is set to YES, additional index files
		930	# will be generated that can be used as input for tools like the
		931	# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
		932	# of the generated HTML documentation.
		933
		934	GENERATE_HTMLHELP = NO
		935
		936	# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
		937	# be used to specify the file name of the resulting .chm file. You
		938	# can add a path in front of the file if the result should not be
		939	# written to the html output directory.
		940
		941	CHM_FILE =
		942
		943	# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
		944	# be used to specify the location (absolute path including file name) of
		945	# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
		946	# the HTML help compiler on the generated index.hhp.
		947
		948	HHC_LOCATION =
		949
		950	# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
		951	# controls if a separate .chi index file is generated (YES) or that
		952	# it should be included in the master .chm file (NO).
		953
		954	GENERATE_CHI = NO
		955
		956	# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
		957	# is used to encode HtmlHelp index (hhk), content (hhc) and project file
		958	# content.
		959
		960	CHM_INDEX_ENCODING =
		961
		962	# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
		963	# controls whether a binary table of contents is generated (YES) or a
		964	# normal table of contents (NO) in the .chm file.
		965
		966	BINARY_TOC = NO
		967
		968	# The TOC_EXPAND flag can be set to YES to add extra items for group members
		969	# to the contents of the HTML help documentation and to the tree view.
		970
		971	TOC_EXPAND = NO
		972
		973	# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
		974	# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
		975	# that can be used as input for Qt's qhelpgenerator to generate a
		976	# Qt Compressed Help (.qch) of the generated HTML documentation.
		977
		978	GENERATE_QHP = NO
		979
		980	# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
		981	# be used to specify the file name of the resulting .qch file.
		982	# The path specified is relative to the HTML output folder.
		983
		984	QCH_FILE =
		985
		986	# The QHP_NAMESPACE tag specifies the namespace to use when generating
		987	# Qt Help Project output. For more information please see
		988	# http://doc.trolltech.com/qthelpproject.html#namespace
		989
		990	QHP_NAMESPACE = org.doxygen.Project
		991
		992	# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
		993	# Qt Help Project output. For more information please see
		994	# http://doc.trolltech.com/qthelpproject.html#virtual-folders
		995
		996	QHP_VIRTUAL_FOLDER = doc
		997
		998	# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
		999	# add. For more information please see
		1000	# http://doc.trolltech.com/qthelpproject.html#custom-filters
		1001
		1002	QHP_CUST_FILTER_NAME =
		1003
		1004	# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
		1005	# custom filter to add. For more information please see
		1006	# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">
		1007	# Qt Help Project / Custom Filters</a>.
		1008
		1009	QHP_CUST_FILTER_ATTRS =
		1010
		1011	# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
		1012	# project's
		1013	# filter section matches.
		1014	# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">
		1015	# Qt Help Project / Filter Attributes</a>.
		1016
		1017	QHP_SECT_FILTER_ATTRS =
		1018
		1019	# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
		1020	# be used to specify the location of Qt's qhelpgenerator.
		1021	# If non-empty doxygen will try to run qhelpgenerator on the generated
		1022	# .qhp file.
		1023
		1024	QHG_LOCATION =
		1025
		1026	# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
		1027	# will be generated, which together with the HTML files, form an Eclipse help
		1028	# plugin. To install this plugin and make it available under the help contents
		1029	# menu in Eclipse, the contents of the directory containing the HTML and XML
		1030	# files needs to be copied into the plugins directory of eclipse. The name of
		1031	# the directory within the plugins directory should be the same as
		1032	# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
		1033	# the help appears.
		1034
		1035	GENERATE_ECLIPSEHELP = NO
		1036
		1037	# A unique identifier for the eclipse help plugin. When installing the plugin
		1038	# the directory name containing the HTML and XML files should also have
		1039	# this name.
		1040
		1041	ECLIPSE_DOC_ID = org.doxygen.Project
		1042
		1043	# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
		1044	# top of each HTML page. The value NO (the default) enables the index and
		1045	# the value YES disables it.
		1046
		1047	DISABLE_INDEX = NO
		1048
		1049	# This tag can be used to set the number of enum values (range [1..20])
		1050	# that doxygen will group on one line in the generated HTML documentation.
		1051
		1052	ENUM_VALUES_PER_LINE = 4
		1053
		1054	# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
		1055	# structure should be generated to display hierarchical information.
		1056	# If the tag value is set to YES, a side panel will be generated
		1057	# containing a tree-like index structure (just like the one that
		1058	# is generated for HTML Help). For this to work a browser that supports
		1059	# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
		1060	# Windows users are probably better off using the HTML help feature.
		1061
		1062	GENERATE_TREEVIEW = NO
		1063
		1064	# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
		1065	# and Class Hierarchy pages using a tree view instead of an ordered list.
		1066
		1067	USE_INLINE_TREES = NO
		1068
		1069	# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
		1070	# used to set the initial width (in pixels) of the frame in which the tree
		1071	# is shown.
		1072
		1073	TREEVIEW_WIDTH = 250
		1074
		1075	# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
		1076	# links to external symbols imported via tag files in a separate window.
		1077
		1078	EXT_LINKS_IN_WINDOW = NO
		1079
		1080	# Use this tag to change the font size of Latex formulas included
		1081	# as images in the HTML documentation. The default is 10. Note that
		1082	# when you change the font size after a successful doxygen run you need
		1083	# to manually remove any form_*.png images from the HTML output directory
		1084	# to force them to be regenerated.
		1085
		1086	FORMULA_FONTSIZE = 10
		1087
		1088	# Use the FORMULA_TRANPARENT tag to determine whether or not the images
		1089	# generated for formulas are transparent PNGs. Transparent PNGs are
		1090	# not supported properly for IE 6.0, but are supported on all modern browsers.
		1091	# Note that when changing this option you need to delete any form_*.png files
		1092	# in the HTML output before the changes have effect.
		1093
		1094	FORMULA_TRANSPARENT = YES
		1095
		1096	# When the SEARCHENGINE tag is enabled doxygen will generate a search box
		1097	# for the HTML output. The underlying search engine uses javascript
		1098	# and DHTML and should work on any modern browser. Note that when using
		1099	# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
		1100	# (GENERATE_DOCSET) there is already a search function so this one should
		1101	# typically be disabled. For large projects the javascript based search engine
		1102	# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
		1103
		1104	SEARCHENGINE = YES
		1105
		1106	# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
		1107	# implemented using a PHP enabled web server instead of at the web client
		1108	# using Javascript. Doxygen will generate the search PHP script and index
		1109	# file to put on the web server. The advantage of the server
		1110	# based approach is that it scales better to large projects and allows
		1111	# full text search. The disadvances is that it is more difficult to setup
		1112	# and does not have live searching capabilities.
		1113
		1114	SERVER_BASED_SEARCH = NO
		1115
		1116	#---------------------------------------------------------------------------
		1117	# configuration options related to the LaTeX output
		1118	#---------------------------------------------------------------------------
		1119
		1120	# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
		1121	# generate Latex output.
		1122
		1123	GENERATE_LATEX = YES
		1124
		1125	# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
		1126	# If a relative path is entered the value of OUTPUT_DIRECTORY will be
		1127	# put in front of it. If left blank `latex' will be used as the default path.
		1128
		1129	LATEX_OUTPUT = latex
		1130
		1131	# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
		1132	# invoked. If left blank `latex' will be used as the default command name.
		1133	# Note that when enabling USE_PDFLATEX this option is only used for
		1134	# generating bitmaps for formulas in the HTML output, but not in the
		1135	# Makefile that is written to the output directory.
		1136
		1137	LATEX_CMD_NAME = latex
		1138
		1139	# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
		1140	# generate index for LaTeX. If left blank `makeindex' will be used as the
		1141	# default command name.
		1142
		1143	MAKEINDEX_CMD_NAME = makeindex
		1144
		1145	# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
		1146	# LaTeX documents. This may be useful for small projects and may help to
		1147	# save some trees in general.
		1148
		1149	COMPACT_LATEX = NO
		1150
		1151	# The PAPER_TYPE tag can be used to set the paper type that is used
		1152	# by the printer. Possible values are: a4, a4wide, letter, legal and
		1153	# executive. If left blank a4wide will be used.
		1154
		1155	PAPER_TYPE = a4wide
		1156
		1157	# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
		1158	# packages that should be included in the LaTeX output.
		1159
		1160	EXTRA_PACKAGES =
		1161
		1162	# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
		1163	# the generated latex document. The header should contain everything until
		1164	# the first chapter. If it is left blank doxygen will generate a
		1165	# standard header. Notice: only use this tag if you know what you are doing!
		1166
		1167	LATEX_HEADER =
		1168
		1169	# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
		1170	# is prepared for conversion to pdf (using ps2pdf). The pdf file will
		1171	# contain links (just like the HTML output) instead of page references
		1172	# This makes the output suitable for online browsing using a pdf viewer.
		1173
		1174	PDF_HYPERLINKS = YES
		1175
		1176	# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
		1177	# plain latex in the generated Makefile. Set this option to YES to get a
		1178	# higher quality PDF documentation.
		1179
		1180	USE_PDFLATEX = YES
		1181
		1182	# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
		1183	# command to the generated LaTeX files. This will instruct LaTeX to keep
		1184	# running if errors occur, instead of asking the user for help.
		1185	# This option is also used when generating formulas in HTML.
		1186
		1187	LATEX_BATCHMODE = NO
		1188
		1189	# If LATEX_HIDE_INDICES is set to YES then doxygen will not
		1190	# include the index chapters (such as File Index, Compound Index, etc.)
		1191	# in the output.
		1192
		1193	LATEX_HIDE_INDICES = NO
		1194
		1195	# If LATEX_SOURCE_CODE is set to YES then doxygen will include
		1196	# source code with syntax highlighting in the LaTeX output.
		1197	# Note that which sources are shown also depends on other settings
		1198	# such as SOURCE_BROWSER.
		1199
		1200	LATEX_SOURCE_CODE = NO
		1201
		1202	#---------------------------------------------------------------------------
		1203	# configuration options related to the RTF output
		1204	#---------------------------------------------------------------------------
		1205
		1206	# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
		1207	# The RTF output is optimized for Word 97 and may not look very pretty with
		1208	# other RTF readers or editors.
		1209
		1210	GENERATE_RTF = NO
		1211
		1212	# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
		1213	# If a relative path is entered the value of OUTPUT_DIRECTORY will be
		1214	# put in front of it. If left blank `rtf' will be used as the default path.
		1215
		1216	RTF_OUTPUT = rtf
		1217
		1218	# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
		1219	# RTF documents. This may be useful for small projects and may help to
		1220	# save some trees in general.
		1221
		1222	COMPACT_RTF = NO
		1223
		1224	# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
		1225	# will contain hyperlink fields. The RTF file will
		1226	# contain links (just like the HTML output) instead of page references.
		1227	# This makes the output suitable for online browsing using WORD or other
		1228	# programs which support those fields.
		1229	# Note: wordpad (write) and others do not support links.
		1230
		1231	RTF_HYPERLINKS = NO
		1232
		1233	# Load stylesheet definitions from file. Syntax is similar to doxygen's
		1234	# config file, i.e. a series of assignments. You only have to provide
		1235	# replacements, missing definitions are set to their default value.
		1236
		1237	RTF_STYLESHEET_FILE =
		1238
		1239	# Set optional variables used in the generation of an rtf document.
		1240	# Syntax is similar to doxygen's config file.
		1241
		1242	RTF_EXTENSIONS_FILE =
		1243
		1244	#---------------------------------------------------------------------------
		1245	# configuration options related to the man page output
		1246	#---------------------------------------------------------------------------
		1247
		1248	# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
		1249	# generate man pages
		1250
		1251	GENERATE_MAN = NO
		1252
		1253	# The MAN_OUTPUT tag is used to specify where the man pages will be put.
		1254	# If a relative path is entered the value of OUTPUT_DIRECTORY will be
		1255	# put in front of it. If left blank `man' will be used as the default path.
		1256
		1257	MAN_OUTPUT = man
		1258
		1259	# The MAN_EXTENSION tag determines the extension that is added to
		1260	# the generated man pages (default is the subroutine's section .3)
		1261
		1262	MAN_EXTENSION = .3
		1263
		1264	# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
		1265	# then it will generate one additional man file for each entity
		1266	# documented in the real man page(s). These additional files
		1267	# only source the real man page, but without them the man command
		1268	# would be unable to find the correct page. The default is NO.
		1269
		1270	MAN_LINKS = NO
		1271
		1272	#---------------------------------------------------------------------------
		1273	# configuration options related to the XML output
		1274	#---------------------------------------------------------------------------
		1275
		1276	# If the GENERATE_XML tag is set to YES Doxygen will
		1277	# generate an XML file that captures the structure of
		1278	# the code including all documentation.
		1279
		1280	GENERATE_XML = NO
		1281
		1282	# The XML_OUTPUT tag is used to specify where the XML pages will be put.
		1283	# If a relative path is entered the value of OUTPUT_DIRECTORY will be
		1284	# put in front of it. If left blank `xml' will be used as the default path.
		1285
		1286	XML_OUTPUT = xml
		1287
		1288	# The XML_SCHEMA tag can be used to specify an XML schema,
		1289	# which can be used by a validating XML parser to check the
		1290	# syntax of the XML files.
		1291
		1292	XML_SCHEMA =
		1293
		1294	# The XML_DTD tag can be used to specify an XML DTD,
		1295	# which can be used by a validating XML parser to check the
		1296	# syntax of the XML files.
		1297
		1298	XML_DTD =
		1299
		1300	# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
		1301	# dump the program listings (including syntax highlighting
		1302	# and cross-referencing information) to the XML output. Note that
		1303	# enabling this will significantly increase the size of the XML output.
		1304
		1305	XML_PROGRAMLISTING = YES
		1306
		1307	#---------------------------------------------------------------------------
		1308	# configuration options for the AutoGen Definitions output
		1309	#---------------------------------------------------------------------------
		1310
		1311	# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
		1312	# generate an AutoGen Definitions (see autogen.sf.net) file
		1313	# that captures the structure of the code including all
		1314	# documentation. Note that this feature is still experimental
		1315	# and incomplete at the moment.
		1316
		1317	GENERATE_AUTOGEN_DEF = NO
		1318
		1319	#---------------------------------------------------------------------------
		1320	# configuration options related to the Perl module output
		1321	#---------------------------------------------------------------------------
		1322
		1323	# If the GENERATE_PERLMOD tag is set to YES Doxygen will
		1324	# generate a Perl module file that captures the structure of
		1325	# the code including all documentation. Note that this
		1326	# feature is still experimental and incomplete at the
		1327	# moment.
		1328
		1329	GENERATE_PERLMOD = NO
		1330
		1331	# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
		1332	# the necessary Makefile rules, Perl scripts and LaTeX code to be able
		1333	# to generate PDF and DVI output from the Perl module output.
		1334
		1335	PERLMOD_LATEX = NO
		1336
		1337	# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
		1338	# nicely formatted so it can be parsed by a human reader. This is useful
		1339	# if you want to understand what is going on. On the other hand, if this
		1340	# tag is set to NO the size of the Perl module output will be much smaller
		1341	# and Perl will parse it just the same.
		1342
		1343	PERLMOD_PRETTY = YES
		1344
		1345	# The names of the make variables in the generated doxyrules.make file
		1346	# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
		1347	# This is useful so different doxyrules.make files included by the same
		1348	# Makefile don't overwrite each other's variables.
		1349
		1350	PERLMOD_MAKEVAR_PREFIX =
		1351
		1352	#---------------------------------------------------------------------------
		1353	# Configuration options related to the preprocessor
		1354	#---------------------------------------------------------------------------
		1355
		1356	# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
		1357	# evaluate all C-preprocessor directives found in the sources and include
		1358	# files.
		1359
		1360	ENABLE_PREPROCESSING = YES
		1361
		1362	# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
		1363	# names in the source code. If set to NO (the default) only conditional
		1364	# compilation will be performed. Macro expansion can be done in a controlled
		1365	# way by setting EXPAND_ONLY_PREDEF to YES.
		1366
		1367	MACRO_EXPANSION = NO
		1368
		1369	# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
		1370	# then the macro expansion is limited to the macros specified with the
		1371	# PREDEFINED and EXPAND_AS_DEFINED tags.
		1372
		1373	EXPAND_ONLY_PREDEF = NO
		1374
		1375	# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
		1376	# in the INCLUDE_PATH (see below) will be search if a #include is found.
		1377
		1378	SEARCH_INCLUDES = YES
		1379
		1380	# The INCLUDE_PATH tag can be used to specify one or more directories that
		1381	# contain include files that are not input files but should be processed by
		1382	# the preprocessor.
		1383
		1384	INCLUDE_PATH =
		1385
		1386	# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
		1387	# patterns (like .h and .hpp) to filter out the header-files in the
		1388	# directories. If left blank, the patterns specified with FILE_PATTERNS will
		1389	# be used.
		1390
		1391	INCLUDE_FILE_PATTERNS =
		1392
		1393	# The PREDEFINED tag can be used to specify one or more macro names that
		1394	# are defined before the preprocessor is started (similar to the -D option of
		1395	# gcc). The argument of the tag is a list of macros of the form: name
		1396	# or name=definition (no spaces). If the definition and the = are
		1397	# omitted =1 is assumed. To prevent a macro definition from being
		1398	# undefined via #undef or recursively expanded use the := operator
		1399	# instead of the = operator.
		1400
		1401	PREDEFINED =
		1402
		1403	# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
		1404	# this tag can be used to specify a list of macro names that should be expanded.
		1405	# The macro definition that is found in the sources will be used.
		1406	# Use the PREDEFINED tag if you want to use a different macro definition.
		1407
		1408	EXPAND_AS_DEFINED =
		1409
		1410	# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
		1411	# doxygen's preprocessor will remove all function-like macros that are alone
		1412	# on a line, have an all uppercase name, and do not end with a semicolon. Such
		1413	# function macros are typically used for boiler-plate code, and will confuse
		1414	# the parser if not removed.
		1415
		1416	SKIP_FUNCTION_MACROS = YES
		1417
		1418	#---------------------------------------------------------------------------
		1419	# Configuration::additions related to external references
		1420	#---------------------------------------------------------------------------
		1421
		1422	# The TAGFILES option can be used to specify one or more tagfiles.
		1423	# Optionally an initial location of the external documentation
		1424	# can be added for each tagfile. The format of a tag file without
		1425	# this location is as follows:
		1426	# TAGFILES = file1 file2 ...
		1427	# Adding location for the tag files is done as follows:
		1428	# TAGFILES = file1=loc1 "file2 = loc2" ...
		1429	# where "loc1" and "loc2" can be relative or absolute paths or
		1430	# URLs. If a location is present for each tag, the installdox tool
		1431	# does not have to be run to correct the links.
		1432	# Note that each tag file must have a unique name
		1433	# (where the name does NOT include the path)
		1434	# If a tag file is not located in the directory in which doxygen
		1435	# is run, you must also specify the path to the tagfile here.
		1436
		1437	TAGFILES =
		1438
		1439	# When a file name is specified after GENERATE_TAGFILE, doxygen will create
		1440	# a tag file that is based on the input files it reads.
		1441
		1442	GENERATE_TAGFILE =
		1443
		1444	# If the ALLEXTERNALS tag is set to YES all external classes will be listed
		1445	# in the class index. If set to NO only the inherited external classes
		1446	# will be listed.
		1447
		1448	ALLEXTERNALS = NO
		1449
		1450	# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
		1451	# in the modules index. If set to NO, only the current project's groups will
		1452	# be listed.
		1453
		1454	EXTERNAL_GROUPS = YES
		1455
		1456	# The PERL_PATH should be the absolute path and name of the perl script
		1457	# interpreter (i.e. the result of `which perl').
		1458
		1459	PERL_PATH = /usr/bin/perl
		1460
		1461	#---------------------------------------------------------------------------
		1462	# Configuration options related to the dot tool
		1463	#---------------------------------------------------------------------------
		1464
		1465	# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
		1466	# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
		1467	# or super classes. Setting the tag to NO turns the diagrams off. Note that
		1468	# this option is superseded by the HAVE_DOT option below. This is only a
		1469	# fallback. It is recommended to install and use dot, since it yields more
		1470	# powerful graphs.
		1471
		1472	CLASS_DIAGRAMS = YES
		1473
		1474	# You can define message sequence charts within doxygen comments using the \msc
		1475	# command. Doxygen will then run the mscgen tool (see
		1476	# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
		1477	# documentation. The MSCGEN_PATH tag allows you to specify the directory where
		1478	# the mscgen tool resides. If left empty the tool is assumed to be found in the
		1479	# default search path.
		1480
		1481	MSCGEN_PATH =
		1482
		1483	# If set to YES, the inheritance and collaboration graphs will hide
		1484	# inheritance and usage relations if the target is undocumented
		1485	# or is not a class.
		1486
		1487	HIDE_UNDOC_RELATIONS = YES
		1488
		1489	# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
		1490	# available from the path. This tool is part of Graphviz, a graph visualization
		1491	# toolkit from AT&T and Lucent Bell Labs. The other options in this section
		1492	# have no effect if this option is set to NO (the default)
		1493
		1494	HAVE_DOT = NO
		1495
		1496	# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
		1497	# allowed to run in parallel. When set to 0 (the default) doxygen will
		1498	# base this on the number of processors available in the system. You can set it
		1499	# explicitly to a value larger than 0 to get control over the balance
		1500	# between CPU load and processing speed.
		1501
		1502	DOT_NUM_THREADS = 0
		1503
		1504	# By default doxygen will write a font called FreeSans.ttf to the output
		1505	# directory and reference it in all dot files that doxygen generates. This
		1506	# font does not include all possible unicode characters however, so when you need
		1507	# these (or just want a differently looking font) you can specify the font name
		1508	# using DOT_FONTNAME. You need need to make sure dot is able to find the font,
		1509	# which can be done by putting it in a standard location or by setting the
		1510	# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
		1511	# containing the font.
		1512
		1513	DOT_FONTNAME = FreeSans.ttf
		1514
		1515	# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
		1516	# The default size is 10pt.
		1517
		1518	DOT_FONTSIZE = 10
		1519
		1520	# By default doxygen will tell dot to use the output directory to look for the
		1521	# FreeSans.ttf font (which doxygen will put there itself). If you specify a
		1522	# different font using DOT_FONTNAME you can set the path where dot
		1523	# can find it using this tag.
		1524
		1525	DOT_FONTPATH =
		1526
		1527	# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
		1528	# will generate a graph for each documented class showing the direct and
		1529	# indirect inheritance relations. Setting this tag to YES will force the
		1530	# the CLASS_DIAGRAMS tag to NO.
		1531
		1532	CLASS_GRAPH = YES
		1533
		1534	# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
		1535	# will generate a graph for each documented class showing the direct and
		1536	# indirect implementation dependencies (inheritance, containment, and
		1537	# class references variables) of the class with other documented classes.
		1538
		1539	COLLABORATION_GRAPH = YES
		1540
		1541	# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
		1542	# will generate a graph for groups, showing the direct groups dependencies
		1543
		1544	GROUP_GRAPHS = YES
		1545
		1546	# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
		1547	# collaboration diagrams in a style similar to the OMG's Unified Modeling
		1548	# Language.
		1549
		1550	UML_LOOK = NO
		1551
		1552	# If set to YES, the inheritance and collaboration graphs will show the
		1553	# relations between templates and their instances.
		1554
		1555	TEMPLATE_RELATIONS = NO
		1556
		1557	# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
		1558	# tags are set to YES then doxygen will generate a graph for each documented
		1559	# file showing the direct and indirect include dependencies of the file with
		1560	# other documented files.
		1561
		1562	INCLUDE_GRAPH = YES
		1563
		1564	# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
		1565	# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
		1566	# documented header file showing the documented files that directly or
		1567	# indirectly include this file.
		1568
		1569	INCLUDED_BY_GRAPH = YES
		1570
		1571	# If the CALL_GRAPH and HAVE_DOT options are set to YES then
		1572	# doxygen will generate a call dependency graph for every global function
		1573	# or class method. Note that enabling this option will significantly increase
		1574	# the time of a run. So in most cases it will be better to enable call graphs
		1575	# for selected functions only using the \callgraph command.
		1576
		1577	CALL_GRAPH = NO
		1578
		1579	# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
		1580	# doxygen will generate a caller dependency graph for every global function
		1581	# or class method. Note that enabling this option will significantly increase
		1582	# the time of a run. So in most cases it will be better to enable caller
		1583	# graphs for selected functions only using the \callergraph command.
		1584
		1585	CALLER_GRAPH = NO
		1586
		1587	# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
		1588	# will graphical hierarchy of all classes instead of a textual one.
		1589
		1590	GRAPHICAL_HIERARCHY = YES
		1591
		1592	# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
		1593	# then doxygen will show the dependencies a directory has on other directories
		1594	# in a graphical way. The dependency relations are determined by the #include
		1595	# relations between the files in the directories.
		1596
		1597	DIRECTORY_GRAPH = YES
		1598
		1599	# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
		1600	# generated by dot. Possible values are png, jpg, or gif
		1601	# If left blank png will be used.
		1602
		1603	DOT_IMAGE_FORMAT = png
		1604
		1605	# The tag DOT_PATH can be used to specify the path where the dot tool can be
		1606	# found. If left blank, it is assumed the dot tool can be found in the path.
		1607
		1608	DOT_PATH =
		1609
		1610	# The DOTFILE_DIRS tag can be used to specify one or more directories that
		1611	# contain dot files that are included in the documentation (see the
		1612	# \dotfile command).
		1613
		1614	DOTFILE_DIRS =
		1615
		1616	# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
		1617	# nodes that will be shown in the graph. If the number of nodes in a graph
		1618	# becomes larger than this value, doxygen will truncate the graph, which is
		1619	# visualized by representing a node as a red box. Note that doxygen if the
		1620	# number of direct children of the root node in a graph is already larger than
		1621	# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
		1622	# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
		1623
		1624	DOT_GRAPH_MAX_NODES = 50
		1625
		1626	# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
		1627	# graphs generated by dot. A depth value of 3 means that only nodes reachable
		1628	# from the root by following a path via at most 3 edges will be shown. Nodes
		1629	# that lay further from the root node will be omitted. Note that setting this
		1630	# option to 1 or 2 may greatly reduce the computation time needed for large
		1631	# code bases. Also note that the size of a graph can be further restricted by
		1632	# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
		1633
		1634	MAX_DOT_GRAPH_DEPTH = 0
		1635
		1636	# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
		1637	# background. This is disabled by default, because dot on Windows does not
		1638	# seem to support this out of the box. Warning: Depending on the platform used,
		1639	# enabling this option may lead to badly anti-aliased labels on the edges of
		1640	# a graph (i.e. they become hard to read).
		1641
		1642	DOT_TRANSPARENT = NO
		1643
		1644	# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
		1645	# files in one run (i.e. multiple -o and -T options on the command line). This
		1646	# makes dot run faster, but since only newer versions of dot (>1.8.10)
		1647	# support this, this feature is disabled by default.
		1648
		1649	DOT_MULTI_TARGETS = NO
		1650
		1651	# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
		1652	# generate a legend page explaining the meaning of the various boxes and
		1653	# arrows in the dot generated graphs.
		1654
		1655	GENERATE_LEGEND = YES
		1656
		1657	# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
		1658	# remove the intermediate dot files that are used to generate
		1659	# the various graphs.
		1660
		1661	DOT_CLEANUP = YES

lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd created 644 +87 0

@@ -0,0 +1,87
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	----------------------------------------------------------------------------------
	20	-- Company:
	21	-- Engineer:
	22	--
	23	-- Create Date: 09:21:03 10/19/2010
	24	-- Design Name:
	25	-- Module Name: FRAME_CLK_GEN - Behavioral
	26	-- Project Name:
	27	-- Target Devices:
	28	-- Tool versions:
	29	-- Description:
	30	--
	31	-- Dependencies:
	32	--
	33	-- Revision:
	34	-- Revision 0.01 - File Created
	35	-- Additional Comments:
	36	--
	37	----------------------------------------------------------------------------------
	38	library IEEE;
	39	use IEEE.STD_LOGIC_1164.ALL;
	40	use IEEE.NUMERIC_STD.ALL;
	41	library lpp;
	42	use lpp.amba_lcd_16x2_ctrlr.all;
	43
	44	entity FRAME_CLK_GEN is
	45	generic(OSC_freqKHz : integer := 50000);
	46	Port ( clk : in STD_LOGIC;
	47	reset : in STD_LOGIC;
	48	FRAME_CLK : out STD_LOGIC);
	49	end FRAME_CLK_GEN;
	50
	51	architecture Behavioral of FRAME_CLK_GEN is
	52
	53	Constant Goal_FRAME_CLK_FREQ : integer := 20;
	54
	55	Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
	56
	57	signal CPT : integer := 0;
	58	signal FRAME_CLK_reg : std_logic :='0';
	59
	60	begin
	61
	62	FRAME_CLK <= FRAME_CLK_reg;
	63
	64	process(reset,clk)
	65	begin
	66	if reset = '0' then
	67	CPT <= 0;
	68	FRAME_CLK_reg <= '0';
	69	elsif clk'event and clk = '1' then
	70	if CPT = FRAME_CLK_TRIG then
	71	CPT <= 0;
	72	FRAME_CLK_reg <= not FRAME_CLK_reg;
	73	else
	74	CPT <= CPT + 1;
	75	end if;
	76	end if;
	77	end process;
	78	end Behavioral;
	79
	80
	81
	82
	83
	84
	85
	86
	87

lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER created 644 +18 0

@@ -0,0 +1,18
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------

lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd created 644 +55 0

@@ -0,0 +1,55
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Package File Template
	20	--
	21	-- Purpose: This package defines supplemental types, subtypes,
	22	-- constants, and functions
	23
	24
	25	library IEEE;
	26	use IEEE.STD_LOGIC_1164.all;
	27	library lpp;
	28	use lpp.amba_lcd_16x2_ctrlr.all;
	29
	30
	31
	32	package LCD_16x2_CFG is
	33
	34
	35	constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
	36	constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
	37	constant RetHome : std_logic_vector(7 downto 0):= X"02";
	38	constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
	39	constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C";
	40
	41	constant CursorON : std_logic_vector(7 downto 0):= X"0E";
	42	constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
	43
	44	--===========================================================\|
	45	--======L C D D R I V E R T I M I N G C O D E=====\|
	46	--===========================================================\|
	47
	48	constant Duration_4us : std_logic_vector(1 downto 0) := "00";
	49	constant Duration_100us : std_logic_vector(1 downto 0) := "01";
	50	constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
	51	constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
	52
	53
	54	end LCD_16x2_CFG;
	55

lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd created 644 +228 0

@@ -0,0 +1,228
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	----------------------------------------------------------------------------------
	20	-- Company:
	21	-- Engineer:
	22	--
	23	-- Create Date: 08:32:21 10/19/2010
	24	-- Design Name:
	25	-- Module Name: LCD_16x2_ENGINE - Behavioral
	26	-- Project Name:
	27	-- Target Devices:
	28	-- Tool versions:
	29	-- Description:
	30	--
	31	-- Dependencies:
	32	--
	33	-- Revision:
	34	-- Revision 0.01 - File Created
	35	-- Additional Comments:
	36	--
	37	----------------------------------------------------------------------------------
	38	library IEEE;
	39	use IEEE.STD_LOGIC_1164.ALL;
	40	use IEEE.NUMERIC_STD.ALL;
	41
	42	library lpp;
	43	use lpp.amba_lcd_16x2_ctrlr.all;
	44	use lpp.LCD_16x2_CFG.all;
	45
	46
	47	entity LCD_16x2_ENGINE is
	48	generic(OSC_freqKHz : integer := 50000);
	49	Port ( clk : in STD_LOGIC;
	50	reset : in STD_LOGIC;
	51	DATA : in std_logic_vector(1628-1 downto 0);
	52	CMD : in std_logic_vector(10 downto 0);
	53	Exec : in std_logic;
	54	Ready : out std_logic;
	55	LCD_CTRL : out LCD_DRVR_CTRL_BUSS
	56	);
	57	end LCD_16x2_ENGINE;
	58
	59	architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
	60
	61	constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
	62
	63
	64
	65	signal SYNCH : LCD_DRVR_SYNCH_BUSS;
	66	signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
	67	signal FRAME_CLK : std_logic;
	68
	69	signal FRAME_CLK_reg : std_logic;
	70	signal RefreshFlag : std_logic;
	71	signal CMD_Flag : std_logic;
	72	signal Exec_Reg : std_logic;
	73
	74	type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
	75	signal state : state_t;
	76	signal i : integer range 0 to 32 := 0;
	77
	78
	79
	80	begin
	81
	82	Driver0 : LCD_16x2_DRIVER
	83	generic map(OSC_freqKHz)
	84	Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
	85
	86	FRAME_CLK_GEN0 : FRAME_CLK_GEN
	87	generic map(OSC_freqKHz)
	88	Port map( clk,reset,FRAME_CLK);
	89
	90
	91
	92	process(reset,clk)
	93	begin
	94	if reset = '0' then
	95	state <= INIT0;
	96	Ready <= '0';
	97	RefreshFlag <= '0';
	98	i <= 0;
	99	elsif clk'event and clk ='1' then
	100	FRAME_CLK_reg <= FRAME_CLK;
	101	Exec_Reg <= Exec;
	102
	103	if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
	104	RefreshFlag <= '1';
	105	elsif state = Refresh or state = Refresh0 or state = Refresh1 then
	106	RefreshFlag <= '0';
	107	end if;
	108
	109	if Exec_Reg = '0' and Exec = '1' then
	110	CMD_Flag <= '1';
	111	elsif state = ExecCMD0 or state = ExecCMD1 then
	112	CMD_Flag <= '0';
	113	end if;
	114
	115	case state is
	116	when INIT0 =>
	117	if SYNCH.DRVR_READY = '1' then
	118	DRIVER_CMD.Exec <= '1';
	119	DRIVER_CMD.Duration <= Duration_20ms;
	120	DRIVER_CMD.CMD_Data <= '0';
	121	DRIVER_CMD.Word <= ConfigTbl(i);
	122	i <= i + 1;
	123	state <= INIT1;
	124	else
	125	DRIVER_CMD.Exec <= '0';
	126	end if;
	127	when INIT1 =>
	128	state <= INIT2;
	129	DRIVER_CMD.Exec <= '0';
	130	when INIT2 =>
	131	if SYNCH.DRVR_READY = '1' then
	132	if i = 5 then
	133	state <= Idle;
	134	else
	135	state <= INIT0;
	136	end if;
	137	end if;
	138	when Idle=>
	139	DRIVER_CMD.Exec <= '0';
	140	if RefreshFlag = '1' then
	141	Ready <= '0';
	142	state <= Refresh;
	143	elsif CMD_Flag = '1' then
	144	Ready <= '0';
	145	state <= ExecCMD0;
	146	else
	147	Ready <= '1';
	148	end if;
	149	i <= 0;
	150	when Refresh=>
	151	if SYNCH.DRVR_READY = '1' then
	152	DRIVER_CMD.Exec <= '1';
	153	DRIVER_CMD.Duration <= Duration_100us;
	154	DRIVER_CMD.CMD_Data <= '1';
	155	DRIVER_CMD.Word <= DATA(i8+7 downto i8);
	156	i <= i + 1;
	157	state <= Refresh0;
	158	else
	159	DRIVER_CMD.Exec <= '0';
	160	end if;
	161	when Refresh0=>
	162	state <= Refresh1;
	163	DRIVER_CMD.Exec <= '0';
	164	when Refresh1=>
	165	if SYNCH.DRVR_READY = '1' then
	166	if i = 32 then
	167	state <= ReturnHome;
	168	elsif i = 16 then
	169	state <= GoLine2;
	170	else
	171	state <= Refresh;
	172	end if;
	173	end if;
	174
	175	when ExecCMD0=>
	176	if SYNCH.DRVR_READY = '1' then
	177	DRIVER_CMD.Exec <= '1';
	178	DRIVER_CMD.Duration <= CMD(9 downto 8);
	179	DRIVER_CMD.CMD_Data <= '0';
	180	DRIVER_CMD.Word <= CMD(7 downto 0);
	181	state <= ExecCMD1;
	182	else
	183	DRIVER_CMD.Exec <= '0';
	184	end if;
	185
	186	when ExecCMD1=>
	187	state <= Idle;
	188	DRIVER_CMD.Exec <= '0';
	189
	190	when GoLine2=>
	191	if SYNCH.DRVR_READY = '1' then
	192	DRIVER_CMD.Exec <= '1';
	193	DRIVER_CMD.Duration <= Duration_100us;
	194	DRIVER_CMD.CMD_Data <= '0';
	195	DRIVER_CMD.Word <= X"C0";
	196	state <= GoLine2_0;
	197	else
	198	DRIVER_CMD.Exec <= '0';
	199	end if;
	200	when GoLine2_0=>
	201	state <= Refresh;
	202	DRIVER_CMD.Exec <= '0';
	203	when ReturnHome=>
	204	if SYNCH.DRVR_READY = '1' then
	205	DRIVER_CMD.Exec <= '1';
	206	DRIVER_CMD.Duration <= Duration_4ms;
	207	DRIVER_CMD.CMD_Data <= '0';
	208	DRIVER_CMD.Word <= X"02";
	209	state <= Idle;
	210	else
	211	DRIVER_CMD.Exec <= '0';
	212	end if;
	213	end case;
	214	end if;
	215	end process;
	216
	217
	218	end ar_LCD_16x2_ENGINE;
	219
	220
	221
	222
	223
	224
	225
	226
	227
	228

lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd created 644 +175 0

@@ -0,0 +1,175
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	----------------------------------------------------------------------------------
	20	-- Company:
	21	-- Engineer:
	22	--
	23	-- Create Date: 10:09:57 10/13/2010
	24	-- Design Name:
	25	-- Module Name: LCD_2x16_DRIVER - Behavioral
	26	-- Project Name:
	27	-- Target Devices:
	28	-- Tool versions:
	29	-- Description:
	30	--
	31	-- Dependencies:
	32	--
	33	-- Revision:
	34	-- Revision 0.01 - File Created
	35	-- Additional Comments:
	36	--
	37	----------------------------------------------------------------------------------
	38	library IEEE;
	39	use IEEE.STD_LOGIC_1164.ALL;
	40	use IEEE.NUMERIC_STD.all;
	41	library lpp;
	42	use lpp.amba_lcd_16x2_ctrlr.all;
	43
	44	entity LCD_2x16_DRIVER is
	45	generic(
	46	OSC_Freq_MHz : integer:=60;
	47	Refresh_RateHz : integer:=5
	48	);
	49	Port ( clk : in STD_LOGIC;
	50	reset : in STD_LOGIC;
	51	FramBUFF : in STD_LOGIC_VECTOR(1628-1 downto 0);
	52	LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
	53	LCD_RS : out STD_LOGIC;
	54	LCD_RW : out STD_LOGIC;
	55	LCD_E : out STD_LOGIC;
	56	LCD_RET : out STD_LOGIC;
	57	LCD_CS1 : out STD_LOGIC;
	58	LCD_CS2 : out STD_LOGIC;
	59	STATEOUT: out std_logic_vector(3 downto 0);
	60	refreshPulse : out std_logic
	61	);
	62	end LCD_2x16_DRIVER;
	63
	64	architecture Behavioral of LCD_2x16_DRIVER is
	65
	66	type stateT is(Rst,Configure,IDLE,RefreshScreen);
	67	signal state : stateT;
	68
	69	signal ShortTimePulse : std_logic;
	70	signal MidleTimePulse : std_logic;
	71	signal Refresh_RatePulse : std_logic;
	72	signal Start : STD_LOGIC;
	73
	74	signal CFGM_LCD_RS : std_logic;
	75	signal CFGM_LCD_RW : std_logic;
	76	signal CFGM_LCD_E : std_logic;
	77	signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
	78	signal CFGM_Enable : std_logic;
	79	signal CFGM_completed : std_logic;
	80
	81
	82	signal FRMW_LCD_RS : std_logic;
	83	signal FRMW_LCD_RW : std_logic;
	84	signal FRMW_LCD_E : std_logic;
	85	signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
	86	signal FRMW_Enable : std_logic;
	87	signal FRMW_completed : std_logic;
	88
	89	begin
	90
	91
	92	Counter : LCD_Counter
	93	generic map(OSC_Freq_MHz,Refresh_RateHz)
	94	port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
	95
	96	ConfigModule : Config_Module
	97	port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
	98
	99
	100	FrameWriter : FRAME_WRITER
	101	port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
	102
	103
	104	STATEOUT(0) <= '1' when state = Rst else '0';
	105	STATEOUT(1) <= '1' when state = Configure else '0';
	106	STATEOUT(2) <= '1' when state = IDLE else '0';
	107	STATEOUT(3) <= '1' when state = RefreshScreen else '0';
	108
	109
	110
	111	refreshPulse <= Refresh_RatePulse;
	112
	113	Start <= '1';
	114
	115	process(reset,clk)
	116	begin
	117	if reset = '0' then
	118	LCD_data <= (others=>'0');
	119	LCD_RS <= '0';
	120	LCD_RW <= '0';
	121	LCD_RET <= '0';
	122	LCD_CS1 <= '0';
	123	LCD_CS2 <= '0';
	124	LCD_E <= '0';
	125	state <= Rst;
	126	CFGM_Enable <= '0';
	127	FRMW_Enable <= '0';
	128	elsif clk'event and clk ='1' then
	129	case state is
	130	when Rst =>
	131	LCD_data <= (others=>'0');
	132	LCD_RS <= '0';
	133	LCD_RW <= '0';
	134	LCD_E <= '0';
	135	CFGM_Enable <= '1';
	136	FRMW_Enable <= '0';
	137	if Refresh_RatePulse = '1' then
	138	state <= Configure;
	139	end if;
	140	when Configure =>
	141	LCD_data <= CFGM_LCD_data;
	142	LCD_RS <= CFGM_LCD_RS;
	143	LCD_RW <= CFGM_LCD_RW;
	144	LCD_E <= CFGM_LCD_E;
	145	CFGM_Enable <= '0';
	146	if CFGM_completed = '1' then
	147	state <= IDLE;
	148	end if;
	149	when IDLE =>
	150	if Refresh_RatePulse = '1' then
	151	state <= RefreshScreen;
	152	FRMW_Enable <= '1';
	153	end if;
	154	LCD_RS <= '0';
	155	LCD_RW <= '0';
	156	LCD_E <= '0';
	157	LCD_data <= (others=>'0');
	158	when RefreshScreen =>
	159	LCD_data <= FRMW_LCD_data;
	160	LCD_RS <= FRMW_LCD_RS;
	161	LCD_RW <= FRMW_LCD_RW;
	162	LCD_E <= FRMW_LCD_E;
	163	FRMW_Enable <= '0';
	164	if FRMW_completed = '1' then
	165	state <= IDLE;
	166	end if;
	167	end case;
	168	end if;
	169	end process;
	170	end Behavioral;
	171
	172
	173
	174
	175

lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd created 644 +91 0

@@ -0,0 +1,91
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	----------------------------------------------------------------------------------
	20	-- Company:
	21	-- Engineer:
	22	--
	23	-- Create Date: 08:52:25 10/18/2010
	24	-- Design Name:
	25	-- Module Name: LCD_CLK_GENERATOR - Behavioral
	26	-- Project Name:
	27	-- Target Devices:
	28	-- Tool versions:
	29	-- Description:
	30	--
	31	-- Dependencies:
	32	--
	33	-- Revision:
	34	-- Revision 0.01 - File Created
	35	-- Additional Comments:
	36	--
	37	----------------------------------------------------------------------------------
	38	library IEEE;
	39	use IEEE.STD_LOGIC_1164.ALL;
	40	use IEEE.NUMERIC_STD.ALL;
	41	library lpp;
	42	use lpp.amba_lcd_16x2_ctrlr.all;
	43
	44	entity LCD_CLK_GENERATOR is
	45	generic(OSC_freqKHz : integer := 50000);
	46	Port ( clk : in STD_LOGIC;
	47	reset : in STD_LOGIC;
	48	clk_1us : out STD_LOGIC);
	49	end LCD_CLK_GENERATOR;
	50
	51	architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
	52
	53	Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
	54
	55
	56	signal cpt1 : integer;
	57
	58	signal clk_1us_int : std_logic := '0';
	59
	60
	61	begin
	62
	63	clk_1us <= clk_1us_int;
	64
	65
	66	process(reset,clk)
	67	begin
	68	if reset = '0' then
	69	cpt1 <= 0;
	70	clk_1us_int <= '0';
	71	elsif clk'event and clk = '1' then
	72	if cpt1 = clk_1usTRIGER then
	73	clk_1us_int <= not clk_1us_int;
	74	cpt1 <= 0;
	75	else
	76	cpt1 <= cpt1 + 1;
	77	end if;
	78	end if;
	79	end process;
	80
	81
	82	end ar_LCD_CLK_GENERATOR;
	83
	84
	85
	86
	87
	88
	89
	90
	91

lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd created 644 +124 0

@@ -0,0 +1,124
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	----------------------------------------------------------------------------------
	20	-- Company:
	21	-- Engineer:
	22	--
	23	-- Create Date: 08:44:41 10/14/2010
	24	-- Design Name:
	25	-- Module Name: Top_LCD - Behavioral
	26	-- Project Name:
	27	-- Target Devices:
	28	-- Tool versions:
	29	-- Description:
	30	--
	31	-- Dependencies:
	32	--
	33	-- Revision:
	34	-- Revision 0.01 - File Created
	35	-- Additional Comments:
	36	--
	37	----------------------------------------------------------------------------------
	38	library IEEE;
	39	use IEEE.STD_LOGIC_1164.ALL;
	40
	41	library lpp;
	42	use lpp.amba_lcd_16x2_ctrlr.all;
	43	use lpp.LCD_16x2_CFG.all;
	44
	45
	46	entity AMBA_LCD_16x2_DRIVER is
	47	Port ( reset : in STD_LOGIC;
	48	clk : in STD_LOGIC;
	49	Bp0 : in STD_LOGIC;
	50	Bp1 : in STD_LOGIC;
	51	Bp2 : in STD_LOGIC;
	52	LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
	53	LCD_RS : out STD_LOGIC;
	54	LCD_RW : out STD_LOGIC;
	55	LCD_E : out STD_LOGIC;
	56	LCD_RET : out STD_LOGIC;
	57	LCD_CS1 : out STD_LOGIC;
	58	LCD_CS2 : out STD_LOGIC;
	59	SF_CE0 : out std_logic
	60	);
	61	end AMBA_LCD_16x2_DRIVER;
	62
	63	architecture Behavioral of AMBA_LCD_16x2_DRIVER is
	64
	65	signal FramBUFF : STD_LOGIC_VECTOR(1628-1 downto 0);
	66	signal CMD : std_logic_vector(10 downto 0);
	67	signal Exec : std_logic;
	68	signal Ready : std_logic;
	69	signal rst : std_logic;
	70	signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
	71
	72	begin
	73
	74	LCD_data <= LCD_CTRL.LCD_DATA;
	75	LCD_RS <= LCD_CTRL.LCD_RS;
	76	LCD_RW <= LCD_CTRL.LCD_RW;
	77	LCD_E <= LCD_CTRL.LCD_E;
	78
	79
	80	LCD_RET <= '0';
	81	LCD_CS1 <= '0';
	82	LCD_CS2 <= '0';
	83
	84	SF_CE0 <= '1';
	85
	86	rst <= not reset;
	87
	88
	89
	90	Driver0 : LCD_16x2_ENGINE
	91	generic map(50000)
	92	Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
	93
	94	FramBUFF(08+7 downto 08) <= X"41" when Bp0 = '1' else
	95	X"42" when Bp1 = '1' else
	96	X"43" when Bp2 = '1' else
	97	X"44";
	98
	99	FramBUFF(18+7 downto 18)<= X"46" when Bp0 = '1' else
	100	X"47" when Bp1 = '1' else
	101	X"48" when Bp2 = '1' else
	102	X"49";
	103
	104
	105	CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
	106	Duration_100us & CursorOFF;
	107
	108
	109	Exec <= Bp1;
	110
	111	FramBUFF(28+7 downto 28) <= X"23";
	112	FramBUFF(38+7 downto 38) <= X"66";
	113	FramBUFF(48+7 downto 48) <= X"67";
	114	FramBUFF(58+7 downto 58) <= X"68";
	115	FramBUFF(178+7 downto 178) <= X"69";
	116	--FramBUFF(1628-1 downto 16) <= (others => '0');
	117
	118	end Behavioral;
	119
	120
	121
	122
	123
	124

lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf created 644 +37 0

@@ -0,0 +1,37
	1
	2	NET "SF_CE0" LOC = "D16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	3
	4	NET "LCD_E" LOC = "M18" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	5
	6	NET "LCD_RS" LOC = "L18" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	7
	8	NET "LCD_RW" LOC = "L17" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	9
	10	NET "LCD_RET" LOC = "E3" \| IOSTANDARD = SSTL2_I;
	11	NET "LCD_CS1" LOC = "P3" \| IOSTANDARD = SSTL2_I;
	12	NET "LCD_CS2" LOC = "P4" \| IOSTANDARD = SSTL2_I;
	13
	14	NET "LCD_data<0>" LOC = "R15" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	15	NET "LCD_data<1>" LOC = "R16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	16	NET "LCD_data<2>" LOC = "P17" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	17	NET "LCD_data<3>" LOC = "M15" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	18	NET "LCD_data<4>" LOC = "M16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	19	NET "LCD_data<5>" LOC = "P6" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	20	NET "LCD_data<6>" LOC = "R8" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	21	NET "LCD_data<7>" LOC = "T8" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ;
	22
	23	NET "reset" LOC = "K17" \| IOSTANDARD = LVTTL \| PULLDOWN;
	24	NET "Bp0" LOC = "H13" \| IOSTANDARD = LVTTL \| PULLDOWN;
	25	NET "Bp1" LOC = "V4" \| IOSTANDARD = LVTTL \| PULLDOWN;
	26	NET "Bp2" LOC = "D18" \| IOSTANDARD = LVTTL \| PULLDOWN;
	27
	28	net "clk" LOC = "C9" \| IOSTANDARD = LVCMOS33;
	29	net "clk" PERIOD = 20.0ns HIGH 40%;
	30	#net "clkOUT" LOC = "N14" \| IOSTANDARD = LVCMOS33;
	31
	32	#net "STATEOUT<0>" LOC = "V5" \| IOSTANDARD = LVCMOS33 \| SLEW = FAST ;
	33	#net "STATEOUT<1>" LOC = "V6" \| IOSTANDARD = LVCMOS33 \| SLEW = FAST ;
	34	#net "STATEOUT<2>" LOC = "N12" \| IOSTANDARD = LVCMOS33 \| SLEW = FAST ;
	35	#net "STATEOUT<3>" LOC = "P12" \| IOSTANDARD = LVCMOS33 \| SLEW = FAST ;
	36
	37	#net "refreshPulse" LOC = "N15" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = SLOW ; No newline at end of file

lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd created 644 +162 0

@@ -0,0 +1,162
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19
	20	library ieee;
	21	use ieee.std_logic_1164.all;
	22
	23
	24
	25	package amba_lcd_16x2_ctrlr is
	26
	27
	28	type LCD_DRVR_CTRL_BUSS is
	29	record
	30	LCD_RW : std_logic;
	31	LCD_RS : std_logic;
	32	LCD_E : std_logic;
	33	LCD_DATA : std_logic_vector(7 downto 0);
	34	end record;
	35
	36	type LCD_DRVR_SYNCH_BUSS is
	37	record
	38	DRVR_READY : std_logic;
	39	LCD_INITIALISED : std_logic;
	40	end record;
	41
	42
	43	type LCD_DRVR_CMD_BUSS is
	44	record
	45	Word : std_logic_vector(7 downto 0);
	46	CMD_Data : std_logic; --CMD = '0' and data = '1'
	47	Exec : std_logic;
	48	Duration : std_logic_vector(1 downto 0);
	49	end record;
	50	type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
	51
	52
	53
	54
	55
	56
	57	component amba_lcd_16x2_driver is
	58	Port ( reset : in STD_LOGIC;
	59	clk : in STD_LOGIC;
	60	Bp0 : in STD_LOGIC;
	61	Bp1 : in STD_LOGIC;
	62	Bp2 : in STD_LOGIC;
	63	LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
	64	LCD_RS : out STD_LOGIC;
	65	LCD_RW : out STD_LOGIC;
	66	LCD_E : out STD_LOGIC;
	67	LCD_RET : out STD_LOGIC;
	68	LCD_CS1 : out STD_LOGIC;
	69	LCD_CS2 : out STD_LOGIC;
	70	SF_CE0 : out std_logic
	71	);
	72	end component;
	73
	74
	75
	76	component FRAME_CLK_GEN is
	77	generic(OSC_freqKHz : integer := 50000);
	78	Port ( clk : in STD_LOGIC;
	79	reset : in STD_LOGIC;
	80	FRAME_CLK : out STD_LOGIC);
	81	end component;
	82
	83
	84
	85	component LCD_2x16_DRIVER is
	86	generic(
	87	OSC_Freq_MHz : integer:=60;
	88	Refresh_RateHz : integer:=5
	89	);
	90	Port ( clk : in STD_LOGIC;
	91	reset : in STD_LOGIC;
	92	FramBUFF : in STD_LOGIC_VECTOR(1628-1 downto 0);
	93	LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
	94	LCD_RS : out STD_LOGIC;
	95	LCD_RW : out STD_LOGIC;
	96	LCD_E : out STD_LOGIC;
	97	LCD_RET : out STD_LOGIC;
	98	LCD_CS1 : out STD_LOGIC;
	99	LCD_CS2 : out STD_LOGIC;
	100	STATEOUT: out std_logic_vector(3 downto 0);
	101	refreshPulse : out std_logic
	102	);
	103	end component;
	104
	105
	106	component LCD_CLK_GENERATOR is
	107	generic(OSC_freqKHz : integer := 50000);
	108	Port ( clk : in STD_LOGIC;
	109	reset : in STD_LOGIC;
	110	clk_1us : out STD_LOGIC);
	111	end component;
	112
	113	component AMBA_LCD_16x2_DRIVER is
	114	Port ( reset : in STD_LOGIC;
	115	clk : in STD_LOGIC;
	116	Bp0 : in STD_LOGIC;
	117	Bp1 : in STD_LOGIC;
	118	Bp2 : in STD_LOGIC;
	119	LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
	120	LCD_RS : out STD_LOGIC;
	121	LCD_RW : out STD_LOGIC;
	122	LCD_E : out STD_LOGIC;
	123	LCD_RET : out STD_LOGIC;
	124	LCD_CS1 : out STD_LOGIC;
	125	LCD_CS2 : out STD_LOGIC;
	126	SF_CE0 : out std_logic
	127	);
	128	end component;
	129
	130	component LCD_16x2_ENGINE is
	131	generic(OSC_freqKHz : integer := 50000);
	132	Port ( clk : in STD_LOGIC;
	133	reset : in STD_LOGIC;
	134	DATA : in std_logic_vector(1628-1 downto 0);
	135	CMD : in std_logic_vector(10 downto 0);
	136	Exec : in std_logic;
	137	Ready : out std_logic;
	138	LCD_CTRL : out LCD_DRVR_CTRL_BUSS
	139	);
	140	end component;
	141
	142
	143	component AMBA_LCD_16x2_DRIVER is
	144	Port ( reset : in STD_LOGIC;
	145	clk : in STD_LOGIC;
	146	Bp0 : in STD_LOGIC;
	147	Bp1 : in STD_LOGIC;
	148	Bp2 : in STD_LOGIC;
	149	LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
	150	LCD_RS : out STD_LOGIC;
	151	LCD_RW : out STD_LOGIC;
	152	LCD_E : out STD_LOGIC;
	153	LCD_RET : out STD_LOGIC;
	154	LCD_CS1 : out STD_LOGIC;
	155	LCD_CS2 : out STD_LOGIC;
	156	SF_CE0 : out std_logic
	157	);
	158	end component;
	159
	160
	161
	162	end;

lib/lpp/amba_lcd_16x2_ctrlr/temp.sh created 644 +1 0

	@@ -0,0 +1,1
				1	ls\|grep .vhd\|grep -i -v test>vhdlsyn.txt

lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt created 644 +7 0

@@ -0,0 +1,7
	1	amba_lcd_16x2_ctrlr.vhd
	2	FRAME_CLK.vhd
	3	LCD_16x2_CFG.vhd
	4	LCD_16x2_ENGINE.vhd
	5	LCD_2x16_DRIVER.vhd
	6	LCD_CLK_GENERATOR.vhd
	7	Top_LCD.vhd

lib/lpp/dirs.txt created 644 +4 0

@@ -0,0 +1,4
	1	./general_purpose
	2	./lpp_amba
	3	./dsp/iir_filter
	4	./amba_lcd_16x2_ctrlr

lib/lpp/doc/html/installdox created 755 +117 0

@@ -0,0 +1,117
	1	#!/usr/bin/perl
	2
	3	%subst = ( );
	4	$quiet = 0;
	5
	6	if (open(F,"search.cfg"))
	7	{
	8	$_=<F> ; s/[ \t\n]*$//g ; $subst{"_doc"} = $_;
	9	$_=<F> ; s/[ \t\n]*$//g ; $subst{"_cgi"} = $_;
	10	}
	11
	12	while ( @ARGV ) {
	13	$_ = shift @ARGV;
	14	if ( s/^-// ) {
	15	if ( /^l(.*)/ ) {
	16	$v = ($1 eq "") ? shift @ARGV : $1;
	17	($v =~ /\/$/) \|\| ($v .= "/");
	18	$_ = $v;
	19	if ( /(.+)\@(.+)/ ) {
	20	if ( exists $subst{$1} ) {
	21	$subst{$1} = $2;
	22	} else {
	23	print STDERR "Unknown tag file $1 given with option -l\n";
	24	&usage();
	25	}
	26	} else {
	27	print STDERR "Argument $_ is invalid for option -l\n";
	28	&usage();
	29	}
	30	}
	31	elsif ( /^q/ ) {
	32	$quiet = 1;
	33	}
	34	elsif ( /^\?\|^h/ ) {
	35	&usage();
	36	}
	37	else {
	38	print STDERR "Illegal option -$_\n";
	39	&usage();
	40	}
	41	}
	42	else {
	43	push (@files, $_ );
	44	}
	45	}
	46
	47	foreach $sub (keys %subst)
	48	{
	49	if ( $subst{$sub} eq "" )
	50	{
	51	print STDERR "No substitute given for tag file `$sub'\n";
	52	&usage();
	53	}
	54	elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
	55	{
	56	print "Substituting $subst{$sub} for each occurrence of tag file $sub\n";
	57	}
	58	}
	59
	60	if ( ! @files ) {
	61	if (opendir(D,".")) {
	62	foreach $file ( readdir(D) ) {
	63	$match = ".html";
	64	next if ( $file =~ /^\.\.?$/ );
	65	($file =~ /$match/) && (push @files, $file);
	66	($file =~ "tree.js") && (push @files, $file);
	67	}
	68	closedir(D);
	69	}
	70	}
	71
	72	if ( ! @files ) {
	73	print STDERR "Warning: No input files given and none found!\n";
	74	}
	75
	76	foreach $f (@files)
	77	{
	78	if ( ! $quiet ) {
	79	print "Editing: $f...\n";
	80	}
	81	$oldf = $f;
	82	$f .= ".bak";
	83	unless (rename $oldf,$f) {
	84	print STDERR "Error: cannot rename file $oldf\n";
	85	exit 1;
	86	}
	87	if (open(F,"<$f")) {
	88	unless (open(G,">$oldf")) {
	89	print STDERR "Error: opening file $oldf for writing\n";
	90	exit 1;
	91	}
	92	if ($oldf ne "tree.js") {
	93	while (<F>) {
	94	s/doxygen\=\"([^ \"\:\t\>\<])\:([^ \"\t\>\<])\" (href\|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
	95	print G "$_";
	96	}
	97	}
	98	else {
	99	while (<F>) {
	100	s/\"([^ \"\:\t\>\<])\:([^ \"\t\>\<])\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
	101	print G "$_";
	102	}
	103	}
	104	}
	105	else {
	106	print STDERR "Warning file $f does not exist\n";
	107	}
	108	unlink $f;
	109	}
	110
	111	sub usage {
	112	print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
	113	print STDERR "Options:\n";
	114	print STDERR " -l tagfile\@linkName tag file + URL or directory \n";
	115	print STDERR " -q Quiet mode\n\n";
	116	exit 1;
	117	}

lib/lpp/doc/html/search/search.js created 644 +734 0

This diff has been collapsed as it changes many lines, (734 lines changed) Show them Hide them
	@@ -0,0 +1,734
		1	// Search script generated by doxygen
		2	// Copyright (C) 2009 by Dimitri van Heesch.
		3
		4	// The code in this file is loosly based on main.js, part of Natural Docs,
		5	// which is Copyright (C) 2003-2008 Greg Valure
		6	// Natural Docs is licensed under the GPL.
		7
		8	var indexSectionsWithContent =
		9	{
		10	0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101001111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
		11	1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101101001100001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
		12	2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101001100001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
		13	3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
		14	4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101001111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
		15	};
		16
		17	var indexSectionNames =
		18	{
		19	0: "all",
		20	1: "classes",
		21	2: "files",
		22	3: "functions",
		23	4: "variables"
		24	};
		25
		26	function convertToId(search)
		27	{
		28	var result = '';
		29	for (i=0;i<search.length;i++)
		30	{
		31	var c = search.charAt(i);
		32	var cn = c.charCodeAt(0);
		33	if (c.match(/[a-z0-9]/))
		34	{
		35	result+=c;
		36	}
		37	else if (cn<16)
		38	{
		39	result+="_0"+cn.toString(16);
		40	}
		41	else
		42	{
		43	result+="_"+cn.toString(16);
		44	}
		45	}
		46	return result;
		47	}
		48
		49	function getXPos(item)
		50	{
		51	var x = 0;
		52	if (item.offsetWidth)
		53	{
		54	while (item && item!=document.body)
		55	{
		56	x += item.offsetLeft;
		57	item = item.offsetParent;
		58	}
		59	}
		60	return x;
		61	}
		62
		63	function getYPos(item)
		64	{
		65	var y = 0;
		66	if (item.offsetWidth)
		67	{
		68	while (item && item!=document.body)
		69	{
		70	y += item.offsetTop;
		71	item = item.offsetParent;
		72	}
		73	}
		74	return y;
		75	}
		76
		77	/* A class handling everything associated with the search panel.
		78
		79	Parameters:
		80	name - The name of the global variable that will be
		81	storing this instance. Is needed to be able to set timeouts.
		82	resultPath - path to use for external files
		83	*/
		84	function SearchBox(name, resultsPath, inFrame, label)
		85	{
		86	if (!name \|\| !resultsPath) { alert("Missing parameters to SearchBox."); }
		87
		88	// ---------- Instance variables
		89	this.name = name;
		90	this.resultsPath = resultsPath;
		91	this.keyTimeout = 0;
		92	this.keyTimeoutLength = 500;
		93	this.closeSelectionTimeout = 300;
		94	this.lastSearchValue = "";
		95	this.lastResultsPage = "";
		96	this.hideTimeout = 0;
		97	this.searchIndex = 0;
		98	this.searchActive = false;
		99	this.insideFrame = inFrame;
		100	this.searchLabel = label;
		101
		102	// ----------- DOM Elements
		103
		104	this.DOMSearchField = function()
		105	{ return document.getElementById("MSearchField"); }
		106
		107	this.DOMSearchSelect = function()
		108	{ return document.getElementById("MSearchSelect"); }
		109
		110	this.DOMSearchSelectWindow = function()
		111	{ return document.getElementById("MSearchSelectWindow"); }
		112
		113	this.DOMPopupSearchResults = function()
		114	{ return document.getElementById("MSearchResults"); }
		115
		116	this.DOMPopupSearchResultsWindow = function()
		117	{ return document.getElementById("MSearchResultsWindow"); }
		118
		119	this.DOMSearchClose = function()
		120	{ return document.getElementById("MSearchClose"); }
		121
		122	this.DOMSearchBox = function()
		123	{ return document.getElementById("MSearchBox"); }
		124
		125	// ------------ Event Handlers
		126
		127	// Called when focus is added or removed from the search field.
		128	this.OnSearchFieldFocus = function(isActive)
		129	{
		130	this.Activate(isActive);
		131	}
		132
		133	this.OnSearchSelectShow = function()
		134	{
		135	var searchSelectWindow = this.DOMSearchSelectWindow();
		136	var searchField = this.DOMSearchSelect();
		137
		138	if (this.insideFrame)
		139	{
		140	var left = getXPos(searchField);
		141	var top = getYPos(searchField);
		142	left += searchField.offsetWidth + 6;
		143	top += searchField.offsetHeight;
		144
		145	// show search selection popup
		146	searchSelectWindow.style.display='block';
		147	left -= searchSelectWindow.offsetWidth;
		148	searchSelectWindow.style.left = left + 'px';
		149	searchSelectWindow.style.top = top + 'px';
		150	}
		151	else
		152	{
		153	var left = getXPos(searchField);
		154	var top = getYPos(searchField);
		155	top += searchField.offsetHeight;
		156
		157	// show search selection popup
		158	searchSelectWindow.style.display='block';
		159	searchSelectWindow.style.left = left + 'px';
		160	searchSelectWindow.style.top = top + 'px';
		161	}
		162
		163	// stop selection hide timer
		164	if (this.hideTimeout)
		165	{
		166	clearTimeout(this.hideTimeout);
		167	this.hideTimeout=0;
		168	}
		169	return false; // to avoid "image drag" default event
		170	}
		171
		172	this.OnSearchSelectHide = function()
		173	{
		174	this.hideTimeout = setTimeout(this.name +".CloseSelectionWindow()",
		175	this.closeSelectionTimeout);
		176	}
		177
		178	// Called when the content of the search field is changed.
		179	this.OnSearchFieldChange = function(evt)
		180	{
		181	if (this.keyTimeout) // kill running timer
		182	{
		183	clearTimeout(this.keyTimeout);
		184	this.keyTimeout = 0;
		185	}
		186
		187	var e = (evt) ? evt : window.event; // for IE
		188	if (e.keyCode==40 \|\| e.keyCode==13)
		189	{
		190	if (e.shiftKey==1)
		191	{
		192	this.OnSearchSelectShow();
		193	var win=this.DOMSearchSelectWindow();
		194	for (i=0;i<win.childNodes.length;i++)
		195	{
		196	var child = win.childNodes[i]; // get span within a
		197	if (child.className=='SelectItem')
		198	{
		199	child.focus();
		200	return;
		201	}
		202	}
		203	return;
		204	}
		205	else if (window.frames.MSearchResults.searchResults)
		206	{
		207	var elem = window.frames.MSearchResults.searchResults.NavNext(0);
		208	if (elem) elem.focus();
		209	}
		210	}
		211	else if (e.keyCode==27) // Escape out of the search field
		212	{
		213	this.DOMSearchField().blur();
		214	this.DOMPopupSearchResultsWindow().style.display = 'none';
		215	this.DOMSearchClose().style.display = 'none';
		216	this.lastSearchValue = '';
		217	this.Activate(false);
		218	return;
		219	}
		220
		221	// strip whitespaces
		222	var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
		223
		224	if (searchValue != this.lastSearchValue) // search value has changed
		225	{
		226	if (searchValue != "") // non-empty search
		227	{
		228	// set timer for search update
		229	this.keyTimeout = setTimeout(this.name + '.Search()',
		230	this.keyTimeoutLength);
		231	}
		232	else // empty search field
		233	{
		234	this.DOMPopupSearchResultsWindow().style.display = 'none';
		235	this.DOMSearchClose().style.display = 'none';
		236	this.lastSearchValue = '';
		237	}
		238	}
		239	}
		240
		241	this.SelectItemCount = function(id)
		242	{
		243	var count=0;
		244	var win=this.DOMSearchSelectWindow();
		245	for (i=0;i<win.childNodes.length;i++)
		246	{
		247	var child = win.childNodes[i]; // get span within a
		248	if (child.className=='SelectItem')
		249	{
		250	count++;
		251	}
		252	}
		253	return count;
		254	}
		255
		256	this.SelectItemSet = function(id)
		257	{
		258	var i,j=0;
		259	var win=this.DOMSearchSelectWindow();
		260	for (i=0;i<win.childNodes.length;i++)
		261	{
		262	var child = win.childNodes[i]; // get span within a
		263	if (child.className=='SelectItem')
		264	{
		265	var node = child.firstChild;
		266	if (j==id)
		267	{
		268	node.innerHTML='•';
		269	}
		270	else
		271	{
		272	node.innerHTML=' ';
		273	}
		274	j++;
		275	}
		276	}
		277	}
		278
		279	// Called when an search filter selection is made.
		280	// set item with index id as the active item
		281	this.OnSelectItem = function(id)
		282	{
		283	this.searchIndex = id;
		284	this.SelectItemSet(id);
		285	var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
		286	if (searchValue!="" && this.searchActive) // something was found -> do a search
		287	{
		288	this.Search();
		289	}
		290	}
		291
		292	this.OnSearchSelectKey = function(evt)
		293	{
		294	var e = (evt) ? evt : window.event; // for IE
		295	if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down
		296	{
		297	this.searchIndex++;
		298	this.OnSelectItem(this.searchIndex);
		299	}
		300	else if (e.keyCode==38 && this.searchIndex>0) // Up
		301	{
		302	this.searchIndex--;
		303	this.OnSelectItem(this.searchIndex);
		304	}
		305	else if (e.keyCode==13 \|\| e.keyCode==27)
		306	{
		307	this.OnSelectItem(this.searchIndex);
		308	this.CloseSelectionWindow();
		309	this.DOMSearchField().focus();
		310	}
		311	return false;
		312	}
		313
		314	// --------- Actions
		315
		316	// Closes the results window.
		317	this.CloseResultsWindow = function()
		318	{
		319	this.DOMPopupSearchResultsWindow().style.display = 'none';
		320	this.DOMSearchClose().style.display = 'none';
		321	this.Activate(false);
		322	}
		323
		324	this.CloseSelectionWindow = function()
		325	{
		326	this.DOMSearchSelectWindow().style.display = 'none';
		327	}
		328
		329	// Performs a search.
		330	this.Search = function()
		331	{
		332	this.keyTimeout = 0;
		333
		334	// strip leading whitespace
		335	var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
		336
		337	var code = searchValue.toLowerCase().charCodeAt(0);
		338	var hexCode;
		339	if (code<16)
		340	{
		341	hexCode="0"+code.toString(16);
		342	}
		343	else
		344	{
		345	hexCode=code.toString(16);
		346	}
		347
		348	var resultsPage;
		349	var resultsPageWithSearch;
		350	var hasResultsPage;
		351
		352	if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
		353	{
		354	resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
		355	resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
		356	hasResultsPage = true;
		357	}
		358	else // nothing available for this search term
		359	{
		360	resultsPage = this.resultsPath + '/nomatches.html';
		361	resultsPageWithSearch = resultsPage;
		362	hasResultsPage = false;
		363	}
		364
		365	window.frames.MSearchResults.location.href = resultsPageWithSearch;
		366	var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
		367
		368	if (domPopupSearchResultsWindow.style.display!='block')
		369	{
		370	var domSearchBox = this.DOMSearchBox();
		371	this.DOMSearchClose().style.display = 'inline';
		372	if (this.insideFrame)
		373	{
		374	var domPopupSearchResults = this.DOMPopupSearchResults();
		375	domPopupSearchResultsWindow.style.position = 'relative';
		376	domPopupSearchResultsWindow.style.display = 'block';
		377	var width = document.body.clientWidth - 8; // the -8 is for IE :-(
		378	domPopupSearchResultsWindow.style.width = width + 'px';
		379	domPopupSearchResults.style.width = width + 'px';
		380	}
		381	else
		382	{
		383	var domPopupSearchResults = this.DOMPopupSearchResults();
		384	var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
		385	var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1;
		386	domPopupSearchResultsWindow.style.display = 'block';
		387	left -= domPopupSearchResults.offsetWidth;
		388	domPopupSearchResultsWindow.style.top = top + 'px';
		389	domPopupSearchResultsWindow.style.left = left + 'px';
		390	}
		391	}
		392
		393	this.lastSearchValue = searchValue;
		394	this.lastResultsPage = resultsPage;
		395	}
		396
		397	// -------- Activation Functions
		398
		399	// Activates or deactivates the search panel, resetting things to
		400	// their default values if necessary.
		401	this.Activate = function(isActive)
		402	{
		403	if (isActive \|\| // open it
		404	this.DOMPopupSearchResultsWindow().style.display == 'block'
		405	)
		406	{
		407	this.DOMSearchBox().className = 'MSearchBoxActive';
		408
		409	var searchField = this.DOMSearchField();
		410
		411	if (searchField.value == this.searchLabel) // clear "Search" term upon entry
		412	{
		413	searchField.value = '';
		414	this.searchActive = true;
		415	}
		416	}
		417	else if (!isActive) // directly remove the panel
		418	{
		419	this.DOMSearchBox().className = 'MSearchBoxInactive';
		420	this.DOMSearchField().value = this.searchLabel;
		421	this.searchActive = false;
		422	this.lastSearchValue = ''
		423	this.lastResultsPage = '';
		424	}
		425	}
		426	}
		427
		428	// -----------------------------------------------------------------------
		429
		430	// The class that handles everything on the search results page.
		431	function SearchResults(name)
		432	{
		433	// The number of matches from the last run of <Search()>.
		434	this.lastMatchCount = 0;
		435	this.lastKey = 0;
		436	this.repeatOn = false;
		437
		438	// Toggles the visibility of the passed element ID.
		439	this.FindChildElement = function(id)
		440	{
		441	var parentElement = document.getElementById(id);
		442	var element = parentElement.firstChild;
		443
		444	while (element && element!=parentElement)
		445	{
		446	if (element.nodeName == 'DIV' && element.className == 'SRChildren')
		447	{
		448	return element;
		449	}
		450
		451	if (element.nodeName == 'DIV' && element.hasChildNodes())
		452	{
		453	element = element.firstChild;
		454	}
		455	else if (element.nextSibling)
		456	{
		457	element = element.nextSibling;
		458	}
		459	else
		460	{
		461	do
		462	{
		463	element = element.parentNode;
		464	}
		465	while (element && element!=parentElement && !element.nextSibling);
		466
		467	if (element && element!=parentElement)
		468	{
		469	element = element.nextSibling;
		470	}
		471	}
		472	}
		473	}
		474
		475	this.Toggle = function(id)
		476	{
		477	var element = this.FindChildElement(id);
		478	if (element)
		479	{
		480	if (element.style.display == 'block')
		481	{
		482	element.style.display = 'none';
		483	}
		484	else
		485	{
		486	element.style.display = 'block';
		487	}
		488	}
		489	}
		490
		491	// Searches for the passed string. If there is no parameter,
		492	// it takes it from the URL query.
		493	//
		494	// Always returns true, since other documents may try to call it
		495	// and that may or may not be possible.
		496	this.Search = function(search)
		497	{
		498	if (!search) // get search word from URL
		499	{
		500	search = window.location.search;
		501	search = search.substring(1); // Remove the leading '?'
		502	search = unescape(search);
		503	}
		504
		505	search = search.replace(/^ +/, ""); // strip leading spaces
		506	search = search.replace(/ +$/, ""); // strip trailing spaces
		507	search = search.toLowerCase();
		508	search = convertToId(search);
		509
		510	var resultRows = document.getElementsByTagName("div");
		511	var matches = 0;
		512
		513	var i = 0;
		514	while (i < resultRows.length)
		515	{
		516	var row = resultRows.item(i);
		517	if (row.className == "SRResult")
		518	{
		519	var rowMatchName = row.id.toLowerCase();
		520	rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
		521
		522	if (search.length<=rowMatchName.length &&
		523	rowMatchName.substr(0, search.length)==search)
		524	{
		525	row.style.display = 'block';
		526	matches++;
		527	}
		528	else
		529	{
		530	row.style.display = 'none';
		531	}
		532	}
		533	i++;
		534	}
		535	document.getElementById("Searching").style.display='none';
		536	if (matches == 0) // no results
		537	{
		538	document.getElementById("NoMatches").style.display='block';
		539	}
		540	else // at least one result
		541	{
		542	document.getElementById("NoMatches").style.display='none';
		543	}
		544	this.lastMatchCount = matches;
		545	return true;
		546	}
		547
		548	// return the first item with index index or higher that is visible
		549	this.NavNext = function(index)
		550	{
		551	var focusItem;
		552	while (1)
		553	{
		554	var focusName = 'Item'+index;
		555	focusItem = document.getElementById(focusName);
		556	if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
		557	{
		558	break;
		559	}
		560	else if (!focusItem) // last element
		561	{
		562	break;
		563	}
		564	focusItem=null;
		565	index++;
		566	}
		567	return focusItem;
		568	}
		569
		570	this.NavPrev = function(index)
		571	{
		572	var focusItem;
		573	while (1)
		574	{
		575	var focusName = 'Item'+index;
		576	focusItem = document.getElementById(focusName);
		577	if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
		578	{
		579	break;
		580	}
		581	else if (!focusItem) // last element
		582	{
		583	break;
		584	}
		585	focusItem=null;
		586	index--;
		587	}
		588	return focusItem;
		589	}
		590
		591	this.ProcessKeys = function(e)
		592	{
		593	if (e.type == "keydown")
		594	{
		595	this.repeatOn = false;
		596	this.lastKey = e.keyCode;
		597	}
		598	else if (e.type == "keypress")
		599	{
		600	if (!this.repeatOn)
		601	{
		602	if (this.lastKey) this.repeatOn = true;
		603	return false; // ignore first keypress after keydown
		604	}
		605	}
		606	else if (e.type == "keyup")
		607	{
		608	this.lastKey = 0;
		609	this.repeatOn = false;
		610	}
		611	return this.lastKey!=0;
		612	}
		613
		614	this.Nav = function(evt,itemIndex)
		615	{
		616	var e = (evt) ? evt : window.event; // for IE
		617	if (e.keyCode==13) return true;
		618	if (!this.ProcessKeys(e)) return false;
		619
		620	if (this.lastKey==38) // Up
		621	{
		622	var newIndex = itemIndex-1;
		623	var focusItem = this.NavPrev(newIndex);
		624	if (focusItem)
		625	{
		626	var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
		627	if (child && child.style.display == 'block') // children visible
		628	{
		629	var n=0;
		630	var tmpElem;
		631	while (1) // search for last child
		632	{
		633	tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
		634	if (tmpElem)
		635	{
		636	focusItem = tmpElem;
		637	}
		638	else // found it!
		639	{
		640	break;
		641	}
		642	n++;
		643	}
		644	}
		645	}
		646	if (focusItem)
		647	{
		648	focusItem.focus();
		649	}
		650	else // return focus to search field
		651	{
		652	parent.document.getElementById("MSearchField").focus();
		653	}
		654	}
		655	else if (this.lastKey==40) // Down
		656	{
		657	var newIndex = itemIndex+1;
		658	var focusItem;
		659	var item = document.getElementById('Item'+itemIndex);
		660	var elem = this.FindChildElement(item.parentNode.parentNode.id);
		661	if (elem && elem.style.display == 'block') // children visible
		662	{
		663	focusItem = document.getElementById('Item'+itemIndex+'_c0');
		664	}
		665	if (!focusItem) focusItem = this.NavNext(newIndex);
		666	if (focusItem) focusItem.focus();
		667	}
		668	else if (this.lastKey==39) // Right
		669	{
		670	var item = document.getElementById('Item'+itemIndex);
		671	var elem = this.FindChildElement(item.parentNode.parentNode.id);
		672	if (elem) elem.style.display = 'block';
		673	}
		674	else if (this.lastKey==37) // Left
		675	{
		676	var item = document.getElementById('Item'+itemIndex);
		677	var elem = this.FindChildElement(item.parentNode.parentNode.id);
		678	if (elem) elem.style.display = 'none';
		679	}
		680	else if (this.lastKey==27) // Escape
		681	{
		682	parent.searchBox.CloseResultsWindow();
		683	parent.document.getElementById("MSearchField").focus();
		684	}
		685	else if (this.lastKey==13) // Enter
		686	{
		687	return true;
		688	}
		689	return false;
		690	}
		691
		692	this.NavChild = function(evt,itemIndex,childIndex)
		693	{
		694	var e = (evt) ? evt : window.event; // for IE
		695	if (e.keyCode==13) return true;
		696	if (!this.ProcessKeys(e)) return false;
		697
		698	if (this.lastKey==38) // Up
		699	{
		700	if (childIndex>0)
		701	{
		702	var newIndex = childIndex-1;
		703	document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
		704	}
		705	else // already at first child, jump to parent
		706	{
		707	document.getElementById('Item'+itemIndex).focus();
		708	}
		709	}
		710	else if (this.lastKey==40) // Down
		711	{
		712	var newIndex = childIndex+1;
		713	var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
		714	if (!elem) // last child, jump to parent next parent
		715	{
		716	elem = this.NavNext(itemIndex+1);
		717	}
		718	if (elem)
		719	{
		720	elem.focus();
		721	}
		722	}
		723	else if (this.lastKey==27) // Escape
		724	{
		725	parent.searchBox.CloseResultsWindow();
		726	parent.document.getElementById("MSearchField").focus();
		727	}
		728	else if (this.lastKey==13) // Enter
		729	{
		730	return true;
		731	}
		732	return false;
		733	}
		734	}

lib/lpp/doc/latex/Makefile created 644 +19 0

@@ -0,0 +1,19
	1	all: clean refman.pdf
	2
	3	pdf: refman.pdf
	4
	5	refman.pdf: refman.tex
	6	pdflatex refman.tex
	7	makeindex refman.idx
	8	pdflatex refman.tex
	9	latex_count=5 ; \
	10	while egrep -s 'Rerun (LaTeX\|to get cross-references right)' refman.log && [ $$latex_count -gt 0 ] ;\
	11	do \
	12	echo "Rerunning latex...." ;\
	13	pdflatex refman.tex ;\
	14	latex_count=`expr $$latex_count - 1` ;\
	15	done
	16
	17
	18	clean:
	19	rm -f .ps .dvi .aux .toc .idx .ind .ilg .log *.out refman.pdf

lib/lpp/doc/latex/doxygen.sty created 644 +356 0

@@ -0,0 +1,356
	1	\NeedsTeXFormat{LaTeX2e}
	2	\ProvidesPackage{doxygen}
	3
	4	% Packages used by this style file
	5	\RequirePackage{alltt}
	6	\RequirePackage{array}
	7	\RequirePackage{calc}
	8	\RequirePackage{color}
	9	\RequirePackage{fancyhdr}
	10	\RequirePackage{verbatim}
	11
	12	% Setup fancy headings
	13	\pagestyle{fancyplain}
	14	\newcommand{\clearemptydoublepage}{%
	15	\newpage{\pagestyle{empty}\cleardoublepage}%
	16	}
	17	\renewcommand{\chaptermark}[1]{%
	18	\markboth{#1}{}%
	19	}
	20	\renewcommand{\sectionmark}[1]{%
	21	\markright{\thesection\ #1}%
	22	}
	23	\lhead[\fancyplain{}{\bfseries\thepage}]{%
	24	\fancyplain{}{\bfseries\rightmark}%
	25	}
	26	\rhead[\fancyplain{}{\bfseries\leftmark}]{%
	27	\fancyplain{}{\bfseries\thepage}%
	28	}
	29	\rfoot[\fancyplain{}{\bfseries\scriptsize%
	30	Generated on Tue Oct 26 2010 19:42:42 for lib-\/lpp by Doxygen }]{}
	31	\lfoot[]{\fancyplain{}{\bfseries\scriptsize%
	32	Generated on Tue Oct 26 2010 19:42:42 for lib-\/lpp by Doxygen }}
	33	\cfoot{}
	34
	35	%---------- Internal commands used in this style file ----------------
	36
	37	% Generic environment used by all paragraph-based environments defined
	38	% below. Note that the command \title{...} needs to be defined inside
	39	% those environments!
	40	\newenvironment{DoxyDesc}[1]{%
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lib/lpp/doc/latex/refman.aux created 644 +1866 0

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		1	\indexentry{Adder@{Adder}\|hyperpage}{7}
		2	\indexentry{Adder@{Adder}!add@{add}\|hyperpage}{9}
		3	\indexentry{add@{add}!Adder@{Adder}\|hyperpage}{9}
		4	\indexentry{Adder@{Adder}!clk@{clk}\|hyperpage}{9}
		5	\indexentry{clk@{clk}!Adder@{Adder}\|hyperpage}{9}
		6	\indexentry{Adder@{Adder}!clr@{clr}\|hyperpage}{9}
		7	\indexentry{clr@{clr}!Adder@{Adder}\|hyperpage}{9}
		8	\indexentry{Adder@{Adder}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{9}
		9	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!Adder@{Adder}\|hyperpage}{9}
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		14	\indexentry{Adder@{Adder}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}\|hyperpage}{9}
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		16	\indexentry{Adder@{Adder}!lpp@{lpp}\|hyperpage}{9}
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		21	\indexentry{OP1@{OP1}!Adder@{Adder}\|hyperpage}{9}
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		23	\indexentry{OP2@{OP2}!Adder@{Adder}\|hyperpage}{9}
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		30	\indexentry{ADDRcntr@{ADDRcntr}\|hyperpage}{9}
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		33	\indexentry{ADDRcntr@{ADDRcntr}!clr@{clr}\|hyperpage}{11}
		34	\indexentry{clr@{clr}!ADDRcntr@{ADDRcntr}\|hyperpage}{11}
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		80	\indexentry{ALU@{ALU}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{13}
		81	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!ALU@{ALU}\|hyperpage}{13}
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		84	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}driver@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}driver}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		85	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{14}
		86	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		87	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{14}
		88	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		89	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!ieee@{ieee}\|hyperpage}{14}
		90	\indexentry{ieee@{ieee}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		91	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{14}
		92	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		93	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{14}
		94	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
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		96	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		97	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{14}
		98	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!amba_lcd_16x2_ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{14}
		99	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{15}
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		101	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		102	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!Bp0@{Bp0}\|hyperpage}{16}
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		104	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!Bp1@{Bp1}\|hyperpage}{16}
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		111	\indexentry{IEEE@{IEEE}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
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		114	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}CS1@{LCD\_\discretionary {-}{}{}CS1}\|hyperpage}{16}
		115	\indexentry{LCD\_\discretionary {-}{}{}CS1@{LCD\_\discretionary {-}{}{}CS1}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		116	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}CS2@{LCD\_\discretionary {-}{}{}CS2}\|hyperpage}{16}
		117	\indexentry{LCD\_\discretionary {-}{}{}CS2@{LCD\_\discretionary {-}{}{}CS2}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		118	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}data@{LCD\_\discretionary {-}{}{}data}\|hyperpage}{16}
		119	\indexentry{LCD\_\discretionary {-}{}{}data@{LCD\_\discretionary {-}{}{}data}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		120	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}\|hyperpage}{16}
		121	\indexentry{LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		122	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RET@{LCD\_\discretionary {-}{}{}RET}\|hyperpage}{16}
		123	\indexentry{LCD\_\discretionary {-}{}{}RET@{LCD\_\discretionary {-}{}{}RET}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		124	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}\|hyperpage}{16}
		125	\indexentry{LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		126	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}\|hyperpage}{16}
		127	\indexentry{LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		128	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!lpp@{lpp}\|hyperpage}{16}
		129	\indexentry{lpp@{lpp}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		130	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!reset@{reset}\|hyperpage}{16}
		131	\indexentry{reset@{reset}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		132	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!SF\_\discretionary {-}{}{}CE0@{SF\_\discretionary {-}{}{}CE0}\|hyperpage}{16}
		133	\indexentry{SF\_\discretionary {-}{}{}CE0@{SF\_\discretionary {-}{}{}CE0}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{16}
		134	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}\|hyperpage}{17}
		135	\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!AMBA_LCD_16x2_DRIVER@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER}\|hyperpage}{17}
		136	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{17}
		137	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!abits@{abits}\|hyperpage}{18}
		138	\indexentry{abits@{abits}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		139	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!amba@{amba}\|hyperpage}{18}
		140	\indexentry{amba@{amba}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		141	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!apbi@{apbi}\|hyperpage}{18}
		142	\indexentry{apbi@{apbi}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		143	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!apbo@{apbo}\|hyperpage}{18}
		144	\indexentry{apbo@{apbo}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		145	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!clk@{clk}\|hyperpage}{18}
		146	\indexentry{clk@{clk}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		147	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!devices@{devices}\|hyperpage}{18}
		148	\indexentry{devices@{devices}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		149	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!FILTERcfg@{FILTERcfg}\|hyperpage}{18}
		150	\indexentry{FILTERcfg@{FILTERcfg}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		151	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{18}
		152	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		153	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!grlib@{grlib}\|hyperpage}{18}
		154	\indexentry{grlib@{grlib}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{18}
		155	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!ieee@{ieee}\|hyperpage}{19}
		156	\indexentry{ieee@{ieee}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		157	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{19}
		158	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		159	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!lpp@{lpp}\|hyperpage}{19}
		160	\indexentry{lpp@{lpp}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		161	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{19}
		162	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		163	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!paddr@{paddr}\|hyperpage}{19}
		164	\indexentry{paddr@{paddr}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		165	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!pindex@{pindex}\|hyperpage}{19}
		166	\indexentry{pindex@{pindex}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		167	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!pirq@{pirq}\|hyperpage}{19}
		168	\indexentry{pirq@{pirq}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		169	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!pmask@{pmask}\|hyperpage}{19}
		170	\indexentry{pmask@{pmask}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		171	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!rst@{rst}\|hyperpage}{19}
		172	\indexentry{rst@{rst}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		173	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}\|hyperpage}{19}
		174	\indexentry{sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		175	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out}\|hyperpage}{19}
		176	\indexentry{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		177	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}\|hyperpage}{19}
		178	\indexentry{sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		179	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}\|hyperpage}{19}
		180	\indexentry{sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		181	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!Sample\_\discretionary {-}{}{}SZ@{Sample\_\discretionary {-}{}{}SZ}\|hyperpage}{19}
		182	\indexentry{Sample\_\discretionary {-}{}{}SZ@{Sample\_\discretionary {-}{}{}SZ}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		183	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{19}
		184	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		185	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!stdlib@{stdlib}\|hyperpage}{19}
		186	\indexentry{stdlib@{stdlib}!APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{19}
		187	\indexentry{Adder::ar\_\discretionary {-}{}{}Adder@{Adder::ar\_\discretionary {-}{}{}Adder}\|hyperpage}{20}
		188	\indexentry{Adder::ar\_\discretionary {-}{}{}Adder@{Adder::ar\_\discretionary {-}{}{}Adder}!PROCESS\_\discretionary {-}{}{}11@{PROCESS\_\discretionary {-}{}{}11}\|hyperpage}{21}
		189	\indexentry{PROCESS\_\discretionary {-}{}{}11@{PROCESS\_\discretionary {-}{}{}11}!Adder::ar_Adder@{Adder::ar\_\discretionary {-}{}{}Adder}\|hyperpage}{21}
		190	\indexentry{Adder::ar\_\discretionary {-}{}{}Adder@{Adder::ar\_\discretionary {-}{}{}Adder}!REG@{REG}\|hyperpage}{21}
		191	\indexentry{REG@{REG}!Adder::ar_Adder@{Adder::ar\_\discretionary {-}{}{}Adder}\|hyperpage}{21}
		192	\indexentry{Adder::ar\_\discretionary {-}{}{}Adder@{Adder::ar\_\discretionary {-}{}{}Adder}!RESADD@{RESADD}\|hyperpage}{21}
		193	\indexentry{RESADD@{RESADD}!Adder::ar_Adder@{Adder::ar\_\discretionary {-}{}{}Adder}\|hyperpage}{21}
		194	\indexentry{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr@{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr}\|hyperpage}{21}
		195	\indexentry{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr@{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr}!PROCESS\_\discretionary {-}{}{}12@{PROCESS\_\discretionary {-}{}{}12}\|hyperpage}{22}
		196	\indexentry{PROCESS\_\discretionary {-}{}{}12@{PROCESS\_\discretionary {-}{}{}12}!ADDRcntr::ar_ADDRcntr@{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr}\|hyperpage}{22}
		197	\indexentry{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr@{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr}!reg@{reg}\|hyperpage}{22}
		198	\indexentry{reg@{reg}!ADDRcntr::ar_ADDRcntr@{ADDRcntr::ar\_\discretionary {-}{}{}ADDRcntr}\|hyperpage}{22}
		199	\indexentry{ALU::ar\_\discretionary {-}{}{}ALU@{ALU::ar\_\discretionary {-}{}{}ALU}\|hyperpage}{22}
		200	\indexentry{ALU::ar\_\discretionary {-}{}{}ALU@{ALU::ar\_\discretionary {-}{}{}ALU}!PROCESS\_\discretionary {-}{}{}13@{PROCESS\_\discretionary {-}{}{}13}\|hyperpage}{23}
		201	\indexentry{PROCESS\_\discretionary {-}{}{}13@{PROCESS\_\discretionary {-}{}{}13}!ALU::ar_ALU@{ALU::ar\_\discretionary {-}{}{}ALU}\|hyperpage}{23}
		202	\indexentry{ALU::ar\_\discretionary {-}{}{}ALU@{ALU::ar\_\discretionary {-}{}{}ALU}!clr\_\discretionary {-}{}{}MAC@{clr\_\discretionary {-}{}{}MAC}\|hyperpage}{23}
		203	\indexentry{clr\_\discretionary {-}{}{}MAC@{clr\_\discretionary {-}{}{}MAC}!ALU::ar_ALU@{ALU::ar\_\discretionary {-}{}{}ALU}\|hyperpage}{23}
		204	\indexentry{ALU::ar\_\discretionary {-}{}{}ALU@{ALU::ar\_\discretionary {-}{}{}ALU}!MACinst@{MACinst}\|hyperpage}{23}
		205	\indexentry{MACinst@{MACinst}!ALU::ar_ALU@{ALU::ar\_\discretionary {-}{}{}ALU}\|hyperpage}{23}
		206	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{23}
		207	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!PROCESS\_\discretionary {-}{}{}4@{PROCESS\_\discretionary {-}{}{}4}\|hyperpage}{24}
		208	\indexentry{PROCESS\_\discretionary {-}{}{}4@{PROCESS\_\discretionary {-}{}{}4}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		209	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!PROCESS\_\discretionary {-}{}{}5@{PROCESS\_\discretionary {-}{}{}5}\|hyperpage}{24}
		210	\indexentry{PROCESS\_\discretionary {-}{}{}5@{PROCESS\_\discretionary {-}{}{}5}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		211	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!regin@{regin}\|hyperpage}{24}
		212	\indexentry{regin@{regin}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		213	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!regout@{regout}\|hyperpage}{24}
		214	\indexentry{regout@{regout}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		215	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!bootmsg@{bootmsg}\|hyperpage}{24}
		216	\indexentry{bootmsg@{bootmsg}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		217	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!filter@{filter}\|hyperpage}{24}
		218	\indexentry{filter@{filter}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		219	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!filter\_\discretionary {-}{}{}reset@{filter\_\discretionary {-}{}{}reset}\|hyperpage}{24}
		220	\indexentry{filter\_\discretionary {-}{}{}reset@{filter\_\discretionary {-}{}{}reset}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		221	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!FILTERreg@{FILTERreg}\|hyperpage}{24}
		222	\indexentry{FILTERreg@{FILTERreg}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		223	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!pconfig@{pconfig}\|hyperpage}{24}
		224	\indexentry{pconfig@{pconfig}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		225	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!r@{r}\|hyperpage}{24}
		226	\indexentry{r@{r}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		227	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!REVISION@{REVISION}\|hyperpage}{24}
		228	\indexentry{REVISION@{REVISION}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		229	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out\_\discretionary {-}{}{}R@{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out\_\discretionary {-}{}{}R}\|hyperpage}{24}
		230	\indexentry{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out\_\discretionary {-}{}{}R@{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}out\_\discretionary {-}{}{}R}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		231	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!smp\_\discretionary {-}{}{}cnt@{smp\_\discretionary {-}{}{}cnt}\|hyperpage}{24}
		232	\indexentry{smp\_\discretionary {-}{}{}cnt@{smp\_\discretionary {-}{}{}cnt}!APB_IIR_CEL::AR_APB_IIR_CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL::AR\_\discretionary {-}{}{}APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{24}
		233	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		234	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}!ALU1@{ALU1}\|hyperpage}{25}
		235	\indexentry{ALU1@{ALU1}!FILTER::ar_FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		236	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}!ALU\_\discretionary {-}{}{}ctrl@{ALU\_\discretionary {-}{}{}ctrl}\|hyperpage}{25}
		237	\indexentry{ALU\_\discretionary {-}{}{}ctrl@{ALU\_\discretionary {-}{}{}ctrl}!FILTER::ar_FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		238	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}!ALU\_\discretionary {-}{}{}OUT@{ALU\_\discretionary {-}{}{}OUT}\|hyperpage}{25}
		239	\indexentry{ALU\_\discretionary {-}{}{}OUT@{ALU\_\discretionary {-}{}{}OUT}!FILTER::ar_FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		240	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}!Coef@{Coef}\|hyperpage}{25}
		241	\indexentry{Coef@{Coef}!FILTER::ar_FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		242	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}!filterctrlr1@{filterctrlr1}\|hyperpage}{25}
		243	\indexentry{filterctrlr1@{filterctrlr1}!FILTER::ar_FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		244	\indexentry{FILTER::ar\_\discretionary {-}{}{}FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}!Sample@{Sample}\|hyperpage}{25}
		245	\indexentry{Sample@{Sample}!FILTER::ar_FILTER@{FILTER::ar\_\discretionary {-}{}{}FILTER}\|hyperpage}{25}
		246	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{26}
		247	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!ADDRcntr\_\discretionary {-}{}{}inst@{ADDRcntr\_\discretionary {-}{}{}inst}\|hyperpage}{28}
		248	\indexentry{ADDRcntr\_\discretionary {-}{}{}inst@{ADDRcntr\_\discretionary {-}{}{}inst}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		249	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!ADDRreg@{ADDRreg}\|hyperpage}{28}
		250	\indexentry{ADDRreg@{ADDRreg}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		251	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!MUX2\_\discretionary {-}{}{}inst1@{MUX2\_\discretionary {-}{}{}inst1}\|hyperpage}{28}
		252	\indexentry{MUX2\_\discretionary {-}{}{}inst1@{MUX2\_\discretionary {-}{}{}inst1}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		253	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!MUX2\_\discretionary {-}{}{}inst1\_\discretionary {-}{}{}sel@{MUX2\_\discretionary {-}{}{}inst1\_\discretionary {-}{}{}sel}\|hyperpage}{28}
		254	\indexentry{MUX2\_\discretionary {-}{}{}inst1\_\discretionary {-}{}{}sel@{MUX2\_\discretionary {-}{}{}inst1\_\discretionary {-}{}{}sel}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		255	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!MUX2\_\discretionary {-}{}{}inst2@{MUX2\_\discretionary {-}{}{}inst2}\|hyperpage}{28}
		256	\indexentry{MUX2\_\discretionary {-}{}{}inst2@{MUX2\_\discretionary {-}{}{}inst2}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		257	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!next\_\discretionary {-}{}{}blk\_\discretionary {-}{}{}D@{next\_\discretionary {-}{}{}blk\_\discretionary {-}{}{}D}\|hyperpage}{28}
		258	\indexentry{next\_\discretionary {-}{}{}blk\_\discretionary {-}{}{}D@{next\_\discretionary {-}{}{}blk\_\discretionary {-}{}{}D}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		259	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!next\_\discretionary {-}{}{}blkRreg@{next\_\discretionary {-}{}{}blkRreg}\|hyperpage}{28}
		260	\indexentry{next\_\discretionary {-}{}{}blkRreg@{next\_\discretionary {-}{}{}blkRreg}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		261	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!RADDR@{RADDR}\|hyperpage}{28}
		262	\indexentry{RADDR@{RADDR}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		263	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!RAMblk@{RAMblk}\|hyperpage}{28}
		264	\indexentry{RAMblk@{RAMblk}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		265	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!RAMblk@{RAMblk}\|hyperpage}{28}
		266	\indexentry{RAMblk@{RAMblk}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		267	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!RD@{RD}\|hyperpage}{28}
		268	\indexentry{RD@{RD}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		269	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!REN@{REN}\|hyperpage}{28}
		270	\indexentry{REN@{REN}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		271	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!run\_\discretionary {-}{}{}D@{run\_\discretionary {-}{}{}D}\|hyperpage}{28}
		272	\indexentry{run\_\discretionary {-}{}{}D@{run\_\discretionary {-}{}{}D}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		273	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!run\_\discretionary {-}{}{}D\_\discretionary {-}{}{}inv@{run\_\discretionary {-}{}{}D\_\discretionary {-}{}{}inv}\|hyperpage}{28}
		274	\indexentry{run\_\discretionary {-}{}{}D\_\discretionary {-}{}{}inv@{run\_\discretionary {-}{}{}D\_\discretionary {-}{}{}inv}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		275	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!run\_\discretionary {-}{}{}inv@{run\_\discretionary {-}{}{}inv}\|hyperpage}{28}
		276	\indexentry{run\_\discretionary {-}{}{}inv@{run\_\discretionary {-}{}{}inv}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		277	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!RunRreg@{RunRreg}\|hyperpage}{28}
		278	\indexentry{RunRreg@{RunRreg}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		279	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WADDR@{WADDR}\|hyperpage}{28}
		280	\indexentry{WADDR@{WADDR}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		281	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WADDR\_\discretionary {-}{}{}back@{WADDR\_\discretionary {-}{}{}back}\|hyperpage}{28}
		282	\indexentry{WADDR\_\discretionary {-}{}{}back@{WADDR\_\discretionary {-}{}{}back}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		283	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D}\|hyperpage}{28}
		284	\indexentry{WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		285	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WADDR\_\discretionary {-}{}{}backreg@{WADDR\_\discretionary {-}{}{}backreg}\|hyperpage}{28}
		286	\indexentry{WADDR\_\discretionary {-}{}{}backreg@{WADDR\_\discretionary {-}{}{}backreg}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		287	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WADDR\_\discretionary {-}{}{}backreg2@{WADDR\_\discretionary {-}{}{}backreg2}\|hyperpage}{28}
		288	\indexentry{WADDR\_\discretionary {-}{}{}backreg2@{WADDR\_\discretionary {-}{}{}backreg2}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		289	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WADDR\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}D}\|hyperpage}{28}
		290	\indexentry{WADDR\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}D}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		291	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WD@{WD}\|hyperpage}{28}
		292	\indexentry{WD@{WD}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		293	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WD\_\discretionary {-}{}{}D@{WD\_\discretionary {-}{}{}D}\|hyperpage}{28}
		294	\indexentry{WD\_\discretionary {-}{}{}D@{WD\_\discretionary {-}{}{}D}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		295	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WDRreg@{WDRreg}\|hyperpage}{28}
		296	\indexentry{WDRreg@{WDRreg}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		297	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!WEN@{WEN}\|hyperpage}{28}
		298	\indexentry{WEN@{WEN}!FILTER_RAM_CTRLR::ar_FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{28}
		299	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{29}
		300	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!PROCESS\_\discretionary {-}{}{}6@{PROCESS\_\discretionary {-}{}{}6}\|hyperpage}{30}
		301	\indexentry{PROCESS\_\discretionary {-}{}{}6@{PROCESS\_\discretionary {-}{}{}6}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		302	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!ADDR@{ADDR}\|hyperpage}{30}
		303	\indexentry{ADDR@{ADDR}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		304	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!ADDR\_\discretionary {-}{}{}D@{ADDR\_\discretionary {-}{}{}D}\|hyperpage}{30}
		305	\indexentry{ADDR\_\discretionary {-}{}{}D@{ADDR\_\discretionary {-}{}{}D}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		306	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!ADDRreg@{ADDRreg}\|hyperpage}{30}
		307	\indexentry{ADDRreg@{ADDRreg}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		308	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!chanelCnt@{chanelCnt}\|hyperpage}{30}
		309	\indexentry{chanelCnt@{chanelCnt}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		310	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!clk\_\discretionary {-}{}{}inv@{clk\_\discretionary {-}{}{}inv}\|hyperpage}{30}
		311	\indexentry{clk\_\discretionary {-}{}{}inv@{clk\_\discretionary {-}{}{}inv}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		312	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!DcoefCnt@{DcoefCnt}\|hyperpage}{30}
		313	\indexentry{DcoefCnt@{DcoefCnt}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		314	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!DENCoefsCnt@{DENCoefsCnt}\|hyperpage}{30}
		315	\indexentry{DENCoefsCnt@{DENCoefsCnt}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		316	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!in\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff@{in\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff}\|hyperpage}{30}
		317	\indexentry{in\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff@{in\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		318	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!NcoefCnt@{NcoefCnt}\|hyperpage}{30}
		319	\indexentry{NcoefCnt@{NcoefCnt}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		320	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!NUMCoefsCnt@{NUMCoefsCnt}\|hyperpage}{30}
		321	\indexentry{NUMCoefsCnt@{NUMCoefsCnt}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		322	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!out\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff@{out\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff}\|hyperpage}{30}
		323	\indexentry{out\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff@{out\_\discretionary {-}{}{}Rotate\_\discretionary {-}{}{}Buff}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		324	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!RAMblk@{RAMblk}\|hyperpage}{30}
		325	\indexentry{RAMblk@{RAMblk}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		326	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!RD@{RD}\|hyperpage}{30}
		327	\indexentry{RD@{RD}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		328	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!REN@{REN}\|hyperpage}{30}
		329	\indexentry{REN@{REN}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{30}
		330	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!Rotate\_\discretionary {-}{}{}BuffT@{Rotate\_\discretionary {-}{}{}BuffT}\|hyperpage}{31}
		331	\indexentry{Rotate\_\discretionary {-}{}{}BuffT@{Rotate\_\discretionary {-}{}{}BuffT}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		332	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old@{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old}\|hyperpage}{31}
		333	\indexentry{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old@{sample\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		334	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!state@{state}\|hyperpage}{31}
		335	\indexentry{state@{state}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		336	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!stateT@{stateT}\|hyperpage}{31}
		337	\indexentry{stateT@{stateT}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		338	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WADDR\_\discretionary {-}{}{}back@{WADDR\_\discretionary {-}{}{}back}\|hyperpage}{31}
		339	\indexentry{WADDR\_\discretionary {-}{}{}back@{WADDR\_\discretionary {-}{}{}back}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		340	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WD@{WD}\|hyperpage}{31}
		341	\indexentry{WD@{WD}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		342	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WD\_\discretionary {-}{}{}D@{WD\_\discretionary {-}{}{}D}\|hyperpage}{31}
		343	\indexentry{WD\_\discretionary {-}{}{}D@{WD\_\discretionary {-}{}{}D}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		344	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WDreg@{WDreg}\|hyperpage}{31}
		345	\indexentry{WDreg@{WDreg}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		346	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WEN@{WEN}\|hyperpage}{31}
		347	\indexentry{WEN@{WEN}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		348	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WEN\_\discretionary {-}{}{}D@{WEN\_\discretionary {-}{}{}D}\|hyperpage}{31}
		349	\indexentry{WEN\_\discretionary {-}{}{}D@{WEN\_\discretionary {-}{}{}D}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		350	\indexentry{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}!WRreg@{WRreg}\|hyperpage}{31}
		351	\indexentry{WRreg@{WRreg}!FilterCTRLR::ar_FilterCTRLR@{FilterCTRLR::ar\_\discretionary {-}{}{}FilterCTRLR}\|hyperpage}{31}
		352	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{31}
		353	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!PROCESS\_\discretionary {-}{}{}7@{PROCESS\_\discretionary {-}{}{}7}\|hyperpage}{34}
		354	\indexentry{PROCESS\_\discretionary {-}{}{}7@{PROCESS\_\discretionary {-}{}{}7}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		355	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!ALU\_\discretionary {-}{}{}Coef\_\discretionary {-}{}{}in@{ALU\_\discretionary {-}{}{}Coef\_\discretionary {-}{}{}in}\|hyperpage}{34}
		356	\indexentry{ALU\_\discretionary {-}{}{}Coef\_\discretionary {-}{}{}in@{ALU\_\discretionary {-}{}{}Coef\_\discretionary {-}{}{}in}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		357	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!ALU\_\discretionary {-}{}{}ctrl@{ALU\_\discretionary {-}{}{}ctrl}\|hyperpage}{34}
		358	\indexentry{ALU\_\discretionary {-}{}{}ctrl@{ALU\_\discretionary {-}{}{}ctrl}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		359	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!ALU\_\discretionary {-}{}{}inst@{ALU\_\discretionary {-}{}{}inst}\|hyperpage}{34}
		360	\indexentry{ALU\_\discretionary {-}{}{}inst@{ALU\_\discretionary {-}{}{}inst}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		361	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!ALU\_\discretionary {-}{}{}out@{ALU\_\discretionary {-}{}{}out}\|hyperpage}{34}
		362	\indexentry{ALU\_\discretionary {-}{}{}out@{ALU\_\discretionary {-}{}{}out}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		363	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!ALU\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in@{ALU\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in}\|hyperpage}{34}
		364	\indexentry{ALU\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in@{ALU\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		365	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!count@{count}\|hyperpage}{34}
		366	\indexentry{count@{count}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		367	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!curentCel@{curentCel}\|hyperpage}{34}
		368	\indexentry{curentCel@{curentCel}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		369	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!curentChan@{curentChan}\|hyperpage}{34}
		370	\indexentry{curentChan@{curentChan}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		371	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!fsmIIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}T@{fsmIIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}T}\|hyperpage}{34}
		372	\indexentry{fsmIIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}T@{fsmIIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}T}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		373	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!GO\_\discretionary {-}{}{}0@{GO\_\discretionary {-}{}{}0}\|hyperpage}{34}
		374	\indexentry{GO\_\discretionary {-}{}{}0@{GO\_\discretionary {-}{}{}0}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		375	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}STATE@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}STATE}\|hyperpage}{34}
		376	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}STATE@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}STATE}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		377	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!RAM\_\discretionary {-}{}{}CTRLR2inst@{RAM\_\discretionary {-}{}{}CTRLR2inst}\|hyperpage}{34}
		378	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2inst@{RAM\_\discretionary {-}{}{}CTRLR2inst}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		379	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in@{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in}\|hyperpage}{34}
		380	\indexentry{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in@{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		381	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}bk@{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}bk}\|hyperpage}{34}
		382	\indexentry{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}bk@{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}bk}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		383	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}out@{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}out}\|hyperpage}{34}
		384	\indexentry{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}out@{RAM\_\discretionary {-}{}{}sample\_\discretionary {-}{}{}out}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		385	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!Read@{Read}\|hyperpage}{34}
		386	\indexentry{Read@{Read}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		387	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}BUFF@{sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}BUFF}\|hyperpage}{34}
		388	\indexentry{sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}BUFF@{sample\_\discretionary {-}{}{}in\_\discretionary {-}{}{}BUFF}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		389	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}out\_\discretionary {-}{}{}BUFF@{sample\_\discretionary {-}{}{}out\_\discretionary {-}{}{}BUFF}\|hyperpage}{34}
		390	\indexentry{sample\_\discretionary {-}{}{}out\_\discretionary {-}{}{}BUFF@{sample\_\discretionary {-}{}{}out\_\discretionary {-}{}{}BUFF}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		391	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!smpl\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old@{smpl\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old}\|hyperpage}{34}
		392	\indexentry{smpl\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old@{smpl\_\discretionary {-}{}{}clk\_\discretionary {-}{}{}old}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		393	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!SVG\_\discretionary {-}{}{}ADDR@{SVG\_\discretionary {-}{}{}ADDR}\|hyperpage}{34}
		394	\indexentry{SVG\_\discretionary {-}{}{}ADDR@{SVG\_\discretionary {-}{}{}ADDR}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		395	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!WADDR\_\discretionary {-}{}{}sel@{WADDR\_\discretionary {-}{}{}sel}\|hyperpage}{34}
		396	\indexentry{WADDR\_\discretionary {-}{}{}sel@{WADDR\_\discretionary {-}{}{}sel}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		397	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!WD\_\discretionary {-}{}{}sel@{WD\_\discretionary {-}{}{}sel}\|hyperpage}{34}
		398	\indexentry{WD\_\discretionary {-}{}{}sel@{WD\_\discretionary {-}{}{}sel}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		399	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!Write@{Write}\|hyperpage}{34}
		400	\indexentry{Write@{Write}!IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{34}
		401	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{35}
		402	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!CTRLR@{CTRLR}\|hyperpage}{35}
		403	\indexentry{CTRLR@{CTRLR}!IIR_CEL_FILTER::ar_IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{35}
		404	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!virg\_\discretionary {-}{}{}pos@{virg\_\discretionary {-}{}{}pos}\|hyperpage}{35}
		405	\indexentry{virg\_\discretionary {-}{}{}pos@{virg\_\discretionary {-}{}{}pos}!IIR_CEL_FILTER::ar_IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER::ar\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{35}
		406	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{35}
		407	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!PROCESS\_\discretionary {-}{}{}1@{PROCESS\_\discretionary {-}{}{}1}\|hyperpage}{37}
		408	\indexentry{PROCESS\_\discretionary {-}{}{}1@{PROCESS\_\discretionary {-}{}{}1}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		409	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!CMD\_\discretionary {-}{}{}Flag@{CMD\_\discretionary {-}{}{}Flag}\|hyperpage}{37}
		410	\indexentry{CMD\_\discretionary {-}{}{}Flag@{CMD\_\discretionary {-}{}{}Flag}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		411	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!ConfigTbl@{ConfigTbl}\|hyperpage}{37}
		412	\indexentry{ConfigTbl@{ConfigTbl}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		413	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!Driver0@{Driver0}\|hyperpage}{37}
		414	\indexentry{Driver0@{Driver0}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		415	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!DRIVER\_\discretionary {-}{}{}CMD@{DRIVER\_\discretionary {-}{}{}CMD}\|hyperpage}{37}
		416	\indexentry{DRIVER\_\discretionary {-}{}{}CMD@{DRIVER\_\discretionary {-}{}{}CMD}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		417	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!Exec\_\discretionary {-}{}{}Reg@{Exec\_\discretionary {-}{}{}Reg}\|hyperpage}{37}
		418	\indexentry{Exec\_\discretionary {-}{}{}Reg@{Exec\_\discretionary {-}{}{}Reg}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		419	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!FRAME\_\discretionary {-}{}{}CLK@{FRAME\_\discretionary {-}{}{}CLK}\|hyperpage}{37}
		420	\indexentry{FRAME\_\discretionary {-}{}{}CLK@{FRAME\_\discretionary {-}{}{}CLK}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		421	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN0@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN0}\|hyperpage}{37}
		422	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN0@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN0}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		423	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg}\|hyperpage}{37}
		424	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		425	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!i@{i}\|hyperpage}{37}
		426	\indexentry{i@{i}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		427	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!RefreshFlag@{RefreshFlag}\|hyperpage}{37}
		428	\indexentry{RefreshFlag@{RefreshFlag}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		429	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!state@{state}\|hyperpage}{37}
		430	\indexentry{state@{state}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		431	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!state\_\discretionary {-}{}{}t@{state\_\discretionary {-}{}{}t}\|hyperpage}{37}
		432	\indexentry{state\_\discretionary {-}{}{}t@{state\_\discretionary {-}{}{}t}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		433	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!SYNCH@{SYNCH}\|hyperpage}{37}
		434	\indexentry{SYNCH@{SYNCH}!LCD_16x2_ENGINE::ar_LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{37}
		435	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{37}
		436	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!PROCESS\_\discretionary {-}{}{}3@{PROCESS\_\discretionary {-}{}{}3}\|hyperpage}{38}
		437	\indexentry{PROCESS\_\discretionary {-}{}{}3@{PROCESS\_\discretionary {-}{}{}3}!LCD_CLK_GENERATOR::ar_LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{38}
		438	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!clk\_\discretionary {-}{}{}1us\_\discretionary {-}{}{}int@{clk\_\discretionary {-}{}{}1us\_\discretionary {-}{}{}int}\|hyperpage}{38}
		439	\indexentry{clk\_\discretionary {-}{}{}1us\_\discretionary {-}{}{}int@{clk\_\discretionary {-}{}{}1us\_\discretionary {-}{}{}int}!LCD_CLK_GENERATOR::ar_LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{38}
		440	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!clk\_\discretionary {-}{}{}1usTRIGER@{clk\_\discretionary {-}{}{}1usTRIGER}\|hyperpage}{38}
		441	\indexentry{clk\_\discretionary {-}{}{}1usTRIGER@{clk\_\discretionary {-}{}{}1usTRIGER}!LCD_CLK_GENERATOR::ar_LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{38}
		442	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!cpt1@{cpt1}\|hyperpage}{38}
		443	\indexentry{cpt1@{cpt1}!LCD_CLK_GENERATOR::ar_LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR::ar\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{38}
		444	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{38}
		445	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!add@{add}\|hyperpage}{42}
		446	\indexentry{add@{add}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		447	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!add\_\discretionary {-}{}{}D@{add\_\discretionary {-}{}{}D}\|hyperpage}{42}
		448	\indexentry{add\_\discretionary {-}{}{}D@{add\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		449	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!adder\_\discretionary {-}{}{}inst@{adder\_\discretionary {-}{}{}inst}\|hyperpage}{42}
		450	\indexentry{adder\_\discretionary {-}{}{}inst@{adder\_\discretionary {-}{}{}inst}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		451	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!ADDERinA@{ADDERinA}\|hyperpage}{42}
		452	\indexentry{ADDERinA@{ADDERinA}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		453	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!ADDERinB@{ADDERinB}\|hyperpage}{42}
		454	\indexentry{ADDERinB@{ADDERinB}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		455	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!ADDERout@{ADDERout}\|hyperpage}{42}
		456	\indexentry{ADDERout@{ADDERout}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		457	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!addREG@{addREG}\|hyperpage}{42}
		458	\indexentry{addREG@{addREG}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		459	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D@{clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D}\|hyperpage}{42}
		460	\indexentry{clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D@{clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		461	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D@{clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D}\|hyperpage}{42}
		462	\indexentry{clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D@{clr\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		463	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!clr\_\discretionary {-}{}{}MACREG1@{clr\_\discretionary {-}{}{}MACREG1}\|hyperpage}{42}
		464	\indexentry{clr\_\discretionary {-}{}{}MACREG1@{clr\_\discretionary {-}{}{}MACREG1}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		465	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!clr\_\discretionary {-}{}{}MACREG2@{clr\_\discretionary {-}{}{}MACREG2}\|hyperpage}{42}
		466	\indexentry{clr\_\discretionary {-}{}{}MACREG2@{clr\_\discretionary {-}{}{}MACREG2}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		467	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MAC\_\discretionary {-}{}{}CONTROLER1@{MAC\_\discretionary {-}{}{}CONTROLER1}\|hyperpage}{42}
		468	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER1@{MAC\_\discretionary {-}{}{}CONTROLER1}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		469	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MAC\_\discretionary {-}{}{}MUX2\_\discretionary {-}{}{}inst@{MAC\_\discretionary {-}{}{}MUX2\_\discretionary {-}{}{}inst}\|hyperpage}{42}
		470	\indexentry{MAC\_\discretionary {-}{}{}MUX2\_\discretionary {-}{}{}inst@{MAC\_\discretionary {-}{}{}MUX2\_\discretionary {-}{}{}inst}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		471	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUX2sel@{MACMUX2sel}\|hyperpage}{42}
		472	\indexentry{MACMUX2sel@{MACMUX2sel}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		473	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUX2sel\_\discretionary {-}{}{}D@{MACMUX2sel\_\discretionary {-}{}{}D}\|hyperpage}{42}
		474	\indexentry{MACMUX2sel\_\discretionary {-}{}{}D@{MACMUX2sel\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		475	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUX2sel\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D@{MACMUX2sel\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D}\|hyperpage}{42}
		476	\indexentry{MACMUX2sel\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D@{MACMUX2sel\_\discretionary {-}{}{}D\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		477	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUX2selREG@{MACMUX2selREG}\|hyperpage}{42}
		478	\indexentry{MACMUX2selREG@{MACMUX2selREG}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		479	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUX2selREG2@{MACMUX2selREG2}\|hyperpage}{42}
		480	\indexentry{MACMUX2selREG2@{MACMUX2selREG2}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		481	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUX\_\discretionary {-}{}{}inst@{MACMUX\_\discretionary {-}{}{}inst}\|hyperpage}{42}
		482	\indexentry{MACMUX\_\discretionary {-}{}{}inst@{MACMUX\_\discretionary {-}{}{}inst}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		483	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUXsel@{MACMUXsel}\|hyperpage}{42}
		484	\indexentry{MACMUXsel@{MACMUXsel}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		485	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUXsel\_\discretionary {-}{}{}D@{MACMUXsel\_\discretionary {-}{}{}D}\|hyperpage}{42}
		486	\indexentry{MACMUXsel\_\discretionary {-}{}{}D@{MACMUXsel\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		487	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MACMUXselREG@{MACMUXselREG}\|hyperpage}{42}
		488	\indexentry{MACMUXselREG@{MACMUXselREG}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		489	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!mult@{mult}\|hyperpage}{42}
		490	\indexentry{mult@{mult}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		491	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!Multiplieri\_\discretionary {-}{}{}nst@{Multiplieri\_\discretionary {-}{}{}nst}\|hyperpage}{42}
		492	\indexentry{Multiplieri\_\discretionary {-}{}{}nst@{Multiplieri\_\discretionary {-}{}{}nst}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		493	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MULTout@{MULTout}\|hyperpage}{42}
		494	\indexentry{MULTout@{MULTout}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		495	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MULTout\_\discretionary {-}{}{}D@{MULTout\_\discretionary {-}{}{}D}\|hyperpage}{42}
		496	\indexentry{MULTout\_\discretionary {-}{}{}D@{MULTout\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		497	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!MULToutREG@{MULToutREG}\|hyperpage}{42}
		498	\indexentry{MULToutREG@{MULToutREG}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		499	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!OP1\_\discretionary {-}{}{}D@{OP1\_\discretionary {-}{}{}D}\|hyperpage}{42}
		500	\indexentry{OP1\_\discretionary {-}{}{}D@{OP1\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		501	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!OP1\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz@{OP1\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz}\|hyperpage}{42}
		502	\indexentry{OP1\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz@{OP1\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		503	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!OP1REG@{OP1REG}\|hyperpage}{42}
		504	\indexentry{OP1REG@{OP1REG}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		505	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!OP2\_\discretionary {-}{}{}D@{OP2\_\discretionary {-}{}{}D}\|hyperpage}{42}
		506	\indexentry{OP2\_\discretionary {-}{}{}D@{OP2\_\discretionary {-}{}{}D}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		507	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!OP2\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz@{OP2\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz}\|hyperpage}{42}
		508	\indexentry{OP2\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz@{OP2\_\discretionary {-}{}{}D\_\discretionary {-}{}{}Resz}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		509	\indexentry{MAC::ar\_\discretionary {-}{}{}MAC@{MAC::ar\_\discretionary {-}{}{}MAC}!OP2REG@{OP2REG}\|hyperpage}{42}
		510	\indexentry{OP2REG@{OP2REG}!MAC::ar_MAC@{MAC::ar\_\discretionary {-}{}{}MAC}\|hyperpage}{42}
		511	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{43}
		512	\indexentry{MAC\_\discretionary {-}{}{}MUX::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{43}
		513	\indexentry{MAC\_\discretionary {-}{}{}MUX2::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{44}
		514	\indexentry{MAC\_\discretionary {-}{}{}REG::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}REG}\|hyperpage}{45}
		515	\indexentry{MAC\_\discretionary {-}{}{}REG::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}REG}!PROCESS\_\discretionary {-}{}{}14@{PROCESS\_\discretionary {-}{}{}14}\|hyperpage}{46}
		516	\indexentry{PROCESS\_\discretionary {-}{}{}14@{PROCESS\_\discretionary {-}{}{}14}!MAC_REG::ar_MAC_REG@{MAC\_\discretionary {-}{}{}REG::ar\_\discretionary {-}{}{}MAC\_\discretionary {-}{}{}REG}\|hyperpage}{46}
		517	\indexentry{Multiplier::ar\_\discretionary {-}{}{}Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}\|hyperpage}{46}
		518	\indexentry{Multiplier::ar\_\discretionary {-}{}{}Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}!PROCESS\_\discretionary {-}{}{}15@{PROCESS\_\discretionary {-}{}{}15}\|hyperpage}{47}
		519	\indexentry{PROCESS\_\discretionary {-}{}{}15@{PROCESS\_\discretionary {-}{}{}15}!Multiplier::ar_Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}\|hyperpage}{47}
		520	\indexentry{Multiplier::ar\_\discretionary {-}{}{}Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}!REG@{REG}\|hyperpage}{47}
		521	\indexentry{REG@{REG}!Multiplier::ar_Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}\|hyperpage}{47}
		522	\indexentry{Multiplier::ar\_\discretionary {-}{}{}Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}!RESMULT@{RESMULT}\|hyperpage}{47}
		523	\indexentry{RESMULT@{RESMULT}!Multiplier::ar_Multiplier@{Multiplier::ar\_\discretionary {-}{}{}Multiplier}\|hyperpage}{47}
		524	\indexentry{MUX2::ar\_\discretionary {-}{}{}MUX2@{MUX2::ar\_\discretionary {-}{}{}MUX2}\|hyperpage}{48}
		525	\indexentry{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{48}
		526	\indexentry{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}!PROCESS\_\discretionary {-}{}{}9@{PROCESS\_\discretionary {-}{}{}9}\|hyperpage}{49}
		527	\indexentry{PROCESS\_\discretionary {-}{}{}9@{PROCESS\_\discretionary {-}{}{}9}!RAM_CEL::ar_RAM_CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{49}
		528	\indexentry{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}!RAMarray@{RAMarray}\|hyperpage}{49}
		529	\indexentry{RAMarray@{RAMarray}!RAM_CEL::ar_RAM_CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{49}
		530	\indexentry{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}!RAMarrayT@{RAMarrayT}\|hyperpage}{49}
		531	\indexentry{RAMarrayT@{RAMarrayT}!RAM_CEL::ar_RAM_CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{49}
		532	\indexentry{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}!RD\_\discretionary {-}{}{}int@{RD\_\discretionary {-}{}{}int}\|hyperpage}{49}
		533	\indexentry{RD\_\discretionary {-}{}{}int@{RD\_\discretionary {-}{}{}int}!RAM_CEL::ar_RAM_CEL@{RAM\_\discretionary {-}{}{}CEL::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{49}
		534	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{50}
		535	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!ADDRcntr\_\discretionary {-}{}{}inst@{ADDRcntr\_\discretionary {-}{}{}inst}\|hyperpage}{51}
		536	\indexentry{ADDRcntr\_\discretionary {-}{}{}inst@{ADDRcntr\_\discretionary {-}{}{}inst}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		537	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!ADDRreg@{ADDRreg}\|hyperpage}{51}
		538	\indexentry{ADDRreg@{ADDRreg}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		539	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!MUX2\_\discretionary {-}{}{}inst1@{MUX2\_\discretionary {-}{}{}inst1}\|hyperpage}{51}
		540	\indexentry{MUX2\_\discretionary {-}{}{}inst1@{MUX2\_\discretionary {-}{}{}inst1}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		541	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!MUX2\_\discretionary {-}{}{}inst2@{MUX2\_\discretionary {-}{}{}inst2}\|hyperpage}{51}
		542	\indexentry{MUX2\_\discretionary {-}{}{}inst2@{MUX2\_\discretionary {-}{}{}inst2}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		543	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!RADDR@{RADDR}\|hyperpage}{51}
		544	\indexentry{RADDR@{RADDR}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		545	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!RAMblk@{RAMblk}\|hyperpage}{51}
		546	\indexentry{RAMblk@{RAMblk}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		547	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!RAMblk@{RAMblk}\|hyperpage}{51}
		548	\indexentry{RAMblk@{RAMblk}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		549	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!RD@{RD}\|hyperpage}{51}
		550	\indexentry{RD@{RD}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		551	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!REN@{REN}\|hyperpage}{51}
		552	\indexentry{REN@{REN}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		553	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WADDR@{WADDR}\|hyperpage}{51}
		554	\indexentry{WADDR@{WADDR}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		555	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WADDR\_\discretionary {-}{}{}back@{WADDR\_\discretionary {-}{}{}back}\|hyperpage}{51}
		556	\indexentry{WADDR\_\discretionary {-}{}{}back@{WADDR\_\discretionary {-}{}{}back}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		557	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D}\|hyperpage}{51}
		558	\indexentry{WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}back\_\discretionary {-}{}{}D}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		559	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WADDR\_\discretionary {-}{}{}backreg@{WADDR\_\discretionary {-}{}{}backreg}\|hyperpage}{51}
		560	\indexentry{WADDR\_\discretionary {-}{}{}backreg@{WADDR\_\discretionary {-}{}{}backreg}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		561	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WADDR\_\discretionary {-}{}{}backreg2@{WADDR\_\discretionary {-}{}{}backreg2}\|hyperpage}{51}
		562	\indexentry{WADDR\_\discretionary {-}{}{}backreg2@{WADDR\_\discretionary {-}{}{}backreg2}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		563	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WADDR\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}D}\|hyperpage}{51}
		564	\indexentry{WADDR\_\discretionary {-}{}{}D@{WADDR\_\discretionary {-}{}{}D}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		565	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WD@{WD}\|hyperpage}{51}
		566	\indexentry{WD@{WD}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		567	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WD\_\discretionary {-}{}{}D@{WD\_\discretionary {-}{}{}D}\|hyperpage}{51}
		568	\indexentry{WD\_\discretionary {-}{}{}D@{WD\_\discretionary {-}{}{}D}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		569	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WDRreg@{WDRreg}\|hyperpage}{51}
		570	\indexentry{WDRreg@{WDRreg}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		571	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}!WEN@{WEN}\|hyperpage}{51}
		572	\indexentry{WEN@{WEN}!RAM_CTRLR2::ar_RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2::ar\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{51}
		573	\indexentry{REG::ar\_\discretionary {-}{}{}REG@{REG::ar\_\discretionary {-}{}{}REG}\|hyperpage}{52}
		574	\indexentry{REG::ar\_\discretionary {-}{}{}REG@{REG::ar\_\discretionary {-}{}{}REG}!PROCESS\_\discretionary {-}{}{}16@{PROCESS\_\discretionary {-}{}{}16}\|hyperpage}{52}
		575	\indexentry{PROCESS\_\discretionary {-}{}{}16@{PROCESS\_\discretionary {-}{}{}16}!REG::ar_REG@{REG::ar\_\discretionary {-}{}{}REG}\|hyperpage}{52}
		576	\indexentry{RShifter::ar\_\discretionary {-}{}{}RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}\|hyperpage}{52}
		577	\indexentry{RShifter::ar\_\discretionary {-}{}{}RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}!PROCESS\_\discretionary {-}{}{}17@{PROCESS\_\discretionary {-}{}{}17}\|hyperpage}{53}
		578	\indexentry{PROCESS\_\discretionary {-}{}{}17@{PROCESS\_\discretionary {-}{}{}17}!RShifter::ar_RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}\|hyperpage}{53}
		579	\indexentry{RShifter::ar\_\discretionary {-}{}{}RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}!REG@{REG}\|hyperpage}{53}
		580	\indexentry{REG@{REG}!RShifter::ar_RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}\|hyperpage}{53}
		581	\indexentry{RShifter::ar\_\discretionary {-}{}{}RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}!RESSHIFT@{RESSHIFT}\|hyperpage}{53}
		582	\indexentry{RESSHIFT@{RESSHIFT}!RShifter::ar_RShifter@{RShifter::ar\_\discretionary {-}{}{}RShifter}\|hyperpage}{53}
		583	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{53}
		584	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!PROCESS\_\discretionary {-}{}{}18@{PROCESS\_\discretionary {-}{}{}18}\|hyperpage}{54}
		585	\indexentry{PROCESS\_\discretionary {-}{}{}18@{PROCESS\_\discretionary {-}{}{}18}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		586	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!ADD@{ADD}\|hyperpage}{54}
		587	\indexentry{ADD@{ADD}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		588	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!ALU1@{ALU1}\|hyperpage}{54}
		589	\indexentry{ALU1@{ALU1}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		590	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!clk@{clk}\|hyperpage}{54}
		591	\indexentry{clk@{clk}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		592	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!clr\_\discretionary {-}{}{}mac@{clr\_\discretionary {-}{}{}mac}\|hyperpage}{54}
		593	\indexentry{clr\_\discretionary {-}{}{}mac@{clr\_\discretionary {-}{}{}mac}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		594	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!ctrl@{ctrl}\|hyperpage}{54}
		595	\indexentry{ctrl@{ctrl}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		596	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!IDLE@{IDLE}\|hyperpage}{54}
		597	\indexentry{IDLE@{IDLE}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{54}
		598	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!MAC@{MAC}\|hyperpage}{55}
		599	\indexentry{MAC@{MAC}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		600	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!MULT@{MULT}\|hyperpage}{55}
		601	\indexentry{MULT@{MULT}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		602	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!OP1sz@{OP1sz}\|hyperpage}{55}
		603	\indexentry{OP1sz@{OP1sz}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		604	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!OP2sz@{OP2sz}\|hyperpage}{55}
		605	\indexentry{OP2sz@{OP2sz}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		606	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!Operand1@{Operand1}\|hyperpage}{55}
		607	\indexentry{Operand1@{Operand1}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		608	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!Operand2@{Operand2}\|hyperpage}{55}
		609	\indexentry{Operand2@{Operand2}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		610	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!reset@{reset}\|hyperpage}{55}
		611	\indexentry{reset@{reset}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		612	\indexentry{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}!Resultat@{Resultat}\|hyperpage}{55}
		613	\indexentry{Resultat@{Resultat}!TestbenshALU::ar_TestbenshALU@{TestbenshALU::ar\_\discretionary {-}{}{}TestbenshALU}\|hyperpage}{55}
		614	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{55}
		615	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!PROCESS\_\discretionary {-}{}{}10@{PROCESS\_\discretionary {-}{}{}10}\|hyperpage}{56}
		616	\indexentry{PROCESS\_\discretionary {-}{}{}10@{PROCESS\_\discretionary {-}{}{}10}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		617	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!ADD@{ADD}\|hyperpage}{56}
		618	\indexentry{ADD@{ADD}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		619	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!clk@{clk}\|hyperpage}{56}
		620	\indexentry{clk@{clk}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		621	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!clrMAC@{clrMAC}\|hyperpage}{56}
		622	\indexentry{clrMAC@{clrMAC}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		623	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!IDLE@{IDLE}\|hyperpage}{56}
		624	\indexentry{IDLE@{IDLE}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		625	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!MAC@{MAC}\|hyperpage}{56}
		626	\indexentry{MAC@{MAC}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		627	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!MAC1@{MAC1}\|hyperpage}{56}
		628	\indexentry{MAC1@{MAC1}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		629	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD@{MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD}\|hyperpage}{56}
		630	\indexentry{MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD@{MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		631	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!MULT@{MULT}\|hyperpage}{56}
		632	\indexentry{MULT@{MULT}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{56}
		633	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!OP1sz@{OP1sz}\|hyperpage}{57}
		634	\indexentry{OP1sz@{OP1sz}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{57}
		635	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!OP2sz@{OP2sz}\|hyperpage}{57}
		636	\indexentry{OP2sz@{OP2sz}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{57}
		637	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!Operand1@{Operand1}\|hyperpage}{57}
		638	\indexentry{Operand1@{Operand1}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{57}
		639	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!Operand2@{Operand2}\|hyperpage}{57}
		640	\indexentry{Operand2@{Operand2}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{57}
		641	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!reset@{reset}\|hyperpage}{57}
		642	\indexentry{reset@{reset}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{57}
		643	\indexentry{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}!Resultat@{Resultat}\|hyperpage}{57}
		644	\indexentry{Resultat@{Resultat}!TestbenshMAC::ar_TestbenshMAC@{TestbenshMAC::ar\_\discretionary {-}{}{}TestbenshMAC}\|hyperpage}{57}
		645	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{57}
		646	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!CMD@{CMD}\|hyperpage}{58}
		647	\indexentry{CMD@{CMD}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		648	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!Driver0@{Driver0}\|hyperpage}{58}
		649	\indexentry{Driver0@{Driver0}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		650	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!Exec@{Exec}\|hyperpage}{58}
		651	\indexentry{Exec@{Exec}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		652	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!FramBUFF@{FramBUFF}\|hyperpage}{58}
		653	\indexentry{FramBUFF@{FramBUFF}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		654	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!LCD\_\discretionary {-}{}{}CTRL@{LCD\_\discretionary {-}{}{}CTRL}\|hyperpage}{58}
		655	\indexentry{LCD\_\discretionary {-}{}{}CTRL@{LCD\_\discretionary {-}{}{}CTRL}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		656	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!Ready@{Ready}\|hyperpage}{58}
		657	\indexentry{Ready@{Ready}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		658	\indexentry{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}!rst@{rst}\|hyperpage}{58}
		659	\indexentry{rst@{rst}!AMBA_LCD_16x2_DRIVER::Behavioral@{AMBA\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		660	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{58}
		661	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!PROCESS\_\discretionary {-}{}{}2@{PROCESS\_\discretionary {-}{}{}2}\|hyperpage}{60}
		662	\indexentry{PROCESS\_\discretionary {-}{}{}2@{PROCESS\_\discretionary {-}{}{}2}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		663	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!CFGM\_\discretionary {-}{}{}completed@{CFGM\_\discretionary {-}{}{}completed}\|hyperpage}{60}
		664	\indexentry{CFGM\_\discretionary {-}{}{}completed@{CFGM\_\discretionary {-}{}{}completed}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		665	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!CFGM\_\discretionary {-}{}{}Enable@{CFGM\_\discretionary {-}{}{}Enable}\|hyperpage}{60}
		666	\indexentry{CFGM\_\discretionary {-}{}{}Enable@{CFGM\_\discretionary {-}{}{}Enable}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		667	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA}\|hyperpage}{60}
		668	\indexentry{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		669	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E}\|hyperpage}{60}
		670	\indexentry{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		671	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS}\|hyperpage}{60}
		672	\indexentry{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		673	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW}\|hyperpage}{60}
		674	\indexentry{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW@{CFGM\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		675	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!ConfigModule@{ConfigModule}\|hyperpage}{60}
		676	\indexentry{ConfigModule@{ConfigModule}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		677	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!Counter@{Counter}\|hyperpage}{60}
		678	\indexentry{Counter@{Counter}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		679	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FrameWriter@{FrameWriter}\|hyperpage}{60}
		680	\indexentry{FrameWriter@{FrameWriter}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		681	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FRMW\_\discretionary {-}{}{}completed@{FRMW\_\discretionary {-}{}{}completed}\|hyperpage}{60}
		682	\indexentry{FRMW\_\discretionary {-}{}{}completed@{FRMW\_\discretionary {-}{}{}completed}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		683	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FRMW\_\discretionary {-}{}{}Enable@{FRMW\_\discretionary {-}{}{}Enable}\|hyperpage}{60}
		684	\indexentry{FRMW\_\discretionary {-}{}{}Enable@{FRMW\_\discretionary {-}{}{}Enable}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		685	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA}\|hyperpage}{60}
		686	\indexentry{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}DATA}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		687	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E}\|hyperpage}{60}
		688	\indexentry{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}E}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		689	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS}\|hyperpage}{60}
		690	\indexentry{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RS}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		691	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW}\|hyperpage}{60}
		692	\indexentry{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW@{FRMW\_\discretionary {-}{}{}LCD\_\discretionary {-}{}{}RW}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		693	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!MidleTimePulse@{MidleTimePulse}\|hyperpage}{60}
		694	\indexentry{MidleTimePulse@{MidleTimePulse}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		695	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!Refresh\_\discretionary {-}{}{}RatePulse@{Refresh\_\discretionary {-}{}{}RatePulse}\|hyperpage}{60}
		696	\indexentry{Refresh\_\discretionary {-}{}{}RatePulse@{Refresh\_\discretionary {-}{}{}RatePulse}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		697	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!ShortTimePulse@{ShortTimePulse}\|hyperpage}{60}
		698	\indexentry{ShortTimePulse@{ShortTimePulse}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		699	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!Start@{Start}\|hyperpage}{60}
		700	\indexentry{Start@{Start}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		701	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!state@{state}\|hyperpage}{60}
		702	\indexentry{state@{state}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		703	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}!stateT@{stateT}\|hyperpage}{60}
		704	\indexentry{stateT@{stateT}!LCD_2x16_DRIVER::Behavioral@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER::Behavioral}\|hyperpage}{60}
		705	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}\|hyperpage}{61}
		706	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}!PROCESS\_\discretionary {-}{}{}0@{PROCESS\_\discretionary {-}{}{}0}\|hyperpage}{61}
		707	\indexentry{PROCESS\_\discretionary {-}{}{}0@{PROCESS\_\discretionary {-}{}{}0}!FRAME_CLK_GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}\|hyperpage}{61}
		708	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}!CPT@{CPT}\|hyperpage}{61}
		709	\indexentry{CPT@{CPT}!FRAME_CLK_GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}\|hyperpage}{61}
		710	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}!FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg}\|hyperpage}{61}
		711	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}reg}!FRAME_CLK_GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}\|hyperpage}{61}
		712	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}!FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}TRIG@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}TRIG}\|hyperpage}{61}
		713	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}TRIG@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}TRIG}!FRAME_CLK_GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}\|hyperpage}{61}
		714	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}!Goal\_\discretionary {-}{}{}FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}FREQ@{Goal\_\discretionary {-}{}{}FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}FREQ}\|hyperpage}{62}
		715	\indexentry{Goal\_\discretionary {-}{}{}FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}FREQ@{Goal\_\discretionary {-}{}{}FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}FREQ}!FRAME_CLK_GEN::Behavioral@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN::Behavioral}\|hyperpage}{62}
		716	\indexentry{RAM::DEF\_\discretionary {-}{}{}ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}\|hyperpage}{62}
		717	\indexentry{RAM::DEF\_\discretionary {-}{}{}ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}!PROCESS\_\discretionary {-}{}{}8@{PROCESS\_\discretionary {-}{}{}8}\|hyperpage}{63}
		718	\indexentry{PROCESS\_\discretionary {-}{}{}8@{PROCESS\_\discretionary {-}{}{}8}!RAM::DEF_ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}\|hyperpage}{63}
		719	\indexentry{RAM::DEF\_\discretionary {-}{}{}ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}!RAMarray@{RAMarray}\|hyperpage}{63}
		720	\indexentry{RAMarray@{RAMarray}!RAM::DEF_ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}\|hyperpage}{63}
		721	\indexentry{RAM::DEF\_\discretionary {-}{}{}ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}!RAMarrayT@{RAMarrayT}\|hyperpage}{63}
		722	\indexentry{RAMarrayT@{RAMarrayT}!RAM::DEF_ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}\|hyperpage}{63}
		723	\indexentry{RAM::DEF\_\discretionary {-}{}{}ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}!RD\_\discretionary {-}{}{}int@{RD\_\discretionary {-}{}{}int}\|hyperpage}{63}
		724	\indexentry{RD\_\discretionary {-}{}{}int@{RD\_\discretionary {-}{}{}int}!RAM::DEF_ARCH@{RAM::DEF\_\discretionary {-}{}{}ARCH}\|hyperpage}{63}
		725	\indexentry{FILTER@{FILTER}\|hyperpage}{63}
		726	\indexentry{FILTER@{FILTER}!clk@{clk}\|hyperpage}{64}
		727	\indexentry{clk@{clk}!FILTER@{FILTER}\|hyperpage}{64}
		728	\indexentry{FILTER@{FILTER}!FILTERcfg@{FILTERcfg}\|hyperpage}{64}
		729	\indexentry{FILTERcfg@{FILTERcfg}!FILTER@{FILTER}\|hyperpage}{64}
		730	\indexentry{FILTER@{FILTER}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{64}
		731	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!FILTER@{FILTER}\|hyperpage}{64}
		732	\indexentry{FILTER@{FILTER}!IEEE@{IEEE}\|hyperpage}{64}
		733	\indexentry{IEEE@{IEEE}!FILTER@{FILTER}\|hyperpage}{64}
		734	\indexentry{FILTER@{FILTER}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{64}
		735	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FILTER@{FILTER}\|hyperpage}{64}
		736	\indexentry{FILTER@{FILTER}!lpp@{lpp}\|hyperpage}{64}
		737	\indexentry{lpp@{lpp}!FILTER@{FILTER}\|hyperpage}{64}
		738	\indexentry{FILTER@{FILTER}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{64}
		739	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!FILTER@{FILTER}\|hyperpage}{64}
		740	\indexentry{FILTER@{FILTER}!reset@{reset}\|hyperpage}{64}
		741	\indexentry{reset@{reset}!FILTER@{FILTER}\|hyperpage}{64}
		742	\indexentry{FILTER@{FILTER}!sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}\|hyperpage}{64}
		743	\indexentry{sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}!FILTER@{FILTER}\|hyperpage}{64}
		744	\indexentry{FILTER@{FILTER}!Sample\_\discretionary {-}{}{}IN@{Sample\_\discretionary {-}{}{}IN}\|hyperpage}{65}
		745	\indexentry{Sample\_\discretionary {-}{}{}IN@{Sample\_\discretionary {-}{}{}IN}!FILTER@{FILTER}\|hyperpage}{65}
		746	\indexentry{FILTER@{FILTER}!Sample\_\discretionary {-}{}{}OUT@{Sample\_\discretionary {-}{}{}OUT}\|hyperpage}{65}
		747	\indexentry{Sample\_\discretionary {-}{}{}OUT@{Sample\_\discretionary {-}{}{}OUT}!FILTER@{FILTER}\|hyperpage}{65}
		748	\indexentry{FILTER@{FILTER}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{65}
		749	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!FILTER@{FILTER}\|hyperpage}{65}
		750	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{65}
		751	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!B\_\discretionary {-}{}{}A@{B\_\discretionary {-}{}{}A}\|hyperpage}{66}
		752	\indexentry{B\_\discretionary {-}{}{}A@{B\_\discretionary {-}{}{}A}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		753	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!clk@{clk}\|hyperpage}{66}
		754	\indexentry{clk@{clk}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		755	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!FILTERcfg@{FILTERcfg}\|hyperpage}{66}
		756	\indexentry{FILTERcfg@{FILTERcfg}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		757	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{66}
		758	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		759	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!GO\_\discretionary {-}{}{}0@{GO\_\discretionary {-}{}{}0}\|hyperpage}{66}
		760	\indexentry{GO\_\discretionary {-}{}{}0@{GO\_\discretionary {-}{}{}0}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		761	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!IEEE@{IEEE}\|hyperpage}{66}
		762	\indexentry{IEEE@{IEEE}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		763	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{66}
		764	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		765	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!lpp@{lpp}\|hyperpage}{66}
		766	\indexentry{lpp@{lpp}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		767	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!next\_\discretionary {-}{}{}blk@{next\_\discretionary {-}{}{}blk}\|hyperpage}{66}
		768	\indexentry{next\_\discretionary {-}{}{}blk@{next\_\discretionary {-}{}{}blk}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		769	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{66}
		770	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		771	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!reset@{reset}\|hyperpage}{66}
		772	\indexentry{reset@{reset}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		773	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!run@{run}\|hyperpage}{66}
		774	\indexentry{run@{run}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{66}
		775	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}\|hyperpage}{67}
		776	\indexentry{sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{67}
		777	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}\|hyperpage}{67}
		778	\indexentry{sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{67}
		779	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{67}
		780	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{67}
		781	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!writeForce@{writeForce}\|hyperpage}{67}
		782	\indexentry{writeForce@{writeForce}!FILTER_RAM_CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{67}
		783	\indexentry{FILTERcfg@{FILTERcfg}\|hyperpage}{67}
		784	\indexentry{FILTERcfg@{FILTERcfg}!NumCoefs@{NumCoefs}\|hyperpage}{71}
		785	\indexentry{NumCoefs@{NumCoefs}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		786	\indexentry{FILTERcfg@{FILTERcfg}!DenCoefs@{DenCoefs}\|hyperpage}{71}
		787	\indexentry{DenCoefs@{DenCoefs}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		788	\indexentry{FILTERcfg@{FILTERcfg}!config@{config}\|hyperpage}{71}
		789	\indexentry{config@{config}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		790	\indexentry{FILTERcfg@{FILTERcfg}!coefsTB@{coefsTB}\|hyperpage}{71}
		791	\indexentry{coefsTB@{coefsTB}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		792	\indexentry{FILTERcfg@{FILTERcfg}!virgPos@{virgPos}\|hyperpage}{71}
		793	\indexentry{virgPos@{virgPos}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		794	\indexentry{FILTERcfg@{FILTERcfg}!config@{config}\|hyperpage}{71}
		795	\indexentry{config@{config}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		796	\indexentry{FILTERcfg@{FILTERcfg}!status@{status}\|hyperpage}{71}
		797	\indexentry{status@{status}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		798	\indexentry{FILTERcfg@{FILTERcfg}!a0@{a0}\|hyperpage}{71}
		799	\indexentry{a0@{a0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		800	\indexentry{FILTERcfg@{FILTERcfg}!a0\_\discretionary {-}{}{}0@{a0\_\discretionary {-}{}{}0}\|hyperpage}{71}
		801	\indexentry{a0\_\discretionary {-}{}{}0@{a0\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		802	\indexentry{FILTERcfg@{FILTERcfg}!a0\_\discretionary {-}{}{}1@{a0\_\discretionary {-}{}{}1}\|hyperpage}{71}
		803	\indexentry{a0\_\discretionary {-}{}{}1@{a0\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		804	\indexentry{FILTERcfg@{FILTERcfg}!a0\_\discretionary {-}{}{}2@{a0\_\discretionary {-}{}{}2}\|hyperpage}{71}
		805	\indexentry{a0\_\discretionary {-}{}{}2@{a0\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		806	\indexentry{FILTERcfg@{FILTERcfg}!a1@{a1}\|hyperpage}{71}
		807	\indexentry{a1@{a1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		808	\indexentry{FILTERcfg@{FILTERcfg}!a1\_\discretionary {-}{}{}0@{a1\_\discretionary {-}{}{}0}\|hyperpage}{71}
		809	\indexentry{a1\_\discretionary {-}{}{}0@{a1\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		810	\indexentry{FILTERcfg@{FILTERcfg}!a1\_\discretionary {-}{}{}1@{a1\_\discretionary {-}{}{}1}\|hyperpage}{71}
		811	\indexentry{a1\_\discretionary {-}{}{}1@{a1\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		812	\indexentry{FILTERcfg@{FILTERcfg}!a1\_\discretionary {-}{}{}2@{a1\_\discretionary {-}{}{}2}\|hyperpage}{71}
		813	\indexentry{a1\_\discretionary {-}{}{}2@{a1\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		814	\indexentry{FILTERcfg@{FILTERcfg}!a2@{a2}\|hyperpage}{71}
		815	\indexentry{a2@{a2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		816	\indexentry{FILTERcfg@{FILTERcfg}!a2\_\discretionary {-}{}{}0@{a2\_\discretionary {-}{}{}0}\|hyperpage}{71}
		817	\indexentry{a2\_\discretionary {-}{}{}0@{a2\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		818	\indexentry{FILTERcfg@{FILTERcfg}!a2\_\discretionary {-}{}{}1@{a2\_\discretionary {-}{}{}1}\|hyperpage}{71}
		819	\indexentry{a2\_\discretionary {-}{}{}1@{a2\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		820	\indexentry{FILTERcfg@{FILTERcfg}!a2\_\discretionary {-}{}{}2@{a2\_\discretionary {-}{}{}2}\|hyperpage}{71}
		821	\indexentry{a2\_\discretionary {-}{}{}2@{a2\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		822	\indexentry{FILTERcfg@{FILTERcfg}!a3@{a3}\|hyperpage}{71}
		823	\indexentry{a3@{a3}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		824	\indexentry{FILTERcfg@{FILTERcfg}!a3\_\discretionary {-}{}{}0@{a3\_\discretionary {-}{}{}0}\|hyperpage}{71}
		825	\indexentry{a3\_\discretionary {-}{}{}0@{a3\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		826	\indexentry{FILTERcfg@{FILTERcfg}!a3\_\discretionary {-}{}{}1@{a3\_\discretionary {-}{}{}1}\|hyperpage}{71}
		827	\indexentry{a3\_\discretionary {-}{}{}1@{a3\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		828	\indexentry{FILTERcfg@{FILTERcfg}!a3\_\discretionary {-}{}{}2@{a3\_\discretionary {-}{}{}2}\|hyperpage}{71}
		829	\indexentry{a3\_\discretionary {-}{}{}2@{a3\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		830	\indexentry{FILTERcfg@{FILTERcfg}!a4@{a4}\|hyperpage}{71}
		831	\indexentry{a4@{a4}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		832	\indexentry{FILTERcfg@{FILTERcfg}!a4\_\discretionary {-}{}{}0@{a4\_\discretionary {-}{}{}0}\|hyperpage}{71}
		833	\indexentry{a4\_\discretionary {-}{}{}0@{a4\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		834	\indexentry{FILTERcfg@{FILTERcfg}!a4\_\discretionary {-}{}{}1@{a4\_\discretionary {-}{}{}1}\|hyperpage}{71}
		835	\indexentry{a4\_\discretionary {-}{}{}1@{a4\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		836	\indexentry{FILTERcfg@{FILTERcfg}!a4\_\discretionary {-}{}{}2@{a4\_\discretionary {-}{}{}2}\|hyperpage}{71}
		837	\indexentry{a4\_\discretionary {-}{}{}2@{a4\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		838	\indexentry{FILTERcfg@{FILTERcfg}!a5\_\discretionary {-}{}{}0@{a5\_\discretionary {-}{}{}0}\|hyperpage}{71}
		839	\indexentry{a5\_\discretionary {-}{}{}0@{a5\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		840	\indexentry{FILTERcfg@{FILTERcfg}!a5\_\discretionary {-}{}{}1@{a5\_\discretionary {-}{}{}1}\|hyperpage}{71}
		841	\indexentry{a5\_\discretionary {-}{}{}1@{a5\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		842	\indexentry{FILTERcfg@{FILTERcfg}!a5\_\discretionary {-}{}{}2@{a5\_\discretionary {-}{}{}2}\|hyperpage}{71}
		843	\indexentry{a5\_\discretionary {-}{}{}2@{a5\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		844	\indexentry{FILTERcfg@{FILTERcfg}!a6\_\discretionary {-}{}{}0@{a6\_\discretionary {-}{}{}0}\|hyperpage}{71}
		845	\indexentry{a6\_\discretionary {-}{}{}0@{a6\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		846	\indexentry{FILTERcfg@{FILTERcfg}!a6\_\discretionary {-}{}{}1@{a6\_\discretionary {-}{}{}1}\|hyperpage}{71}
		847	\indexentry{a6\_\discretionary {-}{}{}1@{a6\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		848	\indexentry{FILTERcfg@{FILTERcfg}!a6\_\discretionary {-}{}{}2@{a6\_\discretionary {-}{}{}2}\|hyperpage}{71}
		849	\indexentry{a6\_\discretionary {-}{}{}2@{a6\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		850	\indexentry{FILTERcfg@{FILTERcfg}!ADD@{ADD}\|hyperpage}{71}
		851	\indexentry{ADD@{ADD}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		852	\indexentry{FILTERcfg@{FILTERcfg}!b0@{b0}\|hyperpage}{71}
		853	\indexentry{b0@{b0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		854	\indexentry{FILTERcfg@{FILTERcfg}!b0\_\discretionary {-}{}{}0@{b0\_\discretionary {-}{}{}0}\|hyperpage}{71}
		855	\indexentry{b0\_\discretionary {-}{}{}0@{b0\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{71}
		856	\indexentry{FILTERcfg@{FILTERcfg}!b0\_\discretionary {-}{}{}1@{b0\_\discretionary {-}{}{}1}\|hyperpage}{73}
		857	\indexentry{b0\_\discretionary {-}{}{}1@{b0\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		858	\indexentry{FILTERcfg@{FILTERcfg}!b0\_\discretionary {-}{}{}2@{b0\_\discretionary {-}{}{}2}\|hyperpage}{73}
		859	\indexentry{b0\_\discretionary {-}{}{}2@{b0\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		860	\indexentry{FILTERcfg@{FILTERcfg}!b1@{b1}\|hyperpage}{73}
		861	\indexentry{b1@{b1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		862	\indexentry{FILTERcfg@{FILTERcfg}!b1\_\discretionary {-}{}{}0@{b1\_\discretionary {-}{}{}0}\|hyperpage}{73}
		863	\indexentry{b1\_\discretionary {-}{}{}0@{b1\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		864	\indexentry{FILTERcfg@{FILTERcfg}!b1\_\discretionary {-}{}{}1@{b1\_\discretionary {-}{}{}1}\|hyperpage}{73}
		865	\indexentry{b1\_\discretionary {-}{}{}1@{b1\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		866	\indexentry{FILTERcfg@{FILTERcfg}!b1\_\discretionary {-}{}{}2@{b1\_\discretionary {-}{}{}2}\|hyperpage}{73}
		867	\indexentry{b1\_\discretionary {-}{}{}2@{b1\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		868	\indexentry{FILTERcfg@{FILTERcfg}!b2@{b2}\|hyperpage}{73}
		869	\indexentry{b2@{b2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		870	\indexentry{FILTERcfg@{FILTERcfg}!b2\_\discretionary {-}{}{}0@{b2\_\discretionary {-}{}{}0}\|hyperpage}{73}
		871	\indexentry{b2\_\discretionary {-}{}{}0@{b2\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		872	\indexentry{FILTERcfg@{FILTERcfg}!b2\_\discretionary {-}{}{}1@{b2\_\discretionary {-}{}{}1}\|hyperpage}{73}
		873	\indexentry{b2\_\discretionary {-}{}{}1@{b2\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		874	\indexentry{FILTERcfg@{FILTERcfg}!b2\_\discretionary {-}{}{}2@{b2\_\discretionary {-}{}{}2}\|hyperpage}{73}
		875	\indexentry{b2\_\discretionary {-}{}{}2@{b2\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		876	\indexentry{FILTERcfg@{FILTERcfg}!b3@{b3}\|hyperpage}{73}
		877	\indexentry{b3@{b3}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		878	\indexentry{FILTERcfg@{FILTERcfg}!b3\_\discretionary {-}{}{}0@{b3\_\discretionary {-}{}{}0}\|hyperpage}{73}
		879	\indexentry{b3\_\discretionary {-}{}{}0@{b3\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		880	\indexentry{FILTERcfg@{FILTERcfg}!b3\_\discretionary {-}{}{}1@{b3\_\discretionary {-}{}{}1}\|hyperpage}{73}
		881	\indexentry{b3\_\discretionary {-}{}{}1@{b3\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		882	\indexentry{FILTERcfg@{FILTERcfg}!b3\_\discretionary {-}{}{}2@{b3\_\discretionary {-}{}{}2}\|hyperpage}{73}
		883	\indexentry{b3\_\discretionary {-}{}{}2@{b3\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		884	\indexentry{FILTERcfg@{FILTERcfg}!b4@{b4}\|hyperpage}{73}
		885	\indexentry{b4@{b4}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		886	\indexentry{FILTERcfg@{FILTERcfg}!b4\_\discretionary {-}{}{}0@{b4\_\discretionary {-}{}{}0}\|hyperpage}{73}
		887	\indexentry{b4\_\discretionary {-}{}{}0@{b4\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		888	\indexentry{FILTERcfg@{FILTERcfg}!b4\_\discretionary {-}{}{}1@{b4\_\discretionary {-}{}{}1}\|hyperpage}{73}
		889	\indexentry{b4\_\discretionary {-}{}{}1@{b4\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		890	\indexentry{FILTERcfg@{FILTERcfg}!b4\_\discretionary {-}{}{}2@{b4\_\discretionary {-}{}{}2}\|hyperpage}{73}
		891	\indexentry{b4\_\discretionary {-}{}{}2@{b4\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		892	\indexentry{FILTERcfg@{FILTERcfg}!b5@{b5}\|hyperpage}{73}
		893	\indexentry{b5@{b5}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		894	\indexentry{FILTERcfg@{FILTERcfg}!b5\_\discretionary {-}{}{}0@{b5\_\discretionary {-}{}{}0}\|hyperpage}{73}
		895	\indexentry{b5\_\discretionary {-}{}{}0@{b5\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		896	\indexentry{FILTERcfg@{FILTERcfg}!b5\_\discretionary {-}{}{}1@{b5\_\discretionary {-}{}{}1}\|hyperpage}{73}
		897	\indexentry{b5\_\discretionary {-}{}{}1@{b5\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		898	\indexentry{FILTERcfg@{FILTERcfg}!b5\_\discretionary {-}{}{}2@{b5\_\discretionary {-}{}{}2}\|hyperpage}{73}
		899	\indexentry{b5\_\discretionary {-}{}{}2@{b5\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		900	\indexentry{FILTERcfg@{FILTERcfg}!b6@{b6}\|hyperpage}{73}
		901	\indexentry{b6@{b6}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		902	\indexentry{FILTERcfg@{FILTERcfg}!b6\_\discretionary {-}{}{}0@{b6\_\discretionary {-}{}{}0}\|hyperpage}{73}
		903	\indexentry{b6\_\discretionary {-}{}{}0@{b6\_\discretionary {-}{}{}0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		904	\indexentry{FILTERcfg@{FILTERcfg}!b6\_\discretionary {-}{}{}1@{b6\_\discretionary {-}{}{}1}\|hyperpage}{73}
		905	\indexentry{b6\_\discretionary {-}{}{}1@{b6\_\discretionary {-}{}{}1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		906	\indexentry{FILTERcfg@{FILTERcfg}!b6\_\discretionary {-}{}{}2@{b6\_\discretionary {-}{}{}2}\|hyperpage}{73}
		907	\indexentry{b6\_\discretionary {-}{}{}2@{b6\_\discretionary {-}{}{}2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		908	\indexentry{FILTERcfg@{FILTERcfg}!cela0@{cela0}\|hyperpage}{73}
		909	\indexentry{cela0@{cela0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		910	\indexentry{FILTERcfg@{FILTERcfg}!cela1@{cela1}\|hyperpage}{73}
		911	\indexentry{cela1@{cela1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		912	\indexentry{FILTERcfg@{FILTERcfg}!cela2@{cela2}\|hyperpage}{73}
		913	\indexentry{cela2@{cela2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		914	\indexentry{FILTERcfg@{FILTERcfg}!cela3@{cela3}\|hyperpage}{73}
		915	\indexentry{cela3@{cela3}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		916	\indexentry{FILTERcfg@{FILTERcfg}!cela4@{cela4}\|hyperpage}{73}
		917	\indexentry{cela4@{cela4}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		918	\indexentry{FILTERcfg@{FILTERcfg}!cela5@{cela5}\|hyperpage}{73}
		919	\indexentry{cela5@{cela5}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		920	\indexentry{FILTERcfg@{FILTERcfg}!cela6@{cela6}\|hyperpage}{73}
		921	\indexentry{cela6@{cela6}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		922	\indexentry{FILTERcfg@{FILTERcfg}!celb0@{celb0}\|hyperpage}{73}
		923	\indexentry{celb0@{celb0}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		924	\indexentry{FILTERcfg@{FILTERcfg}!celb1@{celb1}\|hyperpage}{73}
		925	\indexentry{celb1@{celb1}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		926	\indexentry{FILTERcfg@{FILTERcfg}!celb2@{celb2}\|hyperpage}{73}
		927	\indexentry{celb2@{celb2}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		928	\indexentry{FILTERcfg@{FILTERcfg}!celb3@{celb3}\|hyperpage}{73}
		929	\indexentry{celb3@{celb3}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		930	\indexentry{FILTERcfg@{FILTERcfg}!celb4@{celb4}\|hyperpage}{73}
		931	\indexentry{celb4@{celb4}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		932	\indexentry{FILTERcfg@{FILTERcfg}!celb5@{celb5}\|hyperpage}{73}
		933	\indexentry{celb5@{celb5}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		934	\indexentry{FILTERcfg@{FILTERcfg}!celb6@{celb6}\|hyperpage}{73}
		935	\indexentry{celb6@{celb6}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		936	\indexentry{FILTERcfg@{FILTERcfg}!Cels\_\discretionary {-}{}{}count@{Cels\_\discretionary {-}{}{}count}\|hyperpage}{73}
		937	\indexentry{Cels\_\discretionary {-}{}{}count@{Cels\_\discretionary {-}{}{}count}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		938	\indexentry{FILTERcfg@{FILTERcfg}!ChanelsCNT@{ChanelsCNT}\|hyperpage}{73}
		939	\indexentry{ChanelsCNT@{ChanelsCNT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		940	\indexentry{FILTERcfg@{FILTERcfg}!clr\_\discretionary {-}{}{}mac@{clr\_\discretionary {-}{}{}mac}\|hyperpage}{73}
		941	\indexentry{clr\_\discretionary {-}{}{}mac@{clr\_\discretionary {-}{}{}mac}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		942	\indexentry{FILTERcfg@{FILTERcfg}!coef\_\discretionary {-}{}{}celT@{coef\_\discretionary {-}{}{}celT}\|hyperpage}{73}
		943	\indexentry{coef\_\discretionary {-}{}{}celT@{coef\_\discretionary {-}{}{}celT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		944	\indexentry{FILTERcfg@{FILTERcfg}!Coef\_\discretionary {-}{}{}SZ@{Coef\_\discretionary {-}{}{}SZ}\|hyperpage}{73}
		945	\indexentry{Coef\_\discretionary {-}{}{}SZ@{Coef\_\discretionary {-}{}{}SZ}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		946	\indexentry{FILTERcfg@{FILTERcfg}!coefs\_\discretionary {-}{}{}celsT@{coefs\_\discretionary {-}{}{}celsT}\|hyperpage}{73}
		947	\indexentry{coefs\_\discretionary {-}{}{}celsT@{coefs\_\discretionary {-}{}{}celsT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		948	\indexentry{FILTERcfg@{FILTERcfg}!coefs\_\discretionary {-}{}{}celT@{coefs\_\discretionary {-}{}{}celT}\|hyperpage}{73}
		949	\indexentry{coefs\_\discretionary {-}{}{}celT@{coefs\_\discretionary {-}{}{}celT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		950	\indexentry{FILTERcfg@{FILTERcfg}!coefsT@{coefsT}\|hyperpage}{73}
		951	\indexentry{coefsT@{coefsT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		952	\indexentry{FILTERcfg@{FILTERcfg}!coefT@{coefT}\|hyperpage}{73}
		953	\indexentry{coefT@{coefT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		954	\indexentry{FILTERcfg@{FILTERcfg}!DenCoefs\_\discretionary {-}{}{}cel@{DenCoefs\_\discretionary {-}{}{}cel}\|hyperpage}{73}
		955	\indexentry{DenCoefs\_\discretionary {-}{}{}cel@{DenCoefs\_\discretionary {-}{}{}cel}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		956	\indexentry{FILTERcfg@{FILTERcfg}!DenominatorCoefs@{DenominatorCoefs}\|hyperpage}{73}
		957	\indexentry{DenominatorCoefs@{DenominatorCoefs}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		958	\indexentry{FILTERcfg@{FILTERcfg}!IDLE@{IDLE}\|hyperpage}{73}
		959	\indexentry{IDLE@{IDLE}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		960	\indexentry{FILTERcfg@{FILTERcfg}!IEEE@{IEEE}\|hyperpage}{73}
		961	\indexentry{IEEE@{IEEE}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		962	\indexentry{FILTERcfg@{FILTERcfg}!in\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg@{in\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg}\|hyperpage}{73}
		963	\indexentry{in\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg@{in\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		964	\indexentry{FILTERcfg@{FILTERcfg}!MAC\_\discretionary {-}{}{}op@{MAC\_\discretionary {-}{}{}op}\|hyperpage}{73}
		965	\indexentry{MAC\_\discretionary {-}{}{}op@{MAC\_\discretionary {-}{}{}op}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		966	\indexentry{FILTERcfg@{FILTERcfg}!Mem\_\discretionary {-}{}{}use@{Mem\_\discretionary {-}{}{}use}\|hyperpage}{73}
		967	\indexentry{Mem\_\discretionary {-}{}{}use@{Mem\_\discretionary {-}{}{}use}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		968	\indexentry{FILTERcfg@{FILTERcfg}!MULT@{MULT}\|hyperpage}{73}
		969	\indexentry{MULT@{MULT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		970	\indexentry{FILTERcfg@{FILTERcfg}!NumCoefs\_\discretionary {-}{}{}cel@{NumCoefs\_\discretionary {-}{}{}cel}\|hyperpage}{73}
		971	\indexentry{NumCoefs\_\discretionary {-}{}{}cel@{NumCoefs\_\discretionary {-}{}{}cel}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		972	\indexentry{FILTERcfg@{FILTERcfg}!NumeratorCoefs@{NumeratorCoefs}\|hyperpage}{73}
		973	\indexentry{NumeratorCoefs@{NumeratorCoefs}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		974	\indexentry{FILTERcfg@{FILTERcfg}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{73}
		975	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		976	\indexentry{FILTERcfg@{FILTERcfg}!out\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg@{out\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg}\|hyperpage}{73}
		977	\indexentry{out\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg@{out\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}reg}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		978	\indexentry{FILTERcfg@{FILTERcfg}!sample\_\discretionary {-}{}{}Tbl@{sample\_\discretionary {-}{}{}Tbl}\|hyperpage}{73}
		979	\indexentry{sample\_\discretionary {-}{}{}Tbl@{sample\_\discretionary {-}{}{}Tbl}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		980	\indexentry{FILTERcfg@{FILTERcfg}!samplT@{samplT}\|hyperpage}{73}
		981	\indexentry{samplT@{samplT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		982	\indexentry{FILTERcfg@{FILTERcfg}!Scalefac\_\discretionary {-}{}{}SZ@{Scalefac\_\discretionary {-}{}{}SZ}\|hyperpage}{73}
		983	\indexentry{Scalefac\_\discretionary {-}{}{}SZ@{Scalefac\_\discretionary {-}{}{}SZ}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		984	\indexentry{FILTERcfg@{FILTERcfg}!scaleValT@{scaleValT}\|hyperpage}{73}
		985	\indexentry{scaleValT@{scaleValT}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		986	\indexentry{FILTERcfg@{FILTERcfg}!Smpl\_\discretionary {-}{}{}SZ@{Smpl\_\discretionary {-}{}{}SZ}\|hyperpage}{73}
		987	\indexentry{Smpl\_\discretionary {-}{}{}SZ@{Smpl\_\discretionary {-}{}{}SZ}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		988	\indexentry{FILTERcfg@{FILTERcfg}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{73}
		989	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		990	\indexentry{FILTERcfg@{FILTERcfg}!use\_\discretionary {-}{}{}CEL@{use\_\discretionary {-}{}{}CEL}\|hyperpage}{73}
		991	\indexentry{use\_\discretionary {-}{}{}CEL@{use\_\discretionary {-}{}{}CEL}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		992	\indexentry{FILTERcfg@{FILTERcfg}!use\_\discretionary {-}{}{}RAM@{use\_\discretionary {-}{}{}RAM}\|hyperpage}{73}
		993	\indexentry{use\_\discretionary {-}{}{}RAM@{use\_\discretionary {-}{}{}RAM}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		994	\indexentry{FILTERcfg@{FILTERcfg}!virgPos@{virgPos}\|hyperpage}{73}
		995	\indexentry{virgPos@{virgPos}!FILTERcfg@{FILTERcfg}\|hyperpage}{73}
		996	\indexentry{FilterCTRLR@{FilterCTRLR}\|hyperpage}{74}
		997	\indexentry{FilterCTRLR@{FilterCTRLR}!ALU\_\discretionary {-}{}{}Ctrl@{ALU\_\discretionary {-}{}{}Ctrl}\|hyperpage}{75}
		998	\indexentry{ALU\_\discretionary {-}{}{}Ctrl@{ALU\_\discretionary {-}{}{}Ctrl}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		999	\indexentry{FilterCTRLR@{FilterCTRLR}!clk@{clk}\|hyperpage}{75}
		1000	\indexentry{clk@{clk}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1001	\indexentry{FilterCTRLR@{FilterCTRLR}!coef@{coef}\|hyperpage}{75}
		1002	\indexentry{coef@{coef}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1003	\indexentry{FilterCTRLR@{FilterCTRLR}!FILTERcfg@{FILTERcfg}\|hyperpage}{75}
		1004	\indexentry{FILTERcfg@{FILTERcfg}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1005	\indexentry{FilterCTRLR@{FilterCTRLR}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{75}
		1006	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1007	\indexentry{FilterCTRLR@{FilterCTRLR}!IEEE@{IEEE}\|hyperpage}{75}
		1008	\indexentry{IEEE@{IEEE}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1009	\indexentry{FilterCTRLR@{FilterCTRLR}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{75}
		1010	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1011	\indexentry{FilterCTRLR@{FilterCTRLR}!lpp@{lpp}\|hyperpage}{75}
		1012	\indexentry{lpp@{lpp}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1013	\indexentry{FilterCTRLR@{FilterCTRLR}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{75}
		1014	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1015	\indexentry{FilterCTRLR@{FilterCTRLR}!reset@{reset}\|hyperpage}{75}
		1016	\indexentry{reset@{reset}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1017	\indexentry{FilterCTRLR@{FilterCTRLR}!sample@{sample}\|hyperpage}{75}
		1018	\indexentry{sample@{sample}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{75}
		1019	\indexentry{FilterCTRLR@{FilterCTRLR}!sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}\|hyperpage}{76}
		1020	\indexentry{sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{76}
		1021	\indexentry{FilterCTRLR@{FilterCTRLR}!sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}\|hyperpage}{76}
		1022	\indexentry{sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{76}
		1023	\indexentry{FilterCTRLR@{FilterCTRLR}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{76}
		1024	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{76}
		1025	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{76}
		1026	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{77}
		1027	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1028	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!clk@{clk}\|hyperpage}{77}
		1029	\indexentry{clk@{clk}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1030	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!FRAME\_\discretionary {-}{}{}CLK@{FRAME\_\discretionary {-}{}{}CLK}\|hyperpage}{77}
		1031	\indexentry{FRAME\_\discretionary {-}{}{}CLK@{FRAME\_\discretionary {-}{}{}CLK}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1032	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!IEEE@{IEEE}\|hyperpage}{77}
		1033	\indexentry{IEEE@{IEEE}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1034	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!lpp@{lpp}\|hyperpage}{77}
		1035	\indexentry{lpp@{lpp}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1036	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}\|hyperpage}{77}
		1037	\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1038	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}\|hyperpage}{77}
		1039	\indexentry{OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1040	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!reset@{reset}\|hyperpage}{77}
		1041	\indexentry{reset@{reset}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{77}
		1042	\indexentry{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}\|hyperpage}{78}
		1043	\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}\|hyperpage}{78}
		1044	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{78}
		1045	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!Adder@{Adder}\|hyperpage}{79}
		1046	\indexentry{Adder@{Adder}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1047	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!ADDRcntr@{ADDRcntr}\|hyperpage}{79}
		1048	\indexentry{ADDRcntr@{ADDRcntr}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1049	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!ALU@{ALU}\|hyperpage}{79}
		1050	\indexentry{ALU@{ALU}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1051	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!ieee@{ieee}\|hyperpage}{79}
		1052	\indexentry{ieee@{ieee}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1053	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC@{MAC}\|hyperpage}{79}
		1054	\indexentry{MAC@{MAC}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1055	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{79}
		1056	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1057	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{79}
		1058	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1059	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{79}
		1060	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1061	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{79}
		1062	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1063	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!Multiplier@{Multiplier}\|hyperpage}{79}
		1064	\indexentry{Multiplier@{Multiplier}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1065	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MUX2@{MUX2}\|hyperpage}{79}
		1066	\indexentry{MUX2@{MUX2}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1067	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!REG@{REG}\|hyperpage}{79}
		1068	\indexentry{REG@{REG}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1069	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!RShifter@{RShifter}\|hyperpage}{79}
		1070	\indexentry{RShifter@{RShifter}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{79}
		1071	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{80}
		1072	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!general_purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{80}
		1073	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{80}
		1074	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!clk@{clk}\|hyperpage}{81}
		1075	\indexentry{clk@{clk}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1076	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!coefs@{coefs}\|hyperpage}{81}
		1077	\indexentry{coefs@{coefs}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1078	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!FILTERcfg@{FILTERcfg}\|hyperpage}{81}
		1079	\indexentry{FILTERcfg@{FILTERcfg}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1080	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{81}
		1081	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1082	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!IEEE@{IEEE}\|hyperpage}{81}
		1083	\indexentry{IEEE@{IEEE}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1084	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{81}
		1085	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1086	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!lpp@{lpp}\|hyperpage}{81}
		1087	\indexentry{lpp@{lpp}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1088	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{81}
		1089	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1090	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!reset@{reset}\|hyperpage}{81}
		1091	\indexentry{reset@{reset}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{81}
		1092	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}\|hyperpage}{82}
		1093	\indexentry{sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{82}
		1094	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}\|hyperpage}{82}
		1095	\indexentry{sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{82}
		1096	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}\|hyperpage}{82}
		1097	\indexentry{sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{82}
		1098	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!Sample\_\discretionary {-}{}{}SZ@{Sample\_\discretionary {-}{}{}SZ}\|hyperpage}{82}
		1099	\indexentry{Sample\_\discretionary {-}{}{}SZ@{Sample\_\discretionary {-}{}{}SZ}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{82}
		1100	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{82}
		1101	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{82}
		1102	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!virg\_\discretionary {-}{}{}pos@{virg\_\discretionary {-}{}{}pos}\|hyperpage}{82}
		1103	\indexentry{virg\_\discretionary {-}{}{}pos@{virg\_\discretionary {-}{}{}pos}!IIR_CEL_CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{82}
		1104	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{82}
		1105	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!clk@{clk}\|hyperpage}{84}
		1106	\indexentry{clk@{clk}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1107	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!FILTERcfg@{FILTERcfg}\|hyperpage}{84}
		1108	\indexentry{FILTERcfg@{FILTERcfg}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1109	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{84}
		1110	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1111	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!IEEE@{IEEE}\|hyperpage}{84}
		1112	\indexentry{IEEE@{IEEE}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1113	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{84}
		1114	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1115	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!lpp@{lpp}\|hyperpage}{84}
		1116	\indexentry{lpp@{lpp}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1117	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{84}
		1118	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1119	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!regs\_\discretionary {-}{}{}in@{regs\_\discretionary {-}{}{}in}\|hyperpage}{84}
		1120	\indexentry{regs\_\discretionary {-}{}{}in@{regs\_\discretionary {-}{}{}in}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1121	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!regs\_\discretionary {-}{}{}out@{regs\_\discretionary {-}{}{}out}\|hyperpage}{84}
		1122	\indexentry{regs\_\discretionary {-}{}{}out@{regs\_\discretionary {-}{}{}out}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1123	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!reset@{reset}\|hyperpage}{84}
		1124	\indexentry{reset@{reset}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1125	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}\|hyperpage}{84}
		1126	\indexentry{sample\_\discretionary {-}{}{}clk@{sample\_\discretionary {-}{}{}clk}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{84}
		1127	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}\|hyperpage}{85}
		1128	\indexentry{sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{85}
		1129	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}\|hyperpage}{85}
		1130	\indexentry{sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{85}
		1131	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!Sample\_\discretionary {-}{}{}SZ@{Sample\_\discretionary {-}{}{}SZ}\|hyperpage}{85}
		1132	\indexentry{Sample\_\discretionary {-}{}{}SZ@{Sample\_\discretionary {-}{}{}SZ}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{85}
		1133	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{85}
		1134	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!IIR_CEL_FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{85}
		1135	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{85}
		1136	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!amba@{amba}\|hyperpage}{87}
		1137	\indexentry{amba@{amba}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1138	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}\|hyperpage}{87}
		1139	\indexentry{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL@{APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1140	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!devices@{devices}\|hyperpage}{87}
		1141	\indexentry{devices@{devices}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1142	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FILTER@{FILTER}\|hyperpage}{87}
		1143	\indexentry{FILTER@{FILTER}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1144	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}\|hyperpage}{87}
		1145	\indexentry{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR@{FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1146	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FILTERcfg@{FILTERcfg}\|hyperpage}{87}
		1147	\indexentry{FILTERcfg@{FILTERcfg}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1148	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!FilterCTRLR@{FilterCTRLR}\|hyperpage}{87}
		1149	\indexentry{FilterCTRLR@{FilterCTRLR}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1150	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!grlib@{grlib}\|hyperpage}{87}
		1151	\indexentry{grlib@{grlib}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1152	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!ieee@{ieee}\|hyperpage}{87}
		1153	\indexentry{ieee@{ieee}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1154	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}\|hyperpage}{87}
		1155	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1156	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}\|hyperpage}{87}
		1157	\indexentry{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER@{IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1158	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!lpp@{lpp}\|hyperpage}{87}
		1159	\indexentry{lpp@{lpp}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1160	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!RAM@{RAM}\|hyperpage}{87}
		1161	\indexentry{RAM@{RAM}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1162	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{87}
		1163	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1164	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{87}
		1165	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1166	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{87}
		1167	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1168	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!stdlib@{stdlib}\|hyperpage}{87}
		1169	\indexentry{stdlib@{stdlib}!iir_filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{87}
		1170	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{88}
		1171	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}\|hyperpage}{90}
		1172	\indexentry{LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1173	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}\|hyperpage}{90}
		1174	\indexentry{LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1175	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}\|hyperpage}{90}
		1176	\indexentry{LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1177	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DATA@{LCD\_\discretionary {-}{}{}DATA}\|hyperpage}{90}
		1178	\indexentry{LCD\_\discretionary {-}{}{}DATA@{LCD\_\discretionary {-}{}{}DATA}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1179	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!DRVR\_\discretionary {-}{}{}READY@{DRVR\_\discretionary {-}{}{}READY}\|hyperpage}{90}
		1180	\indexentry{DRVR\_\discretionary {-}{}{}READY@{DRVR\_\discretionary {-}{}{}READY}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1181	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}INITIALISED@{LCD\_\discretionary {-}{}{}INITIALISED}\|hyperpage}{90}
		1182	\indexentry{LCD\_\discretionary {-}{}{}INITIALISED@{LCD\_\discretionary {-}{}{}INITIALISED}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1183	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Word@{Word}\|hyperpage}{90}
		1184	\indexentry{Word@{Word}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1185	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!CMD\_\discretionary {-}{}{}Data@{CMD\_\discretionary {-}{}{}Data}\|hyperpage}{90}
		1186	\indexentry{CMD\_\discretionary {-}{}{}Data@{CMD\_\discretionary {-}{}{}Data}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1187	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Exec@{Exec}\|hyperpage}{90}
		1188	\indexentry{Exec@{Exec}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1189	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration@{Duration}\|hyperpage}{90}
		1190	\indexentry{Duration@{Duration}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1191	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{90}
		1192	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1193	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!ClearDSPLY@{ClearDSPLY}\|hyperpage}{90}
		1194	\indexentry{ClearDSPLY@{ClearDSPLY}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1195	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!CursorOFF@{CursorOFF}\|hyperpage}{90}
		1196	\indexentry{CursorOFF@{CursorOFF}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1197	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!CursorON@{CursorON}\|hyperpage}{90}
		1198	\indexentry{CursorON@{CursorON}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1199	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!DSPL\_\discretionary {-}{}{}CTRL@{DSPL\_\discretionary {-}{}{}CTRL}\|hyperpage}{90}
		1200	\indexentry{DSPL\_\discretionary {-}{}{}CTRL@{DSPL\_\discretionary {-}{}{}CTRL}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1201	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration\_\discretionary {-}{}{}100us@{Duration\_\discretionary {-}{}{}100us}\|hyperpage}{90}
		1202	\indexentry{Duration\_\discretionary {-}{}{}100us@{Duration\_\discretionary {-}{}{}100us}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1203	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration\_\discretionary {-}{}{}20ms@{Duration\_\discretionary {-}{}{}20ms}\|hyperpage}{90}
		1204	\indexentry{Duration\_\discretionary {-}{}{}20ms@{Duration\_\discretionary {-}{}{}20ms}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1205	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration\_\discretionary {-}{}{}4ms@{Duration\_\discretionary {-}{}{}4ms}\|hyperpage}{90}
		1206	\indexentry{Duration\_\discretionary {-}{}{}4ms@{Duration\_\discretionary {-}{}{}4ms}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1207	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration\_\discretionary {-}{}{}4us@{Duration\_\discretionary {-}{}{}4us}\|hyperpage}{90}
		1208	\indexentry{Duration\_\discretionary {-}{}{}4us@{Duration\_\discretionary {-}{}{}4us}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1209	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!FunctionSet@{FunctionSet}\|hyperpage}{90}
		1210	\indexentry{FunctionSet@{FunctionSet}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1211	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!IEEE@{IEEE}\|hyperpage}{90}
		1212	\indexentry{IEEE@{IEEE}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1213	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl@{LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl}\|hyperpage}{90}
		1214	\indexentry{LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl@{LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1215	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS}\|hyperpage}{90}
		1216	\indexentry{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1217	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS}\|hyperpage}{90}
		1218	\indexentry{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1219	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS}\|hyperpage}{90}
		1220	\indexentry{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1221	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!lpp@{lpp}\|hyperpage}{90}
		1222	\indexentry{lpp@{lpp}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1223	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!RetHome@{RetHome}\|hyperpage}{90}
		1224	\indexentry{RetHome@{RetHome}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1225	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!SetEntryMode@{SetEntryMode}\|hyperpage}{90}
		1226	\indexentry{SetEntryMode@{SetEntryMode}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1227	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}\|hyperpage}{90}
		1228	\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{90}
		1229	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{91}
		1230	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{92}
		1231	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1232	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!clk@{clk}\|hyperpage}{92}
		1233	\indexentry{clk@{clk}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1234	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!CMD@{CMD}\|hyperpage}{92}
		1235	\indexentry{CMD@{CMD}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1236	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!DATA@{DATA}\|hyperpage}{92}
		1237	\indexentry{DATA@{DATA}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1238	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!Exec@{Exec}\|hyperpage}{92}
		1239	\indexentry{Exec@{Exec}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1240	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!IEEE@{IEEE}\|hyperpage}{92}
		1241	\indexentry{IEEE@{IEEE}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1242	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}\|hyperpage}{92}
		1243	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1244	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!LCD\_\discretionary {-}{}{}CTRL@{LCD\_\discretionary {-}{}{}CTRL}\|hyperpage}{92}
		1245	\indexentry{LCD\_\discretionary {-}{}{}CTRL@{LCD\_\discretionary {-}{}{}CTRL}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1246	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!lpp@{lpp}\|hyperpage}{92}
		1247	\indexentry{lpp@{lpp}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{92}
		1248	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}\|hyperpage}{93}
		1249	\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{93}
		1250	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}\|hyperpage}{93}
		1251	\indexentry{OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{93}
		1252	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!Ready@{Ready}\|hyperpage}{93}
		1253	\indexentry{Ready@{Ready}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{93}
		1254	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!reset@{reset}\|hyperpage}{93}
		1255	\indexentry{reset@{reset}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{93}
		1256	\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}\|hyperpage}{93}
		1257	\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}\|hyperpage}{93}
		1258	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{93}
		1259	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{95}
		1260	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1261	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!clk@{clk}\|hyperpage}{95}
		1262	\indexentry{clk@{clk}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1263	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!FramBUFF@{FramBUFF}\|hyperpage}{95}
		1264	\indexentry{FramBUFF@{FramBUFF}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1265	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!IEEE@{IEEE}\|hyperpage}{95}
		1266	\indexentry{IEEE@{IEEE}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1267	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}CS1@{LCD\_\discretionary {-}{}{}CS1}\|hyperpage}{95}
		1268	\indexentry{LCD\_\discretionary {-}{}{}CS1@{LCD\_\discretionary {-}{}{}CS1}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1269	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}CS2@{LCD\_\discretionary {-}{}{}CS2}\|hyperpage}{95}
		1270	\indexentry{LCD\_\discretionary {-}{}{}CS2@{LCD\_\discretionary {-}{}{}CS2}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1271	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}data@{LCD\_\discretionary {-}{}{}data}\|hyperpage}{95}
		1272	\indexentry{LCD\_\discretionary {-}{}{}data@{LCD\_\discretionary {-}{}{}data}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1273	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}\|hyperpage}{95}
		1274	\indexentry{LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1275	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RET@{LCD\_\discretionary {-}{}{}RET}\|hyperpage}{95}
		1276	\indexentry{LCD\_\discretionary {-}{}{}RET@{LCD\_\discretionary {-}{}{}RET}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1277	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}\|hyperpage}{95}
		1278	\indexentry{LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1279	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}\|hyperpage}{95}
		1280	\indexentry{LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1281	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!lpp@{lpp}\|hyperpage}{95}
		1282	\indexentry{lpp@{lpp}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1283	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}\|hyperpage}{95}
		1284	\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1285	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz@{OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz}\|hyperpage}{95}
		1286	\indexentry{OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz@{OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1287	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!Refresh\_\discretionary {-}{}{}RateHz@{Refresh\_\discretionary {-}{}{}RateHz}\|hyperpage}{95}
		1288	\indexentry{Refresh\_\discretionary {-}{}{}RateHz@{Refresh\_\discretionary {-}{}{}RateHz}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1289	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!refreshPulse@{refreshPulse}\|hyperpage}{95}
		1290	\indexentry{refreshPulse@{refreshPulse}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1291	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!reset@{reset}\|hyperpage}{95}
		1292	\indexentry{reset@{reset}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1293	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!STATEOUT@{STATEOUT}\|hyperpage}{95}
		1294	\indexentry{STATEOUT@{STATEOUT}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1295	\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}\|hyperpage}{95}
		1296	\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}\|hyperpage}{95}
		1297	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{95}
		1298	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}\|hyperpage}{97}
		1299	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1300	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!clk@{clk}\|hyperpage}{97}
		1301	\indexentry{clk@{clk}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1302	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!clk\_\discretionary {-}{}{}1us@{clk\_\discretionary {-}{}{}1us}\|hyperpage}{97}
		1303	\indexentry{clk\_\discretionary {-}{}{}1us@{clk\_\discretionary {-}{}{}1us}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1304	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!IEEE@{IEEE}\|hyperpage}{97}
		1305	\indexentry{IEEE@{IEEE}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1306	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!lpp@{lpp}\|hyperpage}{97}
		1307	\indexentry{lpp@{lpp}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1308	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}\|hyperpage}{97}
		1309	\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1310	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}\|hyperpage}{97}
		1311	\indexentry{OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1312	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!reset@{reset}\|hyperpage}{97}
		1313	\indexentry{reset@{reset}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1314	\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}\|hyperpage}{97}
		1315	\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}\|hyperpage}{97}
		1316	\indexentry{MAC@{MAC}\|hyperpage}{97}
		1317	\indexentry{MAC@{MAC}!clk@{clk}\|hyperpage}{98}
		1318	\indexentry{clk@{clk}!MAC@{MAC}\|hyperpage}{98}
		1319	\indexentry{MAC@{MAC}!clr\_\discretionary {-}{}{}MAC@{clr\_\discretionary {-}{}{}MAC}\|hyperpage}{98}
		1320	\indexentry{clr\_\discretionary {-}{}{}MAC@{clr\_\discretionary {-}{}{}MAC}!MAC@{MAC}\|hyperpage}{98}
		1321	\indexentry{MAC@{MAC}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{98}
		1322	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC@{MAC}\|hyperpage}{98}
		1323	\indexentry{MAC@{MAC}!IEEE@{IEEE}\|hyperpage}{98}
		1324	\indexentry{IEEE@{IEEE}!MAC@{MAC}\|hyperpage}{98}
		1325	\indexentry{MAC@{MAC}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}\|hyperpage}{99}
		1326	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}!MAC@{MAC}\|hyperpage}{99}
		1327	\indexentry{MAC@{MAC}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}\|hyperpage}{99}
		1328	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}!MAC@{MAC}\|hyperpage}{99}
		1329	\indexentry{MAC@{MAC}!lpp@{lpp}\|hyperpage}{99}
		1330	\indexentry{lpp@{lpp}!MAC@{MAC}\|hyperpage}{99}
		1331	\indexentry{MAC@{MAC}!MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD@{MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD}\|hyperpage}{99}
		1332	\indexentry{MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD@{MAC\_\discretionary {-}{}{}MUL\_\discretionary {-}{}{}ADD}!MAC@{MAC}\|hyperpage}{99}
		1333	\indexentry{MAC@{MAC}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{99}
		1334	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!MAC@{MAC}\|hyperpage}{99}
		1335	\indexentry{MAC@{MAC}!OP1@{OP1}\|hyperpage}{99}
		1336	\indexentry{OP1@{OP1}!MAC@{MAC}\|hyperpage}{99}
		1337	\indexentry{MAC@{MAC}!OP2@{OP2}\|hyperpage}{99}
		1338	\indexentry{OP2@{OP2}!MAC@{MAC}\|hyperpage}{99}
		1339	\indexentry{MAC@{MAC}!RES@{RES}\|hyperpage}{99}
		1340	\indexentry{RES@{RES}!MAC@{MAC}\|hyperpage}{99}
		1341	\indexentry{MAC@{MAC}!reset@{reset}\|hyperpage}{99}
		1342	\indexentry{reset@{reset}!MAC@{MAC}\|hyperpage}{99}
		1343	\indexentry{MAC@{MAC}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{99}
		1344	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!MAC@{MAC}\|hyperpage}{99}
		1345	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{100}
		1346	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!ADD@{ADD}\|hyperpage}{101}
		1347	\indexentry{ADD@{ADD}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1348	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!ctrl@{ctrl}\|hyperpage}{101}
		1349	\indexentry{ctrl@{ctrl}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1350	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{101}
		1351	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1352	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!IEEE@{IEEE}\|hyperpage}{101}
		1353	\indexentry{IEEE@{IEEE}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1354	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!lpp@{lpp}\|hyperpage}{101}
		1355	\indexentry{lpp@{lpp}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1356	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!MACMUX2\_\discretionary {-}{}{}sel@{MACMUX2\_\discretionary {-}{}{}sel}\|hyperpage}{101}
		1357	\indexentry{MACMUX2\_\discretionary {-}{}{}sel@{MACMUX2\_\discretionary {-}{}{}sel}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1358	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!MACMUX\_\discretionary {-}{}{}sel@{MACMUX\_\discretionary {-}{}{}sel}\|hyperpage}{101}
		1359	\indexentry{MACMUX\_\discretionary {-}{}{}sel@{MACMUX\_\discretionary {-}{}{}sel}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1360	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!MULT@{MULT}\|hyperpage}{101}
		1361	\indexentry{MULT@{MULT}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1362	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{101}
		1363	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1364	\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{101}
		1365	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!MAC_CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}\|hyperpage}{101}
		1366	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{101}
		1367	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{103}
		1368	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1369	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!IEEE@{IEEE}\|hyperpage}{103}
		1370	\indexentry{IEEE@{IEEE}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1371	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!INA1@{INA1}\|hyperpage}{103}
		1372	\indexentry{INA1@{INA1}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1373	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!INA2@{INA2}\|hyperpage}{103}
		1374	\indexentry{INA2@{INA2}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1375	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!INB1@{INB1}\|hyperpage}{103}
		1376	\indexentry{INB1@{INB1}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1377	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!INB2@{INB2}\|hyperpage}{103}
		1378	\indexentry{INB2@{INB2}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1379	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}\|hyperpage}{103}
		1380	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1381	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}\|hyperpage}{103}
		1382	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1383	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!lpp@{lpp}\|hyperpage}{103}
		1384	\indexentry{lpp@{lpp}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1385	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{103}
		1386	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1387	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!OUTA@{OUTA}\|hyperpage}{103}
		1388	\indexentry{OUTA@{OUTA}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1389	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!OUTB@{OUTB}\|hyperpage}{103}
		1390	\indexentry{OUTB@{OUTB}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1391	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!sel@{sel}\|hyperpage}{103}
		1392	\indexentry{sel@{sel}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1393	\indexentry{MAC\_\discretionary {-}{}{}MUX@{MAC\_\discretionary {-}{}{}MUX}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{103}
		1394	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!MAC_MUX@{MAC\_\discretionary {-}{}{}MUX}\|hyperpage}{103}
		1395	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{103}
		1396	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{105}
		1397	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1398	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!IEEE@{IEEE}\|hyperpage}{105}
		1399	\indexentry{IEEE@{IEEE}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1400	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!Input\_\discretionary {-}{}{}SZ@{Input\_\discretionary {-}{}{}SZ}\|hyperpage}{105}
		1401	\indexentry{Input\_\discretionary {-}{}{}SZ@{Input\_\discretionary {-}{}{}SZ}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1402	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!lpp@{lpp}\|hyperpage}{105}
		1403	\indexentry{lpp@{lpp}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1404	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{105}
		1405	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1406	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!RES@{RES}\|hyperpage}{105}
		1407	\indexentry{RES@{RES}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1408	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!RES1@{RES1}\|hyperpage}{105}
		1409	\indexentry{RES1@{RES1}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1410	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!RES2@{RES2}\|hyperpage}{105}
		1411	\indexentry{RES2@{RES2}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1412	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!sel@{sel}\|hyperpage}{105}
		1413	\indexentry{sel@{sel}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1414	\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{105}
		1415	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!MAC_MUX2@{MAC\_\discretionary {-}{}{}MUX2}\|hyperpage}{105}
		1416	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{106}
		1417	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!clk@{clk}\|hyperpage}{107}
		1418	\indexentry{clk@{clk}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1419	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!D@{D}\|hyperpage}{107}
		1420	\indexentry{D@{D}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1421	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{107}
		1422	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1423	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!IEEE@{IEEE}\|hyperpage}{107}
		1424	\indexentry{IEEE@{IEEE}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1425	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!lpp@{lpp}\|hyperpage}{107}
		1426	\indexentry{lpp@{lpp}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1427	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{107}
		1428	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1429	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!Q@{Q}\|hyperpage}{107}
		1430	\indexentry{Q@{Q}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1431	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!reset@{reset}\|hyperpage}{107}
		1432	\indexentry{reset@{reset}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1433	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!size@{size}\|hyperpage}{107}
		1434	\indexentry{size@{size}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1435	\indexentry{MAC\_\discretionary {-}{}{}REG@{MAC\_\discretionary {-}{}{}REG}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{107}
		1436	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!MAC_REG@{MAC\_\discretionary {-}{}{}REG}\|hyperpage}{107}
		1437	\indexentry{Multiplier@{Multiplier}\|hyperpage}{107}
		1438	\indexentry{Multiplier@{Multiplier}!clk@{clk}\|hyperpage}{109}
		1439	\indexentry{clk@{clk}!Multiplier@{Multiplier}\|hyperpage}{109}
		1440	\indexentry{Multiplier@{Multiplier}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{109}
		1441	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!Multiplier@{Multiplier}\|hyperpage}{109}
		1442	\indexentry{Multiplier@{Multiplier}!IEEE@{IEEE}\|hyperpage}{109}
		1443	\indexentry{IEEE@{IEEE}!Multiplier@{Multiplier}\|hyperpage}{109}
		1444	\indexentry{Multiplier@{Multiplier}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}\|hyperpage}{109}
		1445	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}!Multiplier@{Multiplier}\|hyperpage}{109}
		1446	\indexentry{Multiplier@{Multiplier}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}\|hyperpage}{109}
		1447	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}!Multiplier@{Multiplier}\|hyperpage}{109}
		1448	\indexentry{Multiplier@{Multiplier}!lpp@{lpp}\|hyperpage}{109}
		1449	\indexentry{lpp@{lpp}!Multiplier@{Multiplier}\|hyperpage}{109}
		1450	\indexentry{Multiplier@{Multiplier}!mult@{mult}\|hyperpage}{109}
		1451	\indexentry{mult@{mult}!Multiplier@{Multiplier}\|hyperpage}{109}
		1452	\indexentry{Multiplier@{Multiplier}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{109}
		1453	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!Multiplier@{Multiplier}\|hyperpage}{109}
		1454	\indexentry{Multiplier@{Multiplier}!OP1@{OP1}\|hyperpage}{109}
		1455	\indexentry{OP1@{OP1}!Multiplier@{Multiplier}\|hyperpage}{109}
		1456	\indexentry{Multiplier@{Multiplier}!OP2@{OP2}\|hyperpage}{109}
		1457	\indexentry{OP2@{OP2}!Multiplier@{Multiplier}\|hyperpage}{109}
		1458	\indexentry{Multiplier@{Multiplier}!RES@{RES}\|hyperpage}{109}
		1459	\indexentry{RES@{RES}!Multiplier@{Multiplier}\|hyperpage}{109}
		1460	\indexentry{Multiplier@{Multiplier}!reset@{reset}\|hyperpage}{109}
		1461	\indexentry{reset@{reset}!Multiplier@{Multiplier}\|hyperpage}{109}
		1462	\indexentry{Multiplier@{Multiplier}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{109}
		1463	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!Multiplier@{Multiplier}\|hyperpage}{109}
		1464	\indexentry{MUX2@{MUX2}\|hyperpage}{109}
		1465	\indexentry{MUX2@{MUX2}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{111}
		1466	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!MUX2@{MUX2}\|hyperpage}{111}
		1467	\indexentry{MUX2@{MUX2}!IEEE@{IEEE}\|hyperpage}{111}
		1468	\indexentry{IEEE@{IEEE}!MUX2@{MUX2}\|hyperpage}{111}
		1469	\indexentry{MUX2@{MUX2}!IN1@{IN1}\|hyperpage}{111}
		1470	\indexentry{IN1@{IN1}!MUX2@{MUX2}\|hyperpage}{111}
		1471	\indexentry{MUX2@{MUX2}!IN2@{IN2}\|hyperpage}{111}
		1472	\indexentry{IN2@{IN2}!MUX2@{MUX2}\|hyperpage}{111}
		1473	\indexentry{MUX2@{MUX2}!Input\_\discretionary {-}{}{}SZ@{Input\_\discretionary {-}{}{}SZ}\|hyperpage}{111}
		1474	\indexentry{Input\_\discretionary {-}{}{}SZ@{Input\_\discretionary {-}{}{}SZ}!MUX2@{MUX2}\|hyperpage}{111}
		1475	\indexentry{MUX2@{MUX2}!lpp@{lpp}\|hyperpage}{111}
		1476	\indexentry{lpp@{lpp}!MUX2@{MUX2}\|hyperpage}{111}
		1477	\indexentry{MUX2@{MUX2}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{111}
		1478	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!MUX2@{MUX2}\|hyperpage}{111}
		1479	\indexentry{MUX2@{MUX2}!RES@{RES}\|hyperpage}{111}
		1480	\indexentry{RES@{RES}!MUX2@{MUX2}\|hyperpage}{111}
		1481	\indexentry{MUX2@{MUX2}!sel@{sel}\|hyperpage}{111}
		1482	\indexentry{sel@{sel}!MUX2@{MUX2}\|hyperpage}{111}
		1483	\indexentry{MUX2@{MUX2}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{111}
		1484	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!MUX2@{MUX2}\|hyperpage}{111}
		1485	\indexentry{RAM@{RAM}\|hyperpage}{111}
		1486	\indexentry{RAM@{RAM}!ieee@{ieee}\|hyperpage}{112}
		1487	\indexentry{ieee@{ieee}!RAM@{RAM}\|hyperpage}{112}
		1488	\indexentry{RAM@{RAM}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{112}
		1489	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!RAM@{RAM}\|hyperpage}{112}
		1490	\indexentry{RAM@{RAM}!RADDR@{RADDR}\|hyperpage}{112}
		1491	\indexentry{RADDR@{RADDR}!RAM@{RAM}\|hyperpage}{112}
		1492	\indexentry{RAM@{RAM}!RD@{RD}\|hyperpage}{112}
		1493	\indexentry{RD@{RD}!RAM@{RAM}\|hyperpage}{112}
		1494	\indexentry{RAM@{RAM}!REN@{REN}\|hyperpage}{112}
		1495	\indexentry{REN@{REN}!RAM@{RAM}\|hyperpage}{112}
		1496	\indexentry{RAM@{RAM}!RESET@{RESET}\|hyperpage}{112}
		1497	\indexentry{RESET@{RESET}!RAM@{RAM}\|hyperpage}{112}
		1498	\indexentry{RAM@{RAM}!RWCLK@{RWCLK}\|hyperpage}{112}
		1499	\indexentry{RWCLK@{RWCLK}!RAM@{RAM}\|hyperpage}{112}
		1500	\indexentry{RAM@{RAM}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{112}
		1501	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!RAM@{RAM}\|hyperpage}{112}
		1502	\indexentry{RAM@{RAM}!WADDR@{WADDR}\|hyperpage}{112}
		1503	\indexentry{WADDR@{WADDR}!RAM@{RAM}\|hyperpage}{112}
		1504	\indexentry{RAM@{RAM}!WD@{WD}\|hyperpage}{113}
		1505	\indexentry{WD@{WD}!RAM@{RAM}\|hyperpage}{113}
		1506	\indexentry{RAM@{RAM}!WEN@{WEN}\|hyperpage}{113}
		1507	\indexentry{WEN@{WEN}!RAM@{RAM}\|hyperpage}{113}
		1508	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{113}
		1509	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!ieee@{ieee}\|hyperpage}{114}
		1510	\indexentry{ieee@{ieee}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1511	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{114}
		1512	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1513	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!RADDR@{RADDR}\|hyperpage}{114}
		1514	\indexentry{RADDR@{RADDR}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1515	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!RD@{RD}\|hyperpage}{114}
		1516	\indexentry{RD@{RD}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1517	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!REN@{REN}\|hyperpage}{114}
		1518	\indexentry{REN@{REN}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1519	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!RESET@{RESET}\|hyperpage}{114}
		1520	\indexentry{RESET@{RESET}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1521	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!RWCLK@{RWCLK}\|hyperpage}{114}
		1522	\indexentry{RWCLK@{RWCLK}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1523	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{114}
		1524	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1525	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!WADDR@{WADDR}\|hyperpage}{114}
		1526	\indexentry{WADDR@{WADDR}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1527	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!WD@{WD}\|hyperpage}{114}
		1528	\indexentry{WD@{WD}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1529	\indexentry{RAM\_\discretionary {-}{}{}CEL@{RAM\_\discretionary {-}{}{}CEL}!WEN@{WEN}\|hyperpage}{114}
		1530	\indexentry{WEN@{WEN}!RAM_CEL@{RAM\_\discretionary {-}{}{}CEL}\|hyperpage}{114}
		1531	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{114}
		1532	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!clk@{clk}\|hyperpage}{116}
		1533	\indexentry{clk@{clk}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1534	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!count@{count}\|hyperpage}{116}
		1535	\indexentry{count@{count}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1536	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!FILTERcfg@{FILTERcfg}\|hyperpage}{116}
		1537	\indexentry{FILTERcfg@{FILTERcfg}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1538	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{116}
		1539	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1540	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!GO\_\discretionary {-}{}{}0@{GO\_\discretionary {-}{}{}0}\|hyperpage}{116}
		1541	\indexentry{GO\_\discretionary {-}{}{}0@{GO\_\discretionary {-}{}{}0}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1542	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!IEEE@{IEEE}\|hyperpage}{116}
		1543	\indexentry{IEEE@{IEEE}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1544	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}\|hyperpage}{116}
		1545	\indexentry{iir\_\discretionary {-}{}{}filter@{iir\_\discretionary {-}{}{}filter}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1546	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}1@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}1}\|hyperpage}{116}
		1547	\indexentry{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}1@{Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}1}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1548	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!lpp@{lpp}\|hyperpage}{116}
		1549	\indexentry{lpp@{lpp}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1550	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{116}
		1551	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1552	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!Read@{Read}\|hyperpage}{116}
		1553	\indexentry{Read@{Read}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{116}
		1554	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!reset@{reset}\|hyperpage}{117}
		1555	\indexentry{reset@{reset}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1556	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}\|hyperpage}{117}
		1557	\indexentry{sample\_\discretionary {-}{}{}in@{sample\_\discretionary {-}{}{}in}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1558	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}\|hyperpage}{117}
		1559	\indexentry{sample\_\discretionary {-}{}{}out@{sample\_\discretionary {-}{}{}out}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1560	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{117}
		1561	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1562	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!SVG\_\discretionary {-}{}{}ADDR@{SVG\_\discretionary {-}{}{}ADDR}\|hyperpage}{117}
		1563	\indexentry{SVG\_\discretionary {-}{}{}ADDR@{SVG\_\discretionary {-}{}{}ADDR}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1564	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!WADDR\_\discretionary {-}{}{}sel@{WADDR\_\discretionary {-}{}{}sel}\|hyperpage}{117}
		1565	\indexentry{WADDR\_\discretionary {-}{}{}sel@{WADDR\_\discretionary {-}{}{}sel}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1566	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!WD\_\discretionary {-}{}{}sel@{WD\_\discretionary {-}{}{}sel}\|hyperpage}{117}
		1567	\indexentry{WD\_\discretionary {-}{}{}sel@{WD\_\discretionary {-}{}{}sel}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1568	\indexentry{RAM\_\discretionary {-}{}{}CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}!Write@{Write}\|hyperpage}{117}
		1569	\indexentry{Write@{Write}!RAM_CTRLR2@{RAM\_\discretionary {-}{}{}CTRLR2}\|hyperpage}{117}
		1570	\indexentry{REG@{REG}\|hyperpage}{117}
		1571	\indexentry{REG@{REG}!clk@{clk}\|hyperpage}{118}
		1572	\indexentry{clk@{clk}!REG@{REG}\|hyperpage}{118}
		1573	\indexentry{REG@{REG}!D@{D}\|hyperpage}{118}
		1574	\indexentry{D@{D}!REG@{REG}\|hyperpage}{118}
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		1576	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!REG@{REG}\|hyperpage}{118}
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		1578	\indexentry{IEEE@{IEEE}!REG@{REG}\|hyperpage}{118}
		1579	\indexentry{REG@{REG}!initial\_\discretionary {-}{}{}VALUE@{initial\_\discretionary {-}{}{}VALUE}\|hyperpage}{118}
		1580	\indexentry{initial\_\discretionary {-}{}{}VALUE@{initial\_\discretionary {-}{}{}VALUE}!REG@{REG}\|hyperpage}{118}
		1581	\indexentry{REG@{REG}!lpp@{lpp}\|hyperpage}{118}
		1582	\indexentry{lpp@{lpp}!REG@{REG}\|hyperpage}{118}
		1583	\indexentry{REG@{REG}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{118}
		1584	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!REG@{REG}\|hyperpage}{118}
		1585	\indexentry{REG@{REG}!Q@{Q}\|hyperpage}{119}
		1586	\indexentry{Q@{Q}!REG@{REG}\|hyperpage}{119}
		1587	\indexentry{REG@{REG}!reset@{reset}\|hyperpage}{119}
		1588	\indexentry{reset@{reset}!REG@{REG}\|hyperpage}{119}
		1589	\indexentry{REG@{REG}!size@{size}\|hyperpage}{119}
		1590	\indexentry{size@{size}!REG@{REG}\|hyperpage}{119}
		1591	\indexentry{REG@{REG}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{119}
		1592	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!REG@{REG}\|hyperpage}{119}
		1593	\indexentry{RShifter@{RShifter}\|hyperpage}{119}
		1594	\indexentry{RShifter@{RShifter}!clk@{clk}\|hyperpage}{120}
		1595	\indexentry{clk@{clk}!RShifter@{RShifter}\|hyperpage}{120}
		1596	\indexentry{RShifter@{RShifter}!cnt@{cnt}\|hyperpage}{120}
		1597	\indexentry{cnt@{cnt}!RShifter@{RShifter}\|hyperpage}{120}
		1598	\indexentry{RShifter@{RShifter}!general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}\|hyperpage}{120}
		1599	\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}!RShifter@{RShifter}\|hyperpage}{120}
		1600	\indexentry{RShifter@{RShifter}!IEEE@{IEEE}\|hyperpage}{120}
		1601	\indexentry{IEEE@{IEEE}!RShifter@{RShifter}\|hyperpage}{120}
		1602	\indexentry{RShifter@{RShifter}!Input\_\discretionary {-}{}{}SZ@{Input\_\discretionary {-}{}{}SZ}\|hyperpage}{120}
		1603	\indexentry{Input\_\discretionary {-}{}{}SZ@{Input\_\discretionary {-}{}{}SZ}!RShifter@{RShifter}\|hyperpage}{120}
		1604	\indexentry{RShifter@{RShifter}!lpp@{lpp}\|hyperpage}{120}
		1605	\indexentry{lpp@{lpp}!RShifter@{RShifter}\|hyperpage}{120}
		1606	\indexentry{RShifter@{RShifter}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{120}
		1607	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!RShifter@{RShifter}\|hyperpage}{120}
		1608	\indexentry{RShifter@{RShifter}!OP@{OP}\|hyperpage}{120}
		1609	\indexentry{OP@{OP}!RShifter@{RShifter}\|hyperpage}{120}
		1610	\indexentry{RShifter@{RShifter}!RES@{RES}\|hyperpage}{120}
		1611	\indexentry{RES@{RES}!RShifter@{RShifter}\|hyperpage}{120}
		1612	\indexentry{RShifter@{RShifter}!reset@{reset}\|hyperpage}{120}
		1613	\indexentry{reset@{reset}!RShifter@{RShifter}\|hyperpage}{120}
		1614	\indexentry{RShifter@{RShifter}!shift@{shift}\|hyperpage}{120}
		1615	\indexentry{shift@{shift}!RShifter@{RShifter}\|hyperpage}{120}
		1616	\indexentry{RShifter@{RShifter}!shift\_\discretionary {-}{}{}SZ@{shift\_\discretionary {-}{}{}SZ}\|hyperpage}{120}
		1617	\indexentry{shift\_\discretionary {-}{}{}SZ@{shift\_\discretionary {-}{}{}SZ}!RShifter@{RShifter}\|hyperpage}{120}
		1618	\indexentry{RShifter@{RShifter}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{120}
		1619	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!RShifter@{RShifter}\|hyperpage}{120}
		1620	\indexentry{TestbenshALU@{TestbenshALU}\|hyperpage}{121}
		1621	\indexentry{TestbenshALU@{TestbenshALU}!IEEE@{IEEE}\|hyperpage}{121}
		1622	\indexentry{IEEE@{IEEE}!TestbenshALU@{TestbenshALU}\|hyperpage}{121}
		1623	\indexentry{TestbenshALU@{TestbenshALU}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{121}
		1624	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!TestbenshALU@{TestbenshALU}\|hyperpage}{121}
		1625	\indexentry{TestbenshALU@{TestbenshALU}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{121}
		1626	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!TestbenshALU@{TestbenshALU}\|hyperpage}{121}
		1627	\indexentry{TestbenshMAC@{TestbenshMAC}\|hyperpage}{122}
		1628	\indexentry{TestbenshMAC@{TestbenshMAC}!IEEE@{IEEE}\|hyperpage}{122}
		1629	\indexentry{IEEE@{IEEE}!TestbenshMAC@{TestbenshMAC}\|hyperpage}{122}
		1630	\indexentry{TestbenshMAC@{TestbenshMAC}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}\|hyperpage}{122}
		1631	\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!TestbenshMAC@{TestbenshMAC}\|hyperpage}{122}
		1632	\indexentry{TestbenshMAC@{TestbenshMAC}!std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}\|hyperpage}{122}
		1633	\indexentry{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164@{std\_\discretionary {-}{}{}logic\_\discretionary {-}{}{}1164}!TestbenshMAC@{TestbenshMAC}\|hyperpage}{122}
		1634	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr.vhd}\|hyperpage}{123}
		1635	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/FRAME\_\discretionary {-}{}{}CLK.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/FRAME\_\discretionary {-}{}{}CLK.vhd}\|hyperpage}{123}
		1636	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG.vhd}\|hyperpage}{123}
		1637	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE.vhd}\|hyperpage}{123}
		1638	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER.vhd}\|hyperpage}{124}
		1639	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR.vhd}\|hyperpage}{124}
		1640	\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/Top\_\discretionary {-}{}{}LCD.vhd@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr/Top\_\discretionary {-}{}{}LCD.vhd}\|hyperpage}{124}
		1641	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL.vhd@{dsp/iir\_\discretionary {-}{}{}filter/APB\_\discretionary {-}{}{}IIR\_\discretionary {-}{}{}CEL.vhd}\|hyperpage}{124}
		1642	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/FILTER.vhd@{dsp/iir\_\discretionary {-}{}{}filter/FILTER.vhd}\|hyperpage}{124}
		1643	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR.vhd@{dsp/iir\_\discretionary {-}{}{}filter/FILTER\_\discretionary {-}{}{}RAM\_\discretionary {-}{}{}CTRLR.vhd}\|hyperpage}{124}
		1644	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/FILTERcfg.vhd@{dsp/iir\_\discretionary {-}{}{}filter/FILTERcfg.vhd}\|hyperpage}{125}
		1645	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/FilterCTRLR.vhd@{dsp/iir\_\discretionary {-}{}{}filter/FilterCTRLR.vhd}\|hyperpage}{125}
		1646	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR.vhd@{dsp/iir\_\discretionary {-}{}{}filter/IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}CTRLR.vhd}\|hyperpage}{125}
		1647	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER.vhd@{dsp/iir\_\discretionary {-}{}{}filter/IIR\_\discretionary {-}{}{}CEL\_\discretionary {-}{}{}FILTER.vhd}\|hyperpage}{125}
		1648	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/iir\_\discretionary {-}{}{}filter.vhd@{dsp/iir\_\discretionary {-}{}{}filter/iir\_\discretionary {-}{}{}filter.vhd}\|hyperpage}{125}
		1649	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/RAM.vhd@{dsp/iir\_\discretionary {-}{}{}filter/RAM.vhd}\|hyperpage}{125}
		1650	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/RAM\_\discretionary {-}{}{}CEL.vhd@{dsp/iir\_\discretionary {-}{}{}filter/RAM\_\discretionary {-}{}{}CEL.vhd}\|hyperpage}{126}
		1651	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/RAM\_\discretionary {-}{}{}CTRLR2.vhd@{dsp/iir\_\discretionary {-}{}{}filter/RAM\_\discretionary {-}{}{}CTRLR2.vhd}\|hyperpage}{126}
		1652	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/TestbenshMAC.vhd@{dsp/iir\_\discretionary {-}{}{}filter/TestbenshMAC.vhd}\|hyperpage}{126}
		1653	\indexentry{dsp/iir\_\discretionary {-}{}{}filter/Top\_\discretionary {-}{}{}Filtre\_\discretionary {-}{}{}IIR.vhd@{dsp/iir\_\discretionary {-}{}{}filter/Top\_\discretionary {-}{}{}Filtre\_\discretionary {-}{}{}IIR.vhd}\|hyperpage}{126}
		1654	\indexentry{general\_\discretionary {-}{}{}purpose/Adder.vhd@{general\_\discretionary {-}{}{}purpose/Adder.vhd}\|hyperpage}{126}
		1655	\indexentry{general\_\discretionary {-}{}{}purpose/ADDRcntr.vhd@{general\_\discretionary {-}{}{}purpose/ADDRcntr.vhd}\|hyperpage}{126}
		1656	\indexentry{general\_\discretionary {-}{}{}purpose/ALU.vhd@{general\_\discretionary {-}{}{}purpose/ALU.vhd}\|hyperpage}{126}
		1657	\indexentry{general\_\discretionary {-}{}{}purpose/general\_\discretionary {-}{}{}purpose.vhd@{general\_\discretionary {-}{}{}purpose/general\_\discretionary {-}{}{}purpose.vhd}\|hyperpage}{127}
		1658	\indexentry{general\_\discretionary {-}{}{}purpose/MAC.vhd@{general\_\discretionary {-}{}{}purpose/MAC.vhd}\|hyperpage}{127}
		1659	\indexentry{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}CONTROLER.vhd@{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}CONTROLER.vhd}\|hyperpage}{127}
		1660	\indexentry{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}MUX.vhd@{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}MUX.vhd}\|hyperpage}{127}
		1661	\indexentry{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}MUX2.vhd@{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}MUX2.vhd}\|hyperpage}{127}
		1662	\indexentry{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}REG.vhd@{general\_\discretionary {-}{}{}purpose/MAC\_\discretionary {-}{}{}REG.vhd}\|hyperpage}{127}
		1663	\indexentry{general\_\discretionary {-}{}{}purpose/Multiplier.vhd@{general\_\discretionary {-}{}{}purpose/Multiplier.vhd}\|hyperpage}{128}
		1664	\indexentry{general\_\discretionary {-}{}{}purpose/MUX2.vhd@{general\_\discretionary {-}{}{}purpose/MUX2.vhd}\|hyperpage}{128}
		1665	\indexentry{general\_\discretionary {-}{}{}purpose/REG.vhd@{general\_\discretionary {-}{}{}purpose/REG.vhd}\|hyperpage}{128}
		1666	\indexentry{general\_\discretionary {-}{}{}purpose/Shifter.vhd@{general\_\discretionary {-}{}{}purpose/Shifter.vhd}\|hyperpage}{128}
		1667	\indexentry{general\_\discretionary {-}{}{}purpose/TestbenshALU.vhd@{general\_\discretionary {-}{}{}purpose/TestbenshALU.vhd}\|hyperpage}{128}

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lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd created 644 +193 0

@@ -0,0 +1,193
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- APB_IIR_CEL.vhd
	20	library ieee;
	21	use ieee.std_logic_1164.all;
	22	use ieee.numeric_std.all;
	23	library grlib;
	24	use grlib.amba.all;
	25	use grlib.stdlib.all;
	26	use grlib.devices.all;
	27	library lpp;
	28	use lpp.iir_filter.all;
	29	use lpp.FILTERcfg.all;
	30	use lpp.general_purpose.all;
	31	use lpp.lpp_amba.all;
	32
	33	entity APB_IIR_CEL is
	34	generic (
	35	pindex : integer := 0;
	36	paddr : integer := 0;
	37	pmask : integer := 16#fff#;
	38	pirq : integer := 0;
	39	abits : integer := 8;
	40	Sample_SZ : integer := Smpl_SZ
	41	);
	42	port (
	43	rst : in std_logic;
	44	clk : in std_logic;
	45	apbi : in apb_slv_in_type;
	46	apbo : out apb_slv_out_type;
	47	sample_clk : in std_logic;
	48	sample_clk_out : out std_logic;
	49	sample_in : in samplT;
	50	sample_out : out samplT
	51	);
	52	end;
	53
	54
	55	architecture AR_APB_IIR_CEL of APB_IIR_CEL is
	56
	57	constant REVISION : integer := 1;
	58
	59	constant pconfig : apb_config_type := (
	60	0 => ahb_device_reg (VENDOR_LPP, ROCKET_TM, 0, REVISION, 0),
	61	1 => apb_iobar(paddr, pmask));
	62
	63
	64
	65	type FILTERreg is record
	66	regin : in_IIR_CEL_reg;
	67	regout : out_IIR_CEL_reg;
	68	end record;
	69
	70	signal r : FILTERreg;
	71	signal filter_reset : std_logic:='0';
	72	signal smp_cnt : integer :=0;
	73	signal sample_clk_out_R : std_logic;
	74	begin
	75
	76	filter_reset <= rst and r.regin.config(0);
	77	sample_clk_out <= sample_clk_out_R;
	78
	79	filter : IIR_CEL_FILTER
	80	generic map(Sample_SZ => Sample_SZ)
	81	port map(
	82	reset => filter_reset,
	83	clk => clk,
	84	sample_clk => sample_clk,
	85	regs_in => r.regin,
	86	regs_out => r.regout,
	87	sample_in => sample_in,
	88	sample_out => sample_out
	89	);
	90
	91	process(rst,sample_clk)
	92	begin
	93	if rst = '0' then
	94	smp_cnt <= 0;
	95	sample_clk_out_R <= '0';
	96	elsif sample_clk'event and sample_clk = '1' then
	97	if smp_cnt = 1 then
	98	smp_cnt <= 0;
	99	sample_clk_out_R <= not sample_clk_out_R;
	100	else
	101	smp_cnt <= smp_cnt +1;
	102	end if;
	103	end if;
	104	end process;
	105
	106
	107	process(rst,clk)
	108	begin
	109	if rst = '0' then
	110	r.regin.coefsTB.NumCoefs <= NumCoefs_cel;
	111	r.regin.coefsTB.DenCoefs <= DenCoefs_cel;
	112	r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
	113
	114	elsif clk'event and clk = '1' then
	115
	116
	117	--APB Write OP
	118	if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
	119	case apbi.paddr(7 downto 2) is
	120	when "000000" =>
	121	r.regin.config(0) <= apbi.pwdata(0);
	122	when "000001" =>
	123	r.regin.virgPos <= apbi.pwdata(4 downto 0);
	124	when others =>
	125	for i in 0 to Cels_count-1 loop
	126	if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
	127	case apbi.paddr(4 downto 2) is
	128	when "000" =>
	129	r.regin.coefsTB.NumCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
	130	when "001" =>
	131	r.regin.coefsTB.NumCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
	132	when "010" =>
	133	r.regin.coefsTB.NumCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
	134	when "011" =>
	135	r.regin.coefsTB.DenCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
	136	when "100" =>
	137	r.regin.coefsTB.DenCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
	138	when "101" =>
	139	r.regin.coefsTB.DenCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
	140	when others =>
	141	end case;
	142	end if;
	143	end loop;
	144	end case;
	145	end if;
	146
	147	--APB READ OP
	148	if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
	149	case apbi.paddr(7 downto 2) is
	150	when "000000" =>
	151
	152	when "000001" =>
	153	apbo.prdata(4 downto 0) <= r.regin.virgPos;
	154	when others =>
	155	for i in 0 to Cels_count-1 loop
	156	if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
	157	case apbi.paddr(4 downto 2) is
	158	when "000" =>
	159	apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(0));
	160	when "001" =>
	161	apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(1));
	162	when "010" =>
	163	apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(2));
	164	when "011" =>
	165	apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(0));
	166	when "100" =>
	167	apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(1));
	168	when "101" =>
	169	apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(2));
	170	when others =>
	171	end case;
	172	end if;
	173	end loop;
	174	end case;
	175	end if;
	176
	177	end if;
	178	apbo.pconfig <= pconfig;
	179	end process;
	180
	181
	182
	183	-- pragma translate_off
	184	bootmsg : report_version
	185	generic map ("apbuart" & tost(pindex) &
	186	": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
	187	", irq " & tost(pirq));
	188	-- pragma translate_on
	189
	190
	191
	192	end ar_APB_IIR_CEL;
	193

lib/lpp/dsp/iir_filter/DOC_APB_ROCKET_TM.odt created 644 binary 0 0

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lib/lpp/dsp/iir_filter/FILTER.vhd created 644 +102 0

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	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- FILTER.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.iir_filter.all;
	25	use lpp.FILTERcfg.all;
	26	use lpp.general_purpose.all;
	27	--Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
	28	--exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
	29	--Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
	30
	31	entity FILTER is
	32	port(
	33
	34	reset : in std_logic;
	35	clk : in std_logic;
	36	sample_clk : in std_logic;
	37	Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
	38	Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
	39	);
	40	end entity;
	41
	42
	43
	44
	45
	46	architecture ar_FILTER of FILTER is
	47
	48
	49
	50
	51	signal ALU_ctrl : std_logic_vector(3 downto 0);
	52	signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
	53	signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
	54	signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
	55
	56	begin
	57
	58	--==============================================================
	59	--=========================A L U================================
	60	--==============================================================
	61	ALU1 : entity ALU
	62	generic map(
	63	Arith_en => 1,
	64	Logic_en => 0,
	65	Input_SZ_1 => Smpl_SZ,
	66	Input_SZ_2 => Coef_SZ
	67
	68	)
	69	port map(
	70	clk => clk,
	71	reset => reset,
	72	ctrl => ALU_ctrl,
	73	OP1 => Sample,
	74	OP2 => Coef,
	75	RES => ALU_OUT
	76	);
	77	--==============================================================
	78
	79	--==============================================================
	80	--===============F I L T E R C O N T R O L E R================
	81	--==============================================================
	82	filterctrlr1 : FilterCTRLR
	83	port map(
	84	reset => reset,
	85	clk => clk,
	86	sample_clk => sample_clk,
	87	ALU_Ctrl => ALU_ctrl,
	88	sample_in => sample_Tbl,
	89	coef => Coef,
	90	sample => Sample
	91	);
	92	--==============================================================
	93
	94	chanelCut : for i in 0 to ChanelsCNT-1 generate
	95	sample_Tbl(i) <= Sample_IN((i+1)Smpl_SZ-1 downto iSmpl_SZ);
	96	end generate;
	97
	98
	99
	100
	101	end ar_FILTER;
	102

lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd created 644 +226 0

@@ -0,0 +1,226
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- FILTER_RAM_CTRLR.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.iir_filter.all;
	25	use lpp.FILTERcfg.all;
	26	use lpp.general_purpose.all;
	27
	28	--TODO am�liorer la flexibilit� de la config de la RAM.
	29
	30	entity FILTER_RAM_CTRLR is
	31	port(
	32	reset : in std_logic;
	33	clk : in std_logic;
	34	run : in std_logic;
	35	GO_0 : in std_logic;
	36	B_A : in std_logic;
	37	writeForce : in std_logic;
	38	next_blk : in std_logic;
	39	sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
	40	sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
	41	);
	42	end FILTER_RAM_CTRLR;
	43
	44
	45	architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
	46
	47	signal WD : std_logic_vector(35 downto 0);
	48	signal WD_D : std_logic_vector(35 downto 0);
	49	signal RD : std_logic_vector(35 downto 0);
	50	signal WEN, REN : std_logic;
	51	signal WADDR_back : std_logic_vector(7 downto 0);
	52	signal WADDR_back_D: std_logic_vector(7 downto 0);
	53	signal RADDR : std_logic_vector(7 downto 0);
	54	signal WADDR : std_logic_vector(7 downto 0);
	55	signal WADDR_D : std_logic_vector(7 downto 0);
	56	signal run_D : std_logic;
	57	signal run_D_inv : std_logic;
	58	signal run_inv : std_logic;
	59	signal next_blk_D : std_logic;
	60	signal MUX2_inst1_sel : std_logic;
	61
	62
	63	begin
	64
	65	sample_out <= RD(Smpl_SZ-1 downto 0);
	66
	67	MUX2_inst1_sel <= run_D and not next_blk;
	68	run_D_inv <= not run_D;
	69	run_inv <= not run;
	70	WEN <= run_D_inv and not writeForce;
	71	REN <= run_inv ;--and not next_blk;
	72
	73
	74	--==============================================================
	75	--=========================R A M================================
	76	--==============================================================
	77	memRAM : if Mem_use = use_RAM generate
	78	RAMblk :RAM
	79	port map(
	80	WD => WD_D,
	81	RD => RD,
	82	WEN => WEN,
	83	REN => REN,
	84	WADDR => WADDR,
	85	RADDR => RADDR,
	86	RWCLK => clk,
	87	RESET => reset
	88	) ;
	89	end generate;
	90
	91	memCEL : if Mem_use = use_CEL generate
	92	RAMblk :RAM_CEL
	93	port map(
	94	WD => WD_D,
	95	RD => RD,
	96	WEN => WEN,
	97	REN => REN,
	98	WADDR => WADDR,
	99	RADDR => RADDR,
	100	RWCLK => clk,
	101	RESET => reset
	102	) ;
	103	end generate;
	104	--==============================================================
	105	--==============================================================
	106
	107
	108	ADDRcntr_inst : ADDRcntr
	109	port map(
	110	clk => clk,
	111	reset => reset,
	112	count => run,
	113	clr => GO_0,
	114	Q => RADDR
	115	);
	116
	117
	118
	119	MUX2_inst1 :MUX2
	120	generic map(Input_SZ => Smpl_SZ)
	121	port map(
	122	sel => MUX2_inst1_sel,
	123	IN1 => sample_in,
	124	IN2 => RD(Smpl_SZ-1 downto 0),
	125	RES => WD(Smpl_SZ-1 downto 0)
	126	);
	127
	128
	129	MUX2_inst2 :MUX2
	130	generic map(Input_SZ => 8)
	131	port map(
	132	sel => next_blk_D,
	133	IN1 => WADDR_D,
	134	IN2 => WADDR_back_D,
	135	RES => WADDR
	136	);
	137
	138
	139	next_blkRreg :REG
	140	generic map(size => 1)
	141	port map(
	142	reset => reset,
	143	clk => clk,
	144	D(0) => next_blk,
	145	Q(0) => next_blk_D
	146	);
	147
	148	WADDR_backreg :REG
	149	generic map(size => 8)
	150	port map(
	151	reset => reset,
	152	clk => B_A,
	153	D => RADDR,
	154	Q => WADDR_back
	155	);
	156
	157	WADDR_backreg2 :REG
	158	generic map(size => 8)
	159	port map(
	160	reset => reset,
	161	clk => B_A,
	162	D => WADDR_back,
	163	Q => WADDR_back_D
	164	);
	165
	166	WDRreg :REG
	167	generic map(size => Smpl_SZ)
	168	port map(
	169	reset => reset,
	170	clk => clk,
	171	D => WD(Smpl_SZ-1 downto 0),
	172	Q => WD_D(Smpl_SZ-1 downto 0)
	173	);
	174
	175	RunRreg :REG
	176	generic map(size => 1)
	177	port map(
	178	reset => reset,
	179	clk => clk,
	180	D(0) => run,
	181	Q(0) => run_D
	182	);
	183
	184
	185
	186	ADDRreg :REG
	187	generic map(size => 8)
	188	port map(
	189	reset => reset,
	190	clk => clk,
	191	D => RADDR,
	192	Q => WADDR_D
	193	);
	194
	195
	196
	197	end ar_FILTER_RAM_CTRLR;
	198
	199
	200
	201
	202
	203
	204
	205
	206
	207
	208
	209
	210
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lib/lpp/dsp/iir_filter/FILTERcfg.vhd created 644 +242 0

@@ -0,0 +1,242
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- FILTERcfg.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23
	24
	25	package FILTERcfg is
	26
	27
	28	--===========================================================\|
	29	--================A L U C O N T R O L======================\|
	30	--===========================================================\|
	31	constant IDLE : std_logic_vector(3 downto 0) := "0000";
	32	constant MAC_op : std_logic_vector(3 downto 0) := "0001";
	33	constant MULT : std_logic_vector(3 downto 0) := "0010";
	34	constant ADD : std_logic_vector(3 downto 0) := "0011";
	35	constant clr_mac : std_logic_vector(3 downto 0) := "0100";
	36
	37
	38	--===========================================================\|
	39	--========F I L T E R C O N F I G V A L U E S=============\|
	40	--===========================================================\|
	41	--____________________________
	42	--Bus Width and chanels number\|
	43	--____________________________\|
	44	constant ChanelsCNT : integer := 6;
	45	constant Smpl_SZ : integer := 16;
	46	constant Coef_SZ : integer := 9;
	47	constant Scalefac_SZ: integer := 3;
	48	constant Cels_count : integer := 5;
	49	--____
	50	--RAM \|
	51	--____\|
	52	constant use_RAM : integer := 1;
	53	constant use_CEL : integer := 0;
	54
	55	constant Mem_use : integer := 1;
	56
	57	--===========================================================\|
	58	--=============C O E F S ====================================\|
	59	--===========================================================\|
	60	-- create a specific type of data for coefs to avoid errors \|
	61	--===========================================================\|
	62
	63	type coefT is array(Coef_SZ-1 downto 0) of std_logic;
	64	type scaleValT is array(natural range <>) of integer;
	65
	66	type coef_celT is array(0 to 2) of coefT;
	67
	68	type coefsT is array(natural range <>) of coefT ;
	69
	70	type coefs_celT is array(natural range <>) of coef_celT;
	71
	72	type samplT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
	73
	74
	75
	76
	77	type coefs_celsT is record
	78	NumCoefs : coefs_celT(0 to Cels_count-1);
	79	DenCoefs : coefs_celT(0 to Cels_count-1);
	80	end record;
	81
	82
	83	type in_IIR_CEL_reg is record
	84	config : std_logic_vector(31 downto 0);
	85	coefsTB : coefs_celsT;
	86	virgPos : std_logic_vector(4 downto 0);
	87	end record;
	88	type out_IIR_CEL_reg is record
	89	config : std_logic_vector(31 downto 0);
	90	status : std_logic_vector(31 downto 0);
	91	end record;
	92
	93
	94	--============================================================
	95	-- create each initial values for each coefs ============
	96	--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
	97	--============================================================
	98	constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
	99	constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
	100	constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
	101	constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
	102	constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
	103	constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
	104	constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
	105
	106	constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	107	constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
	108	constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
	109	constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
	110	constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
	111
	112
	113	constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
	114	constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
	115	constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
	116
	117	constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
	118	constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
	119	constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
	120
	121	constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
	122	constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
	123	constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
	124
	125	constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
	126	constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
	127	constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
	128
	129	constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
	130	constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
	131	constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
	132
	133	constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
	134	constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
	135	constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
	136
	137	constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
	138	constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
	139	constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
	140
	141
	142	constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	143	constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
	144	constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
	145
	146	constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	147	constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
	148	constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
	149
	150	constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	151	constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
	152	constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
	153
	154	constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	155	constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
	156	constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
	157
	158	constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	159	constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
	160	constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
	161
	162	constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
	163	constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	164	constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
	165	constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
	166	constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
	167	constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
	168
	169
	170	constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
	171	constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
	172	constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
	173	constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
	174	constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
	175	constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
	176	constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
	177
	178	constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
	179	constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
	180	constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
	181	constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
	182	constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
	183	constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
	184	constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
	185
	186
	187
	188	constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
	189	constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
	190	constant virgPos : integer := 7;
	191
	192
	193
	194
	195
	196
	197
	198	signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
	199	signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
	200
	201
	202	signal sample_Tbl : samplT;
	203
	204
	205	end;
	206
	207
	208
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lib/lpp/dsp/iir_filter/FilterCTRLR.vhd created 644 +263 0

@@ -0,0 +1,263
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- FilterCTRLR.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.iir_filter.all;
	25	use lpp.FILTERcfg.all;
	26	use lpp.general_purpose.all;
	27
	28	--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
	29
	30	entity FilterCTRLR is
	31	port(
	32	reset : in std_logic;
	33	clk : in std_logic;
	34	sample_clk : in std_logic;
	35	ALU_Ctrl : out std_logic_vector(3 downto 0);
	36	sample_in : in samplT;
	37	coef : out std_logic_vector(Coef_SZ-1 downto 0);
	38	sample : out std_logic_vector(Smpl_SZ-1 downto 0)
	39	);
	40	end FilterCTRLR;
	41
	42
	43	architecture ar_FilterCTRLR of FilterCTRLR is
	44
	45	constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
	46	constant DENCoefsCnt : integer:= DenominatorCoefs'high;
	47
	48	signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
	49	signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
	50
	51	signal chanelCnt : integer range 0 to 15:=0;
	52
	53	signal WD : std_logic_vector(35 downto 0);
	54	signal WD_D : std_logic_vector(35 downto 0);
	55	signal RD : std_logic_vector(35 downto 0);
	56	signal WEN, REN,WEN_D : std_logic;
	57	signal WADDR_back : std_logic_vector(7 downto 0);
	58	signal ADDR : std_logic_vector(7 downto 0);
	59	signal ADDR_D : std_logic_vector(7 downto 0);
	60	signal clk_inv : std_logic;
	61
	62	type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
	63	signal in_Rotate_Buff : Rotate_BuffT;
	64	signal out_Rotate_Buff : Rotate_BuffT;
	65
	66	signal sample_clk_old : std_logic;
	67
	68	type stateT is (waiting,computeNUM,computeDEN,NextChanel);
	69	signal state : stateT;
	70
	71	begin
	72	clk_inv <= not clk;
	73
	74	process(clk,reset)
	75	begin
	76	if reset = '0' then
	77	state <= waiting;
	78	WEN <= '1';
	79	REN <= '1';
	80	ADDR <= (others => '0');
	81	WD <= (others => '0');
	82	NcoefCnt <= 0;
	83	DcoefCnt <= 0;
	84	chanelCnt <= 0;
	85	ALU_Ctrl <= clr_mac;
	86	sample_clk_old <= '0';
	87	coef <= (others => '0');
	88	sample <= (others => '0');
	89	rst:for i in 0 to ChanelsCNT-1 loop
	90	in_Rotate_Buff(i) <= (others => '0');
	91	end loop;
	92	elsif clk'event and clk = '1' then
	93
	94	sample_clk_old <= sample_clk;
	95
	96	--=================================================================
	97	--===============DATA processing===================================
	98	--=================================================================
	99	case state is
	100	when waiting=>
	101
	102	if sample_clk_old = '0' and sample_clk = '1' then
	103	ALU_Ctrl <= MAC_op;
	104	sample <= in_Rotate_Buff(0);
	105	coef <= std_logic_vector(NumeratorCoefs(0));
	106	else
	107	ALU_Ctrl <= clr_mac;
	108	loadinput: for i in 0 to ChanelsCNT-1 loop
	109	in_Rotate_Buff(i) <= sample_in(i);
	110	end loop;
	111	end if;
	112
	113	when computeNUM=>
	114	ALU_Ctrl <= MAC_op;
	115	sample <= RD(Smpl_SZ-1 downto 0);
	116	coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
	117
	118	when computeDEN=>
	119	ALU_Ctrl <= MAC_op;
	120	sample <= RD(Smpl_SZ-1 downto 0);
	121	coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
	122
	123	when NextChanel=>
	124	rotate : for i in 0 to ChanelsCNT-2 loop
	125	in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
	126	end loop;
	127	rotatetoo: if ChanelsCNT > 1 then
	128	sample <= in_Rotate_Buff(1);
	129	coef <= std_logic_vector(NumeratorCoefs(0));
	130	end if;
	131	end case;
	132
	133	--=================================================================
	134	--===============RAM read write====================================
	135	--=================================================================
	136	case state is
	137	when waiting=>
	138	if sample_clk_old = '0' and sample_clk = '1' then
	139	REN <= '0';
	140	else
	141	REN <= '1';
	142	end if;
	143	ADDR <= (others => '0');
	144	WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
	145	WEN <= '1';
	146
	147	when computeNUM=>
	148	WD <= RD;
	149	REN <= '0';
	150	WEN <= '0';
	151	ADDR <= std_logic_vector(unsigned(ADDR)+1);
	152	when computeDEN=>
	153	WD <= RD;
	154	REN <= '0';
	155	WEN <= '0';
	156	ADDR <= std_logic_vector(unsigned(ADDR)+1);
	157	when NextChanel=>
	158	REN <= '1';
	159	WEN <= '1';
	160	end case;
	161	--=================================================================
	162
	163
	164	--=================================================================
	165	--===============FSM Management====================================
	166	--=================================================================
	167	case state is
	168	when waiting=>
	169	if sample_clk_old = '0' and sample_clk = '1' then
	170	state <= computeNUM;
	171	end if;
	172	DcoefCnt <= 0;
	173	NcoefCnt <= 1;
	174	chanelCnt<= 0;
	175	when computeNUM=>
	176	if NcoefCnt = NumCoefsCnt then
	177	state <= computeDEN;
	178	NcoefCnt <= 1;
	179	else
	180	NcoefCnt <= NcoefCnt+1;
	181	end if;
	182	when computeDEN=>
	183	if DcoefCnt = DENCoefsCnt then
	184	state <= NextChanel;
	185	DcoefCnt <= 0;
	186	else
	187	DcoefCnt <= DcoefCnt+1;
	188	end if;
	189	when NextChanel=>
	190	if chanelCnt = (ChanelsCNT-1) then
	191	state <= waiting;
	192	else
	193	chanelCnt<= chanelCnt+1;
	194	state <= computeNUM;
	195	end if;
	196	end case;
	197	--=================================================================
	198
	199	end if;
	200	end process;
	201
	202	ADDRreg : REG
	203	generic map(size => 8)
	204	port map(
	205	reset => reset,
	206	clk => clk,
	207	D => ADDR,
	208	Q => ADDR_D
	209	);
	210
	211	WDreg :REG
	212	generic map(size => 36)
	213	port map(
	214	reset => reset,
	215	clk => clk,
	216	D => WD,
	217	Q => WD_D
	218	);
	219
	220	WRreg :REG
	221	generic map(size => 1)
	222	port map(
	223	reset => reset,
	224	clk => clk,
	225	D(0) => WEN,
	226	Q(0) => WEN_D
	227	);
	228	--==============================================================
	229	--=========================R A M================================
	230	--==============================================================
	231	memRAM : if Mem_use = use_RAM generate
	232	RAMblk :RAM
	233	port map(
	234	WD => WD_D,
	235	RD => RD,
	236	WEN => WEN_D,
	237	REN => REN,
	238	WADDR => ADDR_D,
	239	RADDR => ADDR,
	240	RWCLK => clk_inv,
	241	RESET => reset
	242	) ;
	243	end generate;
	244
	245	memCEL : if Mem_use = use_CEL generate
	246	RAMblk :RAM
	247	port map(
	248	WD => WD_D,
	249	RD => RD,
	250	WEN => WEN_D,
	251	REN => REN,
	252	WADDR => ADDR_D,
	253	RADDR => ADDR,
	254	RWCLK => clk_inv,
	255	RESET => reset
	256	) ;
	257	end generate;
	258
	259	--==============================================================
	260
	261
	262
	263	end ar_FilterCTRLR;

lib/lpp/dsp/iir_filter/GPL_HEADER created 644 +18 0

@@ -0,0 +1,18
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------

lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd created 644 +293 0

@@ -0,0 +1,293
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- IIR_CEL_CTRLR.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.iir_filter.all;
	25	use lpp.FILTERcfg.all;
	26	use lpp.general_purpose.all;
	27
	28	--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
	29
	30	entity IIR_CEL_CTRLR is
	31	generic(Sample_SZ : integer := 16);
	32	port(
	33	reset : in std_logic;
	34	clk : in std_logic;
	35	sample_clk : in std_logic;
	36	sample_in : in samplT;
	37	sample_out : out samplT;
	38	virg_pos : in integer;
	39	coefs : in coefs_celsT
	40	);
	41	end IIR_CEL_CTRLR;
	42
	43
	44
	45
	46	architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
	47
	48	signal smpl_clk_old : std_logic := '0';
	49	signal WD_sel : std_logic := '0';
	50	signal Read : std_logic := '0';
	51	signal SVG_ADDR : std_logic := '0';
	52	signal count : std_logic := '0';
	53	signal Write : std_logic := '0';
	54	signal WADDR_sel : std_logic := '0';
	55	signal GO_0 : std_logic := '0';
	56
	57	signal RAM_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
	58	signal RAM_sample_in_bk: std_logic_vector(Sample_SZ-1 downto 0);
	59	signal RAM_sample_out : std_logic_vector(Sample_SZ-1 downto 0);
	60	signal ALU_ctrl : std_logic_vector(3 downto 0);
	61	signal ALU_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
	62	signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
	63	signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
	64	signal curentCel : integer range 0 to Cels_count-1 := 0;
	65	signal curentChan : integer range 0 to ChanelsCNT-1 := 0;
	66
	67	signal sample_in_BUFF : samplT;
	68	signal sample_out_BUFF : samplT;
	69
	70
	71
	72	type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
	73
	74	signal IIR_CEL_STATE : fsmIIR_CEL_T;
	75
	76	begin
	77
	78
	79
	80
	81
	82	RAM_CTRLR2inst : RAM_CTRLR2
	83	generic map(Input_SZ_1 => Sample_SZ)
	84	port map(
	85	reset => reset,
	86	clk => clk,
	87	WD_sel => WD_sel,
	88	Read => Read,
	89	WADDR_sel => WADDR_sel,
	90	count => count,
	91	SVG_ADDR => SVG_ADDR,
	92	Write => Write,
	93	GO_0 => GO_0,
	94	sample_in => RAM_sample_in,
	95	sample_out => RAM_sample_out
	96	);
	97
	98
	99
	100	ALU_inst :ALU
	101	generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
	102	port map(
	103	clk => clk,
	104	reset => reset,
	105	ctrl => ALU_ctrl,
	106	OP1 => ALU_sample_in,
	107	OP2 => ALU_coef_in,
	108	RES => ALU_out
	109	);
	110
	111
	112
	113
	114
	115
	116	WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
	117	Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
	118	WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
	119	count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
	120	SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
	121	--Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
	122	Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
	123
	124	GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
	125
	126
	127
	128
	129
	130
	131
	132	process(clk,reset)
	133	variable result : std_logic_vector(Sample_SZ-1 downto 0);
	134
	135	begin
	136
	137	if reset = '0' then
	138
	139	smpl_clk_old <= '0';
	140	RAM_sample_in <= (others=> '0');
	141	ALU_ctrl <= IDLE;
	142	ALU_sample_in <= (others=> '0');
	143	ALU_Coef_in <= (others=> '0');
	144	RAM_sample_in_bk<= (others=> '0');
	145	curentCel <= 0;
	146	curentChan <= 0;
	147	IIR_CEL_STATE <= waiting;
	148	reset : for i in 0 to ChanelsCNT-1 loop
	149	sample_in_BUFF(i) <= (others => '0');
	150	sample_out_BUFF(i) <= (others => '0');
	151	sample_out(i) <= (others => '0');
	152	end loop;
	153
	154	elsif clk'event and clk = '1' then
	155
	156	smpl_clk_old <= sample_clk;
	157
	158	case IIR_CEL_STATE is
	159
	160	when waiting =>
	161	if sample_clk = '1' and smpl_clk_old = '0' then
	162	IIR_CEL_STATE <= pipe1;
	163	RAM_sample_in <= sample_in_BUFF(0);
	164	ALU_sample_in <= sample_in_BUFF(0);
	165
	166	else
	167	ALU_ctrl <= IDLE;
	168	sample_in_BUFF <= sample_in;
	169	sample_out <= sample_out_BUFF;
	170
	171	end if;
	172	curentCel <= 0;
	173	curentChan <= 0;
	174
	175	when pipe1 =>
	176	IIR_CEL_STATE <= computeb1;
	177	ALU_ctrl <= MAC_op;
	178	ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(0));
	179
	180	when computeb1 =>
	181
	182	ALU_ctrl <= MAC_op;
	183	ALU_sample_in <= RAM_sample_out;
	184	ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(1));
	185	IIR_CEL_STATE <= computeb2;
	186	RAM_sample_in <= RAM_sample_in_bk;
	187	when computeb2 =>
	188	ALU_sample_in <= RAM_sample_out;
	189	ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(2));
	190	IIR_CEL_STATE <= computea1;
	191
	192
	193	when computea1 =>
	194	ALU_sample_in <= RAM_sample_out;
	195	ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(1));
	196	IIR_CEL_STATE <= computea2;
	197
	198
	199	when computea2 =>
	200	ALU_sample_in <= RAM_sample_out;
	201	ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(2));
	202	IIR_CEL_STATE <= next_cel;
	203
	204
	205	when next_cel =>
	206	ALU_ctrl <= clr_mac;
	207	IIR_CEL_STATE <= pipe2;
	208
	209	when pipe2 =>
	210	IIR_CEL_STATE <= pipe3;
	211
	212
	213	when pipe3 =>
	214
	215	result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
	216
	217	sample_out_BUFF(0) <= result;
	218	RAM_sample_in_bk <= result;
	219	RAM_sample_in <= result;
	220	if curentCel = Cels_count-1 then
	221	IIR_CEL_STATE <= next_chan;
	222	curentCel <= 0;
	223	else
	224	curentCel <= curentCel + 1;
	225	IIR_CEL_STATE <= pipe1;
	226	ALU_sample_in <= result;
	227	end if;
	228	when next_chan =>
	229
	230	rotate : for i in 0 to ChanelsCNT-2 loop
	231	sample_in_BUFF(i) <= sample_in_BUFF(i+1);
	232	sample_out_BUFF(i) <= sample_out_BUFF(i+1);
	233	end loop;
	234	sample_in_BUFF(ChanelsCNT-1) <= sample_in_BUFF(0);
	235	sample_out_BUFF(ChanelsCNT-1)<= sample_out_BUFF(0);
	236
	237	if curentChan = (ChanelsCNT-1) then
	238	IIR_CEL_STATE <= waiting;
	239	ALU_ctrl <= clr_mac;
	240	else
	241	curentChan <= curentChan + 1;
	242	IIR_CEL_STATE <= pipe1;
	243	ALU_sample_in <= sample_in_BUFF(1);
	244	RAM_sample_in <= sample_in_BUFF(1);
	245	end if;
	246	end case;
	247
	248	end if;
	249	end process;
	250
	251
	252
	253
	254
	255
	256	end ar_IIR_CEL_CTRLR;
	257
	258
	259
	260
	261
	262
	263
	264
	265
	266
	267
	268
	269
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lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd created 644 +90 0

@@ -0,0 +1,90
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- IIR_CEL_FILTER.vhd
	20
	21	library IEEE;
	22	use IEEE.numeric_std.all;
	23	use IEEE.std_logic_1164.all;
	24	library lpp;
	25	use lpp.iir_filter.all;
	26	use lpp.FILTERcfg.all;
	27	use lpp.general_purpose.all;
	28
	29	--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
	30
	31	entity IIR_CEL_FILTER is
	32	generic(Sample_SZ : integer := 16);
	33	port(
	34	reset : in std_logic;
	35	clk : in std_logic;
	36	sample_clk : in std_logic;
	37	regs_in : in in_IIR_CEL_reg;
	38	regs_out : in out_IIR_CEL_reg;
	39	sample_in : in samplT;
	40	sample_out : out samplT
	41
	42	);
	43	end IIR_CEL_FILTER;
	44
	45
	46
	47
	48	architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
	49
	50	signal virg_pos : integer;
	51	begin
	52
	53	virg_pos <= to_integer(unsigned(regs_in.virgPos));
	54
	55
	56	CTRLR : IIR_CEL_CTRLR
	57	generic map (Sample_SZ => Sample_SZ)
	58	port map(
	59	reset => reset,
	60	clk => clk,
	61	sample_clk => sample_clk,
	62	sample_in => sample_in,
	63	sample_out => sample_out,
	64	virg_pos => virg_pos,
	65	coefs => regs_in.coefsTB
	66	);
	67
	68
	69
	70
	71
	72	end ar_IIR_CEL_FILTER;
	73
	74
	75
	76
	77
	78
	79
	80
	81
	82
	83
	84
	85
	86
	87
	88
	89
	90

lib/lpp/dsp/iir_filter/RAM.vhd created 644 +62 0

@@ -0,0 +1,62
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- RAM.vhd
	20	library ieee;
	21	use ieee.std_logic_1164.all;
	22	use IEEE.numeric_std.all;
	23
	24	entity RAM is
	25	port( WD : in std_logic_vector(35 downto 0); RD : out
	26	std_logic_vector(35 downto 0);WEN, REN : in std_logic;
	27	WADDR : in std_logic_vector(7 downto 0); RADDR : in
	28	std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
	29	) ;
	30	end RAM;
	31
	32
	33	architecture DEF_ARCH of RAM is
	34	type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
	35	signal RAMarray : RAMarrayT:=(others => X"000000000");
	36	signal RD_int : std_logic_vector(35 downto 0);
	37
	38	begin
	39
	40	RD_int <= RAMarray(to_integer(unsigned(RADDR)));
	41
	42
	43	process(RWclk,reset)
	44	begin
	45	if reset = '0' then
	46	RD <= (X"000000000");
	47	rst:for i in 0 to 255 loop
	48	RAMarray(i) <= (others => '0');
	49	end loop;
	50
	51	elsif RWclk'event and RWclk = '1' then
	52	if REN = '0' then
	53	RD <= RD_int;
	54	end if;
	55
	56	if WEN = '0' then
	57	RAMarray(to_integer(unsigned(WADDR))) <= WD;
	58	end if;
	59
	60	end if;
	61	end process;
	62	end DEF_ARCH;

lib/lpp/dsp/iir_filter/RAM_CEL.vhd created 644 +91 0

@@ -0,0 +1,91
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- RAM_CEL.vhd
	20	library ieee;
	21	use ieee.std_logic_1164.all;
	22	use IEEE.numeric_std.all;
	23
	24	entity RAM_CEL is
	25	port( WD : in std_logic_vector(35 downto 0); RD : out
	26	std_logic_vector(35 downto 0);WEN, REN : in std_logic;
	27	WADDR : in std_logic_vector(7 downto 0); RADDR : in
	28	std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
	29	) ;
	30	end RAM_CEL;
	31
	32
	33
	34	architecture ar_RAM_CEL of RAM_CEL is
	35	type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
	36	signal RAMarray : RAMarrayT:=(others => X"000000000");
	37	signal RD_int : std_logic_vector(35 downto 0);
	38
	39	begin
	40
	41	RD_int <= RAMarray(to_integer(unsigned(RADDR)));
	42
	43
	44	process(RWclk,reset)
	45	begin
	46	if reset = '0' then
	47	RD <= (X"000000000");
	48	rst:for i in 0 to 255 loop
	49	RAMarray(i) <= (others => '0');
	50	end loop;
	51
	52	elsif RWclk'event and RWclk = '1' then
	53	if REN = '0' then
	54	RD <= RD_int;
	55	end if;
	56
	57	if WEN = '0' then
	58	RAMarray(to_integer(unsigned(WADDR))) <= WD;
	59	end if;
	60
	61	end if;
	62	end process;
	63	end ar_RAM_CEL;
	64
	65
	66
	67
	68
	69
	70
	71
	72
	73
	74
	75
	76
	77
	78
	79
	80
	81
	82
	83
	84
	85
	86
	87
	88
	89
	90
	91

lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd created 644 +210 0

@@ -0,0 +1,210
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- RAM_CTRLR2.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.iir_filter.all;
	25	use lpp.FILTERcfg.all;
	26	use lpp.general_purpose.all;
	27
	28	--TODO am�liorer la flexibilit� de la config de la RAM.
	29
	30	entity RAM_CTRLR2 is
	31	generic(
	32	Input_SZ_1 : integer := 16
	33	);
	34	port(
	35	reset : in std_logic;
	36	clk : in std_logic;
	37	WD_sel : in std_logic;
	38	Read : in std_logic;
	39	WADDR_sel : in std_logic;
	40	count : in std_logic;
	41	SVG_ADDR : in std_logic;
	42	Write : in std_logic;
	43	GO_0 : in std_logic;
	44	sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
	45	sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
	46	);
	47	end RAM_CTRLR2;
	48
	49
	50	architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
	51
	52	signal WD : std_logic_vector(35 downto 0);
	53	signal WD_D : std_logic_vector(35 downto 0);
	54	signal RD : std_logic_vector(35 downto 0);
	55	signal WEN, REN : std_logic;
	56	signal WADDR_back : std_logic_vector(7 downto 0);
	57	signal WADDR_back_D: std_logic_vector(7 downto 0);
	58	signal RADDR : std_logic_vector(7 downto 0);
	59	signal WADDR : std_logic_vector(7 downto 0);
	60	signal WADDR_D : std_logic_vector(7 downto 0);
	61
	62
	63
	64	begin
	65
	66	sample_out <= RD(Smpl_SZ-1 downto 0);
	67
	68
	69	WEN <= not Write;
	70	REN <= not read;
	71
	72
	73	--==============================================================
	74	--=========================R A M================================
	75	--==============================================================
	76	memRAM : if Mem_use = use_RAM generate
	77	RAMblk :RAM
	78	port map(
	79	WD => WD_D,
	80	RD => RD,
	81	WEN => WEN,
	82	REN => REN,
	83	WADDR => WADDR,
	84	RADDR => RADDR,
	85	RWCLK => clk,
	86	RESET => reset
	87	) ;
	88	end generate;
	89
	90	memCEL : if Mem_use = use_CEL generate
	91	RAMblk :RAM_CEL
	92	port map(
	93	WD => WD_D,
	94	RD => RD,
	95	WEN => WEN,
	96	REN => REN,
	97	WADDR => WADDR,
	98	RADDR => RADDR,
	99	RWCLK => clk,
	100	RESET => reset
	101	) ;
	102	end generate;
	103	--==============================================================
	104	--==============================================================
	105
	106
	107	ADDRcntr_inst : ADDRcntr
	108	port map(
	109	clk => clk,
	110	reset => reset,
	111	count => count,
	112	clr => GO_0,
	113	Q => RADDR
	114	);
	115
	116
	117
	118	MUX2_inst1 :MUX2
	119	generic map(Input_SZ => Smpl_SZ)
	120	port map(
	121	sel => WD_sel,
	122	IN1 => sample_in,
	123	IN2 => RD(Smpl_SZ-1 downto 0),
	124	RES => WD(Smpl_SZ-1 downto 0)
	125	);
	126
	127
	128	MUX2_inst2 :MUX2
	129	generic map(Input_SZ => 8)
	130	port map(
	131	sel => WADDR_sel,
	132	IN1 => WADDR_D,
	133	IN2 => WADDR_back_D,
	134	RES => WADDR
	135	);
	136
	137
	138
	139
	140	WADDR_backreg :REG
	141	generic map(size => 8,initial_VALUE =>ChanelsCNTCels_count4-2)
	142	port map(
	143	reset => reset,
	144	clk => SVG_ADDR,
	145	D => RADDR,
	146	Q => WADDR_back
	147	);
	148
	149	WADDR_backreg2 :REG
	150	generic map(size => 8)
	151	port map(
	152	reset => reset,
	153	clk => SVG_ADDR,
	154	D => WADDR_back,
	155	Q => WADDR_back_D
	156	);
	157
	158	WDRreg :REG
	159	generic map(size => Smpl_SZ)
	160	port map(
	161	reset => reset,
	162	clk => clk,
	163	D => WD(Smpl_SZ-1 downto 0),
	164	Q => WD_D(Smpl_SZ-1 downto 0)
	165	);
	166
	167
	168
	169
	170	ADDRreg :REG
	171	generic map(size => 8)
	172	port map(
	173	reset => reset,
	174	clk => clk,
	175	D => RADDR,
	176	Q => WADDR_D
	177	);
	178
	179
	180
	181	end ar_RAM_CTRLR2;
	182
	183
	184
	185
	186
	187
	188
	189
	190
	191
	192
	193
	194
	195
	196
	197
	198
	199
	200
	201
	202
	203
	204
	205
	206
	207
	208
	209
	210

lib/lpp/dsp/iir_filter/TestbenshMAC.vhd created 644 +114 0

@@ -0,0 +1,114
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- TestbenshMAC.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23
	24
	25
	26	entity TestbenshMAC is
	27	end TestbenshMAC;
	28
	29
	30
	31
	32	architecture ar_TestbenshMAC of TestbenshMAC is
	33
	34
	35
	36	constant OP1sz : integer := 16;
	37	constant OP2sz : integer := 12;
	38	--IDLE =00 MAC =01 MULT =10 ADD =11
	39	constant IDLE : std_logic_vector(1 downto 0) := "00";
	40	constant MAC : std_logic_vector(1 downto 0) := "01";
	41	constant MULT : std_logic_vector(1 downto 0) := "10";
	42	constant ADD : std_logic_vector(1 downto 0) := "11";
	43
	44	signal clk : std_logic:='0';
	45	signal reset : std_logic:='0';
	46	signal clrMAC : std_logic:='0';
	47	signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
	48	signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
	49	signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
	50	signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
	51
	52
	53
	54
	55	begin
	56
	57
	58	MAC1 : entity LPP_IIR_FILTER.MAC
	59	generic map(
	60	Input_SZ_A => OP1sz,
	61	Input_SZ_B => OP2sz
	62
	63	)
	64	port map(
	65	clk => clk,
	66	reset => reset,
	67	clr_MAC => clrMAC,
	68	MAC_MUL_ADD => MAC_MUL_ADD,
	69	OP1 => Operand1,
	70	OP2 => Operand2,
	71	RES => Resultat
	72	);
	73
	74	clk <= not clk after 25 ns;
	75
	76	process
	77	begin
	78	wait for 40 ns;
	79	reset <= '1';
	80	wait for 11 ns;
	81	Operand1 <= X"0001";
	82	Operand2 <= X"001";
	83	MAC_MUL_ADD <= ADD;
	84	wait for 50 ns;
	85	Operand1 <= X"0001";
	86	Operand2 <= X"100";
	87	wait for 50 ns;
	88	Operand1 <= X"0001";
	89	Operand2 <= X"001";
	90	MAC_MUL_ADD <= MULT;
	91	wait for 50 ns;
	92	Operand1 <= X"0002";
	93	Operand2 <= X"002";
	94	wait for 50 ns;
	95	clrMAC <= '1';
	96	wait for 50 ns;
	97	clrMAC <= '0';
	98	Operand1 <= X"0001";
	99	Operand2 <= X"003";
	100	MAC_MUL_ADD <= MAC;
	101	wait;
	102	end process;
	103	end ar_TestbenshMAC;
	104
	105
	106
	107
	108
	109
	110
	111
	112
	113
	114

lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd created 644 +19 0

@@ -0,0 +1,19
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Top_Filtre_IIR.vhd No newline at end of file

lib/lpp/dsp/iir_filter/iir_filter.vhd created 644 +161 0

@@ -0,0 +1,161
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	library ieee;
	20	use ieee.std_logic_1164.all;
	21	library grlib;
	22	use grlib.amba.all;
	23	use grlib.stdlib.all;
	24	use grlib.devices.all;
	25	library lpp;
	26	use lpp.FILTERcfg.all;
	27
	28
	29
	30	package iir_filter is
	31
	32	component APB_IIR_CEL is
	33	generic (
	34	pindex : integer := 0;
	35	paddr : integer := 0;
	36	pmask : integer := 16#fff#;
	37	pirq : integer := 0;
	38	abits : integer := 8;
	39	Sample_SZ : integer := Smpl_SZ
	40	);
	41	port (
	42	rst : in std_logic;
	43	clk : in std_logic;
	44	apbi : in apb_slv_in_type;
	45	apbo : out apb_slv_out_type;
	46	sample_clk : in std_logic;
	47	sample_clk_out : out std_logic;
	48	sample_in : in samplT;
	49	sample_out : out samplT
	50	);
	51	end component;
	52
	53
	54	component FILTER is
	55	port(
	56
	57	reset : in std_logic;
	58	clk : in std_logic;
	59	sample_clk : in std_logic;
	60	Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
	61	Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
	62	);
	63	end component;
	64
	65
	66
	67	component FilterCTRLR is
	68	port(
	69	reset : in std_logic;
	70	clk : in std_logic;
	71	sample_clk : in std_logic;
	72	ALU_Ctrl : out std_logic_vector(3 downto 0);
	73	sample_in : in samplT;
	74	coef : out std_logic_vector(Coef_SZ-1 downto 0);
	75	sample : out std_logic_vector(Smpl_SZ-1 downto 0)
	76	);
	77	end component;
	78
	79
	80	component FILTER_RAM_CTRLR is
	81	port(
	82	reset : in std_logic;
	83	clk : in std_logic;
	84	run : in std_logic;
	85	GO_0 : in std_logic;
	86	B_A : in std_logic;
	87	writeForce : in std_logic;
	88	next_blk : in std_logic;
	89	sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
	90	sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
	91	);
	92	end component;
	93
	94
	95	component IIR_CEL_CTRLR is
	96	generic(Sample_SZ : integer := 16);
	97	port(
	98	reset : in std_logic;
	99	clk : in std_logic;
	100	sample_clk : in std_logic;
	101	sample_in : in samplT;
	102	sample_out : out samplT;
	103	virg_pos : in integer;
	104	coefs : in coefs_celsT
	105	);
	106	end component;
	107
	108
	109	component RAM is
	110	port( WD : in std_logic_vector(35 downto 0); RD : out
	111	std_logic_vector(35 downto 0);WEN, REN : in std_logic;
	112	WADDR : in std_logic_vector(7 downto 0); RADDR : in
	113	std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
	114	) ;
	115	end component;
	116
	117
	118	component RAM_CEL is
	119	port( WD : in std_logic_vector(35 downto 0); RD : out
	120	std_logic_vector(35 downto 0);WEN, REN : in std_logic;
	121	WADDR : in std_logic_vector(7 downto 0); RADDR : in
	122	std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
	123	) ;
	124	end component;
	125
	126	component IIR_CEL_FILTER is
	127	generic(Sample_SZ : integer := 16);
	128	port(
	129	reset : in std_logic;
	130	clk : in std_logic;
	131	sample_clk : in std_logic;
	132	regs_in : in in_IIR_CEL_reg;
	133	regs_out : in out_IIR_CEL_reg;
	134	sample_in : in samplT;
	135	sample_out : out samplT
	136
	137	);
	138	end component;
	139
	140
	141	component RAM_CTRLR2 is
	142	generic(
	143	Input_SZ_1 : integer := 16
	144	);
	145	port(
	146	reset : in std_logic;
	147	clk : in std_logic;
	148	WD_sel : in std_logic;
	149	Read : in std_logic;
	150	WADDR_sel : in std_logic;
	151	count : in std_logic;
	152	SVG_ADDR : in std_logic;
	153	Write : in std_logic;
	154	GO_0 : in std_logic;
	155	sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
	156	sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
	157	);
	158	end component;
	159
	160
	161	end;

lib/lpp/dsp/iir_filter/temp.sh created 644 +1 0

	@@ -0,0 +1,1
				1	ls\|grep .vhd\|grep -i -v test>vhdlsyn.txt

lib/lpp/dsp/iir_filter/vhdlsyn.txt created 644 +12 0

@@ -0,0 +1,12
	1	APB_IIR_CEL.vhd
	2	FILTERcfg.vhd
	3	FilterCTRLR.vhd
	4	FILTER_RAM_CTRLR.vhd
	5	FILTER.vhd
	6	IIR_CEL_CTRLR.vhd
	7	IIR_CEL_FILTER.vhd
	8	iir_filter.vhd
	9	RAM_CEL.vhd
	10	RAM_CTRLR2.vhd
	11	RAM.vhd
	12	Top_Filtre_IIR.vhd

lib/lpp/general_purpose/ADDRcntr.vhd created 644 +62 0

@@ -0,0 +1,62
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- ADDRcntr.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity ADDRcntr is
	29	port(
	30	clk : in std_logic;
	31	reset : in std_logic;
	32	count : in std_logic;
	33	clr : in std_logic;
	34	Q : out std_logic_vector(7 downto 0)
	35	);
	36	end entity;
	37
	38
	39
	40
	41	architecture ar_ADDRcntr of ADDRcntr is
	42
	43	signal reg : std_logic_vector(7 downto 0);
	44
	45	begin
	46
	47	Q <= REG;
	48
	49	process(clk,reset)
	50	begin
	51	if reset = '0' then
	52	REG <= (others => '0');
	53	elsif clk'event and clk ='1' then
	54	if clr = '1' then
	55	REG <= (others => '0');
	56	elsif count ='1' then
	57	REG <= std_logic_vector(unsigned(REG)+1);
	58	end if;
	59	end if;
	60	end process;
	61
	62	end ar_ADDRcntr;

lib/lpp/general_purpose/ALU.vhd created 644 +101 0

@@ -0,0 +1,101
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- ALU.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25	--IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
	26	--NOT =0101 AND =0110 OR =0111 XOR =1000
	27	--SHIFTleft =1001 SHIFTright =1010
	28
	29	entity ALU is
	30	generic(
	31	Arith_en : integer := 1;
	32	Logic_en : integer := 1;
	33	Input_SZ_1 : integer := 16;
	34	Input_SZ_2 : integer := 9
	35
	36	);
	37	port(
	38	clk : in std_logic;
	39	reset : in std_logic;
	40	ctrl : in std_logic_vector(3 downto 0);
	41	OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
	42	OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
	43	RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
	44	);
	45	end entity;
	46
	47
	48
	49	architecture ar_ALU of ALU is
	50
	51
	52
	53	signal clr_MAC : std_logic:='1';
	54
	55
	56	begin
	57
	58	clr_MAC <= '1' when ctrl = "0100" else '0';
	59
	60
	61	arith : if Arith_en = 1 generate
	62
	63
	64	MACinst : MAC
	65	generic map(
	66	Input_SZ_A => Input_SZ_1,
	67	Input_SZ_B => Input_SZ_2
	68
	69	)
	70	port map(
	71	clk => clk,
	72	reset => reset,
	73	clr_MAC => clr_MAC,
	74	MAC_MUL_ADD => ctrl(1 downto 0),
	75	OP1 => OP1,
	76	OP2 => OP2,
	77	RES => RES
	78	);
	79
	80	end generate;
	81
	82	process(clk,reset)
	83	begin
	84	if reset = '0' then
	85	elsif clk'event and clk ='1' then
	86
	87	end if;
	88	end process;
	89	end architecture;
	90
	91
	92
	93
	94
	95
	96
	97
	98
	99
	100
	101

lib/lpp/general_purpose/Adder.vhd created 644 +70 0

@@ -0,0 +1,70
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Adder.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity Adder is
	29	generic(
	30	Input_SZ_A : integer := 16;
	31	Input_SZ_B : integer := 16
	32
	33	);
	34	port(
	35	clk : in std_logic;
	36	reset : in std_logic;
	37	clr : in std_logic;
	38	add : in std_logic;
	39	OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	40	OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	41	RES : out std_logic_vector(Input_SZ_A-1 downto 0)
	42	);
	43	end entity;
	44
	45
	46
	47
	48	architecture ar_Adder of Adder is
	49
	50	signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
	51	signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
	52
	53	begin
	54
	55	RES <= REG;
	56	RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
	57
	58	process(clk,reset)
	59	begin
	60	if reset = '0' then
	61	REG <= (others => '0');
	62	elsif clk'event and clk ='1' then
	63	if clr = '1' then
	64	REG <= (others => '0');
	65	elsif add = '1' then
	66	REG <= RESADD;
	67	end if;
	68	end if;
	69	end process;
	70	end ar_Adder;

lib/lpp/general_purpose/MAC.vhd created 644 +276 0

@@ -0,0 +1,276
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- MAC.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25	--TODO
	26	--terminer le testbensh puis changer le resize dans les instanciations
	27	--par un resize sur un vecteur en combi
	28
	29
	30
	31
	32
	33	entity MAC is
	34	generic(
	35	Input_SZ_A : integer := 8;
	36	Input_SZ_B : integer := 8
	37
	38	);
	39	port(
	40	clk : in std_logic;
	41	reset : in std_logic;
	42	clr_MAC : in std_logic;
	43	MAC_MUL_ADD : in std_logic_vector(1 downto 0);
	44	OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	45	OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	46	RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
	47	);
	48	end MAC;
	49
	50
	51
	52
	53	architecture ar_MAC of MAC is
	54
	55
	56
	57
	58
	59	signal add,mult : std_logic;
	60	signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	61
	62	signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	63	signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	64	signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	65
	66
	67	signal MACMUXsel : std_logic;
	68	signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	69	signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	70
	71
	72
	73	signal MACMUX2sel : std_logic;
	74
	75	signal add_D : std_logic;
	76	signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
	77	signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
	78	signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	79	signal MACMUXsel_D : std_logic;
	80	signal MACMUX2sel_D : std_logic;
	81	signal MACMUX2sel_D_D : std_logic;
	82	signal clr_MAC_D : std_logic;
	83	signal clr_MAC_D_D : std_logic;
	84
	85
	86
	87
	88
	89	begin
	90
	91
	92
	93
	94	--==============================================================
	95	--=============M A C C O N T R O L E R=========================
	96	--==============================================================
	97	MAC_CONTROLER1 : MAC_CONTROLER
	98	port map(
	99	ctrl => MAC_MUL_ADD,
	100	MULT => mult,
	101	ADD => add,
	102	MACMUX_sel => MACMUXsel,
	103	MACMUX2_sel => MACMUX2sel
	104
	105	);
	106	--==============================================================
	107
	108
	109
	110
	111	--==============================================================
	112	--=============M U L T I P L I E R==============================
	113	--==============================================================
	114	Multiplieri_nst : Multiplier
	115	generic map(
	116	Input_SZ_A => Input_SZ_A,
	117	Input_SZ_B => Input_SZ_B
	118	)
	119	port map(
	120	clk => clk,
	121	reset => reset,
	122	mult => mult,
	123	OP1 => OP1,
	124	OP2 => OP2,
	125	RES => MULTout
	126	);
	127
	128	--==============================================================
	129
	130
	131
	132
	133	--==============================================================
	134	--======================A D D E R ==============================
	135	--==============================================================
	136	adder_inst : Adder
	137	generic map(
	138	Input_SZ_A => Input_SZ_A+Input_SZ_B,
	139	Input_SZ_B => Input_SZ_A+Input_SZ_B
	140	)
	141	port map(
	142	clk => clk,
	143	reset => reset,
	144	clr => clr_MAC_D,
	145	add => add_D,
	146	OP1 => ADDERinA,
	147	OP2 => ADDERinB,
	148	RES => ADDERout
	149	);
	150
	151	--==============================================================
	152
	153
	154	clr_MACREG1 : MAC_REG
	155	generic map(size => 1)
	156	port map(
	157	reset => reset,
	158	clk => clk,
	159	D(0) => clr_MAC,
	160	Q(0) => clr_MAC_D
	161	);
	162
	163	clr_MACREG2 : MAC_REG
	164	generic map(size => 1)
	165	port map(
	166	reset => reset,
	167	clk => clk,
	168	D(0) => clr_MAC_D,
	169	Q(0) => clr_MAC_D_D
	170	);
	171
	172	addREG : MAC_REG
	173	generic map(size => 1)
	174	port map(
	175	reset => reset,
	176	clk => clk,
	177	D(0) => add,
	178	Q(0) => add_D
	179	);
	180
	181	OP1REG : MAC_REG
	182	generic map(size => Input_SZ_A)
	183	port map(
	184	reset => reset,
	185	clk => clk,
	186	D => OP1,
	187	Q => OP1_D
	188	);
	189
	190
	191	OP2REG : MAC_REG
	192	generic map(size => Input_SZ_B)
	193	port map(
	194	reset => reset,
	195	clk => clk,
	196	D => OP2,
	197	Q => OP2_D
	198	);
	199
	200
	201	MULToutREG : MAC_REG
	202	generic map(size => Input_SZ_A+Input_SZ_B)
	203	port map(
	204	reset => reset,
	205	clk => clk,
	206	D => MULTout,
	207	Q => MULTout_D
	208	);
	209
	210
	211	MACMUXselREG : MAC_REG
	212	generic map(size => 1)
	213	port map(
	214	reset => reset,
	215	clk => clk,
	216	D(0) => MACMUXsel,
	217	Q(0) => MACMUXsel_D
	218	);
	219
	220	MACMUX2selREG : MAC_REG
	221	generic map(size => 1)
	222	port map(
	223	reset => reset,
	224	clk => clk,
	225	D(0) => MACMUX2sel,
	226	Q(0) => MACMUX2sel_D
	227	);
	228
	229	MACMUX2selREG2 : MAC_REG
	230	generic map(size => 1)
	231	port map(
	232	reset => reset,
	233	clk => clk,
	234	D(0) => MACMUX2sel_D,
	235	Q(0) => MACMUX2sel_D_D
	236	);
	237
	238	--==============================================================
	239	--======================M A C M U X ===========================
	240	--==============================================================
	241	MACMUX_inst : MAC_MUX
	242	generic map(
	243	Input_SZ_A => Input_SZ_A+Input_SZ_B,
	244	Input_SZ_B => Input_SZ_A+Input_SZ_B
	245
	246	)
	247	port map(
	248	sel => MACMUXsel_D,
	249	INA1 => ADDERout,
	250	INA2 => OP2_D_Resz,
	251	INB1 => MULTout,
	252	INB2 => OP1_D_Resz,
	253	OUTA => ADDERinA,
	254	OUTB => ADDERinB
	255	);
	256	OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
	257	OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
	258	--==============================================================
	259
	260
	261	--==============================================================
	262	--======================M A C M U X2 ==========================
	263	--==============================================================
	264	MAC_MUX2_inst : MAC_MUX2
	265	generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
	266	port map(
	267	sel => MACMUX2sel_D_D,
	268	RES2 => MULTout_D,
	269	RES1 => ADDERout,
	270	RES => RES
	271	);
	272
	273
	274	--==============================================================
	275
	276	end ar_MAC;

lib/lpp/general_purpose/MAC_CONTROLER.vhd created 644 +67 0

@@ -0,0 +1,67
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- MAC_CONTROLER.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27	--IDLE =00 MAC =01 MULT =10 ADD =11
	28
	29
	30	entity MAC_CONTROLER is
	31	port(
	32	ctrl : in std_logic_vector(1 downto 0);
	33	MULT : out std_logic;
	34	ADD : out std_logic;
	35	MACMUX_sel : out std_logic;
	36	MACMUX2_sel : out std_logic
	37
	38	);
	39	end MAC_CONTROLER;
	40
	41
	42
	43
	44
	45	architecture ar_MAC_CONTROLER of MAC_CONTROLER is
	46
	47	begin
	48
	49
	50
	51	MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
	52	ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
	53	MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
	54	MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1';
	55
	56
	57	end ar_MAC_CONTROLER;
	58
	59
	60
	61
	62
	63
	64
	65
	66
	67

lib/lpp/general_purpose/MAC_MUX.vhd created 644 +55 0

@@ -0,0 +1,55
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- MAC_MUX.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity MAC_MUX is
	29	generic(
	30	Input_SZ_A : integer := 16;
	31	Input_SZ_B : integer := 16
	32
	33	);
	34	port(
	35	sel : in std_logic;
	36	INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	37	INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
	38	INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
	39	INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	40	OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
	41	OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
	42	);
	43	end entity;
	44
	45
	46
	47
	48	architecture ar_MAC_MUX of MAC_MUX is
	49
	50	begin
	51
	52	OUTA <= INA1 when sel = '0' else INA2;
	53	OUTB <= INB1 when sel = '0' else INB2;
	54
	55	end ar_MAC_MUX;

lib/lpp/general_purpose/MAC_MUX2.vhd created 644 +47 0

@@ -0,0 +1,47
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- MAC_MUX2.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity MAC_MUX2 is
	29	generic(Input_SZ : integer := 16);
	30	port(
	31	sel : in std_logic;
	32	RES1 : in std_logic_vector(Input_SZ-1 downto 0);
	33	RES2 : in std_logic_vector(Input_SZ-1 downto 0);
	34	RES : out std_logic_vector(Input_SZ-1 downto 0)
	35	);
	36	end entity;
	37
	38
	39
	40
	41	architecture ar_MAC_MUX2 of MAC_MUX2 is
	42
	43	begin
	44
	45	RES <= RES1 when sel = '0' else RES2;
	46
	47	end ar_MAC_MUX2;

lib/lpp/general_purpose/MAC_REG.vhd created 644 +60 0

@@ -0,0 +1,60
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- MAC_REG.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity MAC_REG is
	29	generic(size : integer := 16);
	30	port(
	31	reset : in std_logic;
	32	clk : in std_logic;
	33	D : in std_logic_vector(size-1 downto 0);
	34	Q : out std_logic_vector(size-1 downto 0)
	35	);
	36	end entity;
	37
	38
	39
	40	architecture ar_MAC_REG of MAC_REG is
	41	begin
	42	process(clk,reset)
	43	begin
	44	if reset = '0' then
	45	Q <= (others => '0');
	46	elsif clk'event and clk ='1' then
	47	Q <= D;
	48	end if;
	49	end process;
	50	end ar_MAC_REG;
	51
	52
	53
	54
	55
	56
	57
	58
	59
	60

lib/lpp/general_purpose/MUX2.vhd created 644 +47 0

@@ -0,0 +1,47
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- MUX2.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity MUX2 is
	29	generic(Input_SZ : integer := 16);
	30	port(
	31	sel : in std_logic;
	32	IN1 : in std_logic_vector(Input_SZ-1 downto 0);
	33	IN2 : in std_logic_vector(Input_SZ-1 downto 0);
	34	RES : out std_logic_vector(Input_SZ-1 downto 0)
	35	);
	36	end entity;
	37
	38
	39
	40
	41	architecture ar_MUX2 of MUX2 is
	42
	43	begin
	44
	45	RES <= IN1 when sel = '0' else IN2;
	46
	47	end ar_MUX2;

lib/lpp/general_purpose/Multiplier.vhd created 644 +78 0

@@ -0,0 +1,78
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Multiplier.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23
	24	library lpp;
	25	use lpp.general_purpose.all;
	26
	27
	28
	29	entity Multiplier is
	30	generic(
	31	Input_SZ_A : integer := 16;
	32	Input_SZ_B : integer := 16
	33
	34	);
	35	port(
	36	clk : in std_logic;
	37	reset : in std_logic;
	38	mult : in std_logic;
	39	OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	40	OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	41	RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
	42	);
	43	end Multiplier;
	44
	45
	46
	47
	48
	49	architecture ar_Multiplier of Multiplier is
	50
	51	signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	52	signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
	53
	54
	55	begin
	56
	57	RES <= REG;
	58	RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
	59	process(clk,reset)
	60	begin
	61	if reset = '0' then
	62	REG <= (others => '0');
	63	elsif clk'event and clk ='1' then
	64	if mult = '1' then
	65	REG <= RESMULT;
	66	end if;
	67	end if;
	68	end process;
	69
	70	end ar_Multiplier;
	71
	72
	73
	74
	75
	76
	77
	78

lib/lpp/general_purpose/REG.vhd created 644 +48 0

@@ -0,0 +1,48
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- REG.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26	entity REG is
	27	generic(size : integer := 16 ; initial_VALUE : integer := 0);
	28	port(
	29	reset : in std_logic;
	30	clk : in std_logic;
	31	D : in std_logic_vector(size-1 downto 0);
	32	Q : out std_logic_vector(size-1 downto 0)
	33	);
	34	end entity;
	35
	36
	37
	38	architecture ar_REG of REG is
	39	begin
	40	process(clk,reset)
	41	begin
	42	if reset = '0' then
	43	Q <= std_logic_vector(to_unsigned(initial_VALUE,size));
	44	elsif clk'event and clk ='1' then
	45	Q <= D;
	46	end if;
	47	end process;
	48	end ar_REG;

lib/lpp/general_purpose/Shifter.vhd created 644 +66 0

@@ -0,0 +1,66
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Shifter.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23	library lpp;
	24	use lpp.general_purpose.all;
	25
	26
	27
	28	entity RShifter is
	29	generic(
	30	Input_SZ : integer := 16;
	31	shift_SZ : integer := 4
	32	);
	33	port(
	34	clk : in std_logic;
	35	reset : in std_logic;
	36	shift : in std_logic;
	37	OP : in std_logic_vector(Input_SZ-1 downto 0);
	38	cnt : in std_logic_vector(shift_SZ-1 downto 0);
	39	RES : out std_logic_vector(Input_SZ-1 downto 0)
	40	);
	41	end entity;
	42
	43
	44
	45
	46	architecture ar_RShifter of RShifter is
	47
	48	signal REG : std_logic_vector(Input_SZ-1 downto 0);
	49	signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0);
	50
	51	begin
	52
	53	RES <= REG;
	54	RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt))));
	55
	56	process(clk,reset)
	57	begin
	58	if reset = '0' then
	59	REG <= (others => '0');
	60	elsif clk'event and clk ='1' then
	61	if shift = '1' then
	62	REG <= RESSHIFT;
	63	end if;
	64	end if;
	65	end process;
	66	end ar_RShifter;

lib/lpp/general_purpose/TestbenshALU.vhd created 644 +136 0

@@ -0,0 +1,136
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- TestbenshALU.vhd
	20	library IEEE;
	21	use IEEE.numeric_std.all;
	22	use IEEE.std_logic_1164.all;
	23
	24
	25
	26	entity TestbenshALU is
	27	end TestbenshALU;
	28
	29
	30
	31
	32	architecture ar_TestbenshALU of TestbenshALU is
	33
	34
	35
	36	constant OP1sz : integer := 16;
	37	constant OP2sz : integer := 12;
	38	--IDLE =00 MAC =01 MULT =10 ADD =11
	39	constant IDLE : std_logic_vector(3 downto 0) := "0000";
	40	constant MAC : std_logic_vector(3 downto 0) := "0001";
	41	constant MULT : std_logic_vector(3 downto 0) := "0010";
	42	constant ADD : std_logic_vector(3 downto 0) := "0011";
	43	constant clr_mac : std_logic_vector(3 downto 0) := "0100";
	44
	45	signal clk : std_logic:='0';
	46	signal reset : std_logic:='0';
	47	signal ctrl : std_logic_vector(3 downto 0):=IDLE;
	48	signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
	49	signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
	50	signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
	51
	52
	53
	54
	55	begin
	56
	57	ALU1 : entity LPP_IIR_FILTER.ALU
	58	generic map(
	59	Arith_en => 1,
	60	Logic_en => 0,
	61	Input_SZ_1 => OP1sz,
	62	Input_SZ_2 => OP2sz
	63
	64	)
	65	port map(
	66	clk => clk,
	67	reset => reset,
	68	ctrl => ctrl,
	69	OP1 => Operand1,
	70	OP2 => Operand2,
	71	RES => Resultat
	72	);
	73
	74
	75
	76
	77	clk <= not clk after 25 ns;
	78
	79	process
	80	begin
	81	wait for 40 ns;
	82	reset <= '1';
	83	wait for 11 ns;
	84	Operand1 <= X"0001";
	85	Operand2 <= X"001";
	86	ctrl <= ADD;
	87	wait for 50 ns;
	88	Operand1 <= X"0001";
	89	Operand2 <= X"100";
	90	wait for 50 ns;
	91	Operand1 <= X"0001";
	92	Operand2 <= X"001";
	93	ctrl <= MULT;
	94	wait for 50 ns;
	95	Operand1 <= X"0002";
	96	Operand2 <= X"002";
	97	wait for 50 ns;
	98	ctrl <= clr_mac;
	99	wait for 50 ns;
	100	Operand1 <= X"0001";
	101	Operand2 <= X"003";
	102	ctrl <= MAC;
	103	wait for 50 ns;
	104	Operand1 <= X"0001";
	105	Operand2 <= X"001";
	106	wait for 50 ns;
	107	Operand1 <= X"0011";
	108	Operand2 <= X"003";
	109	wait for 50 ns;
	110	Operand1 <= X"1001";
	111	Operand2 <= X"003";
	112	wait for 50 ns;
	113	Operand1 <= X"0001";
	114	Operand2 <= X"000";
	115	wait for 50 ns;
	116	Operand1 <= X"0001";
	117	Operand2 <= X"003";
	118	wait for 50 ns;
	119	Operand1 <= X"0101";
	120	Operand2 <= X"053";
	121	wait for 50 ns;
	122	ctrl <= clr_mac;
	123	wait;
	124	end process;
	125	end ar_TestbenshALU;
	126
	127
	128
	129
	130
	131
	132
	133
	134
	135
	136

lib/lpp/general_purpose/general_purpose.vhd created 644 +195 0

@@ -0,0 +1,195
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19
	20	library ieee;
	21	use ieee.std_logic_1164.all;
	22
	23
	24
	25	package general_purpose is
	26
	27	component Adder is
	28	generic(
	29	Input_SZ_A : integer := 16;
	30	Input_SZ_B : integer := 16
	31
	32	);
	33	port(
	34	clk : in std_logic;
	35	reset : in std_logic;
	36	clr : in std_logic;
	37	add : in std_logic;
	38	OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	39	OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	40	RES : out std_logic_vector(Input_SZ_A-1 downto 0)
	41	);
	42	end component;
	43
	44	component ADDRcntr is
	45	port(
	46	clk : in std_logic;
	47	reset : in std_logic;
	48	count : in std_logic;
	49	clr : in std_logic;
	50	Q : out std_logic_vector(7 downto 0)
	51	);
	52	end component;
	53
	54	component ALU is
	55	generic(
	56	Arith_en : integer := 1;
	57	Logic_en : integer := 1;
	58	Input_SZ_1 : integer := 16;
	59	Input_SZ_2 : integer := 9
	60
	61	);
	62	port(
	63	clk : in std_logic;
	64	reset : in std_logic;
	65	ctrl : in std_logic_vector(3 downto 0);
	66	OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
	67	OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
	68	RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
	69	);
	70	end component;
	71
	72
	73	component MAC is
	74	generic(
	75	Input_SZ_A : integer := 8;
	76	Input_SZ_B : integer := 8
	77
	78	);
	79	port(
	80	clk : in std_logic;
	81	reset : in std_logic;
	82	clr_MAC : in std_logic;
	83	MAC_MUL_ADD : in std_logic_vector(1 downto 0);
	84	OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	85	OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	86	RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
	87	);
	88	end component;
	89
	90
	91	component MAC_CONTROLER is
	92	port(
	93	ctrl : in std_logic_vector(1 downto 0);
	94	MULT : out std_logic;
	95	ADD : out std_logic;
	96	MACMUX_sel : out std_logic;
	97	MACMUX2_sel : out std_logic
	98
	99	);
	100	end component;
	101
	102	component MAC_MUX is
	103	generic(
	104	Input_SZ_A : integer := 16;
	105	Input_SZ_B : integer := 16
	106
	107	);
	108	port(
	109	sel : in std_logic;
	110	INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	111	INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
	112	INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
	113	INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	114	OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
	115	OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
	116	);
	117	end component;
	118
	119
	120	component MAC_MUX2 is
	121	generic(Input_SZ : integer := 16);
	122	port(
	123	sel : in std_logic;
	124	RES1 : in std_logic_vector(Input_SZ-1 downto 0);
	125	RES2 : in std_logic_vector(Input_SZ-1 downto 0);
	126	RES : out std_logic_vector(Input_SZ-1 downto 0)
	127	);
	128	end component;
	129
	130
	131	component MAC_REG is
	132	generic(size : integer := 16);
	133	port(
	134	reset : in std_logic;
	135	clk : in std_logic;
	136	D : in std_logic_vector(size-1 downto 0);
	137	Q : out std_logic_vector(size-1 downto 0)
	138	);
	139	end component;
	140
	141
	142	component MUX2 is
	143	generic(Input_SZ : integer := 16);
	144	port(
	145	sel : in std_logic;
	146	IN1 : in std_logic_vector(Input_SZ-1 downto 0);
	147	IN2 : in std_logic_vector(Input_SZ-1 downto 0);
	148	RES : out std_logic_vector(Input_SZ-1 downto 0)
	149	);
	150	end component;
	151
	152	component Multiplier is
	153	generic(
	154	Input_SZ_A : integer := 16;
	155	Input_SZ_B : integer := 16
	156
	157	);
	158	port(
	159	clk : in std_logic;
	160	reset : in std_logic;
	161	mult : in std_logic;
	162	OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
	163	OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
	164	RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
	165	);
	166	end component;
	167
	168	component REG is
	169	generic(size : integer := 16 ; initial_VALUE : integer := 0);
	170	port(
	171	reset : in std_logic;
	172	clk : in std_logic;
	173	D : in std_logic_vector(size-1 downto 0);
	174	Q : out std_logic_vector(size-1 downto 0)
	175	);
	176	end component;
	177
	178
	179
	180	component RShifter is
	181	generic(
	182	Input_SZ : integer := 16;
	183	shift_SZ : integer := 4
	184	);
	185	port(
	186	clk : in std_logic;
	187	reset : in std_logic;
	188	shift : in std_logic;
	189	OP : in std_logic_vector(Input_SZ-1 downto 0);
	190	cnt : in std_logic_vector(shift_SZ-1 downto 0);
	191	RES : out std_logic_vector(Input_SZ-1 downto 0)
	192	);
	193	end component;
	194
	195	end;

lib/lpp/general_purpose/temp.sh created 644 +1 0

	@@ -0,0 +1,1
				1	ls\|grep .vhd\|grep -i -v test>vhdlsyn.txt

lib/lpp/general_purpose/vhdlsyn.txt created 644 +13 0

@@ -0,0 +1,13
	1	Adder.vhd
	2	ADDRcntr.vhd
	3	ALU.vhd
	4	general_purpose.vhd
	5	MAC_CONTROLER.vhd
	6	MAC_MUX2.vhd
	7	MAC_MUX.vhd
	8	MAC_REG.vhd
	9	MAC.vhd
	10	Multiplier.vhd
	11	MUX2.vhd
	12	REG.vhd
	13	Shifter.vhd

lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd created 644 +129 0

@@ -0,0 +1,129
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- APB_SIMPLE_DIODE.vhd
	20
	21	library ieee;
	22	use ieee.std_logic_1164.all;
	23	--use ieee.numeric_std.all;
	24	library grlib;
	25	use grlib.amba.all;
	26	use grlib.stdlib.all;
	27	use grlib.devices.all;
	28	library lpp;
	29	use lpp.lpp_amba.all;
	30
	31
	32	entity APB_SIMPLE_DIODE is
	33	generic (
	34	pindex : integer := 0;
	35	paddr : integer := 0;
	36	pmask : integer := 16#fff#;
	37	pirq : integer := 0;
	38	abits : integer := 8);
	39	port (
	40	rst : in std_ulogic;
	41	clk : in std_ulogic;
	42	apbi : in apb_slv_in_type;
	43	apbo : out apb_slv_out_type;
	44	LED : out std_ulogic
	45	);
	46	end;
	47
	48
	49	architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
	50
	51	constant REVISION : integer := 1;
	52
	53	constant pconfig : apb_config_type := (
	54	0 => ahb_device_reg (VENDOR_LPP, ROCKET_TM, 0, REVISION, 0),
	55	1 => apb_iobar(paddr, pmask));
	56
	57
	58
	59	type LEDregs is record
	60	DATAin : std_logic_vector(31 downto 0);
	61	DATAout : std_logic_vector(31 downto 0);
	62	end record;
	63
	64	signal r : LEDregs;
	65
	66
	67	begin
	68
	69	r.DATAout <= r.DATAin xor X"FFFFFFFF";
	70
	71	process(rst,clk)
	72	begin
	73	if rst = '0' then
	74	LED <= '0';
	75	r.DATAin <= (others => '0');
	76	apbo.prdata <= (others => '0');
	77	elsif clk'event and clk = '1' then
	78
	79	LED <= r.DATAin(0);
	80
	81	--APB Write OP
	82	if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
	83	case apbi.paddr(abits-1 downto 2) is
	84	when "000000" =>
	85	r.DATAin <= apbi.pwdata;
	86	when others =>
	87	null;
	88	end case;
	89	end if;
	90
	91	--APB READ OP
	92	if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
	93	case apbi.paddr(abits-1 downto 2) is
	94	when "000000" =>
	95	apbo.prdata <= r.DATAin;
	96	when others =>
	97	apbo.prdata <= r.DATAout;
	98	end case;
	99	end if;
	100
	101	end if;
	102	apbo.pconfig <= pconfig;
	103	end process;
	104
	105
	106
	107	-- pragma translate_off
	108	bootmsg : report_version
	109	generic map ("apbuart" & tost(pindex) &
	110	": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
	111	", irq " & tost(pirq));
	112	-- pragma translate_on
	113
	114
	115
	116	end ar_APB_SIMPLE_DIODE;
	117
	118
	119
	120
	121
	122
	123
	124
	125
	126
	127
	128
	129

lib/lpp/lpp_amba/lpp_amba.vhd created 644 +59 0

@@ -0,0 +1,59
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19
	20	library ieee;
	21	use ieee.std_logic_1164.all;
	22	library grlib;
	23	use grlib.amba.all;
	24	-- pragma translate_off
	25	use std.textio.all;
	26	-- pragma translate_on
	27
	28
	29
	30
	31
	32	package lpp_amba is
	33
	34	constant VENDOR_LPP : amba_vendor_type := 16#19#;
	35
	36	-- LPP device ids
	37
	38	constant ROCKET_TM : amba_device_type := 16#001#;
	39	constant otherCore : amba_device_type := 16#002#;
	40
	41
	42	component APB_SIMPLE_DIODE is
	43	generic (
	44	pindex : integer := 0;
	45	paddr : integer := 0;
	46	pmask : integer := 16#fff#;
	47	pirq : integer := 0;
	48	abits : integer := 8);
	49	port (
	50	rst : in std_ulogic;
	51	clk : in std_ulogic;
	52	apbi : in apb_slv_in_type;
	53	apbo : out apb_slv_out_type;
	54	LED : out std_ulogic
	55	);
	56	end component;
	57
	58
	59	end;

lib/lpp/lpp_amba/vhdlsyn.txt created 644 +2 0

@@ -0,0 +1,2
	1	APB_SIMPLE_DIODE.vhd
	2	lpp_amba.vhd

lib/lpp/makeDirs.sh created 644 +50 0

@@ -0,0 +1,50
	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP VHDL lib makeDirs "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '----------------------------------------------------------------------------------------
	7	This file is a part of the LPP VHDL IP LIBRARY
	8	Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	----------------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28
	29
	30	LPP_PATCHPATH=`pwd -L`
	31
	32	cd $LPP_PATCHPATH/lib/lpp
	33
	34
	35	#find . -type d\|grep ./>$LPP_PATCHPATH/lib/lpp/dirs.txt
	36
	37	rm $LPP_PATCHPATH/lib/lpp/dirs.txt
	38
	39	for folders in $(find . -type d\|grep ./)
	40	do
	41	echo "enter folder : $folders"
	42	files=$(ls $folders\|grep .vhd)
	43	if(ls $folders\|grep .vhd\|grep -i -v .html\|grep -i -v .tex); then
	44	echo "found $files"
	45	echo $folders>>$LPP_PATCHPATH/lib/lpp/dirs.txt
	46	fi
	47	done
	48
	49
	50	cd $LPP_PATCHPATH

lib/lpp/vhdlsynPatcher.sh created 644 +61 0

@@ -0,0 +1,61
	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP vhdlsyn PATCHER "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '----------------------------------------------------------------------------------------
	7	This file is a part of the LPP VHDL IP LIBRARY
	8	Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	----------------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28	# Absolute path to this script. /home/user/bin/foo.sh
	29	#SCRIPT=$(readlink -f $0)
	30	# Absolute path this script is in. /home/user/bin
	31
	32	#LPP_PATCHPATH=`dirname $SCRIPT`
	33	LPP_PATCHPATH=`pwd -L`
	34
	35	cd $LPP_PATCHPATH/lib/lpp
	36
	37	echo `pwd -L`
	38
	39	case $1 in
	40	-h \| --help \| --h \| -help)
	41	echo 'Help:
	42	This script add all non testbensh VHDL files in vhdlsyn.txt file of each folder.'
	43	;;
	44	* )
	45	for folders in $(find . -type d\|grep ./)
	46	do
	47	echo "enter folder : $folders"
	48	files=$(ls $folders \| grep .vhd \| grep -i -v "test")
	49	echo "found $files"
	50	rm $folders/vhdlsyn.txt
	51	for file in $files
	52	do
	53	echo $file>>$folders/vhdlsyn.txt
	54	done
	55	done
	56	;;
	57
	58	esac
	59
	60	cd $LPP_PATCHPATH
	61

lib/patchlibs.sh created 644 +64 0

@@ -0,0 +1,64
	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP's GRLIB IPs PATCHER "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '----------------------------------------------------------------------------------------
	7	This file is a part of the LPP VHDL IP LIBRARY
	8	Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
	9
	10	This program is free software; you can redistribute it and/or modify
	11	it under the terms of the GNU General Public License as published by
	12	the Free Software Foundation; either version 2 of the License, or
	13	(at your option) any later version.
	14
	15	This program is distributed in the hope that it will be useful,
	16	but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	GNU General Public License for more details.
	19
	20	You should have received a copy of the GNU General Public License
	21	along with this program; if not, write to the Free Software
	22	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	----------------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28
	29	LPP_LIBPATH=`pwd -L`
	30
	31	echo "Patching Grlib..."
	32	echo
	33	echo
	34
	35	#COPY
	36	echo "Remove old lib Files..."
	37	rm -R -v $1/lib/lpp
	38	echo "Copy lib Files..."
	39	cp -R -v $LPP_LIBPATH/lib $1
	40	echo
	41	echo
	42	echo
	43
	44
	45	#PATCH libs.txt
	46	echo "Patch $1/lib/libs.txt..."
	47	if(grep -q lpp $1/lib/libs.txt); then
	48	echo "No need to Patch $1/lib/libs.txt..."
	49	else
	50	echo lpp>>$1/lib/libs.txt
	51	fi
	52
	53	echo
	54	echo
	55	echo
	56
	57	#CLEAN
	58	echo "CLEANING .."
	59	rm -v $1/lib/*.sh
	60	rm -v $1/lib/GPL_HEADER
	61	echo
	62	echo
	63	echo
	64

patch.sh created 644 +89 0

@@ -0,0 +1,89
	1	echo "======================================================================================="
	2	echo "---------------------------------------------------------------------------------------"
	3	echo " LPP's GRLIB GLOBAL PATCHER "
	4	echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
	5	echo "======================================================================================="
	6	echo '------------------------------------------------------------------------------
	7	-- This file is a part of the LPP VHDL IP LIBRARY
	8	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	9	--
	10	-- This program is free software; you can redistribute it and/or modify
	11	-- it under the terms of the GNU General Public License as published by
	12	-- the Free Software Foundation; either version 2 of the License, or
	13	-- (at your option) any later version.
	14	--
	15	-- This program is distributed in the hope that it will be useful,
	16	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	-- GNU General Public License for more details.
	19	--
	20	-- You should have received a copy of the GNU General Public License
	21	-- along with this program; if not, write to the Free Software
	22	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	-------------------------------------------------------------------------------'
	24	echo
	25	echo
	26	echo
	27
	28	# Absolute path to this script. /home/user/bin/foo.sh
	29	#SCRIPT=$(readlink -f $0)
	30	# Absolute path this script is in. /home/user/bin
	31
	32	#LPP_PATCHPATH=`dirname $SCRIPT`
	33	LPP_PATCHPATH=`pwd -L`
	34
	35	GRLIBPATH=$1
	36
	37
	38	if [ -d "$GRLIBPATH" ]; then
	39	if [ -d "$GRLIBPATH/lib" ]; then
	40	if [ -d "$GRLIBPATH/designs" ]; then
	41	if [ -d "$GRLIBPATH/boards" ]; then
	42	#PATCH /lib
	43	echo "patch /lib"
	44	echo
	45
	46	sh $LPP_PATCHPATH/lib/patchlibs.sh $GRLIBPATH
	47
	48	#PATCH /boards
	49	echo "patch /boards"
	50	echo
	51	sh $LPP_PATCHPATH/boards/patchboards.sh $GRLIBPATH
	52
	53	#PATCH /designs
	54	echo "patch /designs"
	55	echo
	56	sh $LPP_PATCHPATH/designs/patchdesigns.sh $GRLIBPATH
	57
	58	echo
	59	echo
	60
	61	#CLEAN
	62	echo "CLEANING .."
	63	rm -v $1/lib/*.sh
	64	rm -v $1/lib/TODO
	65	rm -v $1/lib/Makefile
	66	rm -v $1/lib/log.txt
	67	echo
	68	echo
	69	echo
	70	else
	71	echo "I can't find GRLIB in $1"
	72	fi
	73
	74	else
	75	echo "I can't find GRLIB in $1"
	76	fi
	77	else
	78	echo "I can't find GRLIB in $1"
	79	fi
	80
	81	else
	82	echo "I can't find GRLIB in $1"
	83	fi
	84
	85
	86
	87
	88
	89

LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd removed 0 -68

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LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd removed 0 -57

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LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd removed 0 -206

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LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd removed 0 -156

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LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd removed 0 -72

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LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd removed 0 -102

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LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf removed 0 -37

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LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd removed 0 -68

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LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd removed 0 -57

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LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd removed 0 -206

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LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd removed 0 -156

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LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd removed 0 -72

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LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd removed 0 -102

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LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf removed 0 -37

NO CONTENT: file was removed

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