@@ -425,7 +425,7 BEGIN -- beh | |||
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425 | 425 | pirq_ms => 6, |
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426 | 426 | pirq_wfp => 14, |
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427 | 427 | hindex => 2, |
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428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000107") -- aa.bb.cc version | |
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429 | 429 | PORT MAP ( |
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430 | 430 | clk => clk_25, |
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431 | 431 | rstn => reset, |
@@ -150,10 +150,44 BEGIN -- beh | |||
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150 | 150 | WAIT UNTIL clk25MHz = '1'; |
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151 | 151 | grspw_tick <= '0'; |
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152 | 152 | |
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153 | ||
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154 | ||
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155 | ||
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156 | WAIT FOR 750 ms; | |
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153 | WAIT FOR 250 ms; | |
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154 | TB_string <= "READ 1 "; | |
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155 | apbi.psel(0) <= '1'; | |
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156 | apbi.pwrite <= '0'; | |
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157 | apbi.penable <= '1'; | |
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158 | apbi.paddr <= X"00000008"; | |
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159 | WAIT UNTIL clk25MHz = '1'; | |
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160 | apbi.psel(0) <= '0'; | |
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161 | apbi.pwrite <= '0'; | |
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162 | apbi.penable <= '0'; | |
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163 | apbi.paddr <= (OTHERS => '0'); | |
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164 | WAIT UNTIL clk25MHz = '1'; | |
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165 | WAIT FOR 250 ms; | |
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166 | TB_string <= "READ 2 "; | |
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167 | apbi.psel(0) <= '1'; | |
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168 | apbi.pwrite <= '0'; | |
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169 | apbi.penable <= '1'; | |
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170 | apbi.paddr <= X"00000008"; | |
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171 | WAIT UNTIL clk25MHz = '1'; | |
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172 | apbi.psel(0) <= '0'; | |
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173 | apbi.pwrite <= '0'; | |
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174 | apbi.penable <= '0'; | |
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175 | apbi.paddr <= (OTHERS => '0'); | |
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176 | WAIT UNTIL clk25MHz = '1'; | |
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177 | WAIT FOR 250 ms; | |
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178 | TB_string <= "READ 3 "; | |
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179 | apbi.psel(0) <= '1'; | |
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180 | apbi.pwrite <= '0'; | |
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181 | apbi.penable <= '1'; | |
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182 | apbi.paddr <= X"00000008"; | |
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183 | WAIT UNTIL clk25MHz = '1'; | |
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184 | apbi.psel(0) <= '0'; | |
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185 | apbi.pwrite <= '0'; | |
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186 | apbi.penable <= '0'; | |
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187 | apbi.paddr <= (OTHERS => '0'); | |
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188 | WAIT UNTIL clk25MHz = '1'; | |
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189 | ||
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190 | ||
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157 | 191 | |
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158 | 192 | REPORT "*** END simulation ***" SEVERITY failure; |
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159 | 193 | WAIT; |
@@ -161,6 +195,10 BEGIN -- beh | |||
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161 | 195 | END PROCESS; |
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162 | 196 | |
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163 | 197 | |
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198 | ----------------------------------------------------------------------------- | |
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199 | -- | |
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200 | ----------------------------------------------------------------------------- | |
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201 | ||
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164 | 202 | global_time <= coarse_time & fine_time; |
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165 | 203 | |
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166 | 204 | PROCESS (clk25MHz, resetn) |
@@ -12,8 +12,11 add wave -noupdate /tb/apb_lfr_time_mana | |||
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12 | 12 | add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time |
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13 | 13 | add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time |
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14 | 14 | add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new |
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15 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbi.psel {-radix hexadecimal} /tb/apbi.psel(0) {-radix hexadecimal} /tb/apbi.psel(1) {-radix hexadecimal} /tb/apbi.psel(2) {-radix hexadecimal} /tb/apbi.psel(3) {-radix hexadecimal} /tb/apbi.psel(4) {-radix hexadecimal} /tb/apbi.psel(5) {-radix hexadecimal} /tb/apbi.psel(6) {-radix hexadecimal} /tb/apbi.psel(7) {-radix hexadecimal} /tb/apbi.psel(8) {-radix hexadecimal} /tb/apbi.psel(9) {-radix hexadecimal} /tb/apbi.psel(10) {-radix hexadecimal} /tb/apbi.psel(11) {-radix hexadecimal} /tb/apbi.psel(12) {-radix hexadecimal} /tb/apbi.psel(13) {-radix hexadecimal} /tb/apbi.psel(14) {-radix hexadecimal} /tb/apbi.psel(15) {-radix hexadecimal} /tb/apbi.penable {-radix hexadecimal} /tb/apbi.paddr {-radix hexadecimal} /tb/apbi.pwrite {-radix hexadecimal} /tb/apbi.pwdata {-radix hexadecimal} /tb/apbi.pirq {-radix hexadecimal} /tb/apbi.testen {-radix hexadecimal} /tb/apbi.testrst {-radix hexadecimal} /tb/apbi.scanen {-radix hexadecimal} /tb/apbi.testoen {-radix hexadecimal} /tb/apbi.testin {-radix hexadecimal}} /tb/apbi | |
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16 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbo.prdata {-radix hexadecimal} /tb/apbo.pirq {-radix hexadecimal} /tb/apbo.pconfig {-radix hexadecimal} /tb/apbo.pindex {-radix hexadecimal}} /tb/apbo | |
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17 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apb_lfr_time_management_1/r.ctrl {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time_load {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.fine_time {-radix hexadecimal}} /tb/apb_lfr_time_management_1/r | |
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15 | 18 | TreeUpdate [SetDefaultTree] |
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16 |
WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} { |
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19 | WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} {750199620000 ps} 0} {TRANSITION {169333245705 ps} 1} | |
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17 | 20 | configure wave -namecolwidth 512 |
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18 | 21 | configure wave -valuecolwidth 139 |
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19 | 22 | configure wave -justifyvalue left |
@@ -28,4 +31,4 configure wave -griddelta 40 | |||
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28 | 31 | configure wave -timeline 0 |
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29 | 32 | configure wave -timelineunits ps |
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30 | 33 | update |
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31 |
WaveRestoreZoom {0 ps} { |
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34 | WaveRestoreZoom {0 ps} {1185800469 ns} |
@@ -131,6 +131,7 BEGIN | |||
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131 | 131 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); |
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132 | 132 | coarsetime_reg_updated <= '1'; |
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133 | 133 | WHEN OTHERS => |
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134 | NULL; | |
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134 | 135 | END CASE; |
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135 | 136 | ELSIF r.ctrl = '1' THEN |
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136 | 137 | r.ctrl <= '0'; |
@@ -140,16 +141,17 BEGIN | |||
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140 | 141 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN |
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141 | 142 | CASE apbi.paddr(7 DOWNTO 2) IS |
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142 | 143 | WHEN "000000" => |
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143 | Rdata(0) <= r.ctrl; | |
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144 | Rdata(0) <= r.ctrl; | |
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145 | Rdata(31 DOWNTO 1) <= (others => '0'); | |
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144 | 146 | WHEN "000001" => |
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145 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); | |
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147 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); | |
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146 | 148 | WHEN "000010" => |
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147 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); | |
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149 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); | |
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148 | 150 | WHEN "000011" => |
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149 | 151 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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150 | 152 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
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151 | 153 | WHEN OTHERS => |
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152 |
Rdata(31 DOWNTO 0) <= |
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154 | Rdata(31 DOWNTO 0) <= (others => '0'); | |
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153 | 155 | END CASE; |
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154 | 156 | END IF; |
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155 | 157 | |
@@ -271,4 +273,4 BEGIN | |||
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271 | 273 | coarse_time => coarse_time_49, |
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272 | 274 | coarse_time_new => coarse_time_new_49); |
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273 | 275 | |
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274 |
END Behavioral; |
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276 | END Behavioral; No newline at end of file |
This diff has been collapsed as it changes many lines, (825 lines changed) Show them Hide them | |||
@@ -1,394 +1,431 | |||
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1 | ||
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2 | ------------------------------------------------------------------------------ | |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
5 | -- | |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
|
7 | -- it under the terms of the GNU General Public License as published by | |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
|
9 | -- (at your option) any later version. | |
|
10 | -- | |
|
11 | -- This program is distributed in the hope that it will be useful, | |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
14 | -- GNU General Public License for more details. | |
|
15 | -- | |
|
16 | -- You should have received a copy of the GNU General Public License | |
|
17 | -- along with this program; if not, write to the Free Software | |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
19 | ------------------------------------------------------------------------------- | |
|
20 | -- Author : Jean-christophe Pellion | |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
|
23 | ------------------------------------------------------------------------------- | |
|
24 | -- 1.0 - initial version | |
|
25 | ------------------------------------------------------------------------------- | |
|
26 | LIBRARY ieee; | |
|
27 | USE ieee.std_logic_1164.ALL; | |
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28 | USE ieee.numeric_std.ALL; | |
|
29 | LIBRARY grlib; | |
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30 | USE grlib.amba.ALL; | |
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31 | USE grlib.stdlib.ALL; | |
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32 | USE grlib.devices.ALL; | |
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33 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
34 | LIBRARY lpp; | |
|
35 | USE lpp.lpp_amba.ALL; | |
|
36 | USE lpp.apb_devices_list.ALL; | |
|
37 | USE lpp.lpp_memory.ALL; | |
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38 | USE lpp.lpp_dma_pkg.ALL; | |
|
39 | LIBRARY techmap; | |
|
40 | USE techmap.gencomp.ALL; | |
|
41 | ||
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42 | ||
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43 | ENTITY lpp_lfr_ms_fsmdma IS | |
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44 | PORT ( | |
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45 | -- AMBA AHB system signals | |
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46 | HCLK : IN STD_ULOGIC; | |
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47 | HRESETn : IN STD_ULOGIC; | |
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48 | ||
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49 | --TIME | |
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50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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51 | ||
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52 | -- fifo interface | |
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53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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54 | fifo_empty : IN STD_LOGIC; | |
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55 | fifo_ren : OUT STD_LOGIC; | |
|
56 | ||
|
57 | -- header | |
|
58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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59 | header_val : IN STD_LOGIC; | |
|
60 | header_ack : OUT STD_LOGIC; | |
|
61 | ||
|
62 | -- DMA | |
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63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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65 | dma_valid : OUT STD_LOGIC; | |
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66 | dma_valid_burst : OUT STD_LOGIC; | |
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67 | dma_ren : IN STD_LOGIC; | |
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68 | dma_done : IN STD_LOGIC; | |
|
69 | ||
|
70 | -- Reg out | |
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71 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
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72 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
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73 | ready_matrix_f1 : OUT STD_LOGIC; | |
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74 | ready_matrix_f2 : OUT STD_LOGIC; | |
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75 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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76 | error_bad_component_error : OUT STD_LOGIC; | |
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77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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78 | ||
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79 | -- Reg In | |
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80 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
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81 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
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82 | status_ready_matrix_f1 : IN STD_LOGIC; | |
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83 | status_ready_matrix_f2 : IN STD_LOGIC; | |
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84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
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85 | status_error_bad_component_error : IN STD_LOGIC; | |
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86 | ||
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87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
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88 | config_active_interruption_onError : IN STD_LOGIC; | |
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89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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93 | ||
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94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
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98 | ||
|
99 | ); | |
|
100 | END; | |
|
101 | ||
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102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
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103 | ----------------------------------------------------------------------------- | |
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104 | -- SIGNAL DMAIn : DMA_In_Type; | |
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105 | -- SIGNAL header_dmai : DMA_In_Type; | |
|
106 | -- SIGNAL component_dmai : DMA_In_Type; | |
|
107 | -- SIGNAL DMAOut : DMA_OUt_Type; | |
|
108 | ----------------------------------------------------------------------------- | |
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109 | ||
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110 | ----------------------------------------------------------------------------- | |
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111 | ----------------------------------------------------------------------------- | |
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112 | TYPE state_DMAWriteBurst IS (IDLE, | |
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113 | CHECK_COMPONENT_TYPE, | |
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114 | WRITE_COARSE_TIME, | |
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115 | WRITE_FINE_TIME, | |
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116 | TRASH_FIFO, | |
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117 | SEND_DATA, | |
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118 | WAIT_DATA_ACK | |
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119 | ); | |
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120 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; | |
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121 | ||
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122 | -- SIGNAL nbSend : INTEGER; | |
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123 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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124 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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125 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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126 | SIGNAL header_check_ok : STD_LOGIC; | |
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127 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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128 | SIGNAL send_matrix : STD_LOGIC; | |
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129 | -- SIGNAL request : STD_LOGIC; | |
|
130 | -- SIGNAL remaining_data_request : INTEGER; | |
|
131 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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132 | ----------------------------------------------------------------------------- | |
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133 | ----------------------------------------------------------------------------- | |
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134 | SIGNAL header_select : STD_LOGIC; | |
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135 | ||
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136 | SIGNAL header_send : STD_LOGIC; | |
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137 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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138 | SIGNAL header_send_ok : STD_LOGIC; | |
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139 | SIGNAL header_send_ko : STD_LOGIC; | |
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140 | ||
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141 | SIGNAL component_send : STD_LOGIC; | |
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142 | SIGNAL component_send_ok : STD_LOGIC; | |
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143 | SIGNAL component_send_ko : STD_LOGIC; | |
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144 | ----------------------------------------------------------------------------- | |
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145 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
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146 | SIGNAL component_fifo_ren : STD_LOGIC; | |
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147 | ||
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148 | ----------------------------------------------------------------------------- | |
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149 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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150 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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151 | ||
|
152 | ----------------------------------------------------------------------------- | |
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153 | SIGNAL log_empty_fifo : STD_LOGIC; | |
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154 | ||
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155 | BEGIN | |
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156 | ||
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157 | debug_reg <= debug_reg_s; | |
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158 | ||
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159 | ||
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160 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
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161 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
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162 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
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163 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
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164 | '0'; | |
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165 | ||
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166 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
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167 |
|
|
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168 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
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169 |
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170 | ||
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171 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
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172 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
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173 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
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174 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
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175 | (OTHERS => '0'); | |
|
176 | ||
|
177 | ----------------------------------------------------------------------------- | |
|
178 | -- DMA control | |
|
179 | ----------------------------------------------------------------------------- | |
|
180 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
|
181 | BEGIN -- PROCESS DMAWriteBurst_p | |
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182 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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183 | matrix_type <= (OTHERS => '0'); | |
|
184 | component_type <= (OTHERS => '0'); | |
|
185 | state <= IDLE; | |
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186 | header_ack <= '0'; | |
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187 | ready_matrix_f0_0 <= '0'; | |
|
188 |
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|
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189 |
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190 |
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|
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191 | error_anticipating_empty_fifo <= '0'; | |
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192 | error_bad_component_error <= '0'; | |
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193 | component_type_pre <= "0000"; | |
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194 |
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|
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195 |
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|
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196 | address <= (OTHERS => '0'); | |
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197 | header_select <= '0'; | |
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198 | header_send <= '0'; | |
|
199 | header_data <= (OTHERS => '0'); | |
|
200 |
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|
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201 | ||
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202 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); | |
|
203 | ||
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204 | log_empty_fifo <= '0'; | |
|
205 | ||
|
206 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
207 |
debug_reg_s( |
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|
208 | ||
|
209 | CASE state IS | |
|
210 | WHEN IDLE => | |
|
211 | debug_reg_s(2 DOWNTO 0) <= "000"; | |
|
212 | ||
|
213 | matrix_type <= header(1 DOWNTO 0); | |
|
214 | --component_type <= header(5 DOWNTO 2); | |
|
215 | ||
|
216 | ready_matrix_f0_0 <= '0'; | |
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217 | ready_matrix_f0_1 <= '0'; | |
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218 | ready_matrix_f1 <= '0'; | |
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219 | ready_matrix_f2 <= '0'; | |
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220 | error_bad_component_error <= '0'; | |
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221 | header_select <= '1'; | |
|
222 | IF header_val = '1' THEN | |
|
223 | header_ack <= '1'; | |
|
224 | END IF; | |
|
225 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
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226 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); | |
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227 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); | |
|
228 | ||
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229 | matrix_type <= header(1 DOWNTO 0); | |
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230 | component_type <= header(5 DOWNTO 2); | |
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231 | component_type_pre <= component_type; | |
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232 | state <= CHECK_COMPONENT_TYPE; | |
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233 | END IF; | |
|
234 | log_empty_fifo <= '0'; | |
|
235 | ||
|
236 | WHEN CHECK_COMPONENT_TYPE => | |
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237 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
|
238 |
|
|
|
239 | ||
|
240 | IF header_check_ok = '1' THEN | |
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241 | header_send <= '0'; | |
|
242 | -- | |
|
243 | IF component_type = "0000" THEN | |
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244 | address <= address_matrix; | |
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245 | CASE matrix_type IS | |
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246 | WHEN "00" => matrix_time_f0_0 <= data_time; | |
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247 | WHEN "01" => matrix_time_f0_1 <= data_time; | |
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248 | WHEN "10" => matrix_time_f1 <= data_time; | |
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249 | WHEN "11" => matrix_time_f2 <= data_time ; | |
|
250 | WHEN OTHERS => NULL; | |
|
251 |
E |
|
|
252 | ||
|
253 | header_data <= data_time(31 DOWNTO 0); | |
|
254 |
|
|
|
255 | --state <= WRITE_COARSE_TIME; | |
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256 | --header_send <= '1'; | |
|
257 | state <= SEND_DATA; | |
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258 | header_send <= '0'; | |
|
259 | component_send <= '1'; | |
|
260 | header_select <= '0'; | |
|
261 | ELSE | |
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262 |
|
|
|
263 | END IF; | |
|
264 | -- | |
|
265 | ELSE | |
|
266 | error_bad_component_error <= '1'; | |
|
267 | component_type_pre <= "0000"; | |
|
268 | state <= TRASH_FIFO; | |
|
269 | END IF; | |
|
270 | ||
|
271 | --WHEN WRITE_COARSE_TIME => | |
|
272 | -- debug_reg_s(2 DOWNTO 0) <= "010"; | |
|
273 | ||
|
274 | -- header_ack <= '0'; | |
|
275 | ||
|
276 | -- IF dma_ren = '0' THEN | |
|
277 | -- header_send <= '0'; | |
|
278 | -- ELSE | |
|
279 | -- header_send <= header_send; | |
|
280 | -- END IF; | |
|
281 | ||
|
282 | ||
|
283 |
-- |
|
|
284 | -- header_send <= '0'; | |
|
285 | -- state <= TRASH_FIFO; | |
|
286 | -- error_anticipating_empty_fifo <= '1'; | |
|
287 | -- -- TODO : error sending header | |
|
288 | -- ELSIF header_send_ok = '1' THEN | |
|
289 |
-- |
|
|
290 |
-- header_se |
|
|
291 | -- header_data(15 DOWNTO 0) <= fine_time_reg; | |
|
292 | -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); | |
|
293 | -- state <= WRITE_FINE_TIME; | |
|
294 | -- address <= address + 4; | |
|
295 | -- END IF; | |
|
296 | ||
|
297 | ||
|
298 | --WHEN WRITE_FINE_TIME => | |
|
299 | -- debug_reg_s(2 DOWNTO 0) <= "011"; | |
|
300 | ||
|
301 | -- header_ack <= '0'; | |
|
302 | ||
|
303 | -- IF dma_ren = '0' THEN | |
|
304 | -- header_send <= '0'; | |
|
305 | -- ELSE | |
|
306 | -- header_send <= header_send; | |
|
307 | -- END IF; | |
|
308 | ||
|
309 |
-- IF |
|
|
310 |
-- header_send |
|
|
311 | -- state <= TRASH_FIFO; | |
|
312 | -- error_anticipating_empty_fifo <= '1'; | |
|
313 | -- -- TODO : error sending header | |
|
314 | -- ELSIF header_send_ok = '1' THEN | |
|
315 |
-- |
|
|
316 |
-- header_se |
|
|
317 |
-- state |
|
|
318 | -- address <= address + 4; | |
|
319 | -- END IF; | |
|
320 | ||
|
321 | WHEN TRASH_FIFO => | |
|
322 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
|
323 | ||
|
324 | header_ack <= '0'; | |
|
325 | error_bad_component_error <= '0'; | |
|
326 | error_anticipating_empty_fifo <= '0'; | |
|
327 | IF fifo_empty = '1' THEN | |
|
328 | state <= IDLE; | |
|
329 | fifo_ren_trash <= '1'; | |
|
330 | ELSE | |
|
331 | fifo_ren_trash <= '0'; | |
|
332 | END IF; | |
|
333 | ||
|
334 | WHEN SEND_DATA => | |
|
335 | header_ack <= '0'; | |
|
336 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
|
337 | ||
|
338 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
|
339 | state <= IDLE; | |
|
340 | IF component_type = "1110" THEN --"1110" -- JC | |
|
341 | CASE matrix_type IS | |
|
342 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
|
343 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
|
344 | WHEN "10" => ready_matrix_f1 <= '1'; | |
|
345 | WHEN "11" => ready_matrix_f2 <= '1'; | |
|
346 | WHEN OTHERS => NULL; | |
|
347 |
E |
|
|
348 | ||
|
349 | END IF; | |
|
350 | ELSE | |
|
351 | component_send <= '1'; | |
|
352 | address <= address; | |
|
353 | state <= WAIT_DATA_ACK; | |
|
354 | END IF; | |
|
355 | ||
|
356 | WHEN WAIT_DATA_ACK => | |
|
357 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |
|
358 | ||
|
359 | debug_reg_s(2 DOWNTO 0) <= "110"; | |
|
360 | ||
|
361 | component_send <= '0'; | |
|
362 | IF component_send_ok = '1' THEN | |
|
363 | address <= address + 64; | |
|
364 | state <= SEND_DATA; | |
|
365 | ELSIF component_send_ko = '1' THEN | |
|
366 | error_anticipating_empty_fifo <= '0'; | |
|
367 | state <= TRASH_FIFO; | |
|
368 | END IF; | |
|
369 | ||
|
370 | ||
|
371 | --WHEN CHECK_LENGTH => | |
|
372 | -- component_send <= '0'; | |
|
373 | -- debug_reg_s(2 DOWNTO 0) <= "111"; | |
|
374 |
|
|
|
375 | ||
|
376 | WHEN OTHERS => NULL; | |
|
377 | END CASE; | |
|
378 | ||
|
379 | END IF; | |
|
380 | END PROCESS DMAWriteFSM_p; | |
|
381 | ||
|
382 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; | |
|
383 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; | |
|
384 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; | |
|
385 | dma_addr <= address; | |
|
386 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; | |
|
387 | ||
|
388 |
|
|
|
389 | component_send_ko <= '0'; | |
|
390 | ||
|
391 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; | |
|
392 | header_send_ko <= '0'; | |
|
393 | ||
|
394 | END Behavioral; | |
|
1 | ||
|
2 | ------------------------------------------------------------------------------ | |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
5 | -- | |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
|
7 | -- it under the terms of the GNU General Public License as published by | |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
|
9 | -- (at your option) any later version. | |
|
10 | -- | |
|
11 | -- This program is distributed in the hope that it will be useful, | |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
14 | -- GNU General Public License for more details. | |
|
15 | -- | |
|
16 | -- You should have received a copy of the GNU General Public License | |
|
17 | -- along with this program; if not, write to the Free Software | |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
19 | ------------------------------------------------------------------------------- | |
|
20 | -- Author : Jean-christophe Pellion | |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
|
23 | ------------------------------------------------------------------------------- | |
|
24 | -- 1.0 - initial version | |
|
25 | ------------------------------------------------------------------------------- | |
|
26 | LIBRARY ieee; | |
|
27 | USE ieee.std_logic_1164.ALL; | |
|
28 | USE ieee.numeric_std.ALL; | |
|
29 | LIBRARY grlib; | |
|
30 | USE grlib.amba.ALL; | |
|
31 | USE grlib.stdlib.ALL; | |
|
32 | USE grlib.devices.ALL; | |
|
33 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
34 | LIBRARY lpp; | |
|
35 | USE lpp.lpp_amba.ALL; | |
|
36 | USE lpp.apb_devices_list.ALL; | |
|
37 | USE lpp.lpp_memory.ALL; | |
|
38 | USE lpp.lpp_dma_pkg.ALL; | |
|
39 | LIBRARY techmap; | |
|
40 | USE techmap.gencomp.ALL; | |
|
41 | ||
|
42 | ||
|
43 | ENTITY lpp_lfr_ms_fsmdma IS | |
|
44 | PORT ( | |
|
45 | -- AMBA AHB system signals | |
|
46 | HCLK : IN STD_ULOGIC; | |
|
47 | HRESETn : IN STD_ULOGIC; | |
|
48 | ||
|
49 | --TIME | |
|
50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
51 | ||
|
52 | -- fifo interface | |
|
53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
54 | fifo_empty : IN STD_LOGIC; | |
|
55 | fifo_ren : OUT STD_LOGIC; | |
|
56 | ||
|
57 | -- header | |
|
58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
59 | header_val : IN STD_LOGIC; | |
|
60 | header_ack : OUT STD_LOGIC; | |
|
61 | ||
|
62 | -- DMA | |
|
63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
65 | dma_valid : OUT STD_LOGIC; | |
|
66 | dma_valid_burst : OUT STD_LOGIC; | |
|
67 | dma_ren : IN STD_LOGIC; | |
|
68 | dma_done : IN STD_LOGIC; | |
|
69 | ||
|
70 | -- Reg out | |
|
71 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
|
72 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
73 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
74 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
75 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
76 | error_bad_component_error : OUT STD_LOGIC; | |
|
77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
78 | ||
|
79 | -- Reg In | |
|
80 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
|
81 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
|
82 | status_ready_matrix_f1 : IN STD_LOGIC; | |
|
83 | status_ready_matrix_f2 : IN STD_LOGIC; | |
|
84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
85 | status_error_bad_component_error : IN STD_LOGIC; | |
|
86 | ||
|
87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
|
88 | config_active_interruption_onError : IN STD_LOGIC; | |
|
89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
93 | ||
|
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
98 | ||
|
99 | ); | |
|
100 | END; | |
|
101 | ||
|
102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
|
103 | ----------------------------------------------------------------------------- | |
|
104 | -- SIGNAL DMAIn : DMA_In_Type; | |
|
105 | -- SIGNAL header_dmai : DMA_In_Type; | |
|
106 | -- SIGNAL component_dmai : DMA_In_Type; | |
|
107 | -- SIGNAL DMAOut : DMA_OUt_Type; | |
|
108 | ----------------------------------------------------------------------------- | |
|
109 | ||
|
110 | ----------------------------------------------------------------------------- | |
|
111 | ----------------------------------------------------------------------------- | |
|
112 | TYPE state_DMAWriteBurst IS (IDLE, | |
|
113 | CHECK_COMPONENT_TYPE, | |
|
114 | WRITE_COARSE_TIME, | |
|
115 | WRITE_FINE_TIME, | |
|
116 | TRASH_FIFO, | |
|
117 | SEND_DATA, | |
|
118 | WAIT_DATA_ACK | |
|
119 | ); | |
|
120 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; | |
|
121 | ||
|
122 | -- SIGNAL nbSend : INTEGER; | |
|
123 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
124 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
125 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
126 | SIGNAL header_check_ok : STD_LOGIC; | |
|
127 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
128 | SIGNAL send_matrix : STD_LOGIC; | |
|
129 | -- SIGNAL request : STD_LOGIC; | |
|
130 | -- SIGNAL remaining_data_request : INTEGER; | |
|
131 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | ----------------------------------------------------------------------------- | |
|
133 | ----------------------------------------------------------------------------- | |
|
134 | SIGNAL header_select : STD_LOGIC; | |
|
135 | ||
|
136 | SIGNAL header_send : STD_LOGIC; | |
|
137 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
138 | SIGNAL header_send_ok : STD_LOGIC; | |
|
139 | SIGNAL header_send_ko : STD_LOGIC; | |
|
140 | ||
|
141 | SIGNAL component_send : STD_LOGIC; | |
|
142 | SIGNAL component_send_ok : STD_LOGIC; | |
|
143 | SIGNAL component_send_ko : STD_LOGIC; | |
|
144 | ----------------------------------------------------------------------------- | |
|
145 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
|
146 | SIGNAL component_fifo_ren : STD_LOGIC; | |
|
147 | ||
|
148 | ----------------------------------------------------------------------------- | |
|
149 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
150 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
151 | ||
|
152 | ----------------------------------------------------------------------------- | |
|
153 | SIGNAL log_empty_fifo : STD_LOGIC; | |
|
154 | ----------------------------------------------------------------------------- | |
|
155 | SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
156 | SIGNAL header_reg_val : STD_LOGIC; | |
|
157 | SIGNAL header_reg_ack : STD_LOGIC; | |
|
158 | SIGNAL header_error : STD_LOGIC; | |
|
159 | ||
|
160 | BEGIN | |
|
161 | ||
|
162 | debug_reg <= debug_reg_s; | |
|
163 | ||
|
164 | ||
|
165 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
|
166 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
|
167 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
|
168 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
|
169 | '0'; | |
|
170 | ||
|
171 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
|
172 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE | |
|
173 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
|
174 | '0'; | |
|
175 | ||
|
176 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
|
177 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
|
178 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
|
179 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
|
180 | (OTHERS => '0'); | |
|
181 | ||
|
182 | ----------------------------------------------------------------------------- | |
|
183 | -- DMA control | |
|
184 | ----------------------------------------------------------------------------- | |
|
185 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
|
186 | BEGIN -- PROCESS DMAWriteBurst_p | |
|
187 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
188 | matrix_type <= (OTHERS => '0'); | |
|
189 | component_type <= (OTHERS => '0'); | |
|
190 | state <= IDLE; | |
|
191 | -- header_ack <= '0'; | |
|
192 | ready_matrix_f0_0 <= '0'; | |
|
193 | ready_matrix_f0_1 <= '0'; | |
|
194 | ready_matrix_f1 <= '0'; | |
|
195 | ready_matrix_f2 <= '0'; | |
|
196 | error_anticipating_empty_fifo <= '0'; | |
|
197 | error_bad_component_error <= '0'; | |
|
198 | component_type_pre <= "0000"; | |
|
199 | fifo_ren_trash <= '1'; | |
|
200 | component_send <= '0'; | |
|
201 | address <= (OTHERS => '0'); | |
|
202 | header_select <= '0'; | |
|
203 | header_send <= '0'; | |
|
204 | header_data <= (OTHERS => '0'); | |
|
205 | fine_time_reg <= (OTHERS => '0'); | |
|
206 | ||
|
207 | debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0'); | |
|
208 | debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); | |
|
209 | ||
|
210 | log_empty_fifo <= '0'; | |
|
211 | ||
|
212 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
213 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |
|
214 | header_reg_ack <= '0'; | |
|
215 | ||
|
216 | CASE state IS | |
|
217 | WHEN IDLE => | |
|
218 | debug_reg_s(2 DOWNTO 0) <= "000"; | |
|
219 | ||
|
220 | matrix_type <= header(1 DOWNTO 0); | |
|
221 | --component_type <= header(5 DOWNTO 2); | |
|
222 | ||
|
223 | ready_matrix_f0_0 <= '0'; | |
|
224 | ready_matrix_f0_1 <= '0'; | |
|
225 | ready_matrix_f1 <= '0'; | |
|
226 | ready_matrix_f2 <= '0'; | |
|
227 | error_bad_component_error <= '0'; | |
|
228 | header_select <= '1'; | |
|
229 | ||
|
230 | IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
|
231 | header_reg_ack <= '1'; | |
|
232 | debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0); | |
|
233 | debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2); | |
|
234 | ||
|
235 | matrix_type <= header_reg(1 DOWNTO 0); | |
|
236 | component_type <= header_reg(5 DOWNTO 2); | |
|
237 | component_type_pre <= component_type; | |
|
238 | state <= CHECK_COMPONENT_TYPE; | |
|
239 | END IF; | |
|
240 | log_empty_fifo <= '0'; | |
|
241 | ||
|
242 | WHEN CHECK_COMPONENT_TYPE => | |
|
243 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
|
244 | --header_ack <= '0'; | |
|
245 | ||
|
246 | IF header_check_ok = '1' THEN | |
|
247 | header_send <= '0'; | |
|
248 | -- | |
|
249 | IF component_type = "0000" THEN | |
|
250 | address <= address_matrix; | |
|
251 | CASE matrix_type IS | |
|
252 | WHEN "00" => matrix_time_f0_0 <= data_time; | |
|
253 | WHEN "01" => matrix_time_f0_1 <= data_time; | |
|
254 | WHEN "10" => matrix_time_f1 <= data_time; | |
|
255 | WHEN "11" => matrix_time_f2 <= data_time ; | |
|
256 | WHEN OTHERS => NULL; | |
|
257 | END CASE; | |
|
258 | ||
|
259 | header_data <= data_time(31 DOWNTO 0); | |
|
260 | fine_time_reg <= data_time(47 DOWNTO 32); | |
|
261 | --state <= WRITE_COARSE_TIME; | |
|
262 | --header_send <= '1'; | |
|
263 | state <= SEND_DATA; | |
|
264 | header_send <= '0'; | |
|
265 | component_send <= '1'; | |
|
266 | header_select <= '0'; | |
|
267 | ELSE | |
|
268 | state <= SEND_DATA; | |
|
269 | END IF; | |
|
270 | -- | |
|
271 | ELSE | |
|
272 | error_bad_component_error <= '1'; | |
|
273 | component_type_pre <= "0000"; | |
|
274 | state <= TRASH_FIFO; | |
|
275 | END IF; | |
|
276 | ||
|
277 | --WHEN WRITE_COARSE_TIME => | |
|
278 | -- debug_reg_s(2 DOWNTO 0) <= "010"; | |
|
279 | ||
|
280 | -- header_ack <= '0'; | |
|
281 | ||
|
282 | -- IF dma_ren = '0' THEN | |
|
283 | -- header_send <= '0'; | |
|
284 | -- ELSE | |
|
285 | -- header_send <= header_send; | |
|
286 | -- END IF; | |
|
287 | ||
|
288 | ||
|
289 | -- IF header_send_ko = '1' THEN | |
|
290 | -- header_send <= '0'; | |
|
291 | -- state <= TRASH_FIFO; | |
|
292 | -- error_anticipating_empty_fifo <= '1'; | |
|
293 | -- -- TODO : error sending header | |
|
294 | -- ELSIF header_send_ok = '1' THEN | |
|
295 | -- header_send <= '1'; | |
|
296 | -- header_select <= '1'; | |
|
297 | -- header_data(15 DOWNTO 0) <= fine_time_reg; | |
|
298 | -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); | |
|
299 | -- state <= WRITE_FINE_TIME; | |
|
300 | -- address <= address + 4; | |
|
301 | -- END IF; | |
|
302 | ||
|
303 | ||
|
304 | --WHEN WRITE_FINE_TIME => | |
|
305 | -- debug_reg_s(2 DOWNTO 0) <= "011"; | |
|
306 | ||
|
307 | -- header_ack <= '0'; | |
|
308 | ||
|
309 | -- IF dma_ren = '0' THEN | |
|
310 | -- header_send <= '0'; | |
|
311 | -- ELSE | |
|
312 | -- header_send <= header_send; | |
|
313 | -- END IF; | |
|
314 | ||
|
315 | -- IF header_send_ko = '1' THEN | |
|
316 | -- header_send <= '0'; | |
|
317 | -- state <= TRASH_FIFO; | |
|
318 | -- error_anticipating_empty_fifo <= '1'; | |
|
319 | -- -- TODO : error sending header | |
|
320 | -- ELSIF header_send_ok = '1' THEN | |
|
321 | -- header_send <= '0'; | |
|
322 | -- header_select <= '0'; | |
|
323 | -- state <= SEND_DATA; | |
|
324 | -- address <= address + 4; | |
|
325 | -- END IF; | |
|
326 | ||
|
327 | WHEN TRASH_FIFO => | |
|
328 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
|
329 | ||
|
330 | -- header_ack <= '0'; | |
|
331 | error_bad_component_error <= '0'; | |
|
332 | error_anticipating_empty_fifo <= '0'; | |
|
333 | IF fifo_empty = '1' THEN | |
|
334 | state <= IDLE; | |
|
335 | fifo_ren_trash <= '1'; | |
|
336 | ELSE | |
|
337 | fifo_ren_trash <= '0'; | |
|
338 | END IF; | |
|
339 | ||
|
340 | WHEN SEND_DATA => | |
|
341 | -- header_ack <= '0'; | |
|
342 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
|
343 | ||
|
344 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
|
345 | state <= IDLE; | |
|
346 | IF component_type = "1110" THEN --"1110" -- JC | |
|
347 | CASE matrix_type IS | |
|
348 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
|
349 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
|
350 | WHEN "10" => ready_matrix_f1 <= '1'; | |
|
351 | WHEN "11" => ready_matrix_f2 <= '1'; | |
|
352 | WHEN OTHERS => NULL; | |
|
353 | END CASE; | |
|
354 | ||
|
355 | END IF; | |
|
356 | ELSE | |
|
357 | component_send <= '1'; | |
|
358 | address <= address; | |
|
359 | state <= WAIT_DATA_ACK; | |
|
360 | END IF; | |
|
361 | ||
|
362 | WHEN WAIT_DATA_ACK => | |
|
363 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |
|
364 | ||
|
365 | debug_reg_s(2 DOWNTO 0) <= "110"; | |
|
366 | ||
|
367 | component_send <= '0'; | |
|
368 | IF component_send_ok = '1' THEN | |
|
369 | address <= address + 64; | |
|
370 | state <= SEND_DATA; | |
|
371 | ELSIF component_send_ko = '1' THEN | |
|
372 | error_anticipating_empty_fifo <= '0'; | |
|
373 | state <= TRASH_FIFO; | |
|
374 | END IF; | |
|
375 | ||
|
376 | ||
|
377 | --WHEN CHECK_LENGTH => | |
|
378 | -- component_send <= '0'; | |
|
379 | -- debug_reg_s(2 DOWNTO 0) <= "111"; | |
|
380 | -- state <= IDLE; | |
|
381 | ||
|
382 | WHEN OTHERS => NULL; | |
|
383 | END CASE; | |
|
384 | ||
|
385 | END IF; | |
|
386 | END PROCESS DMAWriteFSM_p; | |
|
387 | ||
|
388 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; | |
|
389 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; | |
|
390 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; | |
|
391 | dma_addr <= address; | |
|
392 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; | |
|
393 | ||
|
394 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; | |
|
395 | component_send_ko <= '0'; | |
|
396 | ||
|
397 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; | |
|
398 | header_send_ko <= '0'; | |
|
399 | ||
|
400 | ||
|
401 | ----------------------------------------------------------------------------- | |
|
402 | -- FSM HEADER ACK | |
|
403 | ----------------------------------------------------------------------------- | |
|
404 | PROCESS (HCLK, HRESETn) | |
|
405 | BEGIN -- PROCESS | |
|
406 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
407 | header_ack <= '0'; | |
|
408 | header_reg <= (OTHERS => '0'); | |
|
409 | header_reg_val <= '0'; | |
|
410 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
|
411 | header_ack <= '0'; | |
|
412 | ||
|
413 | IF header_val = '1' THEN | |
|
414 | header_ack <= '1'; | |
|
415 | header_reg <= header; | |
|
416 | END IF; | |
|
417 | ||
|
418 | IF header_val = '1' THEN | |
|
419 | header_reg_val <= '1'; | |
|
420 | ELSIF header_reg_ack = '1' THEN | |
|
421 | header_reg_val <= '0'; | |
|
422 | END IF; | |
|
423 | ||
|
424 | header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack); | |
|
425 | ||
|
426 | END IF; | |
|
427 | END PROCESS; | |
|
428 | ||
|
429 | debug_reg_s(3) <= header_error; | |
|
430 | ||
|
431 | END Behavioral; No newline at end of file |
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