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LEON3 SoC in staging/LPP/JCP/SOC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 PACKAGE SOC__LPP_JCP IS
28
29 COMPONENT leon3_soc__LPP_JCP
30 GENERIC (
31 fabtech : INTEGER;
32 memtech : INTEGER;
33 padtech : INTEGER;
34 clktech : INTEGER;
35 disas : INTEGER;
36 dbguart : INTEGER;
37 pclow : INTEGER;
38 clk_freq : INTEGER;
39 NB_CPU : INTEGER;
40 ENABLE_FPU : INTEGER;
41 FPU_NETLIST : INTEGER;
42 ENABLE_DSU : INTEGER;
43 ENABLE_AHB_UART : INTEGER;
44 ENABLE_APB_UART : INTEGER;
45 ENABLE_IRQMP : INTEGER;
46 ENABLE_GPT : INTEGER;
47 NB_AHB_MASTER : INTEGER;
48 NB_AHB_SLAVE : INTEGER;
49 NB_APB_SLAVE : INTEGER);
50 PORT (
51 clk : IN STD_ULOGIC;
52 rstn : IN STD_ULOGIC;
53 errorn : OUT STD_ULOGIC;
54 ahbrxd : IN STD_ULOGIC;
55 ahbtxd : OUT STD_ULOGIC;
56 urxd1 : IN STD_ULOGIC;
57 utxd1 : OUT STD_ULOGIC;
58 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
59 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 nSRAM_BE0 : OUT STD_LOGIC;
61 nSRAM_BE1 : OUT STD_LOGIC;
62 nSRAM_BE2 : OUT STD_LOGIC;
63 nSRAM_BE3 : OUT STD_LOGIC;
64 nSRAM_WE : OUT STD_LOGIC;
65 nSRAM_CE : OUT STD_LOGIC;
66 nSRAM_OE : OUT STD_LOGIC;
67 apbi_ext : OUT apb_slv_in_type;
68 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
69 ahbi_s_ext : OUT ahb_slv_in_type;
70 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
71 ahbi_m_ext : OUT AHB_Mst_In_Type;
72 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
73 END COMPONENT;
74
75 END;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
31 LIBRARY gaisler;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
39
40 ENTITY leon3_soc__LPP_JCP IS
41 GENERIC (
42 fabtech : INTEGER := apa3e;
43 memtech : INTEGER := apa3e;
44 padtech : INTEGER := inferred;
45 clktech : INTEGER := inferred;
46 disas : INTEGER := 0; -- Enable disassembly to console
47 dbguart : INTEGER := 0; -- Print UART on console
48 pclow : INTEGER := 2;
49 --
50 clk_freq : INTEGER := 25000; --kHz
51 --
52 NB_CPU : INTEGER := 1;
53 ENABLE_FPU : INTEGER := 1;
54 FPU_NETLIST : INTEGER := 1;
55 ENABLE_DSU : INTEGER := 1;
56 ENABLE_AHB_UART : INTEGER := 1;
57 ENABLE_APB_UART : INTEGER := 1;
58 ENABLE_IRQMP : INTEGER := 1;
59 ENABLE_GPT : INTEGER := 1;
60 --
61 NB_AHB_MASTER : INTEGER := 0;
62 NB_AHB_SLAVE : INTEGER := 0;
63 NB_APB_SLAVE : INTEGER := 0
64 );
65 PORT (
66 clk : IN STD_ULOGIC;
67 rstn : IN STD_ULOGIC;
68
69 errorn : OUT STD_ULOGIC;
70
71 -- UART AHB ---------------------------------------------------------------
72 ahbrxd : IN STD_ULOGIC; -- DSU rx data
73 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
74
75 -- UART APB ---------------------------------------------------------------
76 urxd1 : IN STD_ULOGIC; -- UART1 rx data
77 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
78
79 -- RAM --------------------------------------------------------------------
80 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
81 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 nSRAM_BE0 : OUT STD_LOGIC;
83 nSRAM_BE1 : OUT STD_LOGIC;
84 nSRAM_BE2 : OUT STD_LOGIC;
85 nSRAM_BE3 : OUT STD_LOGIC;
86 nSRAM_WE : OUT STD_LOGIC;
87 nSRAM_CE : OUT STD_LOGIC;
88 nSRAM_OE : OUT STD_LOGIC;
89
90 -- APB --------------------------------------------------------------------
91 apbi_ext : OUT apb_slv_in_type;
92 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
93 -- AHB_Slave --------------------------------------------------------------
94 ahbi_s_ext : OUT ahb_slv_in_type;
95 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
96 -- AHB_Master -------------------------------------------------------------
97 ahbi_m_ext : OUT AHB_Mst_In_Type;
98 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
99
100 );
101 END;
102
103 ARCHITECTURE Behavioral OF leon3_soc__LPP_JCP IS
104
105 -----------------------------------------------------------------------------
106 -- CONFIG -------------------------------------------------------------------
107 -----------------------------------------------------------------------------
108
109 -- Clock generator
110 CONSTANT CFG_CLKMUL : INTEGER := (1);
111 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
112 CONSTANT CFG_OCLKDIV : INTEGER := (1);
113 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
114 -- LEON3 processor core
115 CONSTANT CFG_LEON3 : INTEGER := 1;
116 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
117 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
118 CONSTANT CFG_V8 : INTEGER := 0;
119 CONSTANT CFG_MAC : INTEGER := 0;
120 CONSTANT CFG_SVT : INTEGER := 0;
121 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
122 CONSTANT CFG_LDDEL : INTEGER := (1);
123 CONSTANT CFG_NWP : INTEGER := (0);
124 CONSTANT CFG_PWD : INTEGER := 1*2;
125 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
126 -- 1*(8 + 16 * 0) => grfpu-light
127 -- 1*(8 + 16 * 1) => netlist
128 -- 0*(8 + 16 * 0) => No FPU
129 -- 0*(8 + 16 * 1) => No FPU;
130 CONSTANT CFG_ICEN : INTEGER := 1;
131 CONSTANT CFG_ISETS : INTEGER := 1;
132 CONSTANT CFG_ISETSZ : INTEGER := 4;
133 CONSTANT CFG_ILINE : INTEGER := 4;
134 CONSTANT CFG_IREPL : INTEGER := 0;
135 CONSTANT CFG_ILOCK : INTEGER := 0;
136 CONSTANT CFG_ILRAMEN : INTEGER := 0;
137 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
138 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
139 CONSTANT CFG_DCEN : INTEGER := 1;
140 CONSTANT CFG_DSETS : INTEGER := 1;
141 CONSTANT CFG_DSETSZ : INTEGER := 4;
142 CONSTANT CFG_DLINE : INTEGER := 4;
143 CONSTANT CFG_DREPL : INTEGER := 0;
144 CONSTANT CFG_DLOCK : INTEGER := 0;
145 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
146 CONSTANT CFG_DLRAMEN : INTEGER := 0;
147 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
148 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
149 CONSTANT CFG_MMUEN : INTEGER := 0;
150 CONSTANT CFG_ITLBNUM : INTEGER := 2;
151 CONSTANT CFG_DTLBNUM : INTEGER := 2;
152 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
153 CONSTANT CFG_TLB_REP : INTEGER := 1;
154
155 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
156 CONSTANT CFG_ITBSZ : INTEGER := 0;
157 CONSTANT CFG_ATBSZ : INTEGER := 0;
158
159 -- AMBA settings
160 CONSTANT CFG_DEFMST : INTEGER := (0);
161 CONSTANT CFG_RROBIN : INTEGER := 1;
162 CONSTANT CFG_SPLIT : INTEGER := 0;
163 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
164 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
165
166 -- DSU UART
167 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
168
169 -- LEON2 memory controller
170 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
171
172 -- UART 1
173 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
174 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
175
176 -- LEON3 interrupt controller
177 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
178
179 -- Modular timer
180 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
181 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
182 CONSTANT CFG_GPT_SW : INTEGER := (8);
183 CONSTANT CFG_GPT_TW : INTEGER := (32);
184 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
185 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
186 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
187 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
188 -----------------------------------------------------------------------------
189
190 -----------------------------------------------------------------------------
191 -- SIGNALs
192 -----------------------------------------------------------------------------
193 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
194 -- CLK & RST --
195 SIGNAL clk2x : STD_ULOGIC;
196 SIGNAL clkmn : STD_ULOGIC;
197 SIGNAL clkm : STD_ULOGIC;
198 SIGNAL rstn : STD_ULOGIC;
199 SIGNAL rstraw : STD_ULOGIC;
200 SIGNAL pciclk : STD_ULOGIC;
201 SIGNAL sdclkl : STD_ULOGIC;
202 SIGNAL cgi : clkgen_in_type;
203 SIGNAL cgo : clkgen_out_type;
204 --- AHB / APB
205 SIGNAL apbi : apb_slv_in_type;
206 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
207 SIGNAL ahbsi : ahb_slv_in_type;
208 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
209 SIGNAL ahbmi : ahb_mst_in_type;
210 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
211 --UART
212 SIGNAL ahbuarti : uart_in_type;
213 SIGNAL ahbuarto : uart_out_type;
214 SIGNAL apbuarti : uart_in_type;
215 SIGNAL apbuarto : uart_out_type;
216 --MEM CTRLR
217 SIGNAL memi : memory_in_type;
218 SIGNAL memo : memory_out_type;
219 SIGNAL wpo : wprot_out_type;
220 SIGNAL sdo : sdram_out_type;
221 --IRQ
222 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
223 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
224 --Timer
225 SIGNAL gpti : gptimer_in_type;
226 SIGNAL gpto : gptimer_out_type;
227 --DSU
228 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
229 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
230 SIGNAL dsui : dsu_in_type;
231 SIGNAL dsuo : dsu_out_type;
232 -----------------------------------------------------------------------------
233
234 SIGNAL nSRAM_CE_s : STD_LOGIC;
235 BEGIN
236
237
238 ----------------------------------------------------------------------
239 --- Reset and Clock generation -------------------------------------
240 ----------------------------------------------------------------------
241
242 cgi.pllctrl <= "00";
243 cgi.pllrst <= rstraw;
244
245 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
246
247 clkgen0 : clkgen -- clock generator
248 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
249 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
250 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
251
252 ----------------------------------------------------------------------
253 --- LEON3 processor / DSU / IRQ ------------------------------------
254 ----------------------------------------------------------------------
255
256 l3 : IF CFG_LEON3 = 1 GENERATE
257 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
258 u0 : leon3s -- LEON3 processor
259 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
260 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
261 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
262 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
263 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
264 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
265 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
266 irqi(i), irqo(i), dbgi(i), dbgo(i));
267 END GENERATE;
268 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
269
270 dsugen : IF CFG_DSU = 1 GENERATE
271 dsu0 : dsu3 -- LEON3 Debug Support Unit
272 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
273 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
274 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
275 dsui.enable <= '1';
276 dsui.break <= '0';
277 END GENERATE;
278 END GENERATE;
279
280 nodsu : IF CFG_DSU = 0 GENERATE
281 ahbso(2) <= ahbs_none;
282 dsuo.tstop <= '0';
283 dsuo.active <= '0';
284 END GENERATE;
285
286 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
287 irqctrl0 : irqmp -- interrupt controller
288 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
289 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
290 END GENERATE;
291 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
292 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
293 irqi(i).irl <= "0000";
294 END GENERATE;
295 apbo(2) <= apb_none;
296 END GENERATE;
297
298 ----------------------------------------------------------------------
299 --- Memory controllers ---------------------------------------------
300 ----------------------------------------------------------------------
301 memctrlr : mctrl GENERIC MAP (
302 hindex => 0,
303 pindex => 0,
304 paddr => 0,
305 srbanks => 1
306 )
307 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
308
309 memi.brdyn <= '1';
310 memi.bexcn <= '1';
311 memi.writen <= '1';
312 memi.wrn <= "1111";
313 memi.bwidth <= "10";
314
315 bdr : FOR i IN 0 TO 3 GENERATE
316 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
317 PORT MAP (
318 data(31-i*8 DOWNTO 24-i*8),
319 memo.data(31-i*8 DOWNTO 24-i*8),
320 memo.bdrive(i),
321 memi.data(31-i*8 DOWNTO 24-i*8));
322 END GENERATE;
323
324 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
325 PORT MAP (address, memo.address(21 DOWNTO 2));
326 nSRAM_CE_s <= NOT(memo.ramsn(0));
327 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
328 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
329 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
330 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
331 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
332 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
333 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
334
335 ----------------------------------------------------------------------
336 --- AHB CONTROLLER -------------------------------------------------
337 ----------------------------------------------------------------------
338 ahb0 : ahbctrl -- AHB arbiter/multiplexer
339 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
340 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
341 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
342 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
343
344 ----------------------------------------------------------------------
345 --- AHB UART -------------------------------------------------------
346 ----------------------------------------------------------------------
347 dcomgen : IF CFG_AHB_UART = 1 GENERATE
348 dcom0 : ahbuart
349 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
350 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
351 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
352 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
353 END GENERATE;
354 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
355
356 ----------------------------------------------------------------------
357 --- APB Bridge -----------------------------------------------------
358 ----------------------------------------------------------------------
359 apb0 : apbctrl -- AHB/APB bridge
360 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
361 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
362
363 ----------------------------------------------------------------------
364 --- GPT Timer ------------------------------------------------------
365 ----------------------------------------------------------------------
366 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
367 timer0 : gptimer -- timer unit
368 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
369 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
370 nbits => CFG_GPT_TW)
371 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
372 gpti.dhalt <= dsuo.tstop;
373 gpti.extclk <= '0';
374 END GENERATE;
375 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
376
377
378 ----------------------------------------------------------------------
379 --- APB UART -------------------------------------------------------
380 ----------------------------------------------------------------------
381 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
382 uart1 : apbuart -- UART 1
383 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
384 fifosize => CFG_UART1_FIFO)
385 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
386 apbuarti.rxd <= urxd1;
387 apbuarti.extclk <= '0';
388 utxd1 <= apbuarto.txd;
389 apbuarti.ctsn <= '0';
390 END GENERATE;
391 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
392
393 -------------------------------------------------------------------------------
394 -- AMBA BUS -------------------------------------------------------------------
395 -------------------------------------------------------------------------------
396
397 -- APB --------------------------------------------------------------------
398 apbi_ext <= apbi;
399 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
400 max_16_apb : IF I + 5 < 16 GENERATE
401 apbo(I+5) <= apbo_ext(I+5);
402 END GENERATE max_16_apb;
403 END GENERATE all_apb;
404 -- AHB_Slave --------------------------------------------------------------
405 ahbi_s_ext <= ahbsi;
406 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
407 max_16_ahbs : IF I + 3 < 16 GENERATE
408 ahbso(I+3) <= ahbo_s_ext(I+3);
409 END GENERATE max_16_ahbs;
410 END GENERATE all_ahbs;
411 -- AHB_Master -------------------------------------------------------------
412 ahbi_m_ext <= ahbmi;
413 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
414 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
415 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
416 END GENERATE max_16_ahbm;
417 END GENERATE all_ahbm;
418
419
420
421 END Behavioral;
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1 SOC.vhd
2 leon3_soc.vhd
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